CN115543456A

CN115543456A - FPGA chip loading rate improving method, electronic equipment and storage medium

Info

Publication number: CN115543456A
Application number: CN202211076685.9A
Authority: CN
Inventors: 张朋新; 单德鹏
Original assignee: China Financial Certification Authority Co ltd
Current assignee: China Financial Certification Authority Co ltd
Priority date: 2022-09-02
Filing date: 2022-09-02
Publication date: 2022-12-30

Abstract

The application relates to a method for improving the loading rate of an FPGA chip, electronic equipment and a storage medium. The method comprises the following steps: generating a PCI-E starting configuration file and a user configuration file based on the set compiling environment; the PCI-E starting configuration file is a starting configuration file of a PCI-E interface password card; transmitting the PCI-E starting configuration file and the user configuration file to a programmable read-only memory (PROM) matched with an FPGA chip in a PCI-E interface password card; receiving a starting request of a PCI-E interface password card; and loading the PCI-E starting configuration file in the PROM to the FPGA chip in response to the starting request. According to the scheme provided by the application, the loading rate can be effectively increased, the PCI-E interface password card can be preferentially ensured to rapidly enter the running state, and the development bottleneck problem of the high-performance PCI-E interface password card is solved.

Description

FPGA chip loading rate improving method, electronic equipment and storage medium

Technical Field

The present application relates to the field of chip technologies, and in particular, to a method for increasing a loading rate of an FPGA chip, an electronic device, and a storage medium.

Background

At present, the PCI-E interface password card widely adopts an FPGA chip which is a chip capable of being reprogrammed but generally does not have a nonvolatile characteristic, namely programming information is lost after the FPGA chip is powered off. Therefore, the FPGA chip needs to be additionally configured with a FLASH chip of the nonvolatile memory, so that the program loading operation is automatically completed after the FLASH chip is powered on. Thus, the PCI-E interface password card needs to go through a startup preparation phase from power-on to normal operation, and the preparation time is usually not more than 120ms according to the PCI-E specification. The working content of the stage is mainly that the FPGA chip finishes the loading of the data stored in the FLASH chip, so that the PCI-E interface password card enters an effective running state, and the password server can be ensured to identify and load the PCI-E interface password card in time.

In the prior art, the FPGA chip loading mode for PCI-E interface crypto cards generally includes parallel passive loading and serial passive loading, wherein the parallel passive loading mode includes a BPI flash memory, which is faster, but requires more interfaces; the serial passive loading mode has a QSPI mode, the speed is low, the used peripheral interface resources are few, and the cost is low.

However, with the continuous increase of the device capacity of the FPGA chip and the multiplication of the bit stream length of the FPGA chip configuration, it is more difficult to meet the 120ms time requirement of the PCI-E specification, and the requirement gradually becomes a bottleneck in the development of a high-performance PCI-E interface crypto card based on the FPGA. Therefore, the data loading rate of the FPGA chip needs to be increased to shorten the start preparation time from power-on to normal operation of the PCI-E interface cryptographic card.

Disclosure of Invention

In order to overcome the problems in the related art, the application provides an FPGA chip loading rate improving method, electronic equipment and a storage medium.

A first aspect of the present application provides a method for increasing a loading rate of an FPGA chip, including:

generating a PCI-E starting configuration file and a user configuration file based on the set compiling environment; the PCI-E starting configuration file is a starting configuration file of a PCI-E interface password card;

transmitting the PCI-E starting configuration file and the user configuration file to a programmable read-only memory (PROM) matched with an FPGA chip in a PCI-E interface password card;

receiving a starting request of a PCI-E interface password card;

and loading the PCI-E starting configuration file in the PROM to the FPGA chip in response to the starting request so that the PCI-E interface password card enters a running state.

In one embodiment, the setting of the compiling environment specifically includes:

setting a global clock buffer, wherein the global clock buffer is used for providing a clock for the FPGA chip;

configuring signal driving conditions of an I/O pin of an FPGA chip;

setting a reset logic corresponding to a user configuration program; the user configuration program is a program for loading a user configuration file to the FPGA chip; the reset logic is logic for triggering the user configuration program to reset;

and setting a constraint file, wherein the constraint file is used for constraining the clock timing and/or the configuration flow.

In one embodiment, configuring signal driving conditions of an I/O pin of an FPGA chip includes:

configuring a signal driving condition of the I/O BANK receiving the slot reset signal as a PCI-E starting bit stream driving condition; the PCI-E starting bit stream driving condition is a driving condition corresponding to the PCI-E starting configuration file when the loading task is executed; the receiving slot reset signal is a reset signal generated when the start request is received.

In one embodiment, setting a reset logic corresponding to a user configuration comprises:

the reset logic is set to: and resetting the user configuration program when the password card successful identification signal is received, wherein the password card successful identification signal is a corresponding feedback signal when the PCI-E interface password card enters the running state.

In one embodiment, a constraint file is set, comprising:

setting an IP core constraint file; and

and setting a configuration flow constraint file.

In one embodiment, the IP core constraint file comprises a PCI-E serial constraint file and a BPI flash configuration constraint file;

the configuration flow constraint file includes a bitstream compression execution file and a bitstream separation execution file.

In one embodiment, after loading the PCI-E boot configuration file to the FPGA chip in response to the boot request, the method further includes:

receiving an enumeration request of a PCI-E interface password card;

and loading the user configuration file to the FPGA chip in response to the enumeration request so that the PCI-E interface password card can be configured according to user design.

In one embodiment, generating the PCI-E boot configuration file and the user configuration file based on the set compilation environment includes:

generating a target configuration file based on the set compiling environment, wherein the target configuration file consists of a PCI-E starting configuration file and a user configuration file which are packaged in a sticky mode;

and separating the PCI-E starting configuration file and the user configuration file.

A second aspect of the present application provides an electronic device, comprising:

a processor; and

a memory having executable code stored thereon, which when executed by the processor, causes the processor to perform the method as described above.

A third aspect of the application provides a non-transitory machine-readable storage medium having stored thereon executable code which, when executed by a processor of an electronic device, causes the processor to perform a method as described above.

The technical scheme provided by the application can comprise the following beneficial effects:

the PCI-E starting configuration file and the user configuration file are generated based on the set compiling environment, the PCI-E starting configuration file and the user configuration file are transmitted to a Programmable Read Only Memory (PROM) matched with an FPGA chip in a PCI-E interface password card, a starting request of the PCI-E interface password card is received, the PCI-E starting configuration file in the PROM is loaded to the FPGA chip in response to the starting request, and compared with the prior method that the PCI-E starting configuration file and the user configuration file are simultaneously loaded to the FPGA chip, the file capacity in the starting process can be fully reduced, so that the loading rate is effectively increased, the PCI-E interface password card can be preferentially ensured to be in the operating state, and the bottleneck problem of development of the high-performance PCI-E interface password card is solved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the present application are illustrated by way of example and not by way of limitation, and like or corresponding reference numerals indicate like or corresponding parts.

Fig. 1 is one of schematic flow diagrams of a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application;

fig. 2 is a second schematic flowchart of a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application;

fig. 3 is a third schematic flowchart of a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an electronic device shown in an embodiment of the present application.

Detailed Description

Embodiments will now be described with reference to the accompanying drawings. It will be appreciated that for simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. In addition, this application sets forth numerous specific details in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the embodiments described herein. Moreover, the description should not be taken as limiting the scope of the embodiments described herein.

The PCI-E interface password card needs to go through a starting preparation phase from power-on to normal operation, and the preparation time is usually not more than 120ms according to the PCI-E specification. The working content of the stage is mainly that the FPGA chip finishes the loading of the data stored in the FLASH chip, so that the PCI-E interface password card enters an effective running state, and the password server can be ensured to identify and load the PCI-E interface password card in time. In the prior art, the FPGA chip loading mode for PCI-E interface crypto cards generally includes parallel passive loading and serial passive loading, wherein the parallel passive loading mode includes a BPI flash memory, which is faster, but requires more interfaces; the serial passive loading mode has a QSPI mode, the speed is low, the used peripheral interface resources are few, and the cost is low. However, with the continuous increase of the device capacity of the FPGA chip and the multiplication of the bit stream length of the FPGA chip configuration, it is more difficult to meet the 120ms time requirement of the PCI-E specification, and the requirement gradually becomes a bottleneck in the development of a high-performance PCI-E interface crypto card based on the FPGA. Therefore, the data loading rate of the FPGA chip needs to be increased to shorten the preparation time for starting the PCI-E interface cryptographic card from power-on to normal operation.

In view of the above problems, embodiments of the present application provide a method for increasing a loading rate of an FPGA chip, which can sufficiently reduce a file capacity in a loading process, thereby effectively increasing the loading rate, preferentially ensuring that a PCI-E interface password card can quickly enter an operating state, and solving a bottleneck problem in development of a high-performance PCI-E interface password card.

The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic flowchart of a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application.

Referring to fig. 1, a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application may include:

in step 101, a PCI-E boot configuration file and a user configuration file are generated based on the set compiling environment. The PCI-E boot configuration file is the boot configuration file of the PCI-E interface password card, and the user configuration file is the file used for configuring the user function. The PCI-E is a PCI-Express (peripheral component interconnect Express) and is a high-speed serial computer expansion bus standard, the PCI-E belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices allocate independent channel bandwidth and do not share bus bandwidth, and mainly support functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS), and the like.

The set compiling environment is obtained after the compiling environment corresponding to the loading flow of the standard FPGA chip is changed, so that the set compiling environment can generate independent PCI-E starting configuration files and user configuration files. Taking the standard FPGA chip loading flow of the FPGA parallel loading BPI mode as an example, in the BPI configuration mode, the FPGA chip always starts reading from the NOR flash in an asynchronous reading mode (x 16 data bus), that is, the address bus is incremented from a given start address, and the NOR flash sends back bit stream data. And the maximum frequency to be transmitted needs to be calculated taking into account the BPI FLASH output clock specification. Then, the configuration of the FPGA loading BPI mode in parallel can be expressed by the following formula: configuration time = (file size)/(maximum frequency × data bit width). Assuming that the FPGA chip is XC7K160T, the bit file of the FPGA chip is compressed into 4.6 Mbytes, because the asynchronous FLASH refers to the frequency of a CCLM clock, the maximum frequency is Configrate, and is currently set to 6MHz, the FPGA chip samples data in the FLASH according to the clock frequency of the CCLK by taking the CCLK clock as the reference, and the configuration time is equal to (4.6M 8) bits/(6M 16) =383ms.

As can be seen from the above configuration time, 383ms far exceeds the PCI-E specification time requirement of 120ms, and if the configuration time needs to be shortened, the synchronous NOR FLASH can be sampled and connected with an external clock, and the clock frequency is increased. However, this method requires hardware modifications and also has limitations, and is not a permanent solution.

Therefore, in the embodiment of the application, the set compiling environment is formed by changing the compiling environment corresponding to the loading flow of the standard FPGA chip, so that the PCI-E starting configuration file and the user configuration file in the obtained configuration file are mutually independent, the PCI-E starting configuration file can be preferentially loaded, the starting and loading time of the FPGA chip can be shortened, and the starting configuration time of the PCI-E interface password card can be shortened.

In step 102, the PCI-E boot configuration file and the user configuration file are transferred to a programmable read only memory PROM associated with an FPGA chip in the PCI-E interface crypto card. The PCI-E interface password card is a high-performance basic password device, is based on a hardware password processor and a multi-core processor, accords with the relevant technical specifications of the national password administration on the password device, can meet the requirements of signature/verification, encryption/decryption of application system data, and provides a safe and perfect key management mechanism. The PCI-E interface password card is widely controlled logically by adopting an FPGA chip which is a chip capable of being reprogrammed but generally not having a nonvolatile characteristic, namely programming information is lost after the FPGA chip is powered down. Therefore, the FPGA chip needs to be additionally configured with a FLASH chip of a nonvolatile memory, so that the FLASH chip of the nonvolatile memory can automatically complete program loading and running after being powered on. Exemplarily, when the PROM leaves a factory, the stored contents are all 1, and a user can write some units of the PROM into data 0 according to needs; when some PROMs are all 0 in factory, the user can write some units into 1 to program them. The PROM can be a bipolar fuse structure, if a user needs to rewrite some units, the user can apply enough current to the units and maintain certain time, the fuse of the units can be blown, and the effect of rewriting the units is achieved. The PROM can also be a PROM based on a Schottky diode, when the PROM leaves a factory, the diode is in a reverse cut-off state, and reverse voltage is applied to the Schottky diode through a large current method to cause the Schottky diode to be permanently broken down, so that the purpose of programming the Schottky diode can be realized.

In step 103, a PCI-E interface password card boot request is received. In this embodiment, the PCI-E interface password card may be installed in a slot of the server, and requires power-on activation, so as to generate an activation request to enable the server to receive the activation request. In practical application, the starting request mode of the PCI-E interface password card is various and needs to be determined according to practical application conditions, which is not limited herein.

In step 104, the PCI-E boot configuration file in the PROM is loaded to the FPGA chip in response to the boot request, so that the PCI-E interface cryptographic card enters a running state. The PCI-E starting configuration file is a file of the minimum PCI-E function configuration required by the PCI-E interface password card to be started and identified by the server, so that bit stream data corresponding to the PCI-E starting configuration file is less, and the aims of quickly starting the PCI-E interface password card and enabling the PCI-E interface password card to quickly enter the running state can be achieved.

The PCI-E starting configuration file and the user configuration file are generated based on the set compiling environment, the PCI-E starting configuration file and the user configuration file are transmitted to a Programmable Read Only Memory (PROM) matched with an FPGA chip in a PCI-E interface password card, a starting request of the PCI-E interface password card is received, the PCI-E starting configuration file in the PROM is loaded to the FPGA chip in response to the starting request, and compared with the prior method that the PCI-E starting configuration file and the user configuration file are simultaneously loaded to the FPGA chip, the method can fully reduce the file capacity in the loading process, effectively improve the loading rate, preferentially ensure that the PCI-E interface password card can quickly enter the running state, and solve the bottleneck problem of development of the high-performance PCI-E interface password card.

In some embodiments, the setting mode for setting the compiling environment is further designed, so that the configuration mode of the FPGA chip is set to be the serial configuration mode, and the bit stream data corresponding to the PCI-E boot configuration file is limited to be small enough. Fig. 2 is a second flowchart of the method for increasing the loading rate of the FPGA chip according to the embodiment of the present application. Referring to fig. 2, in the method for increasing a loading rate of an FPGA chip according to the embodiment of the present application, setting a setting manner of a compiling environment may specifically include:

in step 201, a global clock buffer is set. The global clock buffer is used for providing a clock for the FPGA chip.

In step 202, signal driving conditions for I/O pins of the FPGA chip are configured. Configuring a signal driving condition of the I/O BANK receiving the slot reset signal as a PCI-E enabled bitstream driving condition; the PCI-E starting bit stream driving condition is a driving condition corresponding to the PCI-E starting configuration file when the loading task is executed; the receiving slot reset signal is a reset signal generated when the starting request is received. The slot reset signal may be PERST #, an I/O BANK receiving the PERST # needs to be configured as a part of the bitstream data corresponding to the PCI-E boot configuration file, the I/O BANK is an input/output unit in a defined area in the FPGA chip, the I/O BANK includes a plurality of input/output pins, and a driving signal of the I/O BANK, that is, a signal driving condition of the I/O BANK is required by the bitstream data corresponding to the PCI-E boot configuration file.

In step 203, reset logic corresponding to the user configuration program is set. The user configuration program is a program for loading a user configuration file to the FPGA chip, and the reset logic is logic for triggering the user configuration program to reset. The reset logic is set to: and resetting the user configuration program when the password card successful identification signal is received, wherein the password card successful identification signal is a corresponding feedback signal when the PCI-E interface password card enters the running state. In this embodiment of the present application, the successful identification signal of the cryptographic card may be a user _ link _ up signal of the PCI-E successfully identified after PCI-E enumeration, so that once the PCI-E interface cryptographic card is successfully identified, the user enters the user configuration stage without continuously adding and loading the PCI-E startup configuration file, and thus, the bit stream data corresponding to the PCI-E startup configuration file is small enough.

In step 204, a constraint file is set. The constraint file is used for constraining clock timing and/or configuration flow, and specifically, an IP core constraint file and a configuration flow constraint file are set, wherein the IP core constraint file includes a PCI-E tandem constraint file and a BPI flash configuration constraint file, the PCI-E tandem constraint file may be specifically set to include tandem-specific constraints in k7_ conn _ pci.xdc and k7_ conn _ PCI _ distance.xdc, and the k7_ conn _ pci.xdc and the k7_ conn _ pc _ distance.xdc, where the tandem-specific constraints are tandem constraints; in addition, the BPI Flash configuration constraint file may specifically be set to be that both the k7_ conn _ trd _ tpce.xdc and the k7_ conn _ trd _ tprom.xdc, and both the k7_ conn _ trd _ tpce.xdc and the k7_ conn _ trd _ tprom.xdc include constraints for configuring the BPI Flash, where the BPI Flash refers to a BPI Flash memory, and the BPI Flash refers to a Byte-wide Peripheral Interface, that is, a Byte-wide Peripheral Interface, and the BPI Flash provides power-on loading data for the FPGA in a parallel (8 bit, 16 bit) manner.

The PCI-E serial constraint file and the BPI flash configuration constraint file can be regarded as constraint files of an IP core in an FPGA chip and are used for constraining clock time sequence.

Further, the configuration flow constraint file may include a bitstream compression execution file and a bitstream separation execution file. Wherein, the bitstream compression execution file can be specifically set to set _ property bitstream.general.compression true [ current _ design ] for restricting execution of bitstream compression; in addition, the bitstream separation execution file may be specifically set to set _ property bitstream.config.remote _ writebytestream separate [ current _ design ] write _ bitstream-force separate.bit for restricting execution of bitstream separation of the PCI-E startup configuration file and the user configuration file. Under the constraint of the bitstream compression execution file and the bitstream separation execution file, the PCI-E startup configuration file and the user configuration file in the configuration file generated after compilation are independent of each other.

It should be understood that the above description of each constraint file is only exemplary, and in practical applications, the constraint file may be set in various ways, which need to be set according to practical application situations, and is not limited herein.

It should also be understood that there is no strict timing limitation between step 201 and step 204, and the steps may be executed simultaneously or in other execution orders, and the order from step 201 to step 204 is only an exemplary execution order, and needs to be determined according to the actual application, and is not limited herein.

In some embodiments, the PCI-E boot configuration file and the user configuration file need to be separated from the target configuration file generated after the compilation, and then the user function is continuously configured after the PCI-E boot configuration file is loaded, so that the PCI-E interface password card can be normally used by the user.

Fig. 3 is a third schematic flowchart of a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application. Referring to fig. 3, a method for increasing a loading rate of an FPGA chip according to an embodiment of the present application may include:

in step 301, a target configuration file is generated based on the set compilation environment. It will be appreciated that the compilation will result in a general configuration file, i.e., a target configuration file, which consists of a sticky packed PCI-E boot configuration file and a user configuration file.

In step 302, the PCI-E boot profile and the user profile are separated. Although the PCI-E boot profile and the user profile are packaged in a sticky manner, they are independent of each other and can be separated.

In step 303, the PCI-E boot configuration file and the user configuration file are transferred to a programmable read only memory PROM associated with an FPGA chip in the PCI-E interface crypto card. The PCI-E startup configuration file and the user configuration file are packed back to back in the same PROM in the form of a single bit stream, the file and the bit stream in the PROM are independent, and the bit stream is bit stream data.

In step 304, a PCI-E interface cryptographic card boot request is received.

In step 305, the PCI-E boot configuration file in the PROM is loaded to the FPGA chip in response to the boot request, so that the PCI-E interface cryptocard enters a running state.

In the embodiment of the present application, the content in step 304 and step 305 is similar to the content in step 103 and step 104, and is not described herein again.

In step 306, an enumeration request for a PCI-E interface cryptocard is received. The enumeration request is to request PCI-E enumeration of the PCI-E interface password card, and the purpose of PCI-E enumeration is to allow the server to obtain PCI-E devices, i.e., the topology structure of the PCI-E interface password card of the present application.

In step 307, a user configuration file is loaded to the FPGA chip in response to the enumeration request, so that the PCI-E interface crypto card can be configured according to the user design.

When the PCI-E interface password card is enumerated, the server continuously loads the user configuration file to the FPGA chip by adopting a loading path which is the same as the loading path of the PCI-E starting configuration file, so that the PCI-E interface password card can be configured according to the user design after the PCI-E interface password card is activated. In the present application, a serial configuration mode is adopted, in the serial configuration mode, partial reconfiguration is not performed, and unlike partial reconfiguration, each frame in the device is configured only once, and the frame is not reconfigured. If dynamic updates to the user application are required, conventional partial reconfiguration should be used.

In the embodiment of the present application, the serial configuration method of the present application is compared with the conventional configuration method in terms of configuration time, as shown in tables 1 and 2 below, table 1 is the configuration time of the serial configuration method, and table 2 is the configuration time of the conventional configuration method:

table 1:

table 2:

as can be seen from the comparison between the table 1 and the table 2, the serial configuration mode of the present application not only can meet the PCI-E standard time requirement, but also can enter within 100ms, thereby solving the development bottleneck problem of the high-performance PCI-E interface password card.

Corresponding to the embodiment of the application function implementation method, the application also provides electronic equipment for executing the FPGA chip loading rate increasing method and a corresponding embodiment.

Fig. 4 is a block diagram illustrating a hardware configuration of an electronic device 800 that can implement the FPGA chip loading rate increasing method according to the embodiment of the present application. As shown in fig. 4, electronic device 800 may include a processor 810 and a memory 820. In the electronic device 800 of fig. 4, only constituent elements related to the present embodiment are shown. Thus, it will be apparent to one of ordinary skill in the art that: electronic device 800 may also include common constituent elements that are different from the constituent elements shown in fig. 4. Such as: a fixed-point arithmetic unit.

The electronic device 800 may correspond to a computing device having various processing functions, such as functions to generate a neural network, train or learn a neural network, quantize a floating-point neural network into a fixed-point neural network, or retrain a neural network. For example, the electronic device 800 may be implemented as various types of devices, such as a Personal Computer (PC), a server device, a mobile device, and so on.

The processor 810 controls all functions of the electronic device 800. For example, the processor 810 controls all functions of the electronic device 800 by executing programs stored in the memory 820 on the electronic device 800. The processor 810 may be implemented by a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Application Processor (AP), an artificial intelligence processor chip (IPU), etc., provided in the electronic device 800. However, the present application is not limited thereto.

In some embodiments, processor 810 may include an input/output (I/O) unit 811 and a computing unit 812. The I/O unit 811 may be used to receive various data, such as a boot request for a PCI-E interface crypto card. The computing unit 812 may be used to generate PCI-E boot configuration files and user configuration files and to load the PCI-E boot configuration files in the PROM into the FPGA chip in response to a boot request for the PCI-E interface cryptographic card received via the I/O unit 811. This PCI-E boot configuration file may be output by I/O unit 811, for example. The output data may be provided to memory 820 for reading by other devices (not shown) or may be provided directly to other devices for use.

The memory 820 is hardware for storing various data processed in the electronic device 800. For example, the memory 820 may store processed data and data to be processed in the electronic device 800. The memory 820 may store data involved in the FPGA chip load rate up method process that has been or is to be processed by the processor 810. Further, the memory 820 may store applications, drivers, and the like to be driven by the electronic device 800. For example: the memory 820 may store various programs related to the FPGA chip load rate increasing method to be executed by the processor 810. The memory 820 may be a DRAM, but the present application is not limited thereto. The memory 820 may include at least one of volatile memory or nonvolatile memory. The non-volatile memory may include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. Volatile memory can include Dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, ferroelectric RAM (FeRAM), and the like. In an embodiment, the memory 820 may include at least one of a Hard Disk Drive (HDD), a Solid State Drive (SSD), a high density flash memory (CF), a Secure Digital (SD) card, a Micro-digital (Micro-SD) card, a Mini secure digital (Mini-SD) card, an extreme digital (xD) card, a cache (caches), or a memory stick.

In summary, specific functions implemented by the memory 820 and the processor 810 of the electronic device 800 provided in the embodiments of the present disclosure may be explained with reference to the foregoing embodiments in the present disclosure, and technical effects of the foregoing embodiments can be achieved, so that detailed descriptions are omitted here.

In this embodiment, the processor 810 may be implemented in any suitable manner. For example, the processor 810 may take the form of, for example, a microprocessor or processor and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, an embedded microcontroller, and so forth.

It should be understood that the possible terms "first" or "second" etc. in the claims, description and drawings disclosed in this application are used to distinguish different objects, and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

Although the embodiments of the present application are described above, the descriptions are only examples for facilitating understanding of the present application and are not intended to limit the scope and application scenarios of the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

It should also be appreciated that any module, unit, component, server, computer, terminal, or device executing instructions exemplified herein may include or otherwise have access to a computer-readable medium, such as a storage medium, computer storage medium, or data storage device (removable) and/or non-removable), e.g., a magnetic disk, optical disk, or magnetic tape. Computer storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data.

Claims

1. A method for improving the loading rate of an FPGA chip is characterized by comprising the following steps:

transmitting the PCI-E starting configuration file and the user configuration file to a programmable read-only memory (PROM) matched with an FPGA chip in the PCI-E interface password card;

receiving a starting request of the PCI-E interface password card;

2. The method for increasing the loading rate of the FPGA chip according to claim 1, wherein the setting of the compiling environment specifically includes:

configuring a signal driving condition of an I/O pin of the FPGA chip;

setting a reset logic corresponding to a user configuration program; the user configuration program is a program for loading the user configuration file to the FPGA chip; the reset logic is logic for triggering the user configuration program to reset;

setting a constraint file, wherein the constraint file is used for constraining the clock timing sequence and/or the configuration flow.

3. The FPGA chip loading rate promotion method of claim 2,

the configuring of the signal driving condition of the I/O pin of the FPGA chip comprises the following steps:

configuring a signal driving condition of the I/O BANK receiving the slot reset signal as a PCI-E starting bit stream driving condition; the PCI-E starting bit stream driving condition is a driving condition corresponding to the PCI-E starting configuration file when the loading task is executed; the receiving slot reset signal is a reset signal generated when the starting request is received.

4. The FPGA chip loading rate promotion method of claim 2,

the setting of the reset logic corresponding to the user configuration includes:

setting the reset logic to: and resetting the user configuration program when a password card successful identification signal is received, wherein the password card successful identification signal is a corresponding feedback signal when the PCI-E interface password card enters the running state.

5. The FPGA chip loading rate promotion method of claim 2,

the set constraint file includes:

setting an IP core constraint file; and

and setting a configuration flow constraint file.

6. The FPGA chip loading rate promotion method of claim 5,

the IP core constraint file comprises a PCI-E serial constraint file and a BPI flash configuration constraint file;

the configuration flow constraint file comprises a bit stream compression execution file and a bit stream separation execution file.

7. The FPGA chip loading rate promotion method of claim 1,

after the PCI-E boot configuration file is loaded to the FPGA chip in response to the boot request, the method further includes:

receiving an enumeration request of the PCI-E interface password card;

and loading the user configuration file to the FPGA chip in response to the enumeration request, so that the PCI-E interface password card can be configured according to user design.

8. The FPGA chip loading rate promotion method of claim 1,

the generating of the PCI-E starting configuration file and the user configuration file based on the set compiling environment comprises the following steps:

generating a target configuration file based on a set compiling environment, wherein the target configuration file consists of the PCI-E starting configuration file and the user configuration file which are packaged in a sticky mode;

and separating the PCI-E starting configuration file from the user configuration file.

9. An electronic device, comprising:

a processor; and

a memory having executable code stored thereon, which when executed by the processor, causes the processor to perform the method of any one of claims 1-8.

10. A non-transitory machine-readable storage medium having stored thereon executable code that, when executed by a processor of an electronic device, causes the processor to perform the method of any one of claims 1-8.