CN115529015B - Radio frequency transceiver, automatic impedance matching gain adjusting circuit and method thereof - Google Patents
Radio frequency transceiver, automatic impedance matching gain adjusting circuit and method thereof Download PDFInfo
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- CN115529015B CN115529015B CN202211497658.9A CN202211497658A CN115529015B CN 115529015 B CN115529015 B CN 115529015B CN 202211497658 A CN202211497658 A CN 202211497658A CN 115529015 B CN115529015 B CN 115529015B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/12—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of attenuating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
Abstract
The invention relates to the field of radio frequency transceivers, in particular to a radio frequency transceiver, an automatic impedance matching gain adjusting circuit and an automatic impedance matching gain adjusting method of the radio frequency transceiver. The gain adjusting circuit provided by the invention can realize that the integral impedance formed by the parallel connection attenuation circuit and the series connection attenuation circuit presents a specific resistance value according to the proportion copy relationship, realizes the impedance matching with the front and rear stages of the radio frequency transceiver, and ensures the maximum power transmission of the radio frequency transceiver.
Description
Technical Field
The present invention relates to the field of radio frequency transceivers, and in particular, to a radio frequency transceiver, an automatic impedance matching gain adjustment circuit and method thereof.
Background
The rf transceiver is a front-end part of the communication system, is responsible for receiving and transmitting signals, is an indispensable part of the wireless communication system, determines the communication distance, and affects the communication quality. The radio frequency transceiver mainly comprises an antenna, a radio frequency switch, a transceiver amplifier, a gain adjusting circuit and a signal modulation and demodulation circuit, as shown in fig. 1. In communication, the strength of signals received by a transceiver is constantly changed, and the strength of signals to be transmitted has different requirements, so that a receiving and transmitting channel gain adjusting circuit is indispensable.
In the radio frequency transceiver, the impedance matching refers to a working state that the load impedance is matched with the internal impedance of the excitation source to obtain the maximum power output. The impedance of each module of the impedance matching antenna, the radio frequency switch, the transceiving amplifier, the gain adjusting circuit and the signal modulation and demodulation circuit is the same. When the gain of the traditional gain adjusting circuit is changed, the control voltage and the channel impedance are adjusted, so that the channel impedance can generate larger fluctuation, the matching performance of radio frequency receiving and transmitting is influenced, radio frequency signals are reflected, and energy loss is caused.
Disclosure of Invention
The present invention has been made to solve at least one of the problems occurring in the related art. Therefore, the invention provides a gain adjusting circuit which improves the matching efficiency among modules, prevents radio frequency signal reflection and energy loss, has automatic impedance matching and realizes maximum power transmission.
The invention provides an automatic impedance matching gain adjusting circuit, which comprises a main attenuation circuit arranged between input voltage and output voltage, wherein the main attenuation circuit consists of a series attenuation circuit and a parallel attenuation circuit, and further comprises a voltage control circuit connected with the main attenuation circuit in parallel, the voltage control circuit comprises a copy circuit of the main attenuation circuit, the copy circuit comprises a series attenuation copy circuit and a parallel attenuation copy circuit, and the copy circuit feeds back control voltage to the main attenuation circuit through the copy circuit through a negative feedback circuit.
According to the invention, the attenuation amount is controlled by the automatic impedance matching gain adjusting circuit according to the change of the input control voltage.
According to the invention, the series attenuation circuit and the parallel attenuation circuit, and the series attenuation replica circuit and the parallel attenuation replica circuit are composed of attenuation circuits formed by stacking N transistor devices, the sources and the drains of the N transistor devices are connected in series, two ends of the attenuation circuit formed by connecting the N transistor devices in series are respectively a voltage input end Vin and a voltage output end Vout, and the gates of the N transistor devices are connected with a control voltage VC in parallel.
The control voltage VC provided by the invention comprises a series control voltage VCS which is input to the gates of the series attenuation circuit and the series attenuation copy circuit from a voltage control end in parallel, and a parallel control voltage VCp which is connected with the gates of the parallel attenuation circuit and the parallel attenuation copy circuit through a negative feedback circuit.
The transceiver radio frequency signal of the series attenuation circuit and the replica series attenuation circuit provided by the invention is input from a voltage input end Vin and output from a voltage output end Vout.
The transceiver radio frequency signals of the parallel attenuation circuit and the replica parallel attenuation circuit provided by the invention pass through a voltage input end Vin in parallel, and a voltage output end Vout is grounded.
The transistor device provided by the invention is an NMOS transistor.
According to the invention, the main attenuation circuit and the replica circuit are made to have the impedance proportional to each other by making the width and the length of the NMOS transistors of the main attenuation circuit and the replica circuit proportional to the number of the NMOS transistors connected in series.
The invention also provides a radio frequency transceiver which applies the automatic impedance matching gain adjusting circuit.
The invention also provides a method for automatically adjusting the impedance matching gain, which comprises the following steps:
s1, establishing a replica circuit of a main attenuation circuit;
s2, connecting the replica circuit built in the step S1 into a negative feedback circuit driven by control voltage, and simultaneously connecting the control voltage into a main attenuation circuit;
s3, adjusting the width and length of the NMOS transistors and the serial number of the NMOS transistors to enable the impedance of the replica circuit to be proportional to the impedance of the main attenuation circuit;
and S4, controlling the attenuation amount by controlling the change of the voltage to realize the adjustment of the gain value of the radio frequency channel.
One or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:
the gain adjusting circuit provided by the embodiment of the invention can realize that the overall impedance of a set formed by the parallel connection attenuation circuit and the series connection attenuation circuit presents a specific resistance value according to the proportion copy relationship, realize the impedance matching with the front and rear stages of the radio frequency transceiver and ensure the maximum power transmission of the radio frequency transceiver.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional RF transceiver;
FIG. 2 is a gain adjustment circuit provided by an embodiment of the present invention;
FIG. 3 is a parallel damping circuit or a series damping circuit provided by an embodiment of the present invention;
fig. 4 is a voltage control circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. Specific meanings of the above terms in the embodiments of the present invention can be understood in specific cases by those of ordinary skill in the art.
In embodiments of the invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The following describes, with reference to fig. 2 to fig. 4, a gain adjustment circuit proposed by an embodiment of the present invention, which includes a series attenuation circuit, a parallel attenuation circuit, and a voltage control circuit.
The gain adjusting circuit provided by the embodiment of the invention is shown in fig. 2 and comprises a series attenuation circuit, a parallel attenuation circuit and a voltage control circuit, and the gain of a radio frequency channel is adjusted through an externally input voltage.
The series attenuation circuit and the parallel attenuation circuit provided by the embodiment of the invention are composed of attenuation circuits formed by stacking N transistor devices, the attenuation change is realized through the VC voltage change, and as shown in figure 3, higher linearity and power bearing capacity can be realized through stacking a plurality of devices. When the attenuation circuit is used as a series attenuation circuit, the radio-frequency signal of the transceiver is input from Vin and output from Vout; when the attenuation circuit is used as a parallel attenuation circuit, the radio-frequency signal of the transceiver passes through Vin in parallel, and Vout is grounded.
In the attenuation circuit provided in the embodiment of the present invention, the voltage-controlled value is VC, the threshold voltage of the transistor is Vth, the width of the NMOS transistor is W, the length of the NMOS transistor is L, the device mobility coefficient is k, and the number of series connected NMOS transistors is N, then the resistance Rcc (Rs or Rp shown in fig. 4) of the attenuation circuit shown in fig. 3 is:
when the resistance Rs of the series damping circuit and the resistance Rp of the parallel damping circuit shown in fig. 2 are changed, the gain adjusting circuit can realize different damping amounts.
The impedance Rall of the attenuator looking into the input port to the right is:
in the formula:
wherein VCs is the control voltage of the series attenuator, ws is the width of the NMOS transistor of the series attenuator, ls is the length of the NMOS transistor of the series attenuator, and Ns is the number of the NMOS transistors of the series attenuator in series; VCp is the control voltage of the parallel attenuator, wp is the width of the NMOS transistors of the parallel attenuator, lp is the length of the NMOS transistors of the parallel attenuator, and Np is the number of the NMOS transistors of the parallel attenuator connected in series.
In order to ensure that the transceiver can realize the impedance matching of the Rt impedance value under different gain adjustment quantities, then:
from this, the attenuation IL of the gain adjustment circuit can be derived as:
the automatic impedance matching circuit provided by the embodiment of the invention can realize that the resistor Rs of the series attenuation circuit and the resistor Rp of the parallel attenuation circuit always meet the formula (2), and the structure is shown in figure 4.
The operational amplifier in the impedance adjusting circuit provided by the embodiment of the invention enables the input voltage to be equal by establishing negative feedback, wherein Rattc is the integral impedance formed by a parallel attenuation replica circuit and a series attenuation replica circuit:
setting the resistance values of R1, R2, R3 can achieve Rattc + R4 equal to a specific input impedance.
The parallel attenuation replica circuit and the series attenuation replica circuit provided by the embodiment of the invention have the same structure as the parallel attenuation circuit and the series attenuation circuit, and are all shown in fig. 3.
The parallel attenuation replica circuit and the series attenuation replica circuit provided by the embodiment of the invention are not necessarily the same as the parallel attenuation circuit and the series attenuation circuit in transistor size and are in proportional relation.
Referring to the formula (1), the parallel attenuation replica circuit and the series attenuation replica circuit have the same VC and Vth as those of the parallel attenuation circuit and the series attenuation circuit, and W, L, N is different, so that impedance change of a specific ratio of M times can be realized, rall = mx (ratetc + R4) = Rt is realized, and impedance matching is realized.
M satisfies the following formula:
in the formula:
nm is the ratio of the N value of the transistor in the Ratt network to the N value of the transistor in the Rattc network;
lm is the ratio of the value of the transistor L in the Rattc network to the value of the transistor L in the Rattc network;
wm is the ratio of the value of the transistor W in the Rattc network to the value of the transistor W in the Rattc network.
According to the gain adjusting circuit provided by the embodiment of the invention, the integral impedance Ratt formed by the parallel connection attenuation circuit and the series connection attenuation circuit can present a specific resistance value, the impedance matching with the front and rear stages of the radio frequency transceiver is realized, and the maximum power transmission of the radio frequency transceiver is ensured.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An automatic impedance matching gain adjusting circuit comprises a main attenuation circuit arranged between input voltage and output voltage, wherein the main attenuation circuit is composed of a series attenuation circuit and a parallel attenuation circuit.
2. The automatic impedance matching gain adjustment circuit of claim 1, wherein attenuation amount control is performed by the automatic impedance matching gain adjustment circuit according to a change in an input control voltage.
3. The automatic impedance matching gain adjusting circuit according to claim 1 or 2, wherein the series attenuation circuit and the parallel attenuation circuit and the series attenuation replica circuit and the parallel attenuation replica circuit are formed by attenuation circuits formed by stacking N transistor devices, sources and drains of the N transistor devices are connected in series, two ends of the attenuation circuit formed by connecting the N transistor devices in series are respectively a voltage input end Vin and a voltage output end Vout, and gates of the N transistor devices are connected in parallel with a control voltage VC.
4. The automatic impedance-matching gain-adjusting circuit of claim 3, wherein the control voltage VC comprises a series control voltage VCS input from a voltage control terminal in parallel to the gate of the series attenuator circuit and the gate of the series attenuator replica circuit, and a parallel control voltage VCp connecting the gate of the parallel attenuator circuit and the gate of the parallel attenuator replica circuit through a negative feedback circuit.
5. The automatic impedance-matching gain-adjusting circuit of claim 4, wherein the transceiver RF signals of the series attenuation circuit and the series attenuation replica circuit are input from a voltage input terminal Vin and output from a voltage output terminal Vout.
6. The automatic impedance-matching gain-adjusting circuit of claim 4, wherein the transceiver RF signals of the shunt attenuation circuit and the shunt attenuation replica circuit are connected in parallel through a voltage input terminal Vin, and a voltage output terminal Vout is connected to ground.
7. The automatic impedance matching gain adjustment circuit of any one of claims 4-6, wherein the transistor device is an NMOS transistor.
8. The automatic impedance matching gain adjustment circuit of claim 7, wherein the impedance of the main attenuator circuit is made proportional to the impedance of the replica circuit by making the width, length and number of series NMOS transistors of the main attenuator circuit and the replica circuit proportional.
9. A radio frequency transceiver employing the automatic impedance matching gain adjustment circuit of any one of claims 1-8.
10. A method for automatic impedance matching gain adjustment, comprising the steps of:
s1, establishing a replica circuit of a main attenuation circuit;
s2, connecting the replica circuit built in the step S1 into a negative feedback circuit driven by control voltage, and simultaneously connecting the control voltage into a main attenuation circuit;
s3, adjusting the width and length of the NMOS transistors and the serial number of the NMOS transistors to enable the impedance of the replica circuit to be proportional to the impedance of the main attenuation circuit;
and S4, controlling the attenuation amount by controlling the change of the voltage to realize the adjustment of the gain value of the radio frequency channel.
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| EA202191759A1 (en) * | 2019-04-04 | 2021-12-15 | Олег Александрович СЕРЕБРЕННИКОВ | HIERARCHICAL SEQUENCE MEMORY |
| CN112187203B (en) * | 2020-09-14 | 2022-06-21 | 北京航空航天大学 | Automatic gain control circuit and gain adjusting method thereof |
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Address after: Room 102, 1st Floor, Building 13, Ecological Science Park Office Building, No. 2018, Zhongtian Avenue, Zhongxin Tianjin Ecological City, Binhai New Area, Tianjin, 300450 Patentee after: TIANJIN HIGAAS MICROWAVE TECHNOLOGY CO.,LTD. Address before: Corner B-3, Floor 4, No. 22-A, Innovation and Entrepreneurship Park, No. 4668, Xinbei Road, Tanggu Marine Science and Technology Park, Binhai New Area, Tianjin 300451 Patentee before: TIANJIN HIGAAS MICROWAVE TECHNOLOGY CO.,LTD. |