CN115527930A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. In the manufacturing method of the semiconductor device provided by the invention, after the metal silicide barrier layer SAB layer covering the surfaces of the active region, the source region and the drain region is removed by etching, and before the step of forming the metal plug CT for externally connecting each electrode of the semiconductor device, a high tensile stress filling layer (for example, a high tensile stress silicon nitride layer) is formed on the semiconductor substrate by utilizing a special process, and then the high tensile stress filling layer deposited in a partial region is removed by etching. Therefore, the holes formed below the side wall after the SAB layer is removed in the prior art are filled with the high tensile stress filling layer better in the tensile stress characteristic, so that the holes formed below the side wall are eliminated, the technical problems that a TIN (triangulated irregular network) film is drilled out by WF6 (WF 6) generated when a metal plug CT is formed in the subsequent process, volcanic reaction occurs and metal loss in the CT is caused are avoided, and the performance of a semiconductor device is improved finally.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

In the manufacture of semiconductor integrated circuits, semiconductor devices with various requirements are generally required to be integrated together for manufacturing, and the semiconductor devices may be SRAM devices, and the SRAM devices include a plurality of MOS transistors, where the MOS transistors may specifically include a gate structure and source and drain regions. Specifically, in a gate structure formed by using a polysilicon gate, side walls are usually formed on the side surfaces of the polysilicon gate, and a source drain region and a drain source region are formed by performing source drain implantation with the side walls on the two sides of the polysilicon gate as self-aligned boundaries. Also, it is often necessary to form a metal silicide, such as cobalt silicide (cobalt silicide), on top of the source and drain regions and the polysilicon gate to reduce contact resistance.

Currently, in the prior art, in order to protect other regions of the SRAM device that do not need to form a metal silicide, before forming a metal silicide on top of the gate structure, the source, and the drain of the device, a metal silicide Block (SAB) layer is formed, and then the metal silicide is formed on a specific region by etching-deposition or other processes.

However, in the prior art, since a wet etching process is usually used when the SAB layer deposited on the surfaces of the gate structure, the source electrode and the drain electrode is etched and removed, a plurality of small holes are formed below the sidewalls on both sides of the gate structure in the process of etching and removing part of the SAB layer by the wet etching process based on the isotropic etching characteristic, as shown in fig. 1, and further, in the subsequent process of forming the metal plugs CT for electrically connecting the electrodes, poor metal (e.g., TIN) filling may occur, which may cause problems of drilling of the TIN film by WF6, occurrence of a volcanic reaction, and metal loss in the CT.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, and aims to solve the technical problems that in the prior art, due to the fact that a hole formed after an SAB layer is removed and located below a side wall, a WF6 drills a TIN film when a metal plug CT is formed in a subsequent process, volcanic reaction occurs, and metal loss in CT occurs.

In a first aspect, to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, which at least includes the following steps:

providing a semiconductor substrate, forming a plurality of discrete gate structures and side walls positioned at two sides of each gate structure on the semiconductor substrate, and at least covering metal silicide barrier layers on the top surfaces of the gate structures and the surfaces of the semiconductor substrate exposed at two sides of the gate structures;

etching to remove the metal silicide barrier layer, and forming a high tensile stress filling layer on the surface of the semiconductor substrate so as to enable the formed high tensile stress filling layer to fill a hole formed below the side wall when the metal silicide barrier layer is removed by etching;

and removing the high-tensile stress filling layer except the high-tensile stress filling layer filled in the hole, and carrying out subsequent processes on the semiconductor substrate to form an electrical structure comprising a metal plug.

Furthermore, the etching process for removing the metal silicide blocking layer may be a wet etching process.

Further, the high tensile stress filling layer may include a high tensile stress silicon nitride layer.

Further, the thickness of the high tensile stress silicon nitride layer may be in the range of:

to

Wherein, preferably, the thickness of the high tensile stress silicon nitride layer is

Further, the sidewall spacer may have an ONO stack structure composed of an oxide layer-a nitride layer-an oxide layer, or may have an ON stack structure composed of an oxide layer-a nitride layer.

Further, the process for forming the high tensile stress silicon nitride layer comprises a plasma enhanced chemical vapor deposition process, and the process conditions of the plasma enhanced chemical vapor deposition process comprise: the process reaction temperature is 300-500 ℃, the radio frequency power is 50-300W, the process reaction gases are SiH4 and NH3, the gas flow ratio of the SiH 4to the NH3 is 0.2-2, and the reaction pressure is 0.5-2 Torr.

Furthermore, the metal silicide blocking layer covering the top surface of the gate structure and the surface of the semiconductor substrate exposed at the two sides of the gate structure can also extend to cover the surface of the side wall.

Further, the etching process for removing the high tensile stress filling layer except the high tensile stress filling layer filled in the hole may be an isotropic dry etching process, so as to ensure that the high tensile stress filling layer filled in the hole is completely removed.

Further, before the step of forming the gate structure on the surface of the semiconductor substrate, the method for manufacturing the semiconductor device provided by the invention may further include a step of forming a trench isolation structure for defining an active region of the semiconductor device in the semiconductor substrate.

Further, the step of forming a metal plug on the semiconductor substrate may specifically include:

forming an interlayer dielectric layer on the semiconductor substrate so that the interlayer dielectric layer at least fills gaps between the adjacent grid structures;

and etching the interlayer dielectric layer to form openings for electrically connecting the source region and/or the drain region defined by the semiconductor substrate corresponding to the two sides of the grid structure externally in the interlayer dielectric layer, and then filling metal tungsten in the openings to form the metal plugs.

In a second aspect, based on the same inventive concept as the method for manufacturing the semiconductor device provided above, the present invention also provides a semiconductor device, which may be specifically a semiconductor device with a high tensile stress filling layer in a partial region prepared by the method for manufacturing a semiconductor device as described above.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

in the manufacturing method of the semiconductor device provided by the invention, after the metal silicide barrier layer SAB layer covering the surfaces of the active region, the source region and the drain region is removed by etching, and before the step of forming the metal plug CT for externally connecting each electrode of the semiconductor device, a high tensile stress filling layer (for example, a high tensile stress silicon nitride layer) is formed on the semiconductor substrate by utilizing a special process, and then the high tensile stress filling layer deposited in a partial region is removed by etching. Therefore, the holes formed below the side wall after the SAB layer is removed in the prior art are filled better by utilizing the tensile stress characteristic of the high-tensile-stress filling layer, so that the holes formed below the side wall are eliminated, the technical problems that a TIN (tungsten inert gas) film is drilled out by WF6 (WF 6) when a metal plug CT is formed in the subsequent process, the volcanic reaction occurs and the metal loss in the CT is avoided, and the performance of a semiconductor device is finally improved.

In addition, in the manufacturing method provided by the invention, the high-tensile stress filling layer is at least filled in the hole, and the high-tensile stress filling layer formed in the rest area is removed, so that the stress influence of the high-tensile stress filling layer on other structures or film layers can be avoided, and the electrical characteristics of the semiconductor device are kept.

Drawings

FIG. 1 is a schematic view of a TEM structure with a small hole problem under a gate structure sidewall in a semiconductor device formed by a method of the prior art;

fig. 2 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 3a to 3c are schematic structural diagrams of a method for manufacturing a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 4 is a schematic TEM structure of a semiconductor structure formed by the manufacturing method according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

100-a semiconductor substrate; 110-side walls;

120-metal silicide barrier layers; 130/130' -high tensile stress filling layer;

d-small holes; 101-a trench isolation structure;

251-gate structure.

Detailed Description

As described in the background, in the prior art, in order to protect other regions of the SRAM device where metal silicide is not required to be formed, a metal silicide Block (SAB) layer is usually formed before forming metal silicide on top of the gate structure, the source and the drain of the device, and then the metal silicide is formed on a specific region by etching-deposition or the like.

However, in the prior art, since a wet etching process is usually used when the SAB layer deposited on the surfaces of the gate structure, the source electrode and the drain electrode is etched and removed, a plurality of small holes are formed below the side walls on both sides of the gate structure in the process of etching and removing part of the SAB layer by the wet etching process based on the isotropic etching characteristic, as shown in fig. 1, fig. 1 is a TEM schematic diagram of a semiconductor device formed by using a method in the prior art, where a part circled by a dotted line in fig. 1 is a small hole caused by the forming method in the prior art, and further, in the subsequent process of forming a metal plug CT for electrically connecting each electrode, a problem of poor filling of metal (e.g., TIN) occurs, which further causes a problem of drilling of a TIN film by WF6, occurrence of a volcanic reaction, and metal loss in CT.

Aiming at the problem, the invention provides a semiconductor device and a manufacturing method thereof, and aims to solve the technical problems that in the prior art, due to the fact that a hole which is formed after an SAB layer is removed and is positioned below a side wall, a TIN film is drilled out from WF6 when a metal plug CT is formed in a subsequent process, volcanic reaction occurs, and metal loss in CT occurs.

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method of manufacturing a semiconductor device provided in an embodiment of the present invention; the manufacturing method of the semiconductor device at least comprises the following steps:

step S100, providing a semiconductor substrate, forming a plurality of discrete gate structures and side walls positioned at two sides of each gate structure on the semiconductor substrate, and at least covering metal silicide barrier layers on the top surfaces of the gate structures and the surfaces of the semiconductor substrate exposed at two sides of the gate structures;

step S200, etching to remove the metal silicide barrier layer, and forming a high tensile stress filling layer on the surface of the semiconductor substrate so as to enable the formed high tensile stress filling layer to fill the hole formed below the side wall when the metal silicide barrier layer is removed by etching;

step S300, removing the high tensile stress filling layer except the high tensile stress filling layer filled in the hole, and performing a subsequent process on the semiconductor substrate to form an electrical structure including a metal plug.

That is, in the manufacturing method of the semiconductor device provided by the present invention, after the metal silicide blocking layer SAB layer covering the surfaces of the active region, the source region and the drain region is removed by etching, and before the step of forming the metal plug CT for externally connecting each electrode of the semiconductor device, a high tensile stress filling layer (for example, a high tensile stress silicon nitride layer) is formed on the semiconductor substrate by using a special process, and then the high tensile stress filling layer deposited in a partial region is removed by etching. Therefore, the holes formed below the side wall after the SAB layer is removed in the prior art are filled with the high tensile stress filling layer better in the tensile stress characteristic, so that the holes formed below the side wall are eliminated, the technical problems that a TIN (triangulated irregular network) film is drilled out by WF6 (WF 6) generated when a metal plug CT is formed in the subsequent process, volcanic reaction occurs and metal loss in the CT is caused are avoided, and the performance of a semiconductor device is improved finally.

The following describes a method for manufacturing a semiconductor device according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Fig. 3a to 3c are schematic structural diagrams of a method for manufacturing a semiconductor device in a manufacturing process according to an embodiment of the present invention.

In step S100, referring to fig. 3a specifically, a semiconductor substrate 100 is provided, and a plurality of discrete gate structures 251 and spacers 110 located at two sides of each gate structure 251 are formed on a surface of the semiconductor substrate 100, and at least cover the metal silicide blocking layer 120 on a top surface of the gate structures 251 and a surface of the semiconductor substrate 100 exposed at two sides of the gate structures 251. Specifically, the semiconductor substrate 100 proposed in the above-mentioned invention may be any suitable substrate material known in the art, and may be at least one of the following materials, for example: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and further includes a multilayer structure composed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be Double-Side Polished silicon Wafers (DSP), or may be a ceramic substrate such as alumina, quartz, or a glass substrate. Illustratively, the semiconductor substrate 100 in this embodiment is, for example, a silicon wafer. For example, in the embodiment of the present invention, the sidewall 110 may be a multilayer film structure of an ONO stack structure, and the ONO stack structure may be a stack structure composed of an oxide layer, a nitride layer and an oxide layer, that is, a silicon dioxide-silicon nitride-silicon dioxide stack structure. Alternatively, an ON stack structure composed of an oxide layer-nitride layer may also be used. It should be noted that, in the embodiment of the present invention, since the sidewall is generally illustrated by using only one layer 110 for simplifying the drawing process, the ONO stack structure is not specifically embodied by using a three-layer structure. As shown in fig. 3a, the metal silicide blocking layer 120 covering the top surface of the gate structure 251 and the surface of the semiconductor substrate 100 exposed at two sides of the gate structure 251 also extends to cover the surface of the sidewall spacers 110.

Further, before forming the gate structure 251 on the surface of the semiconductor substrate 100, the manufacturing method may further include forming a trench isolation structure 101 for defining an active region of the semiconductor device in the semiconductor substrate 100.

In this embodiment, a semiconductor substrate 100 made of a silicon substrate may be provided, and then ion implantation may be performed thereon to form an N-type well or a P-type well for forming a PMOS or NMOS, and then a trench may be formed in the semiconductor substrate 100 by using an etching-deposition process, and then the trench isolation structure 101 may be formed in a manner that the trench is filled with silicon dioxide. Thereafter, a plurality of discrete gate structures 251 are formed on the surface of the semiconductor substrate 100 corresponding to the active region as shown in fig. 3a by using a deposition-etching process, and in fig. 3a, only one gate structure 251 is schematically shown for simplicity of the drawing, and in other embodiments, a plurality of gate structures 251 may be further provided. Then, a metal silicide blocking layer 120 covering the entire gate structure 251 and the sidewall 110 thereof and the exposed surface of the top surface of the semiconductor substrate 100 is formed on the surface of the semiconductor substrate 100 on which the plurality of discrete gate structures 251 are formed.

In step S200, referring to fig. 3b specifically, the metal silicide blocking layer 120 is removed by etching, and a high tensile stress filling layer 130 is formed on the surface of the semiconductor substrate 100, so that the formed high tensile stress filling layer 130 fills up the hole D formed below the sidewall when the metal silicide blocking layer 120 is removed by etching. Wherein, the etching process for removing the metal silicide blocking layer 120 by etching is a wet etching process. The high tensile stress filling layer 130 is preferably a high tensile stress silicon nitride layer.

In this embodiment, the inventors have found that, due to the isotropic etching characteristic of the wet etching process, in the process of forming a semiconductor device, the wet etching process may cause the small hole and the subsequent problems as shown in fig. 3a, and for the problems, the inventors have found through experiments that the tensile stress silicon nitride film needs to form a tensile stress film, and therefore, the gas flow and the reaction voltage need to be adjusted to adjust the H content, so that the gap filling capability is much stronger than that of the conventional PE-SIN, and the problems can be effectively solved. However, the tensile stress silicon nitride film can cause the NMOS to become fast and the PMOS to run slowly, so the change is large and the application is difficult. Based on this, the inventor of the present invention proposes that the ctw missing problem caused by the existence of small holes below the spacer can be effectively solved by adding two steps of tensile stress silicon nitride film deposition and silicon nitride film etching, that is, a high tensile stress silicon nitride layer 130 is formed on the surface of the whole structure, and then is etched and removed, so that the high tensile stress silicon nitride layer 130' is only filled in the small holes D, as shown in fig. 4, where fig. 4 is a TEM structure schematic diagram of the semiconductor structure formed by using the manufacturing method provided by the present invention, so as to eliminate the holes formed below the side walls, thereby avoiding the technical problems of the generation of volcanic reaction due to the fact that the TIN film is drilled out by WF6 when the metal plug CT is formed in the subsequent process, and the metal loss in the CT, and finally improving the performance of the semiconductor device.

Further, the thickness of the high tensile stress silicon nitride layer 130 may be in the range of:

to

Specifically, it may specifically be

And

preferably, in the embodiment of the present invention, the thickness of the high tensile stress silicon nitride layer 130 is selected as the optimum thickness

The process for forming the high tensile stress silicon nitride layer 130 may be, for example, a plasma enhanced chemical vapor deposition process, and the process conditions of the plasma enhanced chemical vapor deposition process include: the value range of the process reaction temperature can be 300-500 ℃, namely, the temperature can be 300 ℃, 350 ℃, 400 ℃, 450 ℃ and 500 ℃; the range of the RF power may be 50W-300W, i.e., 50W, 100W, 150W, 200W, 250W, 300W, 350W, 40W0W, 450W and 500W; the process reaction gas may be a mixed gas of SiH4 and NH3, and the gas flow ratio of the SiH4 and NH3 is 0.2 to 2, that is, specifically, may be 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, and 2.0; the reaction pressure may be in the range of 0.5Torr to 2Torr, specifically, 0.5Torr, 0.6Torr, 0.7Torr, 0.8Torr, 0.9Torr, 1.0Torr, 1.1Torr, 1.2Torr, 1.3Torr, 1.4Torr, 1.5Torr, 1.6Torr, 1.7Torr, 1.8Torr, 1.9Torr and 2.0Torr.

In step S300, referring to fig. 3c in particular, the high tensile stress filling layer 130 except the high tensile stress filling layer 130' filled in the hole is removed, and a subsequent process is performed on the semiconductor substrate 100 to form an electrical structure including a metal plug (not shown). In this embodiment, the process of removing the high tensile stress filling layer 130 except the high tensile stress filling layer 130' filled in the hole is an isotropic dry etching process to ensure that the high tensile stress filling layer filled in the hole is completely removed.

Illustratively, in an embodiment of the present invention, a step of forming a metal plug (not shown) on the semiconductor substrate 100 may include:

step S301, forming an interlayer dielectric layer (not shown) on the semiconductor substrate 100, so that the interlayer dielectric layer at least fills a gap between adjacent gate structures 251;

step S302, etching the interlayer dielectric layer (not shown) to form openings (not shown) in the interlayer dielectric layer for electrically connecting the source region and/or the drain region defined by the semiconductor substrate 100 corresponding to the two sides of the gate structure 251, and then filling the openings with tungsten to form the metal plugs CT (not shown).

Since the process of forming the metal plug CT is the prior art in the embodiment of the present invention, the detailed description thereof is omitted in the present invention.

In addition, based on the same inventive concept as the method for manufacturing the semiconductor device provided above, the present invention also provides a semiconductor device, which may be specifically a semiconductor device with a high tensile stress filling layer in a partial region prepared by the method for manufacturing a semiconductor device as described above, and for this, specific reference is made to the embodiments corresponding to fig. 2 and fig. 3a to 3c, which will not be described in detail herein.

In summary, in the manufacturing method of the semiconductor device provided by the present invention, after the metal silicide blocking layer SAB layer covering the surfaces of the active region, the source region and the drain region is removed by etching, and before the step of forming the metal plug CT for externally connecting each electrode of the semiconductor device, a high tensile stress filling layer (for example, a high tensile stress silicon nitride layer) is formed on the semiconductor substrate by using a special process, and then the high tensile stress filling layer deposited in a part of the region is removed by etching. Therefore, the holes formed below the side wall after the SAB layer is removed in the prior art are filled better by utilizing the tensile stress characteristic of the high-tensile-stress filling layer, so that the holes formed below the side wall are eliminated, the technical problems that a TIN (tungsten inert gas) film is drilled out by WF6 (WF 6) when a metal plug CT is formed in the subsequent process, the volcanic reaction occurs and the metal loss in the CT is avoided, and the performance of a semiconductor device is finally improved.

In addition, in the manufacturing method provided by the invention, the high-tensile stress filling layer is at least filled in the hole, and the high-tensile stress filling layer formed in the rest area is removed, so that the stress influence of the high-tensile stress filling layer on other structures or film layers can be avoided, and the electrical characteristics of the semiconductor device are kept.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art that many changes and modifications can be made, or equivalents employed, to the presently disclosed embodiments without departing from the intended scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention will still fall within the protection scope of the technical solution of the present invention.

It should also be understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and not for describing a sequential or logical relationship between various components, elements, steps, or the like, unless otherwise specified or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising at least the steps of:

providing a semiconductor substrate, forming a plurality of discrete gate structures and side walls positioned at two sides of each gate structure on the semiconductor substrate, and at least covering metal silicide barrier layers on the top surfaces of the gate structures and the surfaces of the semiconductor substrate exposed at two sides of the gate structures;

etching to remove the metal silicide barrier layer, and forming a high tensile stress filling layer on the surface of the semiconductor substrate so as to enable the formed high tensile stress filling layer to fill the hole formed below the side wall when the metal silicide barrier layer is etched to be removed;

and removing the high-tensile stress filling layer except the high-tensile stress filling layer filled in the hole, and carrying out subsequent processes on the semiconductor substrate to form an electrical structure comprising a metal plug.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the etching process for removing the metal silicide blocking layer is a wet etching process.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the high tensile stress filling layer comprises a high tensile stress silicon nitride layer.

4. A method of manufacturing a semiconductor device according to claim 3, wherein the thickness of the high tensile stress silicon nitride layer is in a range of:

to

5. The method according to claim 1, wherein the sidewall spacer has an ONO stack structure of oxide layer-nitride layer-oxide layer or an ON stack structure of oxide layer-nitride layer.

6. The method of manufacturing a semiconductor device according to claim 4, wherein the process of forming the high tensile stress silicon nitride layer comprises a plasma enhanced chemical vapor deposition process, and process conditions of the plasma enhanced chemical vapor deposition process comprise: the process reaction temperature is 300-500 ℃, the radio frequency power is 50-300W, the process reaction gases are SiH4 and NH3, the gas flow ratio of the SiH 4to the NH3 is 0.2-2, and the reaction pressure is 0.5-2 Torr.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the metal silicide blocking layer covering the top surface of the gate structure and the surface of the semiconductor substrate exposed at both sides of the gate structure further extends to cover the surface of the sidewall.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the process of removing the high tensile stress filling layer other than the high tensile stress filling layer filled in the hole is an isotropic dry etching process to ensure complete removal of the high tensile stress filling layer filled in the hole.

9. The method of manufacturing a semiconductor device according to claim 1, wherein before the gate structure is formed on the surface of the semiconductor substrate, the method further comprises forming a trench isolation structure in the semiconductor substrate for defining an active region of the semiconductor device.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming a metal plug on the semiconductor substrate comprises:

forming an interlayer dielectric layer on the semiconductor substrate so that the interlayer dielectric layer at least fills gaps between the adjacent grid structures;

and etching the interlayer dielectric layer to form openings for electrically connecting the source region and/or the drain region defined by the semiconductor substrate corresponding to the two sides of the grid structure externally in the interlayer dielectric layer, and then filling metal tungsten in the openings to form the metal plugs.

11. A semiconductor device, characterized in that it is a semiconductor device in which a partial region prepared by the method for manufacturing a semiconductor device according to any one of claims 1to 10 contains a high tensile stress filling layer.

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