CN115527922A - Manufacturing method of semiconductor structure and semiconductor structure - Google Patents

Manufacturing method of semiconductor structure and semiconductor structure Download PDF

Info

Publication number
CN115527922A
CN115527922A CN202211182953.5A CN202211182953A CN115527922A CN 115527922 A CN115527922 A CN 115527922A CN 202211182953 A CN202211182953 A CN 202211182953A CN 115527922 A CN115527922 A CN 115527922A
Authority
CN
China
Prior art keywords
layer
forming
sacrificial layer
top silicon
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211182953.5A
Other languages
Chinese (zh)
Inventor
亨利·H·阿达姆松
林鸿霄
苗渊浩
赵雪薇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Greater Bay Area Institute of Integrated Circuit and System
Original Assignee
Guangdong Greater Bay Area Institute of Integrated Circuit and System
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Greater Bay Area Institute of Integrated Circuit and System filed Critical Guangdong Greater Bay Area Institute of Integrated Circuit and System
Priority to CN202211182953.5A priority Critical patent/CN115527922A/en
Publication of CN115527922A publication Critical patent/CN115527922A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Abstract

The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a base, wherein the base comprises a sapphire substrate and a top silicon layer which are sequentially overlapped; forming a preliminary sacrificial layer on the exposed surface of the top silicon layer; sequentially carrying out ion implantation and annealing operation on the preliminary sacrificial layer and the top silicon layer, forming a silicide layer on the top silicon layer after the annealing operation, and forming a sacrificial layer on the preliminary sacrificial layer after the annealing operation; and removing the sacrificial layer. According to the method, the preliminary sacrificial layer is formed on the substrate with the thin top silicon layer and the sapphire substrate, so that the lattice damage of subsequent ion injection to the formed silicide layer is reduced, injected ions in the silicide layer can be distributed uniformly, the crystal quality of the silicide layer is improved, and the problem of low carrier migration rate of a semiconductor structure in the prior art is solved.

Description

Manufacturing method of semiconductor structure and semiconductor structure
Technical Field
The application relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure and the semiconductor structure.
Background
In the prior art, the SOI (Silicon On Insulator) technology can realize dielectric isolation of components in an integrated circuit, and a parasitic latch-up effect in a bulk Silicon CMOS (Complementary Metal Oxide Semiconductor) circuit is eliminated by a substrate. In addition, the SOI technology in the prior art also has the advantages of small parasitic capacitance, high integration level, high speed, simple process, small short channel effect, low voltage, low power consumption, low leakage current, compatibility with the existing silicon process, and the like. FDSOI (Fully Depleted Silicon On Insulator) is an outstanding representative of the SOI system, and has a thin buried oxide layer (BOX) and a thin top Silicon layer, a small parasitic capacitance, a high speed, low power consumption and a strong radiation resistance. However, in the prior art, the SOI is limited by the intrinsic property of the top silicon material, the carrier mobility rate is low, and the performance of the transistor cannot be further improved. The sapphire substrate has the characteristics of large size and mature manufacturing process, has the advantages of high resistivity, low Radio Frequency (RF) loss, strong crosstalk inhibition capability, strong radiation resistance and the like, and is one of important research contents of the FDSOI technology.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, so as to solve the problem of low carrier mobility of the semiconductor structure in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of fabricating a semiconductor structure, including: providing a base, wherein the base comprises a sapphire substrate and a top silicon layer which are sequentially overlapped; forming a preliminary sacrificial layer on an exposed surface of the top silicon layer; sequentially carrying out ion implantation and annealing operations on the preliminary sacrificial layer and the top silicon layer, forming a silicide layer on the top silicon layer after the annealing operation, and forming a sacrificial layer on the preliminary sacrificial layer after the annealing operation; and removing the sacrificial layer.
Further, after removing the sacrificial layer, the method further comprises: planarizing the silicide layer.
Further, sequentially performing ion implantation and annealing operations on the preliminary sacrificial layer and the top silicon layer, including: implanting an ion beam into the preliminary sacrificial layer and the top silicon layer to form a doped preliminary sacrificial layer and a doped top silicon layer, the ion beam having an implantation energy in a range of (0 keV, 40keV)]In a dosage range of [1e 14 cm -2 ，1e 18 cm -2 ](ii) a And carrying out the annealing operation on the doped preparation sacrificial layer and the doped top silicon layer to obtain the sacrificial layer and the silicide layer.
Further, the ion beam is a germanium ion beam.
Further, the annealing operation includes one of: rapid thermal annealing and pulsed laser annealing.
Further, the thickness of the silicide layer after planarization ranges from 5nm to 20nm.
Further, the material of the preliminary sacrificial layer includes at least one of: silicon oxide and silicon nitride.
Further, the thickness of the top silicon layer ranges from 10nm to 30nm.
Further, after removing the sacrificial layer, the method further comprises: forming a transistor on a surface of the silicide layer remote from the sapphire substrate; and forming a back grid on the surface of the sapphire substrate far away from the silicide layer.
Further, forming a transistor on a surface of the silicide layer remote from the sapphire substrate, comprising: sequentially forming a preparation gate dielectric layer and a preparation gate metal layer on the surface of the silicide layer far away from the sapphire substrate; removing part of the preparation gate metal layer and part of the preparation gate dielectric layer, forming a gate dielectric layer on the rest of the preparation gate dielectric layer, forming a gate metal layer on the rest of the preparation gate metal layer, forming a gate electrode by the gate dielectric layer and the gate metal layer, and exposing the silicide layers on two sides of the gate electrode; and respectively forming a source electrode and a drain electrode on the exposed surfaces of the silicide layers on the two sides of the grid electrode to obtain the transistor.
According to another aspect of the present application, a semiconductor structure is provided, and the semiconductor structure is manufactured by using any one of the manufacturing methods of the semiconductor structure.
According to the technical scheme, in the manufacturing method of the semiconductor structure, firstly, a base is provided, and the base comprises a sapphire substrate and a top silicon layer which are sequentially overlapped; then, forming a preparation sacrificial layer on the exposed surface of the top silicon layer; then, sequentially carrying out ion implantation and annealing operation on the preliminary sacrificial layer and the top silicon layer, forming a silicide layer on the top silicon layer after the annealing operation, and forming a sacrificial layer on the preliminary sacrificial layer after the annealing operation; finally, the sacrificial layer is removed. According to the method, the preliminary sacrificial layer is formed on the substrate with the thin top silicon layer and the sapphire substrate, so that the lattice damage of subsequent ion injection to the formed silicide layer is reduced, the crystal quality of the silicide layer is improved, and the problem of low carrier migration rate of a semiconductor structure in the prior art is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 2 shows a schematic structural diagram of a substrate according to an embodiment of the present application;
FIG. 3 shows a schematic diagram of a semiconductor structure after formation of a preliminary sacrificial layer, in accordance with an embodiment of the present application;
FIG. 4 shows a schematic diagram of a semiconductor structure after forming a sacrificial layer, in accordance with embodiments of the present application;
FIG. 5 illustrates a schematic diagram of a semiconductor structure after forming a silicide layer, in accordance with an embodiment of the present application;
FIG. 6 shows a schematic diagram of a semiconductor structure after forming a preliminary gate metal layer, in accordance with embodiments of the present application;
FIG. 7 shows a schematic diagram of a semiconductor structure after forming a gate according to an embodiment of the present application;
FIG. 8 shows a schematic diagram of a semiconductor structure after forming a source and a drain according to an embodiment of the present application;
figure 9 shows a schematic diagram of a semiconductor structure after forming a back gate, in accordance with embodiments of the present application.
Wherein the figures include the following reference numerals:
101. a sapphire substrate; 102. a top silicon layer; 103. a silicide layer; 104. preparing a sacrificial layer; 105. a sacrificial layer; 106. preparing a gate dielectric layer; 107. preparing a gate metal layer; 108. a gate dielectric layer; 109. a gate metal layer; 110. a source electrode; 111. a drain electrode; 112. a back gate; 200. and a gate.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, the carrier mobility of the semiconductor structure in the prior art is low, and in order to solve the above problems, the present application proposes a method for manufacturing a semiconductor structure and a semiconductor structure.
According to an embodiment of the present application, a method of fabricating a semiconductor structure is provided.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, as shown in fig. 2, providing a base, wherein the base comprises a sapphire substrate 101 and a top silicon layer 102 which are sequentially stacked;
step S102, as shown in fig. 3, forming a preliminary sacrificial layer 104 on the exposed surface of the top silicon layer 102;
step S103, as shown in fig. 3 and 4, sequentially performing ion implantation and annealing operations on the preliminary sacrificial layer 104 and the top silicon layer 102, forming a silicide layer 103 on the top silicon layer 102 after the annealing operation, and forming a sacrificial layer 105 on the preliminary sacrificial layer 104 after the annealing operation;
in step S104, as shown in fig. 4 and 5, the sacrificial layer 105 is removed.
In the manufacturing method of the semiconductor structure, firstly, a base is provided, and the base comprises a sapphire substrate and a top silicon layer which are sequentially overlapped; then, forming a preliminary sacrificial layer on the exposed surface of the top silicon layer; then, sequentially carrying out ion implantation and annealing operations on the preliminary sacrificial layer and the top silicon layer, forming a silicide layer on the top silicon layer after the annealing operation, and forming a sacrificial layer on the preliminary sacrificial layer after the annealing operation; and finally, removing the sacrificial layer. According to the method, the preliminary sacrificial layer is formed on the substrate with the thin top silicon layer and the sapphire substrate, so that the lattice damage of subsequent ion injection to the formed silicide layer is reduced, the crystal quality of the silicide layer is improved, and the problem of low carrier migration rate of a semiconductor structure in the prior art is solved.
In order to prevent implantation damage or increase the strain of the silicide layer, in another embodiment of the present application, the material of the preliminary sacrificial layer at least includes one of the following: silicon oxide and silicon nitride.
In practical applications, the silicon oxide may be formed by thermal oxidation or epitaxial growth, and the silicon nitride may be formed by epitaxial growth. The preparation sacrificial layer can effectively protect the top silicon layer from directly colliding with injected ions, and lattice damage caused by ion injection is reduced, so that the reduction of crystal quality is avoided. In addition, the silicon nitride also has the effect of increasing the strain in the silicide layer, the thermal mismatch between the silicon nitride and the silicide layer is large, the strain is introduced in the natural cooling process after the annealing is finished, and the silicon nitride is used as the strain layer, so that the lattice constant of the silicide layer is changed, the relaxed silicide layer becomes the strained silicide layer, and the carrier mobility of the silicide layer is further improved.
Specifically, providing the above substrate includes: as shown in fig. 2, a sapphire substrate 101 is provided, and a top silicon layer 102 is formed on an exposed surface of the sapphire substrate 101, wherein the thickness of the top silicon layer is in a range from 10nm to 30nm in order to meet the size requirement of the integrated circuit semiconductor device.
Implanting ions into the sacrificial layer and the top silicon layer to form silicide, wherein the dosage of the ion beams has an influence on the crystal quality of the finally formed silicide layer, if the dosage is too low, the mobility of carriers is limited to be improved, and if the dosage is too high, the crystal quality is deteriorated and the mobility of the carriers is also influencedThe method comprises the following steps: implanting an ion beam into the preliminary sacrificial layer and the top silicon layer to form a doped preliminary sacrificial layer and a doped top silicon layer, wherein the ion beam has an implantation energy in a range of (0 keV, 40keV)]In a dosage range of [1e 14 cm -2 ，1e 18 cm -2 ](ii) a And performing the annealing operation on the doped preliminary sacrificial layer and the doped top silicon layer to obtain the sacrificial layer and the silicide layer. The content of implanted ions can be controlled by controlling the energy and the dosage of ion implantation, and the preparation process is simple.
In practical application, the carrier migration rate can also be improved by directly forming a thin silicide layer on the top silicon layer, but a certain lattice mismatch exists between the top silicon layer and the silicide layer, so that the quality of a heterogeneous interface is poor, the defects of forming the silicide layer are more, the performance of a semiconductor structure is limited, and the silicide layer is directly formed by injecting ions into silicon, so that the heterogeneous interface can be eliminated, the defects of the silicide layer are reduced, the crystal quality of the silicide layer is further improved, and the carrier migration rate is further improved.
In another embodiment of the present application, the ion beam is a germanium ion beam. The ion beam is germanium ion beam to form silicide layer of silicon germanium, and the silicon germanium channel material has the advantages of being capable of extending on the sapphire substrate, compatible with CMOS process, high in mobility and the like.
In order to activate the implanted ions and rearrange the unit cells, thereby further improving the crystal quality, in another embodiment of the present application, the annealing operation comprises one of the following: rapid thermal annealing and pulsed laser annealing.
In practical applications, the sacrificial layer may be removed by polishing (Grading), dry etching (Dry etch), or gas phase etching based on tetramethylammonium hydroxide.
In order to reduce the roughness of the surface of the silicide layer, make the surface smoother, and facilitate the subsequent processes, in another embodiment of the present application, after removing the sacrificial layer, the method further includes: the silicide layer is planarized.
In another embodiment of the present application, the thickness of the silicide layer after planarization is in a range of 5nm to 20nm. The silicon on the ultrathin insulator naturally limits the depth of a source-drain junction and also limits a depletion region of the source-drain junction, so that short channel effects such as drain induced barrier reduction and the like can be improved, and the sub-threshold characteristic of a device is improved.
Compared with a non-Fully Depleted device, the FDSiGeOI (Fully Depleted SiGe On Insulator) transistor device manufactured by the method has the advantages of higher working speed, smaller short channel effect, low voltage and power consumption, lower leakage current and extremely strong radiation resistance, can be widely applied to the fields of automobile electronics, IT network infrastructure, servers, consumer electronics, internet of things, radars, power supply batteries, wearable electronics, network machine learning, artificial intelligence, intelligent driving and the like, and has great scientific value and economic benefit.
In order to form a semiconductor device with high mobility, in another embodiment of the present application, after removing the sacrificial layer, the method further includes: as shown in fig. 8, a transistor is formed on a surface of the silicide layer 103 away from the sapphire substrate 101; as shown in fig. 9, a back gate 112 is formed on the surface of the sapphire substrate 101 remote from the silicide layer 103.
Specifically, the low germanium content FDSiGeOI technology inherits the advantages of small parasitic capacitance, high integration level, high working speed, simple process, low voltage, low power consumption, low leakage current and the like of the SOI technology, and is a very important silicon-based photoelectron substrate material. Therefore, IT is very important to realize a high-performance transistor on the low-germanium-content FDSiGeOI substrate, and related products can be widely applied to the fields of automobile electronics, IT network infrastructure, servers, consumer electronics, the Internet of things, radars, power supply batteries, wearable electronics, network machine learning, artificial intelligence, intelligent driving and the like, and have great scientific value and economic benefits.
In another embodiment of the present application, forming a transistor on a surface of the silicide layer away from the sapphire substrate includes: as shown in fig. 6, a preliminary gate dielectric layer 106 and a preliminary gate metal layer 107 are sequentially formed on the surface of the silicide layer 103 away from the sapphire substrate 101; as shown in fig. 6 and 7, removing a portion of the preliminary gate metal layer 107 and a portion of the preliminary gate dielectric layer 106, forming a gate dielectric layer 108 on the remaining preliminary gate dielectric layer 106, forming a gate metal layer 109 on the remaining preliminary gate metal layer 107, forming a gate 200 by the gate dielectric layer 108 and the gate metal layer 109, and exposing the silicide layers 103 on both sides of the gate 200; as shown in fig. 8, a source electrode 110 and a drain electrode 111 are formed on the exposed surface of the silicide layer 103 on both sides of the gate electrode 200, respectively, to obtain the transistor.
Specifically, the material of the gate dielectric layer may be a high-K dielectric, and the process for forming each structural layer of the present application may be any suitable process in the prior art, such as forming each structural layer by using one or more of an atomic layer deposition process, liquid phase epitaxy, molecular beam epitaxy, physical vapor deposition, and/or other well-known crystal growth processes. The transistor includes at least one of a planar transistor, a FinFet transistor, and a GAA transistor.
According to another aspect of the present application, a semiconductor structure is provided, which is manufactured by any one of the above methods for manufacturing a semiconductor structure.
The semiconductor structure is manufactured by any one of the manufacturing methods of the semiconductor structure, and the method reduces the lattice damage of subsequent ion injection to the formed silicide layer by forming the preliminary sacrificial layer on the substrate with the thin top silicon layer and the sapphire substrate, so that the crystal quality of the silicide layer is improved, and the problem of low carrier migration rate of the semiconductor structure in the prior art is solved.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described in detail below with reference to specific embodiments.
Examples
The method for manufacturing the semiconductor structure in the embodiment comprises the following steps:
first, a substrate is provided, as shown in fig. 2, a sapphire substrate 101 is provided, and a top silicon layer 102 is formed on an exposed surface of the sapphire substrate 101, wherein the thickness of the top silicon layer is in a range of 10nm to 30nm. The top silicon layer is thinner to meet the requirement of the semiconductor device in the manufacture of integrated circuit.
Thereafter, as shown in fig. 3, a preliminary sacrificial layer 104 is formed on a surface of the top silicon layer 102 away from the sapphire substrate 101. In order to prevent implantation damage or increase the strain of the silicide layer, the material of the preliminary sacrificial layer at least comprises one of the following materials: silicon oxide and silicon nitride. The silicon oxide may be formed by thermal oxidation or epitaxial growth, and the silicon nitride may be formed by epitaxial growth. The preparation sacrificial layer can effectively protect the top silicon layer from directly colliding with injected ions, and lattice damage caused by ion injection is reduced, so that the reduction of crystal quality is avoided. In addition, the silicon nitride also has the effect of increasing the strain in the silicide layer, the thermal mismatch between the silicon nitride and the silicide layer is large, the strain is introduced in the natural cooling process after the annealing is finished, and the silicon nitride is used as the strain layer, so that the lattice constant of the silicide layer is changed, the relaxed silicide layer becomes the strained silicide layer, and the carrier mobility of the silicide layer is further improved.
Thereafter, as shown in fig. 3 and 4, ion implantation and annealing operations are sequentially performed on the preliminary sacrificial layer 104 and the top silicon layer 102, the silicide layer 103 is formed on the top silicon layer 102 after the annealing operation, and the sacrificial layer 105 is formed on the preliminary sacrificial layer 104 after the annealing operation. Specifically, ion beams are implanted into the preliminary sacrificial layer and the top silicon layer to form a doped preliminary sacrificial layer and a doped top silicon layer, wherein the ion beams have implantation energy in a range of (0 keV, 40keV)]In a dosage range of [1e 14 cm -2 ，1e 18 cm -2 ]. Implanting ions in the sacrificial layer and the top silicon layer to form silicide, wherein the dosage of the ion beam has an influence on the crystal quality of the finally formed silicide layer, and if the dosage is over-dosedIf the amount of the dopant is too small, the mobility of the carrier is increased only to a limited extent, and if the amount of the dopant is too large, the crystal quality deteriorates and the mobility of the carrier is also affected. In order to activate the implanted ions and rearrange the unit cells, thereby further improving the crystal quality, the annealing operation comprises one of the following: rapid thermal annealing and pulsed laser annealing.
Thereafter, as shown in fig. 4 and 5, the sacrificial layer 105 is removed by polishing (Grading), dry etching (Dry etch), or gas phase etching based on tetramethylammonium hydroxide.
And then, flattening the silicide layer to reduce the roughness of the surface of the silicide layer, enabling the surface to be smoother and facilitating the subsequent process, wherein the thickness range of the flattened silicide layer is 5 nm-20 nm. The silicon on the ultrathin insulator naturally limits the depth of a source-drain junction and also limits a depletion region of the source-drain junction, so that short channel effects such as reduction of a drain induced barrier and the like can be improved, and the sub-threshold characteristic of a device is improved.
Finally, as shown in fig. 6, a preliminary gate dielectric layer 106 and a preliminary gate metal layer 107 are sequentially formed on the surface of the silicide layer 103 away from the sapphire substrate 101; as shown in fig. 6 and 7, removing a portion of the preliminary gate metal layer 107 and a portion of the preliminary gate dielectric layer 106, forming a gate dielectric layer 108 on the remaining preliminary gate dielectric layer 106, forming a gate metal layer 109 on the remaining preliminary gate metal layer 107, forming a gate 200 by the gate dielectric layer 108 and the gate metal layer 109, and exposing the silicide layers 103 on both sides of the gate 200; as shown in fig. 8, a source 110 and a drain 111 are formed on the exposed surface of the silicide layer 103 on both sides of the gate 200, respectively, to obtain the transistor; as shown in fig. 9, a back gate 112 is formed on a surface of the sapphire substrate 101 remote from the silicide layer 103.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:
1) In the manufacturing method of the semiconductor structure, firstly, a base is provided, wherein the base comprises a sapphire substrate and a top silicon layer which are sequentially overlapped; then, forming a preliminary sacrificial layer on the exposed surface of the top silicon layer; then, sequentially performing ion implantation and annealing operations on the preliminary sacrificial layer and the top silicon layer, wherein a silicide layer is formed on the top silicon layer after the annealing operation, and a sacrificial layer is formed on the preliminary sacrificial layer after the annealing operation; and finally, removing the sacrificial layer. According to the method, the preliminary sacrificial layer is formed on the substrate with the thin top silicon layer and the sapphire substrate, so that the lattice damage of subsequent ion injection to the formed silicide layer is reduced, the crystal quality of the silicide layer is improved, and the problem of low carrier migration rate of a semiconductor structure in the prior art is solved.
2) The semiconductor structure is manufactured by any one of the manufacturing methods of the semiconductor structure, and the method reduces the lattice damage of subsequent ion injection to the formed silicide layer by forming the preliminary sacrificial layer on the substrate with the thin top silicon layer and the sapphire substrate, so that the crystal quality of the silicide layer is improved, and the problem of low carrier migration rate of the semiconductor structure in the prior art is solved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (11)

1. A method for fabricating a semiconductor structure, comprising:
providing a base, wherein the base comprises a sapphire substrate and a top silicon layer which are sequentially overlapped;
forming a preliminary sacrificial layer on an exposed surface of the top silicon layer;
sequentially carrying out ion implantation and annealing operation on the preliminary sacrificial layer and the top silicon layer, forming a silicide layer on the top silicon layer after the annealing operation, and forming a sacrificial layer on the preliminary sacrificial layer after the annealing operation;
and removing the sacrificial layer.
2. The method of claim 1, wherein after removing the sacrificial layer, the method further comprises:
planarizing the silicide layer.
3. The method of claim 1, wherein sequentially performing ion implantation and annealing operations on the preliminary sacrificial layer and the top silicon layer comprises:
implanting an ion beam into the preliminary sacrificial layer and the top silicon layer to form a doped preliminary sacrificial layer and a doped top silicon layer, the ion beam having an implantation energy in a range of (0 keV, 40keV)]The dosage range is [1e14cm ] -2 ，1e18cm- 2 ]；
And carrying out the annealing operation on the doped preparation sacrificial layer and the doped top silicon layer to obtain the sacrificial layer and the silicide layer.
4. The method of claim 3, wherein the ion beam is a germanium ion beam.
5. The method of claim 3, wherein the annealing operation comprises one of: rapid thermal annealing and pulsed laser annealing.
6. The method of claim 2, wherein the silicide layer after planarization has a thickness in the range of 5nm to 20nm.
7. The method of any of claims 1 to 6, wherein the material of the preliminary sacrificial layer comprises at least one of: silicon oxide and silicon nitride.
8. The method of any of claims 1 to 6, wherein the top silicon layer has a thickness in the range of 10nm to 30nm.
9. The method of any of claims 1 to 6, wherein after removing the sacrificial layer, the method further comprises:
forming a transistor on a surface of the silicide layer remote from the sapphire substrate;
and forming a back grid on the surface of the sapphire substrate far away from the silicide layer.
10. The method of claim 9, wherein forming a transistor on a surface of the silicide layer remote from the sapphire substrate comprises:
sequentially forming a preparation gate dielectric layer and a preparation gate metal layer on the surface of the silicide layer far away from the sapphire substrate;
removing part of the preparation gate metal layer and part of the preparation gate dielectric layer, forming a gate dielectric layer on the rest of the preparation gate dielectric layer, forming a gate metal layer on the rest of the preparation gate metal layer, forming a gate electrode by the gate dielectric layer and the gate metal layer, and exposing the silicide layers on two sides of the gate electrode;
and respectively forming a source electrode and a drain electrode on the exposed surfaces of the silicide layers on the two sides of the grid electrode to obtain the transistor.
11. A semiconductor structure, wherein the semiconductor structure is manufactured by the method of any one of claims 1 to 9.
CN202211182953.5A 2022-09-27 2022-09-27 Manufacturing method of semiconductor structure and semiconductor structure Pending CN115527922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211182953.5A CN115527922A (en) 2022-09-27 2022-09-27 Manufacturing method of semiconductor structure and semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211182953.5A CN115527922A (en) 2022-09-27 2022-09-27 Manufacturing method of semiconductor structure and semiconductor structure

Publications (1)

Publication Number Publication Date
CN115527922A true CN115527922A (en) 2022-12-27

Family

ID=84700586

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211182953.5A Pending CN115527922A (en) 2022-09-27 2022-09-27 Manufacturing method of semiconductor structure and semiconductor structure

Country Status (1)

Country Link
CN (1) CN115527922A (en)

Similar Documents

Publication Publication Date Title
US7348225B2 (en) Structure and method of fabricating FINFET with buried channel
US6372559B1 (en) Method for self-aligned vertical double-gate MOSFET
EP1488462B1 (en) Strained fin fets structure and method
JP5041685B2 (en) Super steep retrograde well (SSRW) FET device and method of manufacturing the same
US6921982B2 (en) FET channel having a strained lattice structure along multiple surfaces
US6432754B1 (en) Double SOI device with recess etch and epitaxy
KR100597460B1 (en) Transistor of semiconductor device and fabricating method thereof
US20070235763A1 (en) Substrate band gap engineered multi-gate pMOS devices
WO2013095779A1 (en) Soi finfet with recessed merged fins and liner for enhanced stress coupling
EP2498280B1 (en) DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof
CN113161240B (en) Multi-metal heterogeneous gate dielectric anti-irradiation MOS field effect transistor and method based on 45nm technology
US20020090768A1 (en) Ground-plane device with back oxide topography
EP2477216A1 (en) Hybrid bulk/SOI device with a buried doped layer and manufacturing method thereof
CN112652664B (en) Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
CN115527922A (en) Manufacturing method of semiconductor structure and semiconductor structure
US20220076992A1 (en) Semiconductor structure for digital and radiofrequency applications
CN102751291B (en) A kind of mixing crystal face two strain silicon base CMOS integrated device and preparation method
CN115579322A (en) Method for manufacturing semiconductor device and semiconductor device
US20220076993A1 (en) Semiconductor structure for digital and radiofrequency applications, and method for manufacturing such a structure
CN102751289B (en) A kind of three strained-soi Si base BiCMOS integrated device and preparation methods based on crystal face selection
CN115527923A (en) Method for manufacturing semiconductor device and semiconductor device
CN102738162B (en) Mixed crystal face double polycrystal BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device based on self-aligning process and manufacturing method thereof
CN102820296B (en) A kind of two polycrystalline SOI BiCMOS integrated device based on crystal face selection and preparation method
CN102738166B (en) Mixed crystal face three-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and manufacturing method thereof
CN102723343B (en) Crystal plane-based Tri-polycrystal-plane Bi CMOS (Complentary Metal-Oxide-Semiconductor) integrated device and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination