CN115525485A - Hardware spin lock logic interval checking device supporting multiprocessor programming - Google Patents
Hardware spin lock logic interval checking device supporting multiprocessor programming Download PDFInfo
- Publication number
- CN115525485A CN115525485A CN202210058828.7A CN202210058828A CN115525485A CN 115525485 A CN115525485 A CN 115525485A CN 202210058828 A CN202210058828 A CN 202210058828A CN 115525485 A CN115525485 A CN 115525485A
- Authority
- CN
- China
- Prior art keywords
- logic
- control module
- information
- interval
- logic interval
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a hardware spin lock logic interval inspection device supporting multiprocessor programming, which comprises an interface control module and a logic control module, wherein the interface control module comprises a bus interface, n input message queues, n return message queues and a register control module, and the logic control module comprises a spin lock control module, a logic interval inspection control module, a logic interval information storage array and a spin queue. The n input message queues are respectively connected with n external microprocessors and used for receiving and storing input messages from the microprocessors, the spin lock control module is connected with the n input message queues, the register control module, the logic interval check control module, the spin queues and the n return message queues, and the register control module is connected with the bus interface. The invention reduces the software overhead in the solid state hard disk controller, including reducing the occupation of the on-chip cache resources of the node queue and the inter-core interaction queue maintained by the software, and improving the efficiency of interval inspection.
Description
Technical Field
The invention relates to the field of solid state disks, in particular to a hardware spin lock logic interval checking device supporting multiprocessor programming.
Background
The solid state hard disk controller is a large-scale complex system design, and realizes the signal transmission of a physical interface, the hardware functions of a microprocessor unit MCU, an internal interconnection bus and the like in a chip through a logic circuit; and the dispatching of each module in the chip is realized through firmware code programming, and the flow direction of data in each node of the chip is controlled. With the increasing requirements of functions and performance indexes of the solid state hard disk controller, the on-chip control unit mostly adopts a multi-core microprocessor architecture to improve the computing capacity of the solid state hard disk controller; meanwhile, in order to reduce the workload of the microprocessor and establish an asynchronous processing flow based on event response, a special hardware circuit is designed in the chip to complete specific software work.
In the software scheduling algorithm of the solid state hard disk controller, the software processing flow is generally divided into a data path and a control path for processing respectively. In the control path processing, firstly, commands to be executed by an upper computer are required to be acquired for classification, such as reading, writing and deleting operations; and then, the logic space covered by each command needs to be checked to ensure the execution sequence of each command, so that the situation that the command with the later time sequence is executed before the command with the earlier time sequence is avoided, and the processing flow is disordered. And finally, sequentially transmitting each command to a subsequent execution unit according to the checking result to perform the next processing. Therefore, when the software in the solid state disk controller is used to complete the logical interval check function, after analyzing the received upper computer instruction information and identifying the commands therein, the interval information in each command needs to be stored in a system cache, such as a DRAM in a chip. Each upper computer command occupies one interval information node, and a series of interval information chains are formed when the upper computer commands are increased. Every gap inode that joins the chain after a stroke needs to be checked against the information already present on the chain. With the increase of the length of the interval information chain, the uncertainty of the system delay is increased, and the performance fluctuation of the command processing process is caused.
With the development of hardware, the number of multi-core processors is increased, the conflict among the multiple cores is more severe, and the out-of-order competition cannot guarantee the order of event processing, so that the disorder of a system is easily caused.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a hardware spin lock logic interval checking device supporting multiprocessor programming, which reduces software scheduling work in a solid state hard disk controller, supports a multiprocessor architecture to guarantee the exclusivity of command execution, and can be used as a special hardware accelerator in the solid state hard disk controller.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a hardware spin lock logic interval checking device supporting multiprocessor programming comprises an interface control module and a logic control module, wherein the interface control module comprises a bus interface, n input message queues, n return message queues and a register control module;
the self-locking control module receives the input messages in the input message queues and determines whether to process the input messages or transmit the input messages into the spin queue according to whether the spin lock function is started or not; when processing a message, a spin lock control module determines a working mode according to a command operator in an input message, then a logic interval descriptor in the input message is input into a logic interval check control module, the logic interval check control module is connected with a logic interval information storage array, the logic interval information storage array is used for storing a logic interval, the logic interval check control module compares the logic interval in the input message with the logic interval stored in the logic interval information storage array to complete a corresponding working mode, and then an execution result is returned to a return message queue through the logic interval check module and the spin lock control module;
n is a positive integer.
Further, the input message comprises a command operator, a logic interval descriptor and a message identifier, wherein the command operator comprises four working modes of logic interval check, logic label application with spin and logic label deletion, the logic interval descriptor comprises a logic interval starting value and a logic interval offset value, and the message identifier is used for encoding the message to be processed and is used for generating and recycling the on-chip software management message command.
Furthermore, after the register control module enables the spin lock function of the spin lock module to be started, the spin lock control module firstly judges a locking identification position in an input message, if the locking identification position in the input message in a certain input message queue is set, messages of other input message queues enter the spin lock queue, and an unlocking identification position in the input message queue waiting for the locking identification position is set; the input message queue with the locking identification position is called a locking input message queue, the spin lock control module takes out input messages in the locking input message queue, then adds queue information and continues to transmit to the logic interval inspection control module, the logic interval inspection control module controls to carry out logic interval comparison, and returns information to the spin lock control module after the corresponding working mode is completed, and the spin lock control module analyzes the queue information in the spin lock control module and distributes the queue information to the corresponding return message queue.
Further, the logical interval check is used to check whether there is an overlap between the logical interval information in the input message and the logical interval information in the logical interval storage array, and the operation flow is as follows: the logic interval is placed in an input message, added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval or not is judged, then the judgment result is returned to the spin lock control module, the logic interval descriptor is distributed to a return message queue through a message identifier, and finally a return message is obtained by a microprocessor to obtain a logic interval check result.
Further, the logic tag application is used for adding the logic interval information in the input message to the logic interval information storage array, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval is judged, if the judgment result is that the logic interval descriptor is not overlapped, the logic interval information is added to the logic interval information storage array, a row and column position for storing newly added logic interval information is used as a logic label to be added to a return message, otherwise, the judgment result is directly returned to the spin lock control module, and the return message queue is distributed through a message identifier.
Further, the logic tag application with spin is used for adding the logic interval information in the input message to the logic interval information storage array, and if the interval judgment result is that the input message is overlapped, the input message is distributed to the spin queue for waiting, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval is judged, if the judgment result is that the logic interval descriptor is not overlapped, the logic interval information is added to the logic interval information storage array, a row and column position storing newly added logic interval information is used as a logic label to be added to a return message, if the judgment result is overlapped, the input information is distributed to the spin queue to wait for subsequent operation, then the judgment result is returned to the spin lock control module, and the input information is distributed to the return message queue through a message identifier.
Further, the logic tag deletion is used for recovering the logic tag and clearing the information at the corresponding position of the logic interval information storage array, and the operation flow is as follows: the method comprises the steps of placing a logic label in an input message, binding the logic label with row and column information of a logic interval information storage array, adding the logic label to an input message queue through a bus interface to wait for execution, acquiring the logic label from the input message queue by a spin lock control module, analyzing a row and column position corresponding to the logic interval information storage array according to the logic label, deleting information of the corresponding position, checking input information to be executed in the spin queue, returning a deletion result to the spin lock control module if the spin queue is empty, distributing the deletion result to a return message queue through a message identifier, sequentially taking out the information to be input in the spin queue if the spin queue is not empty, performing interval check from all column information of a starting row in the logic interval information storage array, judging whether the logic interval of the input information is overlapped with the stored logic interval or not, retransmitting the information to the spin queue if the judgment result of the information in the spin queue is overlapped, and adding the logic interval information in the input information to the logic interval information storage array and adding the newly added logic interval information as the row and column information to be returned to the logic interval information if the judgment result is not overlapped.
Further, the location of the logical space information storage array where no logical space information is stored is written with 0, and in the row-based parallel search, the minimum distance where the logical space information can be stored in the logical space information storage array is found by checking the value of 0 in the array.
The invention has the beneficial effects that: 1. the software overhead in the solid state hard disk controller is reduced, the occupation of on-chip cache resources of a node queue and an inter-core interaction queue maintained by software is reduced, the times of accessing on-chip cache are reduced, and the efficiency of interval inspection is obviously improved;
2. an asynchronous processing mechanism is added, and control path delay caused by synchronous operation of software is overcome;
3. a spin lock control and release mechanism is added, the method is suitable for a solid state disk controller architecture of a multiprocessor, and the locking problem needing to be considered during software programming under a multi-core architecture is reduced;
4. in the logic interval information storage array, parallel search based on rows is adopted, so that the interval checking efficiency is improved;
5. the logic label is bound with the row and column information of the logic interval information storage array, and the historical information corresponding to the logic label item can be deleted quickly. And during searching, the minimum distance capable of storing the logic interval information is found by checking the 0 value in the array, so that the checking rapidity is ensured.
Drawings
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
The embodiment discloses a hardware spin lock logic interval checking device supporting multiprocessor programming, wherein a logic interval refers to a group of continuous data operated by a solid state disk controller software algorithm, usually an LBA (Logical Block Address, logical Address Block), and the information consists of a start value and a length and is distributed to a solid state disk device end by an upper computer. The invention allows software to submit operation command to the checking device, set the operations of inserting interval, checking interval, deleting interval, etc. in the command, check if there is logic interval overlap with other interval already recorded in the checking device after receiving the command, and generate corresponding command return message according to the control bit in the command descriptor.
In the working state, the self-locking function can be opened or closed through the register control module of the device, and the resource access conflict under the multiprocessor structure is solved. With the development of hardware, the number of multi-core processors is increased, the conflict among the multiple cores is more and more severe, and the order of event processing cannot be guaranteed by unordered competition, which easily causes disorder of a system. A spinning queue is designed in the checking device and used for protecting context field information during process switching. When the spin lock function is open, the device can only be held by one microprocessor at most, if another microprocessor tries to obtain an already occupied spin lock, the thread will always perform a busy cycle-spin-wait for the lock to be available again, and if the lock is not imposed, the microprocessor requesting the lock can immediately obtain it and continue execution.
As shown in fig. 1, the inspection apparatus in this embodiment includes an interface control module and a logic control module, where the interface control module includes a bus interface, n input message queues, n return message queues, and a register control module, and the logic control module includes a spin lock control module, a logic interval inspection control module, a logic interval information storage array, and a spin queue.
The self-locking control module receives the input messages in the input message queues and determines whether to process the input messages or transmit the input messages into the spin queue according to whether the spin lock function is started or not; when processing information, the spin lock control module determines a working mode according to a command operator character in the input information, then inputs a logic interval descriptor in the input information into a logic interval check control module, the logic interval check control module is connected with a logic interval information storage array, the logic interval information storage array is used for storing logic intervals, the logic interval check control module compares the logic intervals in the input information with the logic intervals stored by the logic interval information storage array to complete a corresponding working mode, and then returns an execution result to a return information queue through the logic interval check module and the spin lock control module; n is a positive integer.
After the register control module enables the spin lock function of the spin lock module to be started, the spin lock control module firstly judges a locking identification position in an input message, if the locking identification position in the input message in a certain input message queue is set, messages of other input message queues enter the spin queue, and an unlocking identification position in the input message queue with the locking identification position is waited; the input message queue with the locking identification position is called a locking input message queue, the spin lock control module takes out input messages in the locking input message queue, then adds queue information and continues to transmit to the logic interval inspection control module, the logic interval inspection control module controls to carry out logic interval comparison, and returns information to the spin lock control module after the corresponding working mode is completed, and the spin lock control module analyzes the queue information in the spin lock control module and distributes the queue information to the corresponding return message queue.
The input message comprises a command operator, a logic interval descriptor and a message identifier, wherein the command operator comprises four working modes of logic interval check, logic label application with spin and logic label deletion, the logic interval descriptor comprises a logic interval starting value and a logic interval offset value, and the message identifier is used for coding the message to be processed and is used for generating and recovering the on-chip software management message command.
The logic interval check is used for checking whether the logic interval information in the input message and the logic interval information in the logic interval storage array have overlap, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input message is overlapped with the stored logic interval or not is judged, then a judgment result is returned to the spin lock control module, the judgment result is distributed to a return message queue through a message identifier, and finally a return message is obtained by a microprocessor to obtain a logic interval check result.
The logic label application is used for adding the logic interval information in the input message to the logic interval information storage array, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval is judged, if the judgment result is that the logic interval descriptor is not overlapped, the logic interval information is added to the logic interval information storage array, a row and column position for storing newly added logic interval information is used as a logic label to be added to a return message, otherwise, the judgment result is directly returned to the spin lock control module, and the return message queue is distributed through a message identifier.
The logic label with spin applies for adding the logic interval information in the input message to the logic interval information storage array, if the interval judgment result is overlapping, the input message is distributed to the spin queue for waiting, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval is judged, if the judgment result is that the logic interval descriptor is not overlapped, the logic interval information is added to the logic interval information storage array, a row and column position storing newly added logic interval information is used as a logic label to be added to a return message, if the judgment result is overlapped, the input information is distributed to the spin queue to wait for subsequent operation, then the judgment result is returned to the spin lock control module, and the input information is distributed to the return message queue through a message identifier.
The logic label deletion is used for recovering the logic label and clearing the information of the corresponding position of the logic interval information storage array, and the operation flow is as follows: the method comprises the steps of placing a logic label in an input message, binding the logic label with row and column information of a logic interval information storage array, adding the logic label to an input message queue through a bus interface to wait for execution, acquiring the logic label from the input message queue by a spin lock control module, analyzing a row and column position corresponding to the logic interval information storage array according to the logic label, deleting information of the corresponding position, checking input information to be executed in the spin queue, returning a deletion result to the spin lock control module if the spin queue is empty, distributing the deletion result to a return message queue through a message identifier, sequentially taking out the information to be input in the spin queue if the spin queue is not empty, performing interval check from all column information of a starting row in the logic interval information storage array, judging whether the logic interval of the input information is overlapped with the stored logic interval or not, retransmitting the information to the spin queue if the judgment result of the information in the spin queue is overlapped, and adding the logic interval information in the input information to the logic interval information storage array and adding the newly added logic interval information as the row and column information to be returned to the logic interval information if the judgment result is not overlapped.
In this embodiment, 0 is written in a location where the logical interval information storage array does not store the logical interval information, and in the parallel search based on the row, the minimum distance where the logical interval information can be stored in the logical interval information storage array is found by checking the value of 0 in the array.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (8)
1. A hardware spinlock logic interval check apparatus that supports multiprocessor programming, characterized by: the system comprises an interface control module and a logic control module, wherein the interface control module comprises a bus interface, n input message queues, n return message queues and a register control module, and the logic control module comprises a spin lock control module, a logic interval inspection control module, a logic interval information storage array and a spin queue;
the self-locking control module receives the input messages in the input message queues and determines whether to process the input messages or transmit the input messages into the spin queue according to whether the spin lock function is started or not; when processing information, the spin lock control module determines a working mode according to a command operator character in the input information, then inputs a logic interval descriptor in the input information into a logic interval check control module, the logic interval check control module is connected with a logic interval information storage array, the logic interval information storage array is used for storing logic intervals, the logic interval check control module compares the logic intervals in the input information with the logic intervals stored by the logic interval information storage array to complete a corresponding working mode, and then returns an execution result to a return information queue through the logic interval check module and the spin lock control module;
n is a positive integer.
2. The hardware spin lock logic interval check device that supports multiprocessor programming of claim 1, wherein: the input message comprises a command operator, a logic interval descriptor and a message identifier, wherein the command operator comprises four working modes of logic interval check, logic label application with spin and logic label deletion, the logic interval descriptor comprises a logic interval starting value and a logic interval offset value, and the message identifier is used for encoding the message to be processed and is used for generating and recycling the on-chip software management message command.
3. The hardware spin lock logic interval check device that supports multiprocessor programming of claim 2, wherein: after the register control module enables the spin lock function of the spin lock module to be started, the spin lock control module firstly judges a locking identification position in an input message, if the locking identification position in the input message in a certain input message queue is set, messages of other input message queues enter the spin queue, and an unlocking identification position in the input message queue with the locking identification position is waited; the input message queue with the locking identification position is called a locking input message queue, the spin lock control module takes out input messages in the locking input message queue, then adds queue information and continues to transmit to the logic interval inspection control module, the logic interval inspection control module controls to carry out logic interval comparison, and returns information to the spin lock control module after the corresponding working mode is completed, and the spin lock control module analyzes the queue information in the spin lock control module and distributes the queue information to the corresponding return message queue.
4. Hardware spin lock logic interval check device supporting multiprocessor programming according to claim 2 or 3, characterized in that: the logic interval check is used for checking whether the logic interval information in the input message and the logic interval information in the logic interval storage array have overlap, and the operation flow is as follows: the logic interval is placed in an input message, added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval or not is judged, then the judgment result is returned to the spin lock control module, the logic interval descriptor is distributed to a return message queue through a message identifier, and finally a return message is obtained by a microprocessor to obtain a logic interval check result.
5. Hardware spinlock logic interval check apparatus supporting multiprocessor programming according to claim 2 or 3, wherein: the logic label application is used for adding the logic interval information in the input message to the logic interval information storage array, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval is judged, if the judgment result is that the logic interval descriptor is not overlapped, the logic interval information is added to the logic interval information storage array, a row and column position for storing newly added logic interval information is used as a logic label to be added to a return message, otherwise, the judgment result is directly returned to the spin lock control module, and the return message queue is distributed through a message identifier.
6. Hardware spinlock logic interval check apparatus supporting multiprocessor programming according to claim 2 or 3, wherein: the logic label with spin applies for adding the logic interval information in the input message to the logic interval information storage array, if the interval judgment result is overlapping, the input message is distributed to the spin queue for waiting, and the operation flow is as follows: the logic interval is placed in an input message, the input message is added to an input message queue through a bus interface to wait for execution, a spin lock control module obtains a logic interval descriptor from the input message queue, then interval check is carried out on all column information of a starting row in a logic interval information storage array, whether the logic interval of the input information is overlapped with the stored logic interval is judged, if the judgment result is that the logic interval descriptor is not overlapped, the logic interval information is added to the logic interval information storage array, a row and column position storing newly added logic interval information is used as a logic label to be added to a return message, if the judgment result is overlapped, the input information is distributed to the spin queue to wait for subsequent operation, then the judgment result is returned to the spin lock control module, and the input information is distributed to the return message queue through a message identifier.
7. Hardware spin lock logic interval check device supporting multiprocessor programming according to claim 2 or 3, characterized in that: the logic label deletion is used for recovering the logic label and clearing the information of the corresponding position of the logic interval information storage array, and the operation flow is as follows: the method comprises the steps of placing a logic label in an input message, binding the logic label with row and column information of a logic interval information storage array, adding the logic label to an input message queue through a bus interface to wait for execution, acquiring the logic label from the input message queue by a spin lock control module, analyzing a row and column position corresponding to the logic interval information storage array according to the logic label, deleting information of the corresponding position, checking input information to be executed in the spin queue, returning a deletion result to the spin lock control module if the spin queue is empty, distributing the deletion result to a return message queue through a message identifier, sequentially taking out the information to be input in the spin queue if the spin queue is not empty, performing interval check from all column information of a starting row in the logic interval information storage array, judging whether the logic interval of the input information is overlapped with the stored logic interval or not, retransmitting the information to the spin queue if the judgment result of the information in the spin queue is overlapped, and adding the logic interval information in the input information to the logic interval information storage array and adding the newly added logic interval information as the row and column information to be returned to the logic interval information if the judgment result is not overlapped.
8. Hardware spin lock logic interval check device supporting multiprocessor programming according to claim 2 or 3, characterized in that: the location of the logical space information storage array where no logical space information is stored is written with 0, and in the row-based parallel search, the minimum distance at which the logical space information can be stored in the logical space information storage array is found by checking the value of 0 in the array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210058828.7A CN115525485A (en) | 2022-01-19 | 2022-01-19 | Hardware spin lock logic interval checking device supporting multiprocessor programming |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210058828.7A CN115525485A (en) | 2022-01-19 | 2022-01-19 | Hardware spin lock logic interval checking device supporting multiprocessor programming |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115525485A true CN115525485A (en) | 2022-12-27 |
Family
ID=84694843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210058828.7A Pending CN115525485A (en) | 2022-01-19 | 2022-01-19 | Hardware spin lock logic interval checking device supporting multiprocessor programming |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115525485A (en) |
-
2022
- 2022-01-19 CN CN202210058828.7A patent/CN115525485A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3566358A (en) | Integrated multi-computer system | |
| CN101452400B (en) | Method and system for processing transaction buffer overflow in multiprocessor system | |
| CN113918101B (en) | Method, system, equipment and storage medium for writing data cache | |
| US8423499B2 (en) | Search device and search method | |
| JPH07191944A (en) | System and method for prevention of deadlock in instruction to many resources by multiporcessor | |
| US11474712B2 (en) | Method, apparatus, device and storage medium for managing access request | |
| CN103399856A (en) | Explosive type data caching and processing system for SCADA system and method thereof | |
| US20220147404A1 (en) | Method And Apparatus For Accessing Critical Resource, Computer Device, And Readable Storage Medium | |
| CN101546275B (en) | Method for realizing multiprocessor system with hardware semaphore module | |
| CN101788922A (en) | Method and device for realizing transaction storage system based on auxiliary thread | |
| CN1510567A (en) | Method and apparatus for machine-processed loading locking instruction by recording board | |
| JPH07105126A (en) | System and method for interface | |
| CN109213423B (en) | Address barrier-based lock-free processing of concurrent IO commands | |
| CN112559210A (en) | Shared resource read-write mutual exclusion method based on RTX real-time system | |
| CN109656868B (en) | Memory data transfer method between CPU and GPU | |
| Peng et al. | FA-Stack: A fast array-based stack with wait-free progress guarantee | |
| CN116701246B (en) | Method, device, equipment and storage medium for improving cache bandwidth | |
| CN112948136A (en) | Method for implementing asynchronous log record of embedded operating system | |
| CN115525485A (en) | Hardware spin lock logic interval checking device supporting multiprocessor programming | |
| CN111198660A (en) | B + tree traversal method and device | |
| CN113282407B (en) | User layer asynchronous IO method and system based on persistent memory | |
| CN113377549B (en) | Queue data control method, system and queue data structure | |
| EP3923151A1 (en) | Write ordering in ssds | |
| CN115586943A (en) | Hardware marking implementation method for dirty pages of virtual machine of intelligent network card | |
| CN112433672B (en) | Solid state disk reading method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |