CN115525341A - Acceleration method of MD5 information abstract algorithm and instruction set processor - Google Patents
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- VUFOSBDICLTFMS-UHFFFAOYSA-M ethyl-hexadecyl-dimethylazanium;bromide Chemical compound [Br-].CCCCCCCCCCCCCCCC[N+](C)(C)CC VUFOSBDICLTFMS-UHFFFAOYSA-M 0.000 description 16
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Abstract
The invention relates to an acceleration method and an instruction set processor of an MD5 message digest algorithm, wherein the method is based on an MD5 round function iteration instruction, and the parallel acceleration of two unrelated MD5 message digest algorithms is realized by executing the MD5 round function iteration instruction through running water; the MD5 round function iteration instruction adopts a RISC framework and is used for executing any one time of message processing round function iteration in an MD5 message digest algorithm according to a source operand; the MD5 round function iteration instruction adopts an MD5 round function parallel algorithm, takes an intermediate iteration variable, a message word and a round iteration serial number in a 16-word message grouping processing process of two groups of irrelevant MD5 message digest algorithms as input, completes respective MD5 round function iteration of two groups of data in parallel, and outputs a result according to a specified form. The instruction set processor supports the MD5 round function iterative instruction pipeline execution.
Description
Technical Field
The invention relates to the technical field of processor design and information security, in particular to an acceleration method of an MD5 information abstract algorithm and an instruction set processor.
Background
With the increasing development of information technology, information security becomes more and more important. Cryptography and related technologies thereof are important guarantees of information security, and a Hash (Hash) cryptographic algorithm represented by an MD algorithm and a SHA algorithm is an important cryptographic algorithm, is widely applied to the technical field of information security, and how to efficiently implement the Hash (Hash) cryptographic algorithm has become one of the hot spots of research. The MD5 Message digest algorithm (MD 5 Message digest algorithm) is a typical Hash (Hash) cryptographic algorithm, the fifth version of MD algorithm (MD 5 for short), designed by Ronald Linn Rivest in 1992, and is specified in the RFC 1321 standard. The MD5 message digest algorithm may generate a 128-bit (16-byte) message digest Hash Value (Hash Value) for a message of arbitrary length. The MD5 message digest algorithm has the characteristics of good compressibility, fixed length, irreversibility, high discreteness, collision resistance and the like, and is widely applied to the fields of message integrity verification, digital signatures, network communication safety and the like.
The calculation process of the MD5 message digest algorithm comprises the following steps: bit stuffing (application Padding Bits), length stuffing (application Length), initializing Buffer (initialization MD Buffer), processing 16-word (512-bit) Message packet (Process Message in 16-WordBlocks) and outputting a 128-bit Message digest value (Output):
1) Bit stuffing refers to bit expansion of an input message M to make the length L of the stuffed message M (number of bits) satisfies L M mod 512=448, i.e. the length of the message is extended by a multiple of 512 minus 64, and bit padding is necessary even if the message length originally satisfies the condition. The bit filling process is to add 1 ' bit after the message M and then add several ' 0 ' bits to make the length of the filled message satisfy L M mod 512=448, the number of padding bits is at least 1 and at most 512.
2) The length padding means that a 64-bit number is used to indicate the length of a message before padding, and the 64 bits are added to the rear of a message in the previous step (after bit padding), if the length of the message before bit padding is more than 2 64 Then only its lower 64 bits are used. The length of the message obtained after bit filling and length filling is exactly a multiple of 512 bits and is also an integral multiple of 16 words (32-bit), so that M is j (j e {0,1,2, \8230; N-1 }) represents a word in the message after bit stuffing and length stuffing, where N is an integer multiple of 16.
3) The initialization buffer refers to the initialization assignment of 4 32-bit registers (a, B, C, D) for storing the intermediate iteration result of the MD5 message digest algorithm, and the initial values (stored with the low byte preceding the high byte succeeding) are the following hexadecimal values: a =01234567, b =89ab cd ef, c = fe dc ba 98, d =76543210.
4) The processing of a 16-word (512-bit) message packet is essentially a process of compressing a 16-word (512-bit) message packet by using a compression function, and the function is to compress a 16-word (512-bit) message packet into 4 32-bit working variables through 4 rounds of loop operations in sequence, wherein 1 to 4 rounds of loop operations respectively correspond to respective nonlinear round functions F (b, c, d) = (b) in sequence&c)|((～b)&d)、G(b,c,d)＝(b&d)|((～d)&c) H (b, c, d) = b ≦ c ≦ d, I (b, c, d) = c ≦ d), and the message word M is set by sequentially performing 16 iterative operations based on the respective nonlinear round functions for each round of loop, and then performing the iterative operations for each round of loop j For the jth (j e [0,15 ] in a 16-word (512-bit) message packet]) A 32-bit message word with an iteration constant T [ i ]]＝2 32 * abs (sin (i)), where i is in radians,<<<s denotes a loop left-shift by s bits, each message packet is first copied to (a, B, C, D) as it undergoes message processing, the iterative work variable (A, B, C, D) is FF (a, B, C, D, j, s, i) the iterative function of round 1 loop is a = B + ((a + F (B, C, D) + M) j +T[i])<<<s), wherein + represents modulo 2 32 The following 16 iterative operations are performed in sequence: FF (ABCD, 0,7, 1), FF (DABC, 1,12, 2), FF (CDAB, 2,17, 3), FF (BCDA, 3,22, 4), FF (ABCD, 4,7, 5), FF (DABC, 5,12, 6), FF (CDAB, 6,17, 7), FF (BCDA, 7,22, 8), FF (ABCD, 8,7, 9), FF (DABC, 9,12, 10), FF (CDAB, 10,17, 11), FF (BCDA, 11,22,12) FF (ABCD, 12,7, 13), FF (DABC, 13,12, 14), FF (CDAB, 14,17, 15), FF (BCDA, 15,22, 16), the iterative function of the 2 nd cycle is GG (a, b, c, d, j, s, i) a = b + ((a + G (b, c, d) + M) j +T[i])<<<s), the following 16 iteration operations are performed in sequence: GG (ABCD, 1,5, 17), GG (DABC, 6,9, 18), GG (CDAB, 11,14, 19), GG (BCDA, 0, 20), GG (ABCD, 5, 21), GG (DABC, 10,9, 22), GG (CDAB, 15,14, 23), GG (BCDA, 4,20, 24), GG (ABCD, 9,5, 25), GG (DABC, 14,9, 26), GG (CDAB, 3,14, 27), GG (BCDA, 8,20, 28), GG (ABCD, 13,5, 29), GG (DABC, 2,9, 30), GG (CDAB, 7,14, 31), GG (BCDA, 12,20, 32), the iterative function of cycle 3 is HH (a, b, c, d, j, s, i): a = b (+ (b, c, d) + M) + j +T[i])<<<s), the following 16 iteration operations are performed in sequence: HH (ABCD, 5,4, 33), HH (DABC, 8,11, 34), HH (CDAB, 11,16, 35), HH (BCDA, 14,23, 36), HH (ABCD, 1,4, 37), HH (DABC, 4,11, 38), HH (CDAB, 7,16, 39), HH (BCDA, 10,23, 40), HH (ABCD, 13,4, 41), HH (DABC, 0,11, 42), HH (CDAB, 3,16, 43), HH (BCDA, 6,23, 44), HH (ABCD, 9,4, 45), HH (DABC, 12,11, 46), HH (CDAB, 15,16, 47), HH (BCDA, 2,23, 48), the iteration function of the 4 th round cycle is II (a, b, c, d, j, s, I) ((a + I) (b, c, d) + (M +) j +T[i])<<<s), the following 16 iteration operations are performed in sequence: II (ABCD, 0,6, 49), II (DABC, 7,10, 50), II (CDAB, 14,15, 51), II (BCDA, 5,21, 52), II (ABCD, 12,6, 53), II (DABC, 3,10, 54), II (CDAB, 10,15, 55), II (BCDA, 1,21, 56), II (ABCD, 8,6, 57), II (DABC, 15,10, 58), II (CDAB, 6,15, 59), II (BCDA, 13,21, 60), II (ABCD, 4,6, 61), II (DABC, 11,10, 62), II (CDAB, 2,15, 63), II (BCDA, 9,21, 64) after completion of the above four cycle operations, and adding the initial values a, B, C and D of the execution result of the loop iteration operation as the initial values of the next packet data respectively until the MD5 round function iteration processing of all 16-word (512-bit) message packets is completed, and cascading and outputting the results A = A + a, B = B + B, C = C + C and D = D + D obtained by the last iteration to obtain 128-bit message digest values (A, B, C and D), wherein A is at the low byte end and D is at the high byte end.
The MD5 message digest algorithm can be implemented by software, but the operation complexity is high, and a large amount of computing resources are required to be occupied, particularly, as the message length increases, the time for executing the MD5 message digest algorithm to obtain a digest value also increases rapidly, and as the data volume increases and the application requirements increase, it is increasingly difficult to implement the MD5 message digest algorithm by software based on a general instruction to meet the actual application requirements. For this reason, hardware is required to further improve the performance of implementing the MD5 message digest algorithm. Currently, dedicated hardware such as an FPGA, an ASIC, and a GPU is usually adopted to accelerate the implementation of the MD5 message digest algorithm, which has the advantages of high acceleration efficiency, but high cost, design flexibility, universality, and expandability are not good. If the acceleration of the MD5 message digest algorithm can be realized by adopting an Instruction Set Architecture (ISA) expansion mode, the method can realize high-efficiency acceleration, has design flexibility and expandability, and can effectively improve the performance of the RSIC processor for realizing the MD5 message digest algorithm.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an acceleration method of an MD5 message digest algorithm and an instruction set processor, which can improve the execution speed of the MD5 message digest algorithm and simplify a software program.
The technical scheme adopted by the invention for solving the technical problem is as follows: the method comprises the steps of providing an acceleration method of an MD5 message digest algorithm, and based on an MD5 round function iteration instruction, executing the MD5 round function iteration instruction through running water to realize parallel acceleration of two data-irrelevant MD5 message digest algorithms; the MD5 round function iteration instruction adopts a RISC structure, adopts a fixed-length 32-bit format, has three 256-bit source operands and a 256-bit target operand, and is used for executing any one message processing round function iteration in an MD5 message digest algorithm according to the source operands; the MD5 round function iteration instruction adopts an MD5 round function parallel algorithm, the MD5 round function parallel algorithm is an algorithm which takes an intermediate iteration variable, a message word and a round iteration sequence number in a 16-word message grouping processing process of two groups of unrelated data MD5 message summary algorithms as input, completes respective MD5 round function iteration of the two groups of data in parallel and outputs an iteration result according to a specified form.
The parallel acceleration of the two unrelated data MD5 message digest algorithms by executing the MD5 round function iteration instruction through running water specifically comprises the following steps:
(1) Initial values of intermediate iteration variables of the MD5 message digest algorithm are set to { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 The format of {192' b0, W } is loaded into the register file, and the message words in the two data-independent messages that are bit-filled and length-filled are pressed 1,j ,W 0,j Is loaded into the register file, and the number of two data-uncorrelated wheel iterations is given by {192' b0, row 1 ,Row 0 -loading said register file with said form of a register file;
(2) With initial values of iteration variables in the register file { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 {192' b0, W in two data-independent messages 1,j ,W 0,j }, two data-uncorrelated wheel iteration numbers {192' b0, row 1 ,Row 0 Executing 1 st MD5 round function iteration instruction for source operand to generate MD5 intermediate iteration variable { C (1) 1 ,B (1) 1 ,A’ (1) 1 ,D (1) 1 ,C (1) 0 ,B (1) 0 ,A’ (1) 0 ,D (1) 0 }；
(3) Sequentially executing the next MD5 round function iteration instruction in a running water manner, and executing the execution result { C } of the previous MD5 round function iteration instruction each time (i-1) 1 ,B (i-1) 1 ,A’ (i-1) 1 ,D (i-1) 1 ,C (i-1) 0 ,B (i-1) 0 ,A’ (i-1) 0 ,D (i-1) 0 Updating to a source operand A of a next instruction, reading data in a register Vb and a register Vc of updated message words and iteration sequence numbers from a register file as a new source operand B and a new source operand C, completing 2-64 rounds of function iteration processing of 16 word message packets in an MD5 message abstract algorithm with irrelevant data, and finally obtaining an MD5 intermediate iteration variable { C (64) 1 ,B (64) 1 ,A’ (64) 1 ,D (64) 1 ,C (64) 0 ,B (64) 0 ,A’ (64) 0 ,D (64) 0 }；
(4) Respectively finishing the MD5 intermediate iteration variable summation in parallel to obtain the MD5 intermediate iteration variable { D 1 +D (64) 1 ,C 1 +C (64) 1 ,B 1 +B (64) 1 ,A 1 +A’ (64) 1 ,D 0 +D (64) 0 ，C 0 +C (64) 0 ,B 0 +B (64) 0 ,A 0 +A’ (64) 0 }；
(5) If the input message also comprises unprocessed 16-word message packets, taking the MD5 intermediate iteration variable obtained in the step (4) as an iteration initial value for processing the next 16-word message packet, and continuing to circularly execute the steps (2) - (4) until the last 16-word message packet in the message is processed to obtain an execution result { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 }；
(6) The execution result { D is processed 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 And outputting to finish the execution of the MD5 message digest algorithm of two groups of irrelevant data, and obtain the digest values of two groups of irrelevant messages.
The instruction format of the MD5 round function iteration instruction is MD5R Va, vb, vc, vd, and is used to indicate the operation of three source operands in 3 256-bit registers Va, vb, vc, and the result is stored in a 256-bit destination register Vd, and [ 31.
The MD5 round function iteration instruction specifically includes: intermediate iteration variable C of MD5 message digest algorithm that is not correlated according to the two sets of data from register Va 1 ,B 1 ,A 1 ,D 1 ,C 0 ,B 0 ,A 0 ,D 0 Two data-independent message words M from register Vb 1 ,M 0 The number of round iterations with no correlation between two data from the register Vc Row 1 ,Row 0 Executing any one time of MD5 message processing round function iteration of the MD5 message digest algorithm, finishing the MD5 round function iteration in the 16-word message grouping processing process of the MD5 message digest algorithm, and obtaining an execution result { C 1 ,B 1 ,A 1 ’,D 1 ,C 0 ,B 0 ,A 0 ’,D 0 Is stored in the destination register Vd, where Row 1 ,Row 0 Legal values are 1-64, for i equal to 0 and 1,A i The generation logic of' is: a' i ＝B i +(A i +Temp i +W i +TRow i )<<<SRow i Wherein "+" is modulo 2 32 The addition is carried out by adding the components,<<<indicating a left shift of the cycle, temp i Is a 32-bit intermediate variable with a round iteration number Row i Determining the selected round function when 0<Row i ＝<Temp at 16 hours i [31:0]＝F(B i ,C i ,D i ) When 16 is used<Row i ＝<Temp at 32 hours i [31:0]＝G(B i ,C i ,D i ) When 32 is present<Row i ＝<Temp at 48 hours i [31:0]＝H(B i ,C i ,D i ) When 48 is used<Row i ＝<Temp at 64 hours i [31:0]＝I(B i ,C i ,D i ) Wherein F, G, H, I are round functions, TRow, specified by the MD5 message digest algorithm i Is a 32-bit round iteration constant, TRow i Can be determined according to the MD5 round iteration number Row i Determination by table lookup, SRow i Is a 32-bit round iteration shift constant, SRow i Can be according to MD5 round iteration number Row i Determining by table lookup; (ii) aWhen any one time of MD5 message processing round function iteration of the MD5 message digest algorithm is executed, hardware logic is adopted to realize round function processing, table look-up operation and shift operation; the MD5 round function iteration instruction is executed once, so that any one MD5 round function iteration of two data-irrelevant MD5 message digest algorithms can be realized, and the MD5 round function iteration processing of 16-word message packets in the two data-irrelevant MD5 message digest algorithms can be realized by continuously executing the MD5 round function iteration instruction for 64 times.
When any one time of MD5 message processing wheel function iteration of the MD5 message digest algorithm is executed, a wheel function is adopted to obtain a temporary parameter based on an intermediate iteration variable and a wheel iteration serial number; obtaining a round iteration constant and a round iteration cyclic shift constant through table lookup based on the round iteration sequence number; and updating the intermediate iteration variable according to the temporary parameter, the message word, the intermediate iteration variable, the round iteration constant and the round iteration cyclic shift constant.
The technical scheme adopted by the invention for solving the technical problem is as follows: an instruction set processor is provided, comprising a register file and an MD5 round function iteration instruction execution unit, wherein the register file is used for storing a source operand A, a source operand B and a source operand C; the MD5 round function iteration instruction execution unit is configured to receive and execute an MD5 round function iteration instruction, and an input signal of the MD5 round function iteration instruction execution unit includes: a 256-bit source operand A, a 256-bit source operand B, and a 256-bit source operand C, the output signals being a 256-bit execution result { C 1 ,B 1 ,A 1 ’,D 1 ,C 0 ,B 0 ,A 0 ’,D 0 }; the MD5 round function iteration instruction execution unit realizes round function processing, table look-up operation and shift operation through hardware logic.
The MD5 round function iteration instruction execution unit comprises: the wheel function module is used for obtaining temporary parameters by adopting a wheel function based on the intermediate iteration variable and the wheel iteration serial number; the first table look-up module is used for obtaining a wheel iteration constant through table look-up based on the wheel iteration sequence number; the second table look-up module is used for obtaining a round iteration cyclic shift constant through table look-up based on the round iteration sequence number; and the logic operation module is used for performing logic operation according to the temporary parameter, the message word, the intermediate iteration variable, the round iteration constant and the round iteration cyclic shift constant so as to update the intermediate iteration variable.
The delay of the MD5 round function iterative instruction is 1 beat, and the output result of the MD5 round function iterative instruction execution unit can bypass the input end of the MD5 round function iterative instruction execution unit and is used as a source operand A of the next MD5 round function iterative instruction; the instruction set processor supports pipelined execution of the MD5 round function iterative instructions.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
the invention can realize the parallel processing of round functions of two unrelated data MD5 message digest algorithms; one VMD5R instruction can complete any iteration in the MD5 message digest algorithm, and the processing of 16-word (512-bit) message packets with the largest operand in the MD5 message digest algorithm can be completed by continuously executing the VMD5R instruction for multiple times, so that the execution speed of the MD5 message digest algorithm is well accelerated, the software program of the MD5 message digest algorithm is simplified, the algorithm writing is facilitated, and the storage overhead of the algorithm is reduced.
The invention adopts the pipeline technology to fully realize the parallel potential of 16 word (512 bit) message grouping processing in the MD5 message summarization algorithm, and can complete the round function iterative processing of a group of 16 word (512 bit) message grouping in two groups of unrelated MD5 message summarization algorithms by sequentially executing 64 VMD5R instructions in a pipeline way, thereby remarkably accelerating the execution speed of the MD5 message summarization algorithm.
The execution delay of the VMD5R instruction of the processor is 1 beat, the running water execution of the VMD5R instruction is supported, and the execution result of the previous VMD5R instruction in two continuous VMD5R instructions can be bypassed to the next VMD5R instruction to be used as an input operand. The processor adopts the internal operation realization steps of optimizing DM5 message grouping processing round function iteration, special hardware logic realization F/G/H/I round function processing, table look-up, shift operation in hardware logic realization algorithm and other methods to improve the execution speed; by adopting the processor, the round function iterative processing of a group of 16-word (512-bit) message groups in two groups of unrelated MD5 message summarization algorithms can be completed only by 64 beats at the shortest time, and the execution speed of the MD5 message summarization algorithm is remarkably accelerated.
The invention fully excavates and realizes the parallel potential of DM5 message packet processing round function iteration in the MD5 message digest algorithm, and effectively accelerates the execution of the MD5 message digest algorithm. The VMD5R instruction, the method and the execution unit for accelerating the MD5 message digest algorithm have the advantages of easy transplantation and good expansibility, are easy to integrate or connect to the RSIC processor in the execution process, and can be applied to the RSIC processor or a special crypto chip so as to improve the performance of executing the MD5 message digest algorithm.
Drawings
FIG. 1 is a block diagram of the execution process of a VMD5R instruction;
FIG. 2 is a flow chart of an MD5 round function parallel algorithm;
FIG. 3 is a flow diagram of an accelerated MD5 message digest algorithm;
FIG. 4 is a schematic diagram of an instruction format of a VMD5R instruction;
FIG. 5 is a block diagram of a processor accelerating the MD5 message digest algorithm;
fig. 6 is a structural diagram of a VMD5R instruction execution unit.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention can be made by those skilled in the art after reading the teaching of the present invention, and these equivalents also fall within the scope of the claims appended to the present application.
The MD5 message digest algorithm includes five steps of bit stuffing, length stuffing, buffer initialization, 16 word (512 bit) message packet processing, and outputting a 128 bit message digest value. The core of the algorithm is in the processing of 16-word (512-bit) message packets, and the process comprises 4 rounds (64 times) of loop iterations, and the iteration results and initial valuesSumming the outputs, each iteration requiring the execution of one of the non-linear round functions (F (b, c, d) or G (b, c, d) or H (b, c, d) or I (b, c, d) specified by the DM5 message digest algorithm, operating primarily as the logical AND, OR, NOT, XOR, modulo 2,4 32 Operations such as addition and cyclic shift; the result of each iteration is used as the input of the next iteration, so that the iterative computations of different times in the same MD5 message digest algorithm cannot be executed in parallel, the key of the accelerated MD5 message digest algorithm is to fully mine and realize the intrinsic parallelism of the MD5 message processing iteration function (FF/GG/HH/II) so as to shorten the time of each iteration, and simultaneously, the parallel execution of different MD5 message digest algorithms with irrelevant data is realized as far as possible.
The invention finds that the 16-word (512-bit) message grouping processing process in the MD5 message digest algorithm has acceleration potential, can fully realize the intrinsic parallelism of the MD5 message processing iterative function (FF/GG/HH/II) by adopting a special instruction, can shorten a key path by optimizing the implementation flow of the MD5 message processing iterative function (FF/GG/HH/II), thereby improving the execution speed, and can realize the purpose of simultaneously executing a plurality of unrelated data MD5 message processing iterative functions by parallel processing of a plurality of unrelated data MD5 algorithms based on the characteristic that a modern processor supports highly parallel data instructions, thereby realizing the acceleration of the MD5 message digest algorithm.
The embodiment of the invention relates to an acceleration method of an MD5 message summarization algorithm, which is based on an MD5 round function iteration instruction (VMD 5R instruction for short), and realizes the parallel acceleration of two data-irrelevant MD5 message summarization algorithms by executing the MD5 round function iteration instruction through running water.
The VMD5R instruction adopts a RISC architecture, adopts a fixed-length 32-bit format, has three 256-bit source operands and a 256-bit target operand as shown in FIG. 1, and can execute any one message processing round function iteration in an MD5 message digest algorithm according to the source operands; the VMD5R instruction adopts an MD5 round function parallel algorithm, as shown in FIG. 2, any one MD5 round function iteration in two groups of MD5 message summarization algorithms irrelevant to data can be completed in parallel at one time; the MD5 round function is parallelThe algorithm refers to an intermediate iteration variable { D) in the 16-word (512-bit) message grouping processing process of the MD5 message digest algorithm with two groups of irrelevant data 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 }, message word W 1,j ,W 0,j And the number of round iterations Row 1 ,Row 0 Using the data as input, completing respective MD5 round function iteration of two groups of data in parallel, and pressing the iteration result according to { C } 1 ,B 1 ,A’ 1 ,D 1 ,C 0 ,B 0 ,A’ 0 ,D 0 An algorithm of the form output.
The acceleration method of the MD5 message digest algorithm realizes parallel acceleration of message processing iteration processes of 16-word (512-bit) message packets of two data-independent MD5 message digest algorithms by executing VMD5R instructions in a running water mode, and as shown in FIG. 3, the specific steps are as follows:
1) Initial values of intermediate iteration variables of MD5 message digest algorithm are expressed as { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 The format of (where A) is loaded into a register file 1 ＝A 0 ＝67452301，B 1 ＝B 0 ＝efcd ab 89，C 1 ＝C 0 ＝98ba dc fe，D 1 ＝D 0 = 10325476), message word by {192' b0, w in two data-uncorrelated messages (16 word packets) bit-padded and length-padded 1,j ,W 0,j Pack into the register file, number of two data-uncorrelated wheel iterations in {192' b0 1 ,Row 0 The form of is loaded into the register file;
2) With initial values of iteration variables in the register file { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 {192' b0, W in two data-uncorrelated messages (16-word packets) 1,j ,W 0,j }, two data-uncorrelated wheel iteration numbers {192' b0, row 1 ,Row 0 Execute the 1 st VMD5R instruction for the source operand, generating the MD5 intermediate iteration variable { C } (1) 1 ,B (1) 1 ,A’ (1) 1 ,D (1) 1 ,C (1) 0 ,B (1) 0 ,A’ (1) 0 ,D (1) 0 }；
3) Continuing to execute 63 VMD5R instructions in sequence in a pipeline manner next to the step 2), and executing the execution result { C of the previous VMD5R instruction each time (i-1) 1 ,B (i-1) 1 ,A’ (i-1) 1 ,D (i-1) 1 ,C (i-1) 0 ,B (i-1) 0 ,A’ (i-1) 0 ,D (i-1) 0 Updating to a source operand A of a next instruction, reading data in source registers Vb and Vc after updating message words and iteration serial numbers from a register file as new operands B and C, completing 2-64 rounds of function iteration processing of 16-word (512-bit) message packets in an MD5 message summary algorithm with two unrelated data, and finally obtaining an MD5 intermediate iteration variable { C (64) 1 ,B (64) 1 ,A’ (64) 1 ,D (64) 1 ,C (64) 0 ,B (64) 0 ,A’ (64) 0 ,D (64) 0 }；
4) Respectively completing the MD5 intermediate iteration variable summation in parallel by adopting general instructions in a processor to obtain MD5 intermediate iteration variables { D } 1 +D (64) 1 ,C 1 +C (64) 1 ,B 1 +B (64) 1 ,A 1 +A’ (64) 1 ,D 0 +D (64) 0 ，C 0 +C (64) 0 ,B 0 +B (64) 0 ,A 0 +A’ (64) 0 }；
5) If the input message also comprises an unprocessed 16-word (512-bit) message packet, taking the MD5 intermediate iteration variable obtained in the step 4) as an iteration initial value of the next 16-word (512-bit) message packet processing, and continuing to circularly execute the steps 2), 3) and 4) until the last 16-word (512-bit) message packet in the message is processed to obtain an execution result { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 }；
6) The execution result { D) in the step 5) is processed 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 And outputting to finish the execution of the MD5 message digest algorithm of two groups of irrelevant data, and obtain the digest values of two groups of irrelevant messages.
In this embodiment, the instruction format of the MD5 round Function iterative instruction (MD 5R) is MD5R Va, vb, vc, vd, and is used to indicate the operation of three source operands in 3 256-bit source registers Va, vb and Vc, and the result is stored in a 256-bit destination register Vd, as shown in fig. 4, the [ 31.
The MD5 round function iteration instruction (MD 5R) is based on the intermediate iteration variable { C ] of the MD5 message digest algorithm of two sets (each set of 4-bit iteration variable words) of unrelated data from the source register Va 1 ,B 1 ,A 1 ,D 1 ,C 0 ,B 0 ,A 0 ,D 0 }, two data-independent message words from the source register Vb (lower 64 bits) { M } 1 ,M 0 The number of wheel iterations { Row } which are uncorrelated with the two data from the source register Vc (lower 64 bits) 1 ,Row 0 }，Row 1 ,Row 0 Legally taking the value of 1-64, executing any one time of MD5 message processing round function iteration of the MD5 message digest algorithm, completing the MD5 round function iteration in the 16-word (512-bit) message grouping processing process of the MD5 message digest algorithm, and obtaining an execution result { C } 1 ,B 1 ,A 1 ,D 1 ,C 0 ,B 0 ,A 0 ,D 0 Store in the destination registerVd. The operation executed by the MD5 round function iteration instruction (MD 5R) is to obtain a temporary parameter by adopting a round function based on an intermediate iteration variable and a round iteration sequence number; obtaining a round iteration constant and a round iteration cyclic shift constant through table look-up based on the round iteration sequence number; and updating the intermediate iteration variable according to the temporary parameter, the message word, the intermediate iteration variable, the round iteration constant and the round iteration cyclic shift constant. The method comprises the following specific steps:
wherein, F _ MD5RLUTT (Row) i ) Function is used for determining the number Row of MD5 round iterations i Determining 1 32-bit round iteration constant TRow in processing 16-word (512-bit) message packet in MD5 message digest algorithm i The specific values are shown in Table 1, wherein Row i Data are all decimal, TRow i The data are 16-system numbers.
TABLE 1F _ MD5RLUTT (Row) in the MD5 round function iteration instruction (MD5R) i ) Function valuing
F_MD5RROT(Row i ) Function for calculating the number Row of iterations of MD5 i Determining iterative cyclic shift constants SRow in round in processing 16-word (512-bit) message packets in an MD5 message digest algorithm i Specific values are shown in table 2, where the data are decimal numbers.
TABLE 2F _ MD5RROT (Row) in MD5 round function iterator instruction (MD5R) i ) Function valuing
| Row i | TRow i | Row i | TRow i | Row i | TRow i | Row i | TRow i |
| 1 | 7 | 2 | 12 | 3 | 17 | 4 | 22 |
| 5 | 7 | 6 | 12 | 7 | 17 | 8 | 22 |
| 9 | 7 | 10 | 12 | 11 | 17 | 12 | 22 |
| 13 | 7 | 14 | 12 | 15 | 17 | 16 | 22 |
| 17 | 5 | 18 | 9 | 19 | 14 | 20 | 20 |
| 21 | 5 | 22 | 9 | 23 | 14 | 24 | 20 |
| 25 | 5 | 26 | 9 | 27 | 14 | 28 | 20 |
| 29 | 5 | 30 | 9 | 31 | 14 | 32 | 20 |
| 33 | 4 | 34 | 11 | 35 | 16 | 36 | 23 |
| 37 | 4 | 38 | 11 | 38 | 16 | 40 | 23 |
| 41 | 4 | 42 | 11 | 43 | 16 | 44 | 23 |
| 45 | 4 | 46 | 11 | 47 | 16 | 48 | 23 |
| 49 | 6 | 50 | 10 | 51 | 15 | 52 | 21 |
| 53 | 6 | 54 | 10 | 55 | 15 | 56 | 21 |
| 57 | 6 | 58 | 10 | 59 | 15 | 60 | 21 |
| 61 | 6 | 62 | 10 | 63 | 15 | 64 | 21 |
The MD5 round function iteration instruction (MD 5R) is executed once, so that any one MD5 round function iteration of two data-irrelevant MD5 message digest algorithms can be realized respectively, and the instruction is continuously executed for 64 times, so that the MD5 round function iteration processing of 16-word (512-bit) message packets in the two data-irrelevant MD5 message digest algorithms can be realized.
The embodiment of the invention relates to an instruction set processor, as shown in fig. 5, comprising an instruction unit, an instruction decoding unit, an instruction scheduling and transmitting unit, an instruction executing unit (comprising a VMD5R instruction executing unit), an instruction submitting ROB unit and a register file comprising 32 256-bit registers, wherein the VMD5R instruction executing unit is used for receiving and executing an MD5 round function iteration instruction (VMD 5R) and is used for executing any MD5 message processing round function iteration according to input information.
The VMD5R instruction execution unit provides a VMD5R instruction execution unit for the VMD5R instruction, the VMD5R instruction execution unit is used for receiving and executing the VMD5R instruction, and the input signals thereof comprise: a 256-bit source operand A (two sets of data-independent MD5 intermediate iteration variables { D) 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 Each group comprises 4 32-bit MD5 intermediate iteration variables, bypass data of a source register Va or a previous VMD5R instruction execution result in the register file, and a 256-bit source operand B (the lower 64 bits are respectively two data-irrelevant MDs5 message word of message digest algorithm W 1 ,W 0 From the register file) and a 256-bit source operand C (the lower 64 bits are the respective round iteration number of the two data-independent MD5 message digest algorithms Row) 1 ,Row 0 }), the output signal is a 256-bit execution result { C 1 ,B 1 ,A’ 1 ,D 1 ,C 0 ,B 0 ,A’ 0 ,D 0 And (5) writing back the register file, and determining whether to bypass the input end of the VMD5R instruction execution unit according to the information of the next instruction.
As shown in fig. 6, the MD5 round function iterative instruction execution unit includes: the wheel function module is used for obtaining temporary parameters by adopting a wheel function based on the intermediate iteration variables and the wheel iteration serial numbers; the first table look-up module is used for obtaining a round iteration constant through table look-up based on the round iteration serial number; the second table look-up module is used for obtaining a round iteration cyclic shift constant through table look-up based on the round iteration serial number; and the logic operation module is used for performing logic operation according to the temporary parameter, the message word, the intermediate iteration variable, the round iteration constant and the round iteration cyclic shift constant so as to update the intermediate iteration variable. The round function module, the first table look-up module, the second table look-up module and the logic operation module are all realized by hardware logic, and the operation steps of the DM5 message processing round function iteration are optimized, so that the execution speed is improved.
The execution delay of the VMD5R instruction in the processor is 1 beat (the beat division of the VMD5R instruction can be adjusted according to the working frequency of a specific processor (processor core)), and the output result of the VMD5R instruction execution unit can be used as a source operand A of the next VMD5R instruction at the input end of the VMD5R instruction execution unit in a bypass way; the minimum time only needs 64 beats to complete the round function iterative processing of 16-word (512-bit) message packets in 2 groups of independent MD5 message digest algorithms. The present invention may be used with various types of processors (processor cores) or special purpose cryptographic chips, including, for example, various general purpose or special purpose RSIC processors (processor cores), special purpose cryptographic chips, or other processors (processor cores).
Claims (8)
1. The acceleration method of the MD5 information abstract algorithm is characterized in that based on an MD5 round function iteration instruction, the MD5 round function iteration instruction is executed through running water to realize parallel acceleration of two data-irrelevant MD5 information abstract algorithms; the MD5 round function iteration instruction adopts a RISC architecture, adopts a fixed-length 32-bit format, has three 256-bit source operands and a 256-bit target operand, and is used for executing any one message processing round function iteration in an MD5 message digest algorithm according to the source operands; the MD5 round function iteration instruction adopts an MD5 round function parallel algorithm, the MD5 round function parallel algorithm is an algorithm which takes an intermediate iteration variable, a message word and a round iteration sequence number in a 16-word message grouping processing process of two groups of unrelated data MD5 message summary algorithms as input, completes respective MD5 round function iteration of the two groups of data in parallel and outputs an iteration result according to a specified form.
2. The method for accelerating the MD5 message digest algorithm according to claim 1, wherein said parallel acceleration of two MD5 message digest algorithms with unrelated data by pipelined execution of said MD5 round function iteration instructions specifically comprises the steps of:
(1) Initial values of intermediate iteration variables of the MD5 message digest algorithm are set to { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 The format of {192 } is packed into a register file, and the message words in the two data-independent messages that are bit-padded and length-padded are pressed by {192' b0 1,j ,W 0,j Is loaded into the register file, and the number of two data-uncorrelated wheel iterations is given by {192' b0, row 1 ,Row 0 -loading said register file with said form of a register file;
(2) With initial values of iteration variables in the register file { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 {192' b0, W in two data-independent messages 1,j ,W 0,j }, two data-uncorrelated wheel iteration numbers {192' b0, row 1 ,Row 0 Performing a fourth for the source operandGenerating MD5 intermediate iteration variable { C by 1 MD5 round function iteration instruction (1) 1 ,B (1) 1 ,A’ (1) 1 ,D (1) 1 ,C (1) 0 ,B (1) 0 ,A’ (1) 0 ,D (1) 0 }；
(3) Sequentially executing the next MD5 round function iteration instruction in a running water manner, and executing the execution result { C } of the previous MD5 round function iteration instruction each time (i-1) 1 ,B (i-1) 1 ,A’ (i-1) 1 ,D (i-1) 1 ,C (i-1) 0 ,B (i-1) 0 ,A’ (i-1) 0 ,D (i-1) 0 Updating to a source operand A of a next instruction, reading data in a register Vb and a register Vc of updated message words and iteration serial numbers from a register file as a new source operand B and a new source operand C, completing 2-64 rounds of function iterative processing of 16 word message packets in an MD5 message digest algorithm with two irrelevant data, and finally obtaining an MD5 intermediate iteration variable { C } (64) 1 ,B (64) 1 ,A’ (64) 1 ,D (64) 1 ,C (64) 0 ,B (64) 0 ,A’ (64) 0 ,D (64) 0 }；
(4) Respectively finishing MD5 intermediate iteration variable summation in parallel to obtain MD5 intermediate iteration variable { D } 1 +D (64) 1 ,C 1 +C (64) 1 ,B 1 +B (64) 1 ,A 1 +A’ (64) 1 ,D 0 +D (64) 0 ，C 0 +C (64) 0 ,B 0 +B (64) 0 ,A 0 +A’ (64) 0 }；
(5) If the input message also comprises an unprocessed 16-word message packet, taking the MD5 intermediate iteration variable obtained in the step (4) as an iteration initial value for processing the next 16-word message packet, and continuing to circularly execute the steps (2) - (4) until the last 16-word message packet in the message is processed to obtain an execution result { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 }；
(6) The execution result { D 1 ,C 1 ,B 1 ,A 1 ,D 0 ,C 0 ,B 0 ,A 0 And outputting to finish the execution of the MD5 message summarization algorithm of two groups of irrelevant data, and obtaining the summarization values of two groups of irrelevant messages.
3. The method for accelerating the MD5 message digest algorithm according to claim 1, wherein the instruction format of the MD5 round function iteration instruction is MD5 rva, vb, vc, vd, which is used to instruct the operation of three source operands in 3 256-bit registers Va, vb, vc, and the result is stored in a 256-bit destination register Vd, the [ 31.
4. The method for accelerating the MD5 message digest algorithm according to claim 1, wherein the MD5 round function iteration instruction specifically is: intermediate iteration variable C of MD5 message digest algorithm that is not correlated according to the two sets of data from register Va 1 ,B 1 ,A 1 ,D 1 ,C 0 ,B 0 ,A 0 ,D 0 Two data-independent message words M from register Vb 1 ,M 0 The number of round iterations with no correlation between two data from the register Vc Row 1 ,Row 0 Executing any one time of MD5 message processing round function iteration of the MD5 message digest algorithm to finish the MD5 round function in the 16-word message grouping processing process of the MD5 message digest algorithmIterate, and obtain the execution result { C 1 ,B 1 ,A 1 ’,D 1 ,C 0 ,B 0 ,A 0 ’,D 0 Is stored in a destination register Vd, where Row 1 ,Row 0 Legal values are 1-64, for i equal to 0 and 1,A i The generation logic of' is: a' i ＝B i +(A i +Temp i +W i +TRow i )<<<SRow i Wherein "+" is modulo 2 32 The addition is carried out by adding the components,<<<indicating a left shift in the cycle, temp i Is a 32-bit intermediate variable with a round iteration number Row i Determining the selected round function when 0<Row i ＝<Temp at 16 hours i [31:0]＝F(B i ,C i ,D i ) When 16 is used<Row i ＝<Temp at 32 hours i [31:0]＝G(B i ,C i ,D i ) When 32 is<Row i ＝<Temp at 48 hours i [31:0]＝H(B i ,C i ,D i ) When 48 is<Row i ＝<Temp 64 time i [31:0]＝I(B i ,C i ,D i ) Wherein F, G, H, I are round functions, TRow, specified by the MD5 message digest algorithm i Is a 32-bit round iteration constant, TRow i Can be according to MD5 round iteration number Row i Determination by table lookup, SRow i Is a 32-bit round-robin cyclic shift constant, SRow i Can be determined according to the MD5 round iteration number Row i Determining by table lookup; when any one time of MD5 message processing round function iteration of the MD5 message digest algorithm is executed, hardware logic is adopted to realize round function processing, table look-up operation and shift operation; the MD5 round function iteration instruction is executed once, so that any one MD5 round function iteration of two data-irrelevant MD5 message digest algorithms can be realized, and the MD5 round function iteration processing of 16-word message packets in the two data-irrelevant MD5 message digest algorithms can be realized by continuously executing the MD5 round function iteration instruction for 64 times.
5. The method for accelerating the MD5 message digest algorithm of claim 4, wherein when any one MD5 message processing round function iteration of the MD5 message digest algorithm is executed, a temporary parameter is obtained by adopting a round function based on an intermediate iteration variable and a round iteration sequence number; obtaining a round iteration constant and a round iteration cyclic shift constant through table lookup based on the round iteration sequence number; and updating the intermediate iteration variable according to the temporary parameter, the message word, the intermediate iteration variable, the round iteration constant and the round iteration cyclic shift constant.
6. An instruction set processor comprising a register file and an MD5 round function iterative instruction execution unit, the register file for holding a source operand a, a source operand B, and a source operand C; the MD5 round function iteration instruction execution unit is configured to receive and execute the MD5 round function iteration instruction, and an input signal of the MD5 round function iteration instruction execution unit includes: a 256-bit source operand A, a 256-bit source operand B, and a 256-bit source operand C, the output signals being a 256-bit execution result { C 1 ,B 1 ,A 1 ’,D 1 ,C 0 ,B 0 ,A 0 ’,D 0 }; the MD5 round function iteration instruction execution unit realizes round function processing, table look-up operation and shift operation through hardware logic.
7. The instruction set processor of claim 6 wherein the MD5 round function iterative instruction execution unit comprises: the wheel function module is used for obtaining temporary parameters by adopting a wheel function based on the intermediate iteration variables and the wheel iteration serial numbers; the first table look-up module is used for obtaining a round iteration constant through table look-up based on the round iteration serial number; the second table look-up module is used for obtaining a round iteration cyclic shift constant through table look-up based on the round iteration serial number; and the logic operation module is used for performing logic operation according to the temporary parameter, the message word, the intermediate iteration variable, the round iteration constant and the round iteration cyclic shift constant so as to update the intermediate iteration variable.
8. The instruction set processor of claim 6, wherein the delay of the MD5 round function iterating instruction is 1 beat, and the output result of the MD5 round function iterating instruction executing unit can be bypassed to the input end of the MD5 round function iterating instruction executing unit and used as the source operand a of the next MD5 round function iterating instruction; the instruction set processor supports pipelined execution of the MD5 round function iteration instructions.
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