CN115514370A

CN115514370A - Calibration algorithm for generating low spurious signals based on high-speed DAC circuit

Info

Publication number: CN115514370A
Application number: CN202211183579.0A
Authority: CN
Inventors: 靖安; 邵合理
Original assignee: Nanjing Farad Technology Co ltd
Current assignee: Nanjing Farad Technology Co ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2022-12-23

Abstract

The invention relates to the technical field of measurement of radar communication countermeasure instruments, in particular to a calibration algorithm for generating low spurious signals based on a high-speed DAC circuit, which comprises a DAC circuit 1 and a DAC circuit 2, wherein both the DAC circuit 1 and the DAC circuit 2 provide clock signals through a clock reference circuit, baseband signals are generated through the control of a DDS (digital synthesis display) in an FPGA (field programmable gate array) unit circuit, the DAC circuit 1 is a main output signal, the DAC circuit 2 is a cancellation circuit for calibration, the DAC circuit 2 generates a frequency signal with the same amplitude as that of the DAC circuit 1, and the frequency signal with the opposite phase and the signal of the DAC circuit 1 perform the cancellation of the main signal through a combiner, so that useful signals and spurious signals entering an ADC (analog-to-digital converter) receiving unit can meet the spurious-free dynamic requirement of the ADC and are unsaturated; the invention improves the suppression degree of the spurious signals, further optimizes the circuit and the algorithm, and can improve the clutter suppression of 20 dBc.

Description

Calibration algorithm for generating low spurious signals based on high-speed DAC circuit

Technical Field

The invention relates to the technical field of measurement of radar communication countermeasure instruments, in particular to a calibration algorithm based on low spurious signals generated by a high-speed DAC circuit, which adopts an optimization circuit for outputting clutter suppression by a high-speed DAC baseband signal and a calibration algorithm.

Background

In the fields of radar, communication, aerospace and the like, the application of high-speed digital baseband signals is very wide, and the performance indexes of the baseband signals directly influence the signal quality of the radar and the communication system. The high-speed DAC baseband signal is generated based on the DDS of waveform storage, the direct digital frequency synthesizer technology is adopted, and the signal has the outstanding advantages of short frequency conversion time, high frequency resolution, continuous output phase, high stability, programmability, full digitalization, easiness in integration and the like.

DDS is a digital frequency synthesis technique that directly synthesizes the desired waveform starting from the concept of phase. The working process is that under the control of clock pulse, the frequency control data and the accumulated phase data output by the accumulation register are added by the adder, and the added result is sent to the input end of the accumulation register. The accumulation register feeds back new phase data generated after the action of the previous clock cycle to the input end of the adder to enable the adder to continue to add with the frequency control data under the action of the next clock, and on the other hand, the value is used as a sampling address value to be sent into a waveform memory of the amplitude/phase conversion circuit, and the amplitude/phase conversion circuit outputs corresponding waveform data according to the address value. And finally converting the waveform data into a required analog waveform through a DAC and a low-pass filter. The phase accumulator performs linear phase accumulation under the action of a reference clock, and overflow is generated once when the phase accumulator is full, so that a period is completed, and the period is the frequency period of the DDS signal.

Due to the inherent characteristics of the digital implementation of the DDS, the spectrum spur of the output signal is determined to be large, and the sources of the spur mainly comprise the following aspects:

1. phase truncation errors, as can be seen from the analysis of errors caused by phase truncation, the error sequence is a periodic sequence, so the frequency spectrum thereof is discrete, and the energy of these spurious components is concentrated on the limited discrete spectral lines, so that the specified spurious-free requirements cannot be met in the output frequency band of the entire DDS. If the destructible periodicity is ensured, the phase truncation error is changed into a random sequence, and the regular stray component can be changed into random phase noise, so that the stray caused by phase truncation is eliminated, and the purity of an output frequency spectrum is improved.

2. Amplitude quantization spurs, which are word length quantization effects due to the binary digital values of the voltage values of the waveform memory, appear as background spurs on the frequency spectrum of the output signal. Since the signal-to-noise ratio of amplitude quantization can be improved by increasing the number of quantization bits, the capacity of the waveform memory is generally increased as much as possible to suppress amplitude quantization errors.

3. DAC nonlinearity error, ideal DAC should be linear, but in practice the DAC is half-wave asymmetric, with the positive half-cycle approximating the ideal DAC, and the negative half-cycle deviating, half-wave asymmetry in the time domain introducing even-order spurs in the frequency domain, and the balanced structure eliminating the even-order component. In addition, the DAC generates transient glitches due to asymmetry of data transfer delay, asymmetry of logic inversion, and the like. The balanced DAC architecture effectively eliminates spurs, thereby reducing the overall stray energy.

4. The image frequency and the nonlinear spurious of fundamental wave and relevant harmonic wave that DAC signal output produced, this type of spurious has following characteristics:

A. changes with changes in the baseband frequency and the frequency value is related to the clock signal.

B. Stray is compared with the first two types of stray, the power level of the stray is higher, and a plurality of frequency points are arranged.

C. As the baseband frequency increases, the frequency points with larger stray increase and the signal-to-noise ratio deteriorates more.

The fourth type of spurs are caused by the characteristics of a DAC circuit chip, the amplitude-frequency characteristics of signals can hardly be changed by the digit and signal disturbance of a DAC, the suppression degree of the spurs can be greatly improved by the circuit and the algorithm, and the clutter suppression of 20dBc can be improved by the optimization circuit and the algorithm.

Disclosure of Invention

According to the technical problem, the invention improves the suppression degree of the spurious signals, further optimizes the circuit and the algorithm, and can improve the clutter suppression of 20dBc and the like.

In order to solve the above problems, the present invention provides the following technical solutions:

a calibration algorithm based on low spurious signals generated by a high-speed DAC circuit comprises that a DAC circuit 1 and a DAC circuit 2 both provide clock signals through a clock reference circuit, baseband signals are generated under the control of DDS in an FPGA unit circuit, the DAC circuit 1 is a main output signal, the DAC circuit 2 is a cancellation circuit for calibration, the DAC circuit 2 generates signals with the same amplitude as the DAC circuit 1, and frequency signals with opposite phases and the signals of the DAC circuit 1 are subjected to main signal cancellation through a combiner, so that useful signals and spurious signals entering an ADC receiving unit can meet the spurious-free dynamic requirements of an ADC and are not saturated.

Further, a calibration algorithm for generating low spurious signals based on a high-speed DAC circuit includes the following steps:

step 1, according to a formula: RFA = | n LO1 +/-m RFout1|, calculate mirror image and mix spurious point frequency;

meaning of formula: LO1 is a clock signal of the DAC circuit 1, RFout1 is a baseband signal of the DAC circuit 1, and RFA is a calculated spurious point;

step 2, two RFout1 signals are generated through the DAC circuit 1 and the DAC circuit 2, the main signal is offset, the influence of a large signal on the detection capability of the stray signal is eliminated, and the ADC is convenient to detect the stray signal;

step 3, detecting the amplitude and phase information of each calculation frequency point through the ADC receiving unit 6, and controlling the DAC circuit 11 to respectively generate signals with the same frequency and amplitude as the spurious signals and opposite phases through a plurality of DDS modules in the FPGA unit circuit 5 so as to offset the spurious signals in the DAC circuit 11, thereby improving the clutter suppression degree of the signals;

and 4, switching the calibrated signal to a high-frequency signal output interface through a switch unit, and optimizing the clutter suppression of the high-frequency signal output by the high-frequency signal output interface by more than 20 dBc.

Compared with the prior art, the calibration algorithm based on the low spurious signal generated by the high-speed DAC circuit has the following beneficial effects:

1. the invention provides a calibration algorithm based on low spurious signals generated by a high-speed DAC circuit, wherein a clock reference circuit provides high-index clock signals for a DAC circuit 1, a DAC circuit 2, an ADC receiving unit and an FPGA unit circuit, a DAC circuit 1 unit module generates signal output required by a system, and a DAC circuit 2 unit module is applied to circuit calibration; the spurious signals such as the image frequency of non-harmonic components and related harmonics in the DAC circuit cause that the spurious signals of the DAC circuit frequency output signals are large, the spurious suppression of the conventional signal output is only about 60dBc, the spurious suppression index can be improved to be better than 80dBc through the calibration algorithm, and the overall spurious suppression index is improved by more than 20 dBc.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of a calibration algorithm for generating low spurious signals based on a high-speed DAC circuit according to the present invention.

The reference numbers in the figures: 1-a DAC circuit 1; a 2-DAC circuit 2; 3-a switching unit; 4-a combiner; 5-FPGA unit circuit; 6-ADC receiving unit; 7-high frequency signal output interface; a clock reference circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in FIG. 1, the calibration algorithm based on the low spurious signal generated by the high-speed DAC circuit comprises that a DAC circuit 11 and a DAC circuit 22 both provide clock signals through a clock reference circuit 8, baseband signals are generated through the control of a DDS in an FPGA unit circuit 5, the DDS circuit 1 is a main output signal, the DDS circuit 2 is a cancellation circuit for calibration, the DDS circuit 2 generates a frequency signal which is equal to the amplitude of the DAC circuit 1, the frequency signal with opposite phase and the signal of the DAC circuit 1 perform the cancellation of the main signal through a combiner 4, so that a useful signal and a spurious signal entering an ADC receiving unit 6 can meet the spurious-free dynamic requirement of an ADC, and the signals are not saturated.

A calibration algorithm for generating low spurious signals based on a high speed DAC circuit, comprising the steps of:

step 2, two RFout1 signals are generated through the DAC circuit 1 and the DAC circuit 2, main signals are offset, the influence of large signals on the detection capability of the stray signals is eliminated, and the ADC is convenient to detect the stray signals;

step 3, detecting the amplitude and phase information of each calculation frequency point through the ADC receiving unit 6, and controlling the DAC circuit 11 to respectively generate signals with the same frequency and amplitude as the spurious signals and opposite phases through a plurality of DDS modules in the FPGA unit circuit 5 so as to counteract the spurious signals in the DAC circuit 11, thereby improving the clutter suppression degree of the signals;

The clock reference circuit provides high-index clock signals for the DAC circuit 1, the DAC circuit 2, the ADC receiving unit and the FPGA unit circuit, a DAC circuit 1 unit module generates signal output required by a system, and a DAC circuit 2 unit module is used for circuit calibration; the spurious signals such as the image frequency of non-harmonic components and related harmonics in the DAC circuit cause that the spurious signals of the DAC circuit frequency output signals are large, the spurious suppression of the conventional signal output is only about 60dBc, the spurious suppression index can be improved to be better than 80dBc through the calibration algorithm, and the overall spurious suppression index is improved by more than 20 dBc.

The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solution of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the appended claims.

Claims

1. A calibration algorithm for generating low spurious signals based on a high-speed DAC circuit is characterized in that: the digital-to-analog converter comprises a DAC circuit 1 (1) and a DAC circuit 2 (2), wherein a clock reference circuit (8) provides clock signals, baseband signals are generated under the control of a DDS in an FPGA unit circuit (5), the DAC circuit 1 is a main output signal, the DAC circuit 2 is a cancellation circuit for calibration, the DAC circuit 2 generates signals which are equal to the DAC circuit 1 (1) in amplitude, and frequency signals with opposite phases and signals of the DAC circuit 1 (1) cancel the main signals through a combiner (4), so that useful signals and spurious signals entering an ADC receiving unit (6) can meet the spurious-free dynamic requirement of an ADC and are not saturated.

2. The algorithm of claim 1, wherein the algorithm comprises: the method comprises the following steps:

step 2, two RFout1 signals are generated through the DAC circuit 1 (1) and the DAC circuit 2 (2), the main signal is offset, the influence of a large signal on the stray signal detection capacity is eliminated, and the ADC is convenient to detect the stray signal;

step 3, detecting amplitude and phase information of each calculation frequency point through an ADC receiving unit (6), and controlling the DAC circuit 1 (1) to respectively generate signals with the same frequency and amplitude as the stray signals and opposite phases through a plurality of DDS modules in an FPGA unit circuit (5) so as to offset the stray signals in the DAC circuit 1 (1), thereby improving the clutter suppression degree of the signals;

and 4, switching the calibrated signal to a high-frequency signal output interface (7) through a switch unit (3), wherein clutter suppression of the high-frequency signal output by the high-frequency signal output interface (7) is optimized to be more than 20 dBc.