CN115514330A

CN115514330A - Amplifier circuit

Info

Publication number: CN115514330A
Application number: CN202211167622.4A
Authority: CN
Inventors: 白玮; 于翔
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2022-12-23

Abstract

An embodiment of the present disclosure provides an amplifier circuit, including: the first to fourth choppers, the first and second amplifying circuits, the low-pass filter circuit, and the ripple suppression circuit. The first chopper modulates the frequency of the input differential signal to a second frequency. The first amplification circuit amplifies an input differential signal to generate a first amplified differential signal. The second chopper modulates a frequency of the first amplified differential signal to a first frequency and modulates a frequency of the offset voltage to a second frequency. The second amplification circuit amplifies the first amplified differential signal to generate a second amplified differential signal. The third chopper negatively feeds back the second amplified differential signal to the first amplifying circuit. The fourth chopper modulates the frequency of the second amplified differential signal to a first frequency and modulates the frequency of the offset voltage to a second frequency. The low pass filter circuit low pass filters the second amplified differential signal and the offset voltage to generate an output differential signal. The ripple suppression circuit eliminates the offset voltage of the first amplification circuit.

Description

Amplifier circuit

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to amplifier circuits.

Background

For most sensor detection applications, the output signal amplitude is small, the signal frequency is low, and the useful signal is usually superimposed on a high common mode input voltage. In order to amplify the useful signal accurately, a special instrumentation amplifier is required. There are two common instrumentation amplifier configurations, the first being an instrumentation amplifier in a voltage feedback configuration, i.e., an amplifier consisting of a resistor and an operational amplifier. The disadvantage of this structure is that the offset voltage caused by the mismatch of the resistors is difficult to cancel, resulting in poor Common Mode Rejection Ratio (CMRR) characteristics. The second structure is a current feedback type instrumentation amplifier, which converts an input voltage and a feedback voltage into a current through a transconductance stage amplifier, and cancels the two by using negative feedback to determine a gain. This structure can achieve a very high CMRR, but has the disadvantage that the linearity is limited by the transconductance of the input stage, and the maximum allowable input differential voltage is typically several tens of millivolts.

To improve the CMRR of an instrumentation amplifier of voltage feedback architecture, it is generally necessary to reduce the mismatch of the resistances by trimming (trim) its gain resistance. But this increases the design complexity and has limited improvement in CMRR. However, for the current feedback type instrumentation amplifier, in order to improve the linear input range thereof, only the current of the input stage can be increased, which undoubtedly increases the power consumption of the circuit, and the improved linear input range is limited.

Disclosure of Invention

Embodiments described herein provide an amplifier circuit.

According to a first aspect of the present disclosure, an amplifier circuit is provided. The amplifier circuit includes: the chopper circuit includes first to fourth choppers, a first amplification circuit, a second amplification circuit, a low-pass filter circuit, and a ripple suppression circuit. Wherein the first chopper is configured to modulate a frequency of the input differential signal having the first frequency to a second frequency. The first amplification circuit is configured to amplify the input differential signal modulated by the first chopper to generate a first amplified differential signal. The second chopper is configured to modulate a frequency of the first amplified differential signal to a first frequency and modulate a frequency of the offset voltage of the first amplification circuit to a second frequency. The second amplification circuit is configured to amplify the first amplified differential signal modulated by the second chopper to generate a second amplified differential signal. The third chopper is configured to modulate a frequency of the second amplified differential signal to a second frequency, modulate a frequency of the offset voltage modulated by the second chopper to a first frequency, and negatively feed back the second amplified differential signal modulated by the third chopper to the first amplification circuit. The fourth chopper is configured to modulate the frequency of the second amplified differential signal modulated by the third chopper to a first frequency, and modulate the frequency of the offset voltage modulated by the third chopper to a second frequency. The low-pass filtering circuit is configured to low-pass filter the second amplified differential signal modulated by the fourth chopper and the offset voltage to generate an output differential signal. The ripple suppression circuit is configured to obtain a ripple component in the output differential signal, generate a feedback current according to the ripple component, and negatively feed back the feedback current to the two input terminals of the second chopper to eliminate an offset voltage of the first amplification circuit. Wherein the second frequency is higher than the first frequency.

In some embodiments of the present disclosure, the first amplification circuit comprises: first to fourth capacitors, a first resistor, a second resistor, and a first operational amplifier. The first end of the first capacitor is coupled to the first output end of the first chopper. The second end of the first capacitor is coupled to the first end of the first resistor, the first input end of the first operational amplifier and the first end of the third capacitor. The first end of the second capacitor is coupled to the second output end of the first chopper. The second terminal of the second capacitor is coupled to the first terminal of the second resistor, the second input terminal of the first operational amplifier, and the first terminal of the fourth capacitor. The second end of the first resistor is coupled to the common mode voltage input end. The second end of the second resistor is coupled to the common mode voltage input end. The first output end of the first operational amplifier is coupled with the first input end of the second chopper. The second output end of the first operational amplifier is coupled with the second input end of the second chopper. The second terminal of the third capacitor is coupled to the second output terminal of the third chopper. The second terminal of the fourth capacitor is coupled to the first output terminal of the third chopper.

In some embodiments of the present disclosure, the resistance values of the first and second resistors are on the order of hundreds of megaohms or more.

In some embodiments of the present disclosure, the second amplification circuit includes: a second operational amplifier, a fifth capacitor, and a sixth capacitor. The first input end of the second operational amplifier is coupled with the first output end of the second chopper and the first end of the fifth capacitor. The second input terminal of the second operational amplifier is coupled to the second output terminal of the second chopper and the first terminal of the sixth capacitor. The first output end of the second operational amplifier is coupled with the first input end of the third chopper and the second end of the fifth capacitor. The second output terminal of the second operational amplifier is coupled to the second input terminal of the third chopper and the second terminal of the sixth capacitor.

In some embodiments of the present disclosure, the low pass filter circuit includes: a third resistor, a fourth resistor, and a seventh capacitor. Wherein the first end of the third resistor is coupled to the first output end of the fourth chopper. A second terminal of the third resistor is coupled to a first terminal of the seventh capacitor and to the first differential signal output terminal of the amplifier circuit. The first end of the fourth resistor is coupled to the second output end of the fourth chopper. A second end of the fourth resistor is coupled to a second end of the seventh capacitor and to the second differential signal output of the amplifier circuit.

In some embodiments of the present disclosure, a ripple suppression circuit includes: the device comprises a ripple acquiring circuit, a fifth chopper, an integrating circuit and a voltage-current converting circuit. Wherein the ripple obtaining circuit is configured to allow only a ripple voltage in the output differential signal to pass through, and obtain a ripple current according to the ripple voltage. The fifth chopper is configured to modulate the frequency of the ripple current to a first frequency. The integrating circuit is configured to integrate the ripple current modulated by the fifth chopper to generate a feedback voltage. The voltage-to-current conversion circuit is configured to convert the feedback voltage into a feedback current.

In some embodiments of the present disclosure, the ripple acquisition circuit includes: an eighth capacitor, and a ninth capacitor. The first end of the eighth capacitor is coupled to the first differential signal output end of the amplifier circuit. A second terminal of the eighth capacitor is coupled to the first input terminal of the fifth chopper. The first terminal of the ninth capacitor is coupled to the second differential signal output terminal of the amplifier circuit. A second terminal of the ninth capacitor is coupled to the second input terminal of the fifth chopper.

In some embodiments of the present disclosure, an integration circuit includes: a third operational amplifier, a tenth capacitor, and an eleventh capacitor. The first input end of the third operational amplifier is coupled to the first output end of the fifth chopper and the first end of the tenth capacitor. A second input terminal of the third operational amplifier is coupled to the second output terminal of the fifth chopper and the first terminal of the eleventh capacitor. The first output terminal of the third operational amplifier is coupled to the first input terminal of the voltage-to-current conversion circuit and the second terminal of the tenth capacitor. The second output end of the third operational amplifier is coupled to the second input end of the voltage-current conversion circuit and the second end of the eleventh capacitor.

In some embodiments of the present disclosure, a voltage-to-current conversion circuit includes: and a fourth operational amplifier. The first input end of the fourth operational amplifier is coupled to the first output end of the third operational amplifier. The second input terminal of the fourth operational amplifier is coupled to the second output terminal of the third operational amplifier. The first output end of the fourth operational amplifier is coupled with the first input end of the second chopper. The second output terminal of the fourth operational amplifier is coupled to the second input terminal of the second chopper.

In some embodiments of the present disclosure, the amplifier circuit is an instrumentation amplifier.

According to a second aspect of the present disclosure, an amplifier circuit is provided. The amplifier circuit includes: first to fifth choppers, first to eleventh capacitors, first to fourth resistors, and first to fourth operational amplifiers. Wherein the first chopper is configured to modulate the frequency of the input differential signal having the first frequency to a second frequency. The first terminal of the first capacitor is coupled to the first output terminal of the first chopper. The second end of the first capacitor is coupled to the first end of the first resistor, the first input end of the first operational amplifier and the first end of the third capacitor. The first end of the second capacitor is coupled to the second output end of the first chopper. The second terminal of the second capacitor is coupled to the first terminal of the second resistor, the second input terminal of the first operational amplifier, and the first terminal of the fourth capacitor. The second end of the first resistor is coupled to the common mode voltage input end. The second end of the second resistor is coupled to the common mode voltage input end. The first output end of the first operational amplifier is coupled with the first input end of the second chopper. The second output end of the first operational amplifier is coupled with the second input end of the second chopper. The second terminal of the third capacitor is coupled to the second output terminal of the third chopper. The second terminal of the fourth capacitor is coupled to the first output terminal of the third chopper. The second chopper is configured to modulate a frequency of the first amplified differential signal output by the first operational amplifier to a first frequency and modulate a frequency of the offset voltage of the first operational amplifier to a second frequency. The first input terminal of the second operational amplifier is coupled to the first output terminal of the second chopper and the first terminal of the fifth capacitor. The second input terminal of the second operational amplifier is coupled to the second output terminal of the second chopper and the first terminal of the sixth capacitor. The first output end of the second operational amplifier is coupled with the first input end of the third chopper and the second end of the fifth capacitor. The second output terminal of the second operational amplifier is coupled to the second input terminal of the third chopper and the second terminal of the sixth capacitor. The third chopper is configured to modulate the frequency of the second amplified differential signal output from the second operational amplifier to a second frequency, modulate the frequency of the offset voltage modulated by the second chopper to a first frequency, and negatively feed back the second amplified differential signal modulated by the third chopper to the first amplification circuit. The fourth chopper is configured to modulate the frequency of the second amplified differential signal modulated by the third chopper to a first frequency, and modulate the frequency of the offset voltage modulated by the third chopper to a second frequency. The first end of the third resistor is coupled to the first output end of the fourth chopper. A second end of the third resistor is coupled to a first end of the seventh capacitor and to the first differential signal output of the amplifier circuit. The first end of the fourth resistor is coupled to the second output end of the fourth chopper. A second end of the fourth resistor is coupled to a second end of the seventh capacitor and to the second differential signal output of the amplifier circuit. A first terminal of the eighth capacitor is coupled to the first differential signal output terminal of the amplifier circuit. A second terminal of the eighth capacitor is coupled to the first input terminal of the fifth chopper. The first terminal of the ninth capacitor is coupled to the second differential signal output terminal of the amplifier circuit. A second terminal of the ninth capacitor is coupled to the second input terminal of the fifth chopper. The first input terminal of the third operational amplifier is coupled to the first output terminal of the fifth chopper and the first terminal of the tenth capacitor. A second input terminal of the third operational amplifier is coupled to the second output terminal of the fifth chopper and the first terminal of the eleventh capacitor. The first output terminal of the third operational amplifier is coupled to the first input terminal of the fourth operational amplifier and the second terminal of the tenth capacitor. The second output terminal of the third operational amplifier is coupled to the second input terminal of the fourth operational amplifier and the second terminal of the eleventh capacitor. The first output end of the fourth operational amplifier is coupled with the first input end of the second chopper. The second output terminal of the fourth operational amplifier is coupled to the second input terminal of the second chopper.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, it being understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

fig. 1 is a schematic block diagram of an amplifier circuit according to an embodiment of the present disclosure; and

fig. 2 is an exemplary circuit diagram of an amplifier circuit according to an embodiment of the present disclosure.

In the drawings, the same reference numerals in the last two digits correspond to the same elements. It should be noted that the elements in the figures are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).

Fig. 1 shows a schematic block diagram of an amplifier circuit 100 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the amplifier circuit is an instrumentation amplifier. The amplifier circuit 100 includes: first to fourth choppers CH1 to CH4, a first amplification circuit 110, a second amplification circuit 120, a low-pass filter circuit 130, and a ripple suppression circuit 140.

A first input terminal of the first chopper CH1 is coupled to the first input voltage terminal Vip. A second input terminal of the first chopper CH1 is coupled to the second input voltage terminal Vin. The voltage signal input from the first input voltage terminal Vip and the voltage signal input from the second input voltage terminal Vin constitute an input differential signal. A first output terminal of the first chopper CH1 is coupled to a first input terminal of the first amplifying circuit 110 via a first node N1. A second output terminal of the first chopper CH1 is coupled to a second input terminal of the first amplifying circuit 110 via a second node N2. The first chopper CH1 may be configured to: the frequency of the input differential signal having the first frequency is modulated to a second frequency, and the input differential signal modulated by the first chopper CH1 is supplied to the first amplification circuit 110. Wherein the second frequency is higher than the first frequency. In some embodiments of the present disclosure, the first frequency is a low frequency and the second frequency is a high frequency. In this context, the second frequency may alternatively be referred to as the chopping frequency.

In the case where the common mode input voltage is a high voltage, the first chopper CH1 needs to be designed as a high-voltage chopper.

A first input terminal of the first amplifying circuit 110 is coupled to a first output terminal of the first chopper CH1 via a first node N1. A second input terminal of the first amplifying circuit 110 is coupled to a second output terminal of the first chopper CH1 via a second node N2. A first feedback terminal of the first amplifying circuit 110 is coupled to a second output terminal of the third chopper CH3 via a tenth node N10. A second feedback terminal of the first amplifying circuit 110 is coupled to a first output terminal of the third chopper CH3 via a ninth node N9. A first output terminal of the first amplifying circuit 110 is coupled to a first input terminal of the second chopper CH2 and a first output terminal of the ripple suppression circuit 140 via a third node N3. A second output terminal of the first amplifying circuit 110 is coupled to a second input terminal of the second chopper CH2 and a second output terminal of the ripple suppression circuit 140 via a fourth node N4. The first amplification circuit 110 may be configured to: the input differential signal modulated by the first chopper CH1 is amplified to generate a first amplified differential signal, and the first amplified differential signal is provided to the second chopper CH 2.

A first input terminal of the second chopper CH2 is coupled to the first output terminal of the first amplifying circuit 110 and the first output terminal of the ripple suppression circuit 140 via a third node N3. A second input terminal of the second chopper CH2 is coupled to the second output terminal of the first amplifying circuit 110 and the second output terminal of the ripple suppression circuit 140 via a fourth node N4. A first output terminal of the second chopper CH2 is coupled to a first input terminal of the second amplifying circuit 120 via a fifth node N5. A second output terminal of the second chopper CH2 is coupled to a second input terminal of the second amplifying circuit 120 via a sixth node N6. The second chopper CH2 may be configured to: the frequency of the first amplified differential signal is modulated to a first frequency, and the frequency of the offset voltage of the first amplification circuit 110 is modulated to a second frequency. The second chopper CH2 supplies the first amplified differential signal modulated by the second chopper CH2 to the second amplification circuit 120. In some embodiments of the present disclosure, the second chopper CH2 modulates the offset voltage to an offset current having a second frequency and supplies the offset current to the second amplification circuit 120.

A first input terminal of the second amplifying circuit 120 is coupled to a first output terminal of the second chopper CH2 via a fifth node N5. A second input terminal of the second amplifying circuit 120 is coupled to a second output terminal of the second chopper CH2 via a sixth node N6. A first output terminal of the second amplifying circuit 120 is coupled to a first input terminal of a third chopper CH3 via a seventh node N7. A second output terminal of the second amplifying circuit 120 is coupled to a second input terminal of the third chopper CH3 via an eighth node N8. The second amplification circuit 120 may be configured to: the first amplified differential signal modulated by the second chopper CH2 is amplified to generate a second amplified differential signal, and the second amplified differential signal is provided to the third chopper CH3. In some embodiments of the present disclosure, the second amplification circuit 120 may be further configured to: the offset current is converted into an offset voltage having a second frequency, and the third chopper CH3 is supplied with the offset voltage having the second frequency.

A first input terminal of the third chopper CH3 is coupled to a first output terminal of the second amplifying circuit 120 via a seventh node N7. A second input terminal of the third chopper CH3 is coupled to a second output terminal of the second amplifying circuit 120 via an eighth node N8. A first output terminal of the third chopper CH3 is coupled to a first input terminal of the fourth chopper CH4 and a second feedback terminal of the first amplification circuit 110 via a ninth node N9. A second output terminal of the third chopper CH3 is coupled to a second input terminal of the fourth chopper CH4 and a first feedback terminal of the first amplification circuit 110 via a tenth node N10. The third chopper CH3 may be configured to: the frequency of the second amplified differential signal is modulated to a second frequency, the frequency of the offset voltage modulated by the second chopper CH2 is modulated to a first frequency, and the second amplified differential signal modulated by the third chopper CH3 is negatively fed back to the first amplification circuit 110. The third chopper CH3 supplies the second amplified differential signal modulated by the third chopper CH3 and the offset voltage modulated by the third chopper CH3 to the fourth chopper CH4.

A first input terminal of the fourth chopper CH4 is coupled to a first output terminal of the third chopper CH3 and a second feedback terminal of the first amplification circuit 110 via a ninth node N9. A second input terminal of the fourth chopper CH4 is coupled to a second output terminal of the third chopper CH3 and a first feedback terminal of the first amplification circuit 110 via a tenth node N10. A first output terminal of the fourth chopper CH4 is coupled to a first input terminal of the low-pass filter circuit 130 via an eleventh node N11. A second output terminal of the fourth chopper CH4 is coupled to a second input terminal of the low-pass filter circuit 130 via a twelfth node N12. The fourth chopper CH4 may be configured to: the frequency of the second amplified differential signal modulated by the third chopper CH3 is modulated to a first frequency, and the frequency of the offset voltage modulated by the third chopper CH3 is modulated to a second frequency. The fourth chopper CH4 supplies the second amplified differential signal modulated by the fourth chopper CH4 and the offset voltage modulated by the fourth chopper CH4 to the low-pass filter circuit 130.

A first input terminal of the low-pass filter circuit 130 is coupled to a first output terminal of the fourth chopper CH4 via an eleventh node N11. A second input terminal of the low-pass filter circuit 130 is coupled to a second output terminal of the fourth chopper CH4 via a twelfth node N12. A first output terminal of the low-pass filter circuit 130 is coupled to the first differential signal output terminal Voutp of the amplifier circuit 100. A second output terminal of the low-pass filter circuit 130 is coupled to the second differential signal output terminal Voutn of the amplifier circuit 100. The low pass filter circuit 130 may be configured to: the second amplified differential signal modulated by the fourth chopper CH4 and the offset voltage modulated by the fourth chopper CH4 are low-pass filtered to generate an output differential signal. The voltage signal output from the first differential signal output terminal Voutp and the voltage signal output from the second differential signal output terminal Voutn constitute an output differential signal.

A first input terminal of the ripple suppression circuit 140 is coupled to the first differential signal output terminal Voutp. A second input terminal of the ripple suppression circuit 140 is coupled to the second differential signal output terminal Voutn. A first output terminal of the ripple suppression circuit 140 is coupled to a first input terminal of a second chopper CH2 via a third node N3. A second output terminal of the ripple suppression circuit 140 is coupled to a second input terminal of the second chopper CH2 via a fourth node N4. The ripple suppression circuit 140 may be configured to: ripple components in the output differential signals are obtained, feedback current is generated according to the ripple components, and the feedback current is negatively fed back to the two input ends of the second chopper CH2 to eliminate the offset voltage of the first amplifying circuit 110. The ripple component is a ripple voltage.

The amplifier circuit 100 according to an embodiment of the present disclosure allows a useful signal of a low frequency to be amplified using a chopping technique, modulates an offset voltage to a high frequency to filter the offset voltage of the high frequency through a low pass filter circuit, and further eliminates the offset voltage through a negative feedback loop, thereby achieving a high Common Mode Rejection Ratio (CMRR).

Fig. 2 illustrates an exemplary circuit diagram of an amplifier circuit 200 according to an embodiment of the present disclosure. The first amplification circuit 210 may include: first to fourth capacitors C1 to C4, a first resistor R1, a second resistor R2, and a first operational amplifier gm1. A first end of the first capacitor C1 is coupled to a first output end of the first chopper CH 1. The second terminal of the first capacitor C1 is coupled to the first terminal of the first resistor R1, the first input terminal of the first operational amplifier gm1 and the first terminal of the third capacitor C3. A first terminal of the second capacitor C2 is coupled to the second output terminal of the first chopper CH 1. A second terminal of the second capacitor C2 is coupled to a first terminal of the second resistor R2, a second input terminal of the first operational amplifier gm1 and a first terminal of the fourth capacitor C4. A second terminal of the first resistor R1 is coupled to the common mode voltage input Vcm. A second terminal of the second resistor R2 is coupled to the common mode voltage input Vcm. The common mode input voltage Vcm is input from the common mode voltage input terminal Vcm. Vcm = (Vip + Vin)/2. A first output terminal of the first operational amplifier gm1 is coupled to a first input terminal of the second chopper CH 2. A second output terminal of the first operational amplifier gm1 is coupled to a second input terminal of the second chopper CH 2. A second terminal (the first feedback terminal of the first amplifying circuit 110) of the third capacitor C3 is coupled to a second output terminal (the tenth node N10) of the third chopper CH3. A second terminal (the second feedback terminal of the first amplifying circuit 110) of the fourth capacitor C4 is coupled to the first output terminal (the ninth node N9) of the third chopper CH3.

In some embodiments of the present disclosure, the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2. The capacitance value of the third capacitor C3 is equal to the capacitance value of the fourth capacitor C4. The amplification factor of the first amplifying circuit 210 is C1/C3, where C1 represents the capacitance of the first capacitor C1 and C3 represents the capacitance of the third capacitor C3.

In the example of fig. 2, the first input terminal of the first operational amplifier gm1 is a non-inverting input terminal. The second input terminal of the first operational amplifier gm1 is an inverting input terminal. The first output terminal of the first operational amplifier gm1 is an inverting output terminal. The second output terminal of the first operational amplifier gm1 is a non-inverting output terminal. An offset voltage Vos may be present at the input of the first operational amplifier gm1.

In some embodiments of the present disclosure, the resistance values of the first and second resistors R1 and R2 may be on the order of hundreds of megaohms or more. So that the static operating voltage at both inputs of the first operational amplifier gm1 can be stabilized to the common mode input voltage Vcm.

The second amplification circuit 220 may include: a second operational amplifier gm2, a fifth capacitor C5, and a sixth capacitor C6. A first input terminal of the second operational amplifier gm2 is coupled to a first output terminal of the second chopper CH2 and a first terminal of the fifth capacitor C5. A second input terminal of the second operational amplifier gm2 is coupled to a second output terminal of the second chopper CH2 and a first terminal of the sixth capacitor C6. A first output terminal of the second operational amplifier gm2 is coupled to a first input terminal of the third chopper CH3 and a second terminal of the fifth capacitor C5. A second output terminal of the second operational amplifier gm2 is coupled to a second input terminal of the third chopper CH3 and a second terminal of the sixth capacitor C6.

In the example of fig. 2, the fifth capacitor C5 and the sixth capacitor C6 are miller compensation capacitors. The first input terminal of the second operational amplifier gm2 is a non-inverting input terminal. The second input terminal of the second operational amplifier gm2 is an inverting input terminal. The first output terminal of the second operational amplifier gm2 is an inverting output terminal. The second output terminal of the second operational amplifier gm2 is a non-inverting output terminal.

The low pass filter circuit 230 may include: a third resistor R3, a fourth resistor R4, and a seventh capacitor C7. Wherein a first end of the third resistor R3 is coupled to a first output end of the fourth chopper CH4. A second end of the third resistor R3 is coupled to a first end of the seventh capacitor C7 and the first differential signal output terminal Voutp of the amplifier circuit 200. A first end of the fourth resistor R4 is coupled to a second output terminal of the fourth chopper CH4. A second end of the fourth resistor R4 is coupled to a second end of the seventh capacitor C7 and the second differential signal output terminal Voutn of the amplifier circuit 200.

The ripple suppression circuit 240 may include: a ripple obtaining circuit 241, a fifth chopper CH5, an integrating circuit 242, and a voltage-current converting circuit 243.

The ripple obtaining circuit 241 may be coupled to the first differential signal output terminal Voutp, the second differential signal output terminal Voutn, and two input terminals of the fifth chopper CH 5. The ripple obtaining circuit 241 may be configured to allow only the ripple voltage in the output differential signal to pass through, and obtain the ripple current according to the ripple voltage. The ripple obtaining circuit 241 may include: an eighth capacitor C8, and a ninth capacitor C9. The first end of the eighth capacitor C8 is coupled to the first differential signal output terminal Voutp. A second terminal of the eighth capacitor C8 is coupled to a first input terminal of the fifth chopper CH 5. A first terminal of the ninth capacitor C9 is coupled to the second differential signal output terminal Voutn. A second terminal of the ninth capacitor C9 is coupled to a second input terminal of the fifth chopper CH 5. The eighth capacitor C8 and the ninth capacitor C9 are induction capacitors. The ripple voltage in the output differential signal is changed into ripple current after passing through the induction capacitor.

Two input terminals of the fifth chopper CH5 are coupled to the ripple obtaining circuit 241. Two output terminals of the fifth chopper CH5 are coupled to two input terminals of the integrating circuit 242. The fifth chopper CH5 may be configured to modulate the frequency of the ripple current to the first frequency. In some embodiments of the present disclosure, the fifth chopper CH5 modulates the ripple current into a low frequency current.

Two input terminals of the integrating circuit 242 are coupled to two output terminals of the fifth chopper CH 5. Two output terminals of the integrating circuit 242 are coupled to two input terminals of the voltage-to-current converting circuit 243. The integrating circuit 242 may be configured to integrate the ripple current modulated by the fifth chopper CH5 to generate a feedback voltage. The integrating circuit 242 may include: a third operational amplifier gm3, a tenth capacitor C10, and an eleventh capacitor C11. Wherein a first input terminal of the third operational amplifier gm3 is coupled to a first output terminal of the fifth chopper CH5 and a first terminal of the tenth capacitor C10. A second input terminal of the third operational amplifier gm3 is coupled to a second output terminal of the fifth chopper CH5 and a first terminal of the eleventh capacitor C11. A first output terminal of the third operational amplifier gm3 is coupled to the first input terminal of the voltage-to-current conversion circuit 243 and the second terminal of the tenth capacitor C10. A second output terminal of the third operational amplifier gm3 is coupled to the second input terminal of the voltage-to-current conversion circuit 243 and the second terminal of the eleventh capacitor C11.

In the example of fig. 2, the first input terminal of the third operational amplifier gm3 is a non-inverting input terminal. The second input terminal of the third operational amplifier gm3 is an inverting input terminal. The first output terminal of the third operational amplifier gm3 is an inverting output terminal. The second output terminal of the third operational amplifier gm3 is a non-inverting output terminal.

The voltage-to-current conversion circuit 243 may be configured to convert the feedback voltage from the integration circuit 242 into a feedback current. The voltage-current conversion circuit 243 may include: a fourth operational amplifier gm4. The first input terminal of the fourth operational amplifier gm4 is coupled to the first output terminal of the third operational amplifier gm 3. The second input terminal of the fourth operational amplifier gm4 is coupled to the second output terminal of the third operational amplifier gm 3. A first output terminal of the fourth operational amplifier gm4 is coupled to a first input terminal of the second chopper CH 2. A second output terminal of the fourth operational amplifier gm4 is coupled to a second input terminal of the second chopper CH 2. In some embodiments of the present disclosure, the fourth operational amplifier gm4 may be considered as a feedback transconductance stage.

In the example of fig. 2, the first input terminal of the fourth operational amplifier gm4 is a non-inverting input terminal. The second input terminal of the fourth operational amplifier gm4 is an inverting input terminal. The first output terminal of the fourth operational amplifier gm4 is an inverting output terminal. The second output terminal of the fourth operational amplifier gm4 is a non-inverting output terminal.

In the example of fig. 2, the first and second capacitors C1 and C2 may be high voltage capacitors, and thus may withstand a high common mode input voltage, without affecting the linear input range. The first capacitor C1 and the second capacitor C2 can isolate the offset voltage and the noise at a low frequency, and the offset voltage hardly varies with the variation of the common mode input voltage, so that the amplifier circuit 200 has a very high CMRR. The input differential signal with low frequency is modulated to the chopping frequency after passing through a first chopper CH1, then amplified by C1/C3 times, and then modulated back to low frequency after passing through a fourth chopper CH4. After large glitches are filtered by the low-pass filter circuit 230, the final output signals Voutp and Voutn are obtained. In order to cancel the offset voltage Vos of the first operational amplifier gm1, a second chopper CH2 and a third chopper CH3 are added before and after the second operational amplifier gm 2. The offset voltage Vos of the first operational amplifier gm1 is modulated to the chopping frequency through the second chopper CH2, then is demodulated to the low frequency through the third chopper CH3, and finally is re-modulated to the chopping frequency through the fourth chopper CH4 before reaching the output end, and appears at the first differential signal output end Voutp and the second differential signal output end Voutn in the form of ripples. To reduce this portion of the ripple, a ripple rejection loop is introduced. The ripple component in the output differential signal may pass through the eighth and ninth capacitors C8 and C9 entirely, but the amplified useful signal of low frequency cannot pass through the eighth and ninth capacitors C8 and C9. The ripple voltage becomes ripple current after passing through an eighth capacitor C8 and a ninth capacitor C9, is modulated into low-frequency current after passing through a fifth chopper CH5, then becomes feedback voltage after charging an integrator formed by a third operational amplifier gm3, a tenth capacitor C10 and an eleventh capacitor C11, and finally is fed back to two output ends of the first operational amplifier gm1 after passing through a feedback transconductance stage, thereby eliminating the offset voltage Vos of the first operational amplifier gm1.

In summary, the embodiments of the present disclosure provide an amplifier circuit (which may also be referred to as a capacitance gain instrumentation amplifier circuit) suitable for low frequency signal detection and capable of withstanding a high common mode input voltage. The gain capacitors (first to fourth capacitors) may use high voltage capacitors to withstand high common mode input voltages. By using the chopping technology, a low-frequency useful signal can easily pass through a capacitance gain network (the capacitance gain network formed by the first operational amplifier, the second operational amplifier and the first capacitor, the second capacitor, the third capacitor and the fourth capacitor), and meanwhile, the offset voltage of the first operational amplifier is well eliminated, and high CMRR is realized. And since the input differential signal is input via the first capacitor and the second capacitor, the input bias current of the input differential signal is low, which can make the power consumption of the amplifier circuit lower.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the words "comprise" and "include" are to be construed as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the disclosure is defined by the appended claims.

Claims

1. An amplifier circuit, comprising: first to fourth choppers, a first amplifying circuit, a second amplifying circuit, a low-pass filter circuit, and a ripple suppression circuit,

wherein the first chopper is configured to modulate a frequency of an input differential signal having a first frequency to a second frequency;

the first amplification circuit is configured to amplify the input differential signal modulated by the first chopper to generate a first amplified differential signal;

a second chopper configured to modulate a frequency of the first amplified differential signal to the first frequency and modulate a frequency of an offset voltage of the first amplification circuit to the second frequency;

the second amplification circuit is configured to amplify the first amplified differential signal modulated by the second chopper to generate a second amplified differential signal;

the third chopper is configured to modulate the frequency of the second amplified differential signal to the second frequency, modulate the frequency of the offset voltage modulated by the second chopper to the first frequency, and negatively feed back the second amplified differential signal modulated by the third chopper to the first amplification circuit;

the fourth chopper is configured to modulate the frequency of the second amplified differential signal modulated by the third chopper to the first frequency and modulate the frequency of the offset voltage modulated by the third chopper to the second frequency;

the low pass filter circuit is configured to low pass filter the second amplified differential signal modulated by the fourth chopper and an offset voltage to generate an output differential signal;

the ripple suppression circuit is configured to obtain a ripple component in the output differential signal, generate a feedback current according to the ripple component, and negatively feed back the feedback current to two input ends of the second chopper to eliminate the offset voltage of the first amplification circuit;

wherein the second frequency is higher than the first frequency.

2. The amplifier circuit of claim 1, wherein the first amplification circuit comprises: first to fourth capacitors, a first resistor, a second resistor, and a first operational amplifier,

wherein a first terminal of the first capacitor is coupled to a first output terminal of the first chopper, and a second terminal of the first capacitor is coupled to a first terminal of the first resistor, a first input terminal of the first operational amplifier, and a first terminal of a third capacitor;

a first terminal of the second capacitor is coupled to the second output terminal of the first chopper, and a second terminal of the second capacitor is coupled to the first terminal of the second resistor, the second input terminal of the first operational amplifier, and the first terminal of a fourth capacitor;

a second end of the first resistor is coupled to a common mode voltage input end;

a second end of the second resistor is coupled to the common mode voltage input;

a first output end of the first operational amplifier is coupled with a first input end of the second chopper, and a second output end of the first operational amplifier is coupled with a second input end of the second chopper;

a second terminal of the third capacitor is coupled to a second output terminal of the third chopper;

a second terminal of the fourth capacitor is coupled to a first output terminal of the third chopper.

3. The amplifier circuit of claim 2, wherein the first and second resistors have a resistance value on the order of hundreds of megaohms or more.

4. The amplifier circuit of claim 1, wherein the second amplification circuit comprises: a second operational amplifier, a fifth capacitor, and a sixth capacitor,

wherein a first input terminal of the second operational amplifier is coupled to the first output terminal of the second chopper and the first terminal of the fifth capacitor, a second input terminal of the second operational amplifier is coupled to the second output terminal of the second chopper and the first terminal of the sixth capacitor, a first output terminal of the second operational amplifier is coupled to the first input terminal of the third chopper and the second terminal of the fifth capacitor, and a second output terminal of the second operational amplifier is coupled to the second input terminal of the third chopper and the second terminal of the sixth capacitor.

5. The amplifier circuit of claim 1, wherein the low pass filter circuit comprises: a third resistor, a fourth resistor, and a seventh capacitor,

wherein a first end of the third resistor is coupled to the first output terminal of the fourth chopper, and a second end of the third resistor is coupled to the first end of the seventh capacitor and the first differential signal output terminal of the amplifier circuit;

a first end of the fourth resistor is coupled to the second output terminal of the fourth chopper, and a second end of the fourth resistor is coupled to the second end of the seventh capacitor and the second differential signal output terminal of the amplifier circuit.

6. The amplifier circuit of claim 1, wherein the ripple suppression circuit comprises: a ripple obtaining circuit, a fifth chopper, an integrating circuit and a voltage-current converting circuit,

wherein the ripple obtaining circuit is configured to allow only a ripple voltage in the output differential signal to pass through and obtain a ripple current according to the ripple voltage;

the fifth chopper is configured to modulate a frequency of the ripple current to the first frequency;

the integrating circuit is configured to integrate the ripple current modulated by the fifth chopper to generate a feedback voltage;

the voltage-to-current conversion circuit is configured to convert the feedback voltage into the feedback current.

7. The amplifier circuit of claim 6, wherein the ripple acquisition circuit comprises: an eighth capacitor, and a ninth capacitor,

wherein a first terminal of the eighth capacitor is coupled to a first differential signal output terminal of the amplifier circuit, and a second terminal of the eighth capacitor is coupled to a first input terminal of the fifth chopper;

a first terminal of the ninth capacitor is coupled to a second differential signal output terminal of the amplifier circuit, and a second terminal of the ninth capacitor is coupled to a second input terminal of the fifth chopper.

8. The amplifier circuit of claim 6 wherein the integrating circuit comprises: a third operational amplifier, a tenth capacitor, and an eleventh capacitor,

wherein a first input terminal of the third operational amplifier is coupled to the first output terminal of the fifth chopper and the first terminal of the tenth capacitor, a second input terminal of the third operational amplifier is coupled to the second output terminal of the fifth chopper and the first terminal of the eleventh capacitor, a first output terminal of the third operational amplifier is coupled to the first input terminal of the voltage-current conversion circuit and the second terminal of the tenth capacitor, and a second output terminal of the third operational amplifier is coupled to the second input terminal of the voltage-current conversion circuit and the second terminal of the eleventh capacitor.

9. The amplifier circuit of claim 8, wherein the voltage-to-current conversion circuit comprises: a fourth operational amplifier for amplifying the first and second signals,

the first input terminal of the fourth operational amplifier is coupled to the first output terminal of the third operational amplifier, the second input terminal of the fourth operational amplifier is coupled to the second output terminal of the third operational amplifier, the first output terminal of the fourth operational amplifier is coupled to the first input terminal of the second chopper, and the second output terminal of the fourth operational amplifier is coupled to the second input terminal of the second chopper.

10. An amplifier circuit, comprising: first to fifth choppers, first to eleventh capacitors, first to fourth resistors, and first to fourth operational amplifiers,

a first terminal of the first capacitor is coupled to a first output terminal of the first chopper, and a second terminal of the first capacitor is coupled to a first terminal of the first resistor, a first input terminal of the first operational amplifier, and a first terminal of a third capacitor;

a first terminal of a second capacitor is coupled to the second output terminal of the first chopper, and a second terminal of the second capacitor is coupled to the first terminal of the second resistor, the second input terminal of the first operational amplifier, and the first terminal of a fourth capacitor;

a second end of the second resistor is coupled to the common mode voltage input end;

a first output end of the first operational amplifier is coupled with a first input end of a second chopper, and a second output end of the first operational amplifier is coupled with a second input end of the second chopper;

a second end of the third capacitor is coupled to a second output end of a third chopper;

a second terminal of the fourth capacitor is coupled to a first output terminal of the third chopper;

the second chopper is configured to modulate a frequency of a first amplified differential signal output by the first operational amplifier to the first frequency and modulate a frequency of an offset voltage of the first operational amplifier to the second frequency;

a first input terminal of a second operational amplifier is coupled to the first output terminal of the second chopper and the first terminal of a fifth capacitor, a second input terminal of the second operational amplifier is coupled to the second output terminal of the second chopper and the first terminal of a sixth capacitor, a first output terminal of the second operational amplifier is coupled to the first input terminal of the third chopper and the second terminal of the fifth capacitor, and a second output terminal of the second operational amplifier is coupled to the second input terminal of the third chopper and the second terminal of the sixth capacitor;

the third chopper is configured to modulate the frequency of the second amplified differential signal output from the second operational amplifier to the second frequency, modulate the frequency of the offset voltage modulated by the second chopper to the first frequency, and negatively feed back the second amplified differential signal modulated by the third chopper to the first amplification circuit;

a first terminal of a third resistor is coupled to the first output terminal of the fourth chopper, and a second terminal of the third resistor is coupled to the first terminal of a seventh capacitor and the first differential signal output terminal of the amplifier circuit;

a first end of a fourth resistor is coupled to the second output end of the fourth chopper, and a second end of the fourth resistor is coupled to the second end of the seventh capacitor and the second differential signal output end of the amplifier circuit;

a first terminal of an eighth capacitor is coupled to the first differential signal output terminal of the amplifier circuit, and a second terminal of the eighth capacitor is coupled to the first input terminal of the fifth chopper;

a first terminal of a ninth capacitor is coupled to a second differential signal output terminal of the amplifier circuit, and a second terminal of the ninth capacitor is coupled to a second input terminal of the fifth chopper;

a first input terminal of a third operational amplifier is coupled to the first output terminal of the fifth chopper and the first terminal of a tenth capacitor, a second input terminal of the third operational amplifier is coupled to the second output terminal of the fifth chopper and the first terminal of the eleventh capacitor, a first output terminal of the third operational amplifier is coupled to the first input terminal of the fourth operational amplifier and the second terminal of the tenth capacitor, and a second output terminal of the third operational amplifier is coupled to the second input terminal of the fourth operational amplifier and the second terminal of the eleventh capacitor;

a first output terminal of the fourth operational amplifier is coupled to the first input terminal of the second chopper, and a second output terminal of the fourth operational amplifier is coupled to the second input terminal of the second chopper.