CN115510783A

CN115510783A - Method, apparatus and storage medium for implementing sequential logic user-defined primitive

Info

Publication number: CN115510783A
Application number: CN202211073686.8A
Authority: CN
Inventors: 张玉晨; 闫亚飞
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2022-09-02
Filing date: 2022-09-02
Publication date: 2022-12-23

Abstract

The present disclosure provides a method, apparatus, and storage medium for implementing sequential logic user-defined primitives. The method comprises the following steps: receiving a description of the user-defined primitive, the description including at least a first input, a second input, and an output associated with the first input and the second input; generating first and second truth tables corresponding to the first and second inputs, respectively, according to the description, wherein the first truth table comprises first and second prior input values and prior output values of the first and second inputs and the output at a previous time, and a first current input value of the first input at a current time; determining a first element value in the first truth table corresponding to the first and second prior input values, the prior output value, and the first current input value; and determining, in the first truth table, a current output value of the output of the user-defined primitive at a current time based on the first element value.

Description

Method, apparatus and storage medium for implementing sequential logic user-defined primitives

Technical Field

The present disclosure relates to the field of computer software, and in particular, to a method, device, and storage medium for implementing sequential logic user-defined primitives.

Background

The Verilog language has various basic circuit elements built into it, such as AND, OR, XOR, etc. In practice, however, users sometimes need to build modules with specific functions, which may be complicated if only the built-in basic elements are used for description. Therefore, verilog also provides users with the ability to write primitives themselves, which are User-Defined primitives (UDP).

The UDP includes a combinational logic UDP and a sequential logic UDP. Wherein the current output value of the sequential logic UDP depends not only on the current input value but also on the current internal state (i.e. last output value).

The UDP implementation typically takes the output by looking up a truth table. Taking the example of edge triggered sequential logic UDP, the possible states of its inputs include 9 (00, 01,0x,10,11,1x, x0, x1, xx, i.e., from 0 to 0, from 0 to 1, from 0 to x, etc.). In this case, for an edge triggered sequential logic UDP with input N, the number of elements in its truth table is 9 ^N *3, where 3 indicates that three states (0, 1, x) are possible for the last output value. The truth table scheme of the conventional sequential logic UDP causes a huge overhead of memory space.

Disclosure of Invention

In view of the above, the present disclosure provides a method, an apparatus, and a storage medium for implementing sequential logic user-defined primitives.

In a first aspect of the present disclosure, a method for implementing a sequential logic user-defined primitive is provided, including: receiving a description of the user-defined primitive, the description including at least a first input, a second input, and an output associated with the first input and the second input; generating a first truth table and a second truth table corresponding to the first input and the second input, respectively, according to the description of the user-defined primitive, wherein the first truth table includes a first previous input value, a second previous input value, and a previous output value of the first input, the second input, and the output at a previous time, and a first current input value of the first input at a current time; determining a first element value in the first truth table corresponding to the first prior input value, the second prior input value, the prior output value, and the first current input value; and determining, in the first truth table, a current output value of the output of the user-defined primitive at a current time based on the first element value.

In a second aspect of the present disclosure, an electronic device implementing a sequential logic user-defined primitive is provided, including: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method according to the first aspect.

In a third aspect of the disclosure, a non-transitory computer-readable storage medium is provided that stores a set of instructions of an electronic device for causing the electronic device to perform the method of the first aspect.

According to the method, the device and the storage medium for realizing the sequential logic user-defined primitive, the corresponding truth table is generated for each input of the UDP, the number of elements in the truth table is effectively reduced, and the occupation of the truth table on the storage space is further reduced. In the simulation operation process, the simulation tool can read the stored truth table more quickly, and the realization efficiency of the UDP is improved.

Drawings

In order to more clearly illustrate the present disclosure or the technical solutions in the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1A shows a schematic structural diagram of an exemplary electronic device according to an embodiment of the present disclosure.

FIG. 1B shows a schematic diagram of an exemplary simulation tool in accordance with an embodiment of the present disclosure.

FIG. 2A illustrates a schematic diagram of a description of an exemplary sequential logical user-defined primitive in accordance with an embodiment of the present disclosure.

Fig. 2B illustrates a schematic diagram of an exemplary conventional truth table in accordance with an embodiment of the present disclosure.

Fig. 2C shows a schematic diagram of an example first truth table corresponding to a first input, in accordance with an embodiment of the present disclosure.

FIG. 3 sets forth a flow chart illustrating an exemplary method of implementing sequential logical user defined primitives according to embodiments of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

As described above, the number of elements in the truth table of the conventional sequential logic User Defined Primitive (UDP) reaches 9 ^N *3, the larger the number of elements, the larger the memory space occupied by the truth table. Therefore, the truth table scheme of the conventional sequential logic UDP causes a huge overhead of memory space.

In view of the foregoing problems, the present disclosure provides a method, an apparatus, and a storage medium for implementing a sequential logic user-defined primitive, in which a corresponding truth table is generated for each input, so that the number of elements in the truth table is effectively reduced, and the occupation of a storage space by the truth table is further reduced.

Fig. 1A shows a schematic structural diagram of an exemplary electronic device 100 according to an embodiment of the present disclosure.

The electronic device 100 may be, for example, a host computer. The electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein the processor 102, memory 104, network interface 106, and peripheral interface 108 may be communicatively coupled to each other within the electronic device 100 via a bus 110.

Processor 102 may be a Central Processing Unit (CPU), an image processor, a neural network processor, a microcontroller, a programmable logic device, a digital signal processor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1A, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, truth tables, etc.). For example, as shown in fig. 1A, the stored data may include program instructions (e.g., for implementing the techniques of this disclosure) as well as truth tables. The processor 102 may also access stored program instructions and truth tables and execute the program instructions to generate or read the truth tables. The memory 104 may include a non-transitory computer readable storage medium, such as a volatile memory device or a non-volatile memory device. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to enable the electronic apparatus 100 to communicate with one or more other external devices via a network. The network may be any wired or wireless network capable of transmitting and/or receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

The peripheral interface 108 may be configured to connect the electronic device 100 with one or more peripheral devices to enable input and output of information. For example, the peripheral devices may include input devices such as a keyboard, mouse, touch pad, touch screen, microphone, various sensors, and output devices such as a display, speaker, vibrator, indicator light.

The bus 110 may be configured to transfer information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), and may be, for example, an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), etc.

In some embodiments, in addition to the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110 illustrated in fig. 1A and described above, the electronic device 100 may include one or more other components necessary to achieve normal operation and/or one or more other components necessary to achieve the solutions of the embodiments of the present disclosure. In some embodiments, electronic device 100 may not include one or more of the components shown in FIG. 1A.

It should be noted that, although the above-mentioned configuration architecture of the electronic device 100 only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in a specific implementation process, the configuration architecture of the electronic device 100 may further include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above-mentioned structural architecture of the electronic device 100 may also only include the components necessary for implementing the embodiments of the present disclosure, and not necessarily include all the components shown in the figures.

FIG. 1B shows a schematic diagram of an exemplary simulation tool 120 according to an embodiment of the present disclosure. The simulation tool 120 may be a computer program running on the electronic device 100.

In the field of chip design, a design may be simulated using a simulation tool. The simulation tool may be, for example, a GalaxSim simulation tool available from Chihua chapter science and technology, inc. The example simulation tool 120 shown in FIG. 1B may include a compiler 122 and a simulator 124. Compiler 122 can receive source code 121 (e.g., a hardware description language such as VHDL, verilog, systemveilog, etc.) and compile into execution code 123 (e.g., machine code, assembly code, software code, truth tables, etc.). The simulator 124 may simulate according to the execution code 123 and output a simulation result 125. For example, the simulation tool 120 may output the simulation results 125 onto an output device (e.g., displayed on a display) via the peripheral interface 108 of FIG. 1A.

In some embodiments, when a module of a particular function needs to be built in source code 121 written in Verilog language, a user may write UDP by himself to meet the functional needs.

For convenience of description, the embodiment of the present disclosure is described by taking a two-input sequential logic UDP as an example.

FIG. 2A illustrates a schematic diagram of a description 200 of an exemplary sequential logical user-defined primitive in accordance with an embodiment of the present disclosure. The description 200 may include a UDP state table. The UDP state table may be user defined and represents UDP output values derived from the input state and the current state of UDP.

As shown in fig. 2A, the description 200 may include at least a first input i1, a second input i2 of UDP, an output value q at a previous time, and an output q + at a current time associated with the first input i1, the second input i2, and the output value q at the previous time. It is understood that the description 200 may include more than 2 inputs. As can be seen from the description 200, when the first input i1 jumps from 0 at the previous time to 1 at the current time (i.e., the first input i1 is a rising edge), the second input i2 is 0, and the output q at the previous time is 1, the output q + at the current time of the UDP is 0; when the first input i1 is a rising edge and the second input i2 is 1, the output q + at the current time point of UDP is 1 regardless of the output value q at the previous time point.

The UDP implementation typically obtains the output by looking up a truth table.

Fig. 2B illustrates a schematic diagram of an exemplary conventional truth table 210 according to an embodiment of the disclosure. For a two-input sequential logic UDP (i.e., input N = 2), the number of elements in the conventional truth table scheme is 243.

In some embodiments, the simulation tool 120 may generate a first truth table corresponding to the first input i1 and a second truth table corresponding to the second input i2, respectively, based on the description 200 as shown in FIG. 2A.

Fig. 2C shows a schematic diagram of an exemplary first truth table 220 corresponding to the first input i1, in accordance with an embodiment of the present disclosure.

As shown in fig. 2C, the first truth table 220 may include a previous input value I1 of the first input I1 of the UDP at a previous time, a previous input value I2 of the second input I2 at a previous time, a previous output value q of the UDP at a previous time, and a current input value I1+ of the first input I1 at a current time. Where the prior input values I1, I2 and the prior output value q may each be (0, 1, x), the first truth table 220 has a value of 3 ³ =27 possible states, i.e. the first truth table 220 may be 27 rows. The current input value I1+ for UDP may be (0, 1, x, z). The simulation tool 120 may obtain the values of the elements in the first truth table 220 corresponding to the prior input values I1, I2, the prior output q, and the current input I1+ according to the description 200 shown in FIG. 2A.

Taking I1= x, I2= x, q = x, I1+ =0 as an example, in this case, the first input I1 is (x 0), the second input I2 is x, and the previous output q is x. Returning to the description 200 as shown in FIG. 2A, this state is undefined, so the current output q + is x (i.e., unknown). The user may define the value of output x to be 3. Therefore, the current output value q + of UDP at this time is x =3.

The first truth table 220 may also include element positions (as shown in the first column of the first truth table 220) for a user to more conveniently look up the output values of UDP after input changes. The element positions are identified starting from 0. In some embodiments, since the current input value I1+ of the first input I1 at the current time may be in four states (0, 1, x, z), the value of the element position of each row is increased by 4 based on the value of the element position of the previous row. The values of the element positions in the first truth table 220 may be 0,4,8, \ 8230;, 104, for a total of 27 values.

The simulation tool 120 may use I1+ instead of I1, q + instead of q, finding in the first truth table 220 that I1=0, I2= x, q = x in the row with element position 36. Based on the value 36 of the element position and the aforementioned obtained current output value 3, the simulation tool 120 may calculate an element value corresponding to I1= x, I2= x, q = x, I1+ = 0. In some embodiments, the simulation tool 120 may use the sum of the value 36 of the element position and the current output value of 3 as the element value. As shown in fig. 2C, the element value corresponding to I1= x, I2= x, q = x, I1+ =0 is 36+3=39.

Similarly, for I1= x, I2= x, q = x, I1+ =1, the simulation tool 120 may repeat the foregoing steps, resulting in a current output q + of x (i.e., 3) from the description 200; in the first truth table 220, I1=1, I2= x, q = x is found in the row with element position 72. Therefore, the element value corresponding to I1= x, I2= x, q = x, I1+ =1 is 72+3=75. And so on until the simulation tool 120 obtains all of the element values in the first truth table 220.

Similarly, the simulation tool 120 can generate the second truth table corresponding to the second input i2 by using the method of generating the first truth table 220, which is not described herein again.

Through the foregoing steps, the simulation tool 120 has generated a first truth table 220 corresponding to the first input i1 and a second truth table corresponding to the second input i2, respectively. During the simulation, when the UDP receives a new first input or second input, the simulation tool 120 can obtain the current output value of the UDP directly by looking up the generated first truth table 220 or second truth table.

Taking the case that UDP receives a new first input I1, for example, I1= x, I2= x, q = x, I1+ =0, when the first input I1 is changed from the previous input x to the current input 0.

In some embodiments, the simulation tool 120 may find the corresponding element value 39 in the first truth table 220. The element value 39 is stored in binary data (100111) in the computer. Based on this element value 39, the simulation tool 120 can retrieve the lower two bits of data (11) stored in the computer for the element value 39, resulting in the current output value of 3 for UDP.

In other embodiments, the simulation tool 120 may obtain the upper data (100100) of the element 39 in addition to the lower two data stored in the computer, which upper data (100100) may indicate the position 36 of the current output value q + in the first truth table 220. The simulation tool 120 may determine the row with the current output at element position 36 in the first truth table 220 based on the value of the high order data. The simulation tool 120 may read the value x (i.e., 3) corresponding to the output (i.e., q columns) from the determined row as the current output value.

In still other embodiments, the simulation tool 120 may perform a modulo operation on the state number 4 of the current input value I1+ of the first input I1 using the element value 39. The result 3 obtained by the modulo operation is the current output value of the UDP at that time.

In some embodiments, the UDP may also receive a new first input i1 and a new second input i2 simultaneously. At this time, the simulation tool 120 may process the new first input i1 in the first truth table 220, and use the output searched from the first truth table 120 as the previous output q; and processing a new second input i2 in a second truth table by using the new first input i1 and the previous output q, and obtaining a current output value q + of the UDP from the second truth table. Thus, the simulation tool 120 obtains the final current output value of UDP by processing the changed input values in two truth tables, respectively, at a time.

Using the method used in the embodiments of the present disclosure, the number of element values in each truth table is 3 ^N+1 *4. For a two-input sequential logic UDP (i.e., input N = 2), the number of elements per truth table is 108 and the total number of elements of the two truth tables is 216. It can be seen that the total number of element values is less than the number of elements 243 in the conventional truth table shown in fig. 2B.

In some embodiments, the input z of UDP is processed the same as the input x, so the current input values I1+ = x and I1+ = z may be merged into the same column processing. In this case, the number of element values of the first truth table 220 may be further reduced to 81. Accordingly, the total number of element values of the two truth tables is 162, further reducing the number of element values in the truth tables.

It will be appreciated that the above embodiment is exemplified by a two-input sequential logic UDPThe description is given. In practical applications, the sequential logic UDP can support at least 9 inputs. In this case, the number of elements in the conventional truth table scheme is up to 10 ¹⁰ Magnitude, and the method used by the disclosed embodiments may reduce the number of element values to 10 ⁶ Magnitude. The advantage of the method provided by the embodiment of the present disclosure in terms of storage space is more and more obvious as the number of inputs is increased.

The method provided by the embodiment of the disclosure effectively reduces the number of elements in the truth table by respectively generating the corresponding truth table for each input of the UDP, thereby reducing the occupation of the truth table on the storage space. During the simulation operation, the simulation tool 120 can read the stored truth table more quickly, thereby improving the implementation efficiency of the UDP.

Fig. 3 illustrates a flow diagram of an exemplary method 300 of implementing a sequential logical User Defined Primitive (UDP), according to an embodiment of the present disclosure. The method 300 may be performed by, for example, the electronic device 100 of FIG. 1A, and more particularly, by the simulation tool 120 running on the electronic device 100. The method 300 may include the following steps.

In step S302, the emulation tool 120 can receive a description of a User Defined Primitive (UDP) (e.g., the description 200 shown in FIG. 2A). The description includes at least a first input (e.g., the first input i1 shown in fig. 2A), a second input (e.g., the second input i2 shown in fig. 2A), and outputs associated with the first input and the second input (e.g., the last-time output value q and the current-time output value q + shown in fig. 2A).

In some embodiments, the UDP description may include a UDP state table.

In step S304, the simulation tool 120 may generate a first truth table (e.g., the first truth table 220 shown in fig. 2C) and a second truth table corresponding to the first input and the second input, respectively, according to the description of the UDP. Wherein the first truth table includes a first previous input value (e.g., previous input value I1 shown in fig. 2C), a second previous input value (e.g., previous input value I2 shown in fig. 2C), and a previous output value (e.g., previous output value q shown in fig. 2C) at a previous time instant of the first input, the second input, and the output, and a first current input value (e.g., current input value I1+ shown in fig. 2C) at a current time instant of the first input.

In step S306, the simulation tool 120 may determine a first element value in the first truth table (e.g., the first truth table 220 shown in fig. 2C) corresponding to the first previous input value (e.g., the previous input value I1 shown in fig. 2C), the second previous input value (e.g., the previous input value I2 shown in fig. 2C), the previous output value (e.g., the previous output value q shown in fig. 2C), and the first current input value (e.g., the current input value I1+ shown in fig. 2C).

In some embodiments, the first truth table also includes an element position (e.g., the first column of "element position" of the first truth table 220 shown in FIG. 2C). In some embodiments, the element position may be configured as a position index of the first truth table, and the value of the element position is determined by the number of states of the first current input value (e.g., the four states of the current input value I1+ of the first input I1 shown in fig. 2C, the number of states being 4). For example, the values of the element positions in the first truth table 220 may be 0,4,8, \ 8230;, 104.

In some embodiments, the simulation tool 120 may determine the current output value of the UDP (e.g., q + = x = 3) from the description of the UDP (e.g., the description 200 shown in fig. 2A) according to the first prior input value (e.g., I1= x), the first current input value (e.g., I1+ = 0), the second prior input value (e.g., I2= x), and the prior output value (e.g., q = x). The simulation tool 120 may determine the element position (e.g., element position 36) in the first truth table according to the first current input value (e.g., I1+ = 0), the second previous input value (e.g., I2= x), and the current output value (e.g., q + = x). The simulation tool 120 may calculate the first element value based on the element position and the current output value.

In some embodiments, the simulation tool 120 may use the sum of the value of the element position (e.g., the value of the element position 36) and the current output value (e.g., q + = 3) as the first element value (e.g., 36+3= 39).

In some embodiments, the simulation tool 120 may generate a second truth table corresponding to the second input using the method of generating the first truth table to determine the second element value in the second truth table.

In step S308, the simulation tool 120 may determine a current output value of the output of the UDP at the current time in the first truth table based on the first element value (e.g., 39).

In some embodiments, simulation tool 120 may obtain the lower two bits of data of the first element value (e.g., lower two bits of data 11 of 39) as the current output value (e.g., 3).

In other embodiments, the simulation tool 120 may obtain the upper data (e.g., the upper data 100100 of 39) other than the lower two data of the first element value. The high data may indicate an element position (e.g., element position 36) of the current output value in the first truth table. The simulation tool 120 may determine the row in the first truth table (e.g., the row indicated by element position 36) in which the current output value is located based on the element position. The simulation tool 120 may determine the current output value from the row (e.g., q columns of values x =3 for the row).

In still other embodiments, the simulation tool 120 may perform a modulo operation based on the first element value (e.g., 39) and the state number (e.g., state number 4) of the first current input value. The simulation tool 120 may take the result of the modulo operation as the current output value (e.g., operation result 3).

In some embodiments, the UDP may receive the new first input and the new second input simultaneously. The simulation tool 120 may determine a prior output value of UDP in the first truth table based on the first element value. The simulation tool 120 may then proceed to determine the current output value of the UDP in the second truth table based on the second element value.

The present disclosure also provides an electronic device implementing sequential logic user-defined primitives. The electronic device may be the electronic device 100 shown in fig. 1A. The electronic device 100 may be configured to execute a computer program stored in the memory 104 to implement a method of implementing sequential logic user-defined primitives, such as the exemplary method described above (e.g., the method 300 shown in fig. 3), consistent with the present disclosure. And will not be described in detail herein.

The present disclosure also provides a non-transitory computer-readable storage medium. The non-transitory computer readable storage medium stores a set of instructions for the electronic device 100. The set of instructions, when executed, cause the electronic device 100 to implement a method of implementing sequential logical user-defined primitives, such as the exemplary method described above (e.g., method 300 shown in fig. 3), consistent with the present disclosure. And will not be described in detail herein.

Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The foregoing description of specific embodiments of the present disclosure has been described. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, also technical features between the above embodiments or different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made without departing from the spirit or scope of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A method of implementing a User-Defined Primitive (UDP), comprising:

receiving a description of the user-defined primitive, the description including at least a first input, a second input, and an output associated with the first input and the second input;

generating a first truth table and a second truth table corresponding to the first input and the second input, respectively, according to the description of the user-defined primitive, wherein the first truth table includes a first previous input value, a second previous input value, and a previous output value of the first input, the second input, and the output at a previous time, and a first current input value of the first input at a current time;

determining a first element value in the first truth table corresponding to the first prior input value, the second prior input value, the prior output value, and the first current input value; and

determining, in the first truth table, a current output value of the output of the user-defined primitive at a current time based on the first element value.

2. The method of claim 1, wherein the first truth table further includes an element position, and determining a first element value in the first truth table corresponding to the first prior input value, the second prior input value, the prior output value, and the first current input value further comprises:

determining the current output value from the description of the user-defined primitive according to the first prior input value, the first current input value, the second prior input value, and the prior output value;

determining the element position in the first truth table based on the first current input value, the second prior input value, and the current output value; and

calculating the first element value according to the element position and the current output value.

3. The method of claim 2, wherein the element position is configured as a position index of the first truth table, and a value of the element position is determined by a state number of the first current input value.

4. The method of claim 3, wherein computing the first element value as a function of the element position and the current output value further comprises:

using a sum of the value of the element position and the current output value as the first element value.

5. The method of claim 4, wherein determining, based on the first element value, a current output value of the output of the user-defined primitive at a current time in the first truth table further comprises:

and acquiring the lower two bits of data of the first element value as the current output value.

6. The method of claim 4, wherein determining, in the first truth table, a current output value of the output of the user-defined primitive at a current time based on the first element value further comprises:

acquiring high-order data except the low two-order data of the first element value, wherein the high-order data indicates the element position of the current output value in the first truth table;

determining a row of the current output value in the first truth table according to the high-order data; and

determining the current output value from the row.

7. The method of claim 4, wherein determining, in the first truth table, a current output value of the output of the user-defined primitive at a current time based on the first element value further comprises:

performing a modulo operation based on the first element value and a state number of the first current input value; and

and taking the result of the modulus operation as the current output value.

8. The method of any of claims 1 to 7, wherein the second truth table comprises first prior input values, second prior input values, and prior output values for the first input, the second input, and the output at a previous time instant, and a second current input value for the second input at a current time instant;

the method further comprises the following steps:

determining a second element value in the second truth table corresponding to the first prior input value, the second prior input value, the prior output value, and the second current input value;

determining the prior output value of the user-defined primitive in the first truth table based on the first element value; and

determining the current output value of the user-defined primitive in the second truth table based on the second element value.

9. An electronic device implementing sequential logic user-defined primitives, comprising:

a memory for storing a set of instructions; and

at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any of claims 1-8.

10. A non-transitory computer readable storage medium storing a set of instructions of an electronic device, which when executed, cause the electronic device to perform the method of any of claims 1 to 8.