CN115499714A - Switch port verification method and device and switch - Google Patents

Switch port verification method and device and switch Download PDF

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Publication number
CN115499714A
CN115499714A CN202211152868.4A CN202211152868A CN115499714A CN 115499714 A CN115499714 A CN 115499714A CN 202211152868 A CN202211152868 A CN 202211152868A CN 115499714 A CN115499714 A CN 115499714A
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China
Prior art keywords
port
tested
signal pin
circuit
management chip
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Chinese (zh)
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卢亮
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Guangdong Dongqin Technology Co ltd
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Guangdong Dongqin Technology Co ltd
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Priority to CN202211152868.4A priority Critical patent/CN115499714A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/02—Constructional details
    • H04Q1/13—Patch panels for monitoring, interconnecting or testing circuits, e.g. patch bay, patch field or jack field; Patching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to the technical field of communication equipment verification, and discloses a method and a device for verifying a port of a switch and the switch, which are realized based on a port test fixture, wherein the port test fixture comprises test contacts for establishing one-to-one corresponding electric connection relation with each signal pin to be tested in a port to be tested; the method comprises the following steps: when the test contact and the signal pin to be tested establish an electrical connection relation, controlling a corresponding register of the port to be tested to execute a preset operation, and acquiring the state change of a circuit where the signal pin to be tested is located; and determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located. Because the manual operation with complicated steps and difficult operation is omitted, the efficiency of verifying the ports of the switch can be effectively improved, and the verification difficulty is reduced.

Description

Switch port verification method and device and switch
Technical Field
The invention relates to the technical field of communication equipment verification, in particular to a method and a device for verifying a switch port and a switch.
Background
In order to ensure the functional correctness of a port management chip (CPLD/FPGA) and the connectivity of a line on a board, all low-speed signals of each port need to be verified, and the contents to be verified mainly include: 1. the correctness of the mapping between the register in the port management chip and the pin is ensured; 2. the port management chip has pin-to-socket signal connectivity. Meanwhile, the signals to be verified include: a port status signal for mapping a port status signal pin input to a status register; and the port control signal is used for controlling the state of the port control signal controlled by the register.
In the prior art, a port low-speed signal (control/status signal) is realized in a manual test mode, which specifically includes the following steps: for port control signals, the state of the control signals is changed by operating the corresponding control register, and then the corresponding control signal state is observed by using a signal testing instrument (an oscilloscope, a universal meter and the like), so that the connectivity of the control signals is judged; for the port state signal, the corresponding state signal state is determined by changing the corresponding state signal level (grounding/pulling up) and reading the state register value, so as to judge the connectivity of the state signal.
Because each type of port comprises a plurality of port low-speed signals needing to be verified, the verification efficiency is low by adopting the existing test mode; meanwhile, the existing verification mode has higher operation difficulty, on one hand, in order to ensure the correct mapping of the signal and the register, the register end and the signal end need to be synchronously operated, and the single person operation is difficult; on the other hand, in order to ensure that the whole hardware channel is verified, the test/control point is positioned in the port, and the signal extraction is difficult.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method and a device for verifying a port of a switch and the switch, and solves the problems of low efficiency and high operation difficulty in verifying a low-speed signal of the port in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a method for verifying a port of an exchanger is realized on the basis of a port verifying device of the exchanger, wherein the port verifying device of the exchanger comprises a port testing clamp, and the port testing clamp comprises testing contacts for establishing one-to-one corresponding electric connection relation with each signal pin to be tested in a port to be tested;
the switch port verification method comprises the following steps:
when the test contact and the signal pin to be tested establish an electrical connection relation, controlling a corresponding register of the port to be tested to execute a preset operation, and acquiring the state change of a circuit where the signal pin to be tested is located;
and determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.
Optionally, the port test fixture includes a control signal test contact for establishing an electrical connection relationship with a control signal pin to be tested, and a signal lamp is arranged on a circuit where the control signal test contact is located;
the acquiring of the state change of the circuit where the signal pin to be detected is located includes:
acquiring the state change of a circuit where the control signal pin to be detected is located based on the change of the signal lamp;
the determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located includes:
and determining the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and the corresponding port in the port management chip.
Optionally, the port test fixture further includes a state signal test contact for establishing an electrical connection relationship with a state signal pin to be tested, and the state signal test contact is connected to a circuit where the control signal test contact is located;
the obtaining of the state change of the circuit where the signal pin to be detected is located further includes:
reading a state register value of the port management chip to acquire the state change of a circuit where the state signal pin to be detected is located;
the determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located further comprises:
and determining the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip and the connectivity of the state signal pin to be tested and the corresponding port in the port management chip according to the value of the state register.
Optionally, the test fixture further includes an in-place signal test contact for establishing an electrical connection relationship with an in-place signal pin to be tested, and a circuit where the in-place signal test contact is located is grounded;
the obtaining of the state change of the circuit where the signal pin to be detected is located further includes:
reading an in-place register value of the port management chip to acquire the state change of a circuit where the in-place signal pin to be detected is located;
the method for determining the functional correctness and the circuit connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located further comprises the following steps:
and determining the mapping correctness of the to-be-tested in-place signal pin and a corresponding in-place register in the port management chip and the connectivity of the to-be-tested in-place signal pin and a corresponding port in the port management chip according to the value of the in-place register.
Optionally, after obtaining the state change of the circuit where the signal pin to be detected is located, the method further includes:
and displaying the state change of the circuit where the signal pin to be tested is located.
The invention also provides a switch port verification device, which is applied to a port management chip and comprises the following components:
the port test fixture is used for connecting a port to be tested and comprises test contacts which establish one-to-one corresponding electrical connection relation with each signal pin to be tested in the port to be tested;
the acquisition module is used for controlling a corresponding register of the port to be tested to execute preset operation and acquiring the state change of a circuit where the signal pin to be tested is located when the test contact is electrically connected with the signal pin to be tested;
and the determining module is used for determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.
Optionally, the port test fixture includes a control signal test contact for establishing an electrical connection relationship with a control signal pin to be tested, and a signal lamp is arranged on a circuit where the control signal test contact is located;
the acquisition module is used for acquiring the state change of a circuit where the control signal pin to be detected is located based on the change of the signal lamp;
the determining module is used for determining the mapping correctness of the control signal pin to be tested and a corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and a corresponding port in the port management chip according to the state change of the circuit where the control signal pin to be tested is located.
Optionally, the port test fixture further includes a state signal test contact for establishing an electrical connection relationship with a state signal pin to be tested, and the state signal test contact is connected to a circuit where the control signal test contact is located;
the acquisition module is used for reading a state register value of the port management chip so as to acquire the state change of a circuit where the state signal pin to be detected is located;
the determining module is used for determining the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip and the connectivity of the state signal pin to be tested and the corresponding port in the port management chip according to the value of the state register.
Optionally, the test fixture further includes an in-place signal test contact for establishing an electrical connection relationship with an in-place signal pin to be tested, and a circuit where the in-place signal test contact is located is grounded;
the acquisition module is used for reading an in-place register value of the port management chip to acquire the state change of a circuit where the in-place signal pin to be detected is located;
the determining module is used for determining the mapping correctness of the to-be-detected in-place signal pin and the corresponding in-place register in the port management chip and the connectivity of the to-be-detected in-place signal pin and the corresponding port in the port management chip according to the value of the in-place register.
The invention also provides a switch, which comprises the switch port verification device.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method and a device for verifying a port of an exchanger and the exchanger, wherein a port test fixture establishes a one-to-one corresponding electrical connection relation with each signal pin to be tested in a port to be tested, and the state change of a circuit where the signal pin to be tested is located is obtained when the electrical connection relation is established successfully, so that the functional correctness and the circuit connectivity between the port to be tested and a port management chip are determined, and the port verification of the exchanger is further realized. The manual operation with complicated steps and difficult operation is omitted, so that the efficiency of verifying the port of the switch can be effectively improved, and the verification difficulty is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor.
FIG. 1 is a block diagram of a switch port low speed signal management in the prior art;
FIG. 2 is a circuit diagram of one of the port test fixtures used in the switch port verification method according to the present invention;
FIG. 3 is a flow chart of a switch port verification method according to the present invention;
fig. 4 is a flowchart of step S1 in a method for verifying a port of a switch according to the present invention;
fig. 5 is a flowchart of step S2 in the switch port verification method provided in the present invention;
fig. 6 is another flowchart of step S1 in the method for verifying a switch port according to the present invention;
fig. 7 is an automatic verification flowchart of a switch port verification method according to the present invention;
fig. 8 is an automatic verification timing chart of a switch port verification method according to the present invention;
fig. 9 is a block diagram of a switch port verification apparatus according to the present invention.
In the above figures: 10. a port test fixture; 20. an acquisition module; 30. a determining module; 40. a port to be tested; 50. and displaying the module.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that the detailed description of the invention is intended to be illustrative of the invention and is not intended to limit the invention. Wherein the exemplary embodiments are described as processes or methods depicted as flowcharts; although a flowchart may describe the operations or processing of steps in a certain order, many of the operations or steps can be performed in parallel, concurrently or simultaneously, and the order of the operations can be re-arranged. When its operations or steps are completed, the corresponding process may be terminated, with additional steps not included in the figures. The aforementioned processes may correspond to methods, functions, procedures, subroutines, and the like, and the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
The term "include" and variations thereof as used herein are intended to be open-ended, i.e., "including but not limited to". The term "based on" is "based at least in part on". The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings; it is to be understood that only some of the structures associated with the present invention are shown in the drawings for convenience of description, not all of the structures.
Referring to fig. 1, which is a block diagram of a common switch port low-speed signal management in the prior art, a master controller controls/obtains a port low-speed signal state by accessing a register inside a port management chip, so as to achieve a purpose of port management.
In order to ensure the functional correctness of a port management chip (CPLD/FPGA) and the connectivity of a circuit on a board card, all low-speed signals of each port need to be verified, and the parts needing to be verified mainly comprise: 1. the correctness of the mapping between the register in the port management chip and the pin is ensured; 2. signal connectivity between a pin of the port management chip and a port socket; the signals to be verified include two types, specifically, a port state signal and a port control signal, the port state signal is used for mapping a pin input of the port state signal to a state register, and the port control signal is used for controlling a state of a port control signal of the register.
Because each type of port comprises a plurality of port low-speed signals needing to be verified, if the existing testing mode is adopted to verify the plurality of signals of each port in sequence, the verification efficiency is low; meanwhile, on one hand, in order to ensure the correct mapping of the signal and the register, the register end and the signal end need to be operated synchronously, and the operation is difficult for a single person; on the other hand, in order to ensure that the whole hardware channel is verified, the test/control point is positioned in the port, so that the signal is difficult to lead out, and the operation difficulty of the existing manual operation mode is higher.
To solve the foregoing problems, the present invention provides a switch port verification scheme, which is described in detail below with reference to the accompanying drawings.
Some of the terms referred to hereinafter are explained:
FPGA: a field programmable gate array;
a CPLD: a complex programmable logic device;
QSFP: a four-channel SFP interface.
Referring to fig. 2, an embodiment of the present invention provides a method for verifying a switch port, which is implemented based on a switch port verification apparatus.
The switch port verification device comprises a port test fixture, wherein the port test fixture comprises test contacts used for establishing one-to-one corresponding electric connection relation with each signal pin to be tested in a port to be tested.
In this embodiment, the switch port verification apparatus is improved based on a loopback, for example, for a QSFP port, the switch port verification apparatus is improved based on a QSFP loopback.
Specifically, the port test fixture includes a control signal test contact for establishing an electrical connection with a control signal pin to be tested, and a signal lamp is disposed on a circuit where the control signal test contact is located.
Taking the QSFP port as an example, two control signal test contacts are arranged, a circuit where the two control signal test contacts are arranged is respectively connected with a signal lamp LED _ R and a signal lamp LED _ G, and one ends of the signal lamp LED _ R and the signal lamp LED _ G, which are far away from the signal test contacts, are respectively connected to a power supply VCC through a resistor R1 and a resistor R2. The two control signal test contacts are respectively used for establishing an electrical connection relation with the control signal pins to be tested corresponding to the control signal RST and the control signal LPMOD.
Furthermore, the port test fixture also comprises a state signal test contact for establishing an electrical connection relation with the state signal pin to be tested; taking the QSFP port as an example, one end of the state signal test contact is used to establish an electrical connection relationship with a state signal pin to be tested corresponding to the state signal INT, and the other end of the state signal test contact is connected to a circuit where the control signal test contact is located.
Furthermore, the test fixture also comprises an in-place signal test contact for establishing an electrical connection relation with the in-place signal pin to be tested; taking QSFP port as an example, one end of the in-place signal test contact is used for establishing an electrical connection relation with an in-place signal pin to be tested corresponding to the in-place signal ABS, and the other end is grounded.
Referring to fig. 3 to fig. 5, in the present embodiment, the method for verifying a switch port includes the following steps:
s1, when the test contact and the signal pin to be tested establish an electrical connection relation, controlling a corresponding register of the port to be tested to execute a preset operation, and obtaining the state change of a circuit where the signal pin to be tested is located.
It can be understood that, in this embodiment, the implementation is realized based on a preset automated test script, before the test contact establishes an electrical connection relationship with the signal pin to be tested, the automated test script needs to be run once, and initial values of registers corresponding to all ports are confirmed, so as to ensure accuracy of a test result.
Specifically, the step S1 specifically includes the following steps to implement state change of a circuit in which the control signal pin to be tested, the state signal pin to be tested, and the in-place signal pin to be tested are located.
S11, acquiring state change of a circuit where a control signal pin to be detected is located based on the change of the signal lamp;
s12, reading a state register value of the port management chip to acquire the state change of a circuit where a state signal pin to be detected is located;
and S13, reading the value of the in-place register of the port management chip to acquire the state change of the circuit where the in-place signal pin to be detected is located.
And S2, determining the functional correctness and the circuit connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.
Specifically, the step S2 includes the following steps to verify the control signal pin to be tested, the state signal pin to be tested, and the in-place signal pin to be tested:
s21, determining the mapping correctness of the control signal pin to be tested and a corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and a corresponding port in the port management chip according to the state change of a circuit in which the control signal pin to be tested is positioned;
s22, determining the mapping correctness of the state signal pin to be tested and a corresponding state register in the port management chip and the connectivity of the state signal pin to be tested and a corresponding port in the port management chip according to the value of the state register;
s23, according to the value of the in-place register, determining the mapping correctness of the to-be-tested in-place signal pin and the corresponding in-place register in the port management chip and the connectivity of the to-be-tested in-place signal pin and the corresponding port in the port management chip.
It is understood that the sequence of steps S11 to S13 and steps S21 to S23 is not limited by the foregoing description sequence, and the sequence of these steps may be adjusted according to the adjustment in practical applications.
In this embodiment, after obtaining the state change of the circuit where the pin of the signal to be detected is located, the method further includes:
and S14, displaying the state change of the circuit where the signal pin to be detected is located.
It is understood that the circuit state change may be displayed by printing it in a graphical manner, or may be displayed in a graphical manner using a display screen.
Referring to fig. 7, based on the foregoing steps, the following takes the QSFP port as an example to further describe the switch port verification method provided in this embodiment:
when the port test fixture is connected with a port to be tested, an in-place signal on an in-place signal pin to be tested is pulled down, the position of the port to be tested is determined by monitoring an in-place register (ABS register), the mapping correctness of the in-place register and the in-place signal pin to be tested is determined by comparing the in-place register with the actual position, and the connectivity of the in-place signal pin to be tested and a corresponding port in a port management chip is determined.
After the position of the port to be tested is determined, the control register corresponding to the port to be tested can be operated through a preset automatic test script, corresponding operation is executed through the control register to change the state of the control signal, the state change of a circuit where the control signal pin to be tested is located is obtained based on the change of the signal lamp, and then the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and the corresponding port in the port management chip are determined.
Furthermore, because the state change of the control signal can cause the change of the state register corresponding to the port to be tested, the state change of the circuit where the state signal pin to be tested is located is obtained by reading the state register value of the port management chip in a polling mode; then, based on the value of the status register, the mapping correctness of the status signal pin to be tested and the corresponding status register in the port management chip and the connectivity of the status signal pin to be tested and the corresponding port in the port management chip are determined.
Referring to fig. 8, it can be seen from the automatic verification timing sequence in the figure that the verification time of a single port in the present invention is reduced to about 10 seconds, whereas the verification time of a single port in the conventional method needs about 2 minutes, so the verification efficiency of the verification scheme provided by the present invention can be improved by about 10 times, i.e., the verification efficiency is effectively improved.
Referring to fig. 9 and referring to fig. 2 again, based on the foregoing embodiments, the present invention further provides a switch port verification apparatus, applied to a port management chip, including:
the port test fixture 10 is used for connecting the port 40 to be tested, and comprises test contacts which establish one-to-one corresponding electrical connection relation with each signal pin to be tested in the port 40 to be tested;
the obtaining module 20 is configured to control a corresponding register of the port to be tested 40 to execute a predetermined operation when the test contact and the signal pin to be tested establish an electrical connection relationship, and obtain a state change of a circuit in which the signal pin to be tested is located;
the determining module 30 is configured to determine functional correctness and line connectivity between the port to be tested 40 and the port management chip based on a state change of a circuit in which the signal pin to be tested is located.
The switch port verification device comprises a port test fixture 10, wherein the port test fixture 10 comprises test contacts for establishing a one-to-one corresponding electrical connection relation with each signal pin to be tested in a port 40 to be tested.
In this embodiment, the switch port verification apparatus is improved based on a loopback, for example, for a QSFP port, the switch port verification apparatus is improved based on a QSFP loopback.
Specifically, the port test fixture 10 includes a control signal test contact for establishing an electrical connection relationship with a control signal pin to be tested, and a signal lamp is disposed on a circuit where the control signal test contact is located.
Taking the QSFP port as an example, two control signal test contacts are provided, the circuits where the two control signal test contacts are located are respectively connected with a signal lamp LED _ R and a signal lamp LED _ G, and one ends of the signal lamp LED _ R and the signal lamp LED _ G, which are far away from the signal test contacts, are respectively connected to the power supply VCC through a resistor R1 and a resistor R2. The two control signal test contacts are respectively used for establishing an electrical connection relation with the control signal pins to be tested corresponding to the control signal RST and the control signal LPMOD.
The port test fixture 10 further includes a state signal test contact for establishing an electrical connection with a state signal pin to be tested; one end of the state signal test contact is used for establishing an electric connection relation with a state signal pin to be tested corresponding to the state signal INT, and the other end of the state signal test contact is connected with a circuit where the control signal test contact is located.
The test fixture also comprises an in-place signal test contact for establishing an electrical connection relation with the in-place signal pin to be tested; one end of the in-place signal test contact is used for establishing an electrical connection relation with an in-place signal pin to be tested corresponding to the in-place signal ABS, and the other end of the in-place signal test contact is grounded.
The obtaining module 20 is configured to execute the following steps to implement state change of a circuit in which the control signal pin to be tested, the state signal pin to be tested, and the in-place signal pin to be tested are located: acquiring the state change of a circuit where a control signal pin to be detected is located based on the change of a signal lamp; reading a state register value of a port management chip to acquire the state change of a circuit where a state signal pin to be detected is located; and reading the in-place register value of the port management chip to acquire the state change of the circuit where the in-place signal pin to be detected is located.
The determining module 30 is configured to execute the following steps to verify the control signal pin to be tested, the status signal pin to be tested, and the in-place signal pin to be tested: determining the mapping correctness of the control signal pin to be tested and a corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and a corresponding port in the port management chip according to the state change of a circuit in which the control signal pin to be tested is positioned; according to the value of the state register, determining the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip and the connectivity of the state signal pin to be tested and the corresponding port in the port management chip; and determining the mapping correctness of the to-be-tested in-place signal pin and the corresponding in-place register in the port management chip and the connectivity of the to-be-tested in-place signal pin and the corresponding port in the port management chip according to the value of the in-place register.
The following takes QSFP ports as an example to further describe the switch port verification apparatus provided in this embodiment:
when the port test fixture 10 is connected to the port 40 to be tested, the in-place signal on the in-place signal pin to be tested is pulled low, the obtaining module 20 monitors the in-place register (ABS register), the determining module 30 determines the position of the port 40 to be tested, and the mapping correctness between the in-place register and the in-place signal pin to be tested and the connectivity between the in-place signal pin to be tested and the corresponding port in the port management chip are determined by comparing with the actual position.
After the position of the port 40 to be tested is determined, the obtaining module 20 may operate a control register corresponding to the port 40 to be tested through a preset automatic test script, execute corresponding operations through the control register to change the state of the control signal, and obtain the state change of the circuit where the control signal pin to be tested is located based on the change of the signal lamp, and the determining module 30 determines the mapping correctness of the control signal pin to be tested and the corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and the corresponding port in the port management chip.
Further, since the state change of the control signal may cause a change of a state register corresponding to the port to be tested 40, at this time, the obtaining module 20 obtains the state change of the circuit where the state signal pin to be tested is located by reading the state register value of the port management chip in a polling manner; then, the determining module 30 determines, based on the value of the status register, the mapping correctness of the status signal pin to be tested and the corresponding status register in the port management chip, and the connectivity of the status signal pin to be tested and the corresponding port in the port management chip.
In this embodiment, the switch port verification apparatus further includes a display module 50, where the display module 50 is configured to display the state change of the circuit where the signal pin to be detected is located after obtaining the state change of the circuit where the signal pin to be detected is located.
Specifically, the display module 50 may be a printer, and displays the state change of the circuit by printing the state change in a graph manner; the state change of the circuit can also be displayed in a graph mode by using the display screen.
Based on the foregoing embodiments, an embodiment of the present invention provides a switch, including the switch port authentication apparatus described in the foregoing embodiments, and capable of executing the foregoing switch port authentication method.
Based on the foregoing embodiments, the present invention has the following advantages:
1. the port test fixture 10 modified by the loop back has a simple circuit structure and is easy to realize;
2. all low-speed signal verification can be better included, and no artificial omission is generated;
3. commands do not need to be manually input, the step of sequentially verifying a plurality of signals of each port is omitted, and the difficulty of test verification is greatly reduced;
4. referring to fig. 8 again, the time required for verifying a single port in the conventional manner is about 2 minutes, the scheme provided by the present invention only requires about 10 seconds, and the verification efficiency is improved by more than 10 times.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A switch port verification method is characterized by being realized based on a switch port verification device, wherein the switch port verification device comprises a port test fixture, and the port test fixture comprises test contacts for establishing one-to-one corresponding electrical connection relation with each signal pin to be tested in a port to be tested;
the switch port verification method comprises the following steps:
when the test contact and the signal pin to be tested establish an electrical connection relation, controlling a corresponding register of the port to be tested to execute a preset operation, and acquiring the state change of a circuit where the signal pin to be tested is located;
and determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.
2. The switch port verification method according to claim 1, wherein the port test fixture includes a control signal test contact for establishing an electrical connection relationship with a control signal pin to be tested, and a signal lamp is arranged on a circuit of the control signal test contact;
the acquiring of the state change of the circuit where the signal pin to be detected is located includes:
acquiring the state change of a circuit where the control signal pin to be detected is located based on the change of the signal lamp;
the determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located includes:
and determining the mapping correctness of the control signal pin to be tested and a corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and a corresponding port in the port management chip according to the state change of the circuit in which the control signal pin to be tested is positioned.
3. The switch port verification method according to claim 2, wherein the port test fixture further comprises a status signal test contact for establishing an electrical connection with a status signal pin to be tested, the status signal test contact being connected to a circuit of the control signal test contact;
the obtaining of the state change of the circuit where the signal pin to be detected is located further includes:
reading a state register value of the port management chip to acquire the state change of a circuit where the state signal pin to be detected is located;
the method for determining the functional correctness and the circuit connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located further comprises the following steps:
and determining the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip and the connectivity of the state signal pin to be tested and the corresponding port in the port management chip according to the value of the state register.
4. The switch port verification method according to claim 2, wherein the test fixture further comprises an in-place signal test contact for establishing an electrical connection relationship with an in-place signal pin to be tested, and a circuit where the in-place signal test contact is located is grounded;
the obtaining of the state change of the circuit where the signal pin to be detected is located further includes:
reading an in-place register value of the port management chip to acquire the state change of a circuit where the in-place signal pin to be detected is located;
the determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located further comprises:
and determining the mapping correctness of the to-be-tested in-place signal pin and a corresponding in-place register in the port management chip and the connectivity of the to-be-tested in-place signal pin and a corresponding port in the port management chip according to the value of the in-place register.
5. The method for verifying the switch port according to claim 1, wherein after the obtaining the state change of the circuit where the signal pin to be tested is located, the method further comprises:
and displaying the state change of the circuit where the signal pin to be detected is located.
6. A switch port verification device is applied to a port management chip and comprises:
the port test fixture is used for connecting a port to be tested and comprises test contacts which establish one-to-one corresponding electrical connection relation with each signal pin to be tested in the port to be tested;
the acquisition module is used for controlling a corresponding register of the port to be tested to execute preset operation and acquiring the state change of a circuit where the signal pin to be tested is located when the test contact and the signal pin to be tested establish an electric connection relation;
and the determining module is used for determining the functional correctness and the line connectivity between the port to be tested and the port management chip based on the state change of the circuit where the signal pin to be tested is located.
7. The switch port verification device according to claim 6, wherein the port test fixture comprises a control signal test contact for establishing an electrical connection relationship with a control signal pin to be tested, and a signal lamp is arranged on a circuit of the control signal test contact;
the acquisition module is used for acquiring the state change of a circuit where the control signal pin to be detected is located based on the change of the signal lamp;
the determining module is used for determining the mapping correctness of the control signal pin to be tested and a corresponding control register in the port management chip and the connectivity of the control signal pin to be tested and a corresponding port in the port management chip according to the state change of the circuit where the control signal pin to be tested is located.
8. The switch port verification device according to claim 7, wherein the port test fixture further comprises a status signal test contact for establishing an electrical connection with a status signal pin to be tested, the status signal test contact being connected to a circuit where the control signal test contact is located;
the acquisition module is used for reading a state register value of the port management chip so as to acquire the state change of a circuit where the state signal pin to be detected is located;
the determining module is used for determining the mapping correctness of the state signal pin to be tested and the corresponding state register in the port management chip and the connectivity of the state signal pin to be tested and the corresponding port in the port management chip according to the value of the state register.
9. The switch port verification device according to claim 7, wherein the test fixture further comprises an in-place signal test contact for establishing an electrical connection with an in-place signal pin to be tested, and a circuit where the in-place signal test contact is located is grounded;
the acquisition module is used for reading an in-place register value of the port management chip to acquire the state change of a circuit where the in-place signal pin to be detected is located;
the determining module is used for determining the mapping correctness of the to-be-detected in-place signal pin and the corresponding in-place register in the port management chip and the connectivity of the to-be-detected in-place signal pin and the corresponding port in the port management chip according to the value of the in-place register.
10. A switch comprising a switch port validation apparatus according to any of claims 6 to 9.
CN202211152868.4A 2022-09-21 2022-09-21 Switch port verification method and device and switch Pending CN115499714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211152868.4A CN115499714A (en) 2022-09-21 2022-09-21 Switch port verification method and device and switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211152868.4A CN115499714A (en) 2022-09-21 2022-09-21 Switch port verification method and device and switch

Publications (1)

Publication Number Publication Date
CN115499714A true CN115499714A (en) 2022-12-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211152868.4A Pending CN115499714A (en) 2022-09-21 2022-09-21 Switch port verification method and device and switch

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Country Link
CN (1) CN115499714A (en)

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