CN115499013A - Power frequency suppression filter suitable for Sigma-delta ADC - Google Patents

Power frequency suppression filter suitable for Sigma-delta ADC Download PDF

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CN115499013A
CN115499013A CN202211249026.0A CN202211249026A CN115499013A CN 115499013 A CN115499013 A CN 115499013A CN 202211249026 A CN202211249026 A CN 202211249026A CN 115499013 A CN115499013 A CN 115499013A
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sinc1
filter
power frequency
stage
sigma
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贺克军
龙善丽
童紫平
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H2017/0072—Theoretical filter design
    • H03H2017/0081—Theoretical filter design of FIR filters

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Abstract

The invention discloses a power frequency suppression filter suitable for a Sigma-delta ADC (analog to digital converter), which comprises SINC1 filters SINC1_ 1-SINC 1_6, FIR filters F1 and F2, extraction modules M1-M6, data selectors MUX1 and MUX2, and mean value filters MF1 and MF2; the power frequency suppression filter circuit applicable to the Sigma-delta ADC provided by the invention can simultaneously suppress power frequency interference of 50Hz and 60 Hz; the invention adopts a multistage SINC1 filter and an FIR cascade structure, and can complete power frequency suppression under a set output sampling frequency; the SINC1 filter multiplexing structure is adopted, so that the circuit area and the power consumption are reduced; the invention adopts the FIR filter multiplexing structure, reduces the use resource of the multiplier to the maximum extent, and optimizes the circuit area and the power consumption.

Description

Power frequency suppression filter suitable for Sigma-delta ADC
Technical Field
The invention relates to the field of filters, in particular to a power frequency suppression filter suitable for a Sigma-delta ADC.
Background
The power frequency interference is caused by a power system, the power frequency in China is composed of 50Hz and harmonic waves thereof, the amplitude is about 50% of the electrocardiosignal, and the power frequency in other countries is also 60 Hz. When the circuit is used for measuring high-precision sensitive signals, the power frequency interference can submerge the measuring signals in power frequency waveforms, and the measuring stability is seriously influenced. The Sigma-delta ADC is commonly used for high-precision signal measurement, and a digital filter circuit is usually integrated in the Sigma-delta ADC, so that a corresponding digital trap needs to be designed by hardware according to the output frequency of the Sigma-delta ADC, so as to filter out 50Hz or 60Hz power frequency and suppress power frequency interference.
The simplest trap filter structure realized by adopting a second-order single-pole IIR filter has the following transfer function:
Figure BDA0003886630190000011
in the formula of omega 0 ＝2πf 0 /f s Represents the notch digital frequency (rad); f. of 0 Is a notch frequency (Hz), f s For the sampling frequency (Hz), r represents the notch depth, the larger the number, the deeper the notch depth. The transfer function can calculate specific coefficients through software, so that the circuit is convenient to realize, and the transfer function for generating parameters is as follows:
Figure BDA0003886630190000012
the implementation structure is shown in fig. 1. The IIR digital filter has a zero and pole structure as shown in the formula (2), namely a feedback loop exists in the system structure, and the positions of the zero and the pole are determined by coefficients, so that the stability of the IIR digital filter system needs to be considered in a key manner during design and is more easily influenced by a finite length algorithm problem; while IIR filter calculations are not advantageous for multi-rate signal processing applications such as Sigma-delta ADCs.
Other commonly used traps are adaptive ones using LMS based algorithms, the main principle of which is shown in fig. 2. x (t) is an input signal superposed by two frequency interference signals, the adaptive filter needs to filter out two interference signals of omega 1 and omega 2, and s (t) is a useful signal needing to be reserved. The adaptive filter needs to use two paths of orthogonal single-frequency signals, such as cos (ω 1 t) and sin (ω 1 t), and adjusts the weights w1 and w2 through an LMS algorithm, so that signals completely identical to interference signals can be synthesized, and limited filtering of the interference signals is realized through subtraction and other operations. The main core of the LMS algorithm notch filter is an FIR filter, where a large number of multiplier resources are used, and two reference signals are required to be input for filtering an interference signal of one frequency, which makes the operation complicated.
Disclosure of Invention
The invention aims at: the power frequency suppression filter suitable for the Sigma-delta ADC is provided, a multistage SINC1 filter and an FIR cascade structure are adopted, and power frequency suppression can be completed under a set output sampling frequency.
The technical scheme of the invention is as follows:
a power frequency suppression filter suitable for a Sigma-delta ADC comprises SINC1 filters SINC1_ 1-SINC 1_6, FIR filters F1 and F2, extraction modules M1-M6, data selectors MUX1 and MUX2, and mean value filters MF1 and MF2;
the input end of an SINC1 filter SINC1_1 is the input end of a power frequency suppression filter, the output end of the SINC1_1 is respectively connected with the input ends of SINC1_2 and SINC1_5, and the output end of the SINC1_2 is respectively connected with the input ends of SINC1_3 and SINC1_ 4; the output end of the SINC1_3 is respectively connected with the input ends of the FIR filter F1 and the extraction module M3; the output ends of the SINC1_4 and the SINC1_5 are respectively connected with the input end of the extraction module M1, and the output end of the FIR filter F1 is connected with the input end of the extraction module M4; the output end of the extraction module M1 is respectively connected with the input ends of an FIR filter F2 and a data selector MUX1, the output end of the FIR filter F2 is connected with the other input end of the data selector MUX1, the output end of the data selector MUX1 is sequentially connected with the extraction modules M2, SINC1_6, the mean value filters MF1 and MF2 in cascade, and the output ends of the mean value filters MF1 and MF2 are respectively connected with the input ends of the extraction modules M5 and M6; the output ends of the extraction modules M3 to M6 are respectively connected with the input end of the data selector MUX2, and the output end of the data selector MUX2 is the output end of the power frequency suppression filter.
Preferably, the SINC1_1 is composed of a 1-stage integrator and a 1-stage 24-differential-delay comb, and provides 50Hz and a notch point at the frequency multiplication position thereof while completing low-pass filtering of a preceding-stage output signal;
the SINC1_2 and the SINC1_4 have the same structure and are both composed of a 1-stage integrator and 1-stage 2-differential-delay combs, and 600Hz and frequency doubling notch points thereof are provided while further filtering is performed;
the SINC1_3 consists of a 1-stage integrator and a 1-stage comb with 20 differential delays, and further provides a notch point of 60Hz and frequency multiplication thereof while filtering;
the SINC1_5 consists of a 1-stage integrator and a 1-stage comb with 11 differential delays, and further filters and provides a trap point of 110Hz and frequency multiplication thereof;
the SINC1_6 consists of a 1-stage integrator and a 1-stage comb with 6 differential delays, finishes filtering after down sampling by a pre-stage filter and provides a trap point of 50Hz and frequency multiplication thereof.
Preferably, the SINC1 filters SINC1_3, SINC1_4, SINC1_5 adopt a multiplexing mode.
Preferably, each of the FIR filters F1 and F2 includes a multiplier-accumulator and a plurality of storage units for storing filter coefficients, the coefficients of each storage unit are multiplied by the data output by the corresponding SINC1 filter, and finally all the products are added.
Preferably, the FIR filters F1 and F2 have the same order, and the two FIR filters use a multiplexing method.
Preferably, the decimation modules M1 to M6 respectively reduce the frequency of the output data to the actually required frequency, and are implemented by using a counter in the circuit, and the count value is adjusted according to the difference of the decimation number.
Preferably, the decimation modules M3 to M6 adopt a multiplexing mode.
The invention has the advantages that:
1. the power frequency suppression filter circuit applicable to the Sigma-delta ADC provided by the invention can simultaneously suppress power frequency interference of 50Hz and 60 Hz;
2. the invention adopts a multistage SINC1 filter and an FIR cascade structure, and can complete power frequency suppression under a set output sampling frequency;
3. the SINC1 filter multiplexing structure is adopted, so that the circuit area and the power consumption are reduced;
4. the invention adopts the FIR filter multiplexing structure, reduces the use resource of the multiplier to the maximum extent, and optimizes the circuit area and the power consumption.
Drawings
The invention is further described with reference to the following figures and examples:
FIG. 1 is a diagram of a typical IIR trap direct type II implementation architecture;
FIG. 2 is a schematic diagram of an adaptive notch filter implementation based on the LMS algorithm;
FIG. 3 is a schematic block diagram of a power frequency suppression filter circuit according to the present invention;
fig. 4 is a block diagram of an implementation architecture of the SINC1 filter according to the present invention;
FIG. 5 is a block diagram of an FIR filter implementation according to the present invention;
FIG. 6 is a block diagram of an implementation of an averaging filter according to the present invention;
FIG. 7 is the simulation result of amplitude-frequency response at the output rate of 27.27Hz in the embodiment;
FIG. 8 is the simulation result of amplitude-frequency response at 25Hz output rate in the embodiment;
FIG. 9 is the simulation result of amplitude-frequency response at 20Hz output rate in the embodiment;
FIG. 10 is the simulation result of the amplitude-frequency response at the output rate of 16.67Hz in the embodiment.
Detailed Description
As shown in fig. 1, the schematic block diagram of the power frequency rejection filter circuit suitable for Sigma-delta ADC according to the present invention is shown, and the filter circuit mainly comprises sub-circuit modules of SINC1 filters SINC1_1 to SINC1_6, fir filters F1 and F2, decimation modules M1 to M6, data selectors MUX1 and MUX2, and averaging filters MF1 and MF 2.
The input end of an SINC1 filter SINC1_1 is the input end of a power frequency suppression filter, the output end of the SINC1_1 is respectively connected with the input ends of SINC1_2 and SINC1_5, and the output end of the SINC1_2 is respectively connected with the input ends of SINC1_3 and SINC1_ 4; the output end of the SINC1_3 is respectively connected with the input ends of the FIR filter F1 and the extraction module M3; the output ends of the SINC1_4 and the SINC1_5 are respectively connected with the input end of the extraction module M1, and the output end of the FIR filter F1 is connected with the input end of the extraction module M4; the output end of the extraction module M1 is respectively connected with the input ends of an FIR filter F2 and a data selector MUX1, the output end of the FIR filter F2 is connected with the other input end of the data selector MUX1, the output end of the data selector MUX1 is sequentially connected with the extraction modules M2, SINC1_6, the mean value filters MF1 and MF2 in a cascade mode, and the output ends of the mean value filters MF1 and MF2 are respectively connected with the input ends of the extraction modules M5 and M6; the output ends of the extraction modules M3 to M6 are respectively connected with the input end of the data selector MUX2, and the output end of the data selector MUX2 is the output end of the power frequency suppression filter.
The input is for example a 1.2kHz frequency signal.
The main architecture of the SINC1 filter is shown in fig. 4, where N represents the number of differential delay units, where:
the SINC1_1 consists of a 1-stage integrator and a 1-stage 24-differential-delay comb, completes low-pass filtering of a preceding-stage output signal and provides 50Hz and a notch point at a frequency doubling position;
the SINC1_2 and the SINC1_4 have the same structure and are both composed of a 1-stage integrator and 1-stage 2-differential-delay combs, and 600Hz and frequency doubling notch points thereof are provided while further filtering is performed;
the SINC1_3 consists of a 1-stage integrator and a 1-stage comb with 20 differential delays, and further provides a notch point of 60Hz and frequency multiplication thereof while filtering;
the SINC1_5 consists of a 1-stage integrator and a 1-stage 11-differential-delay comb, and provides a notch point of 110Hz and frequency multiplication thereof while further filtering;
the SINC1_6 consists of a 1-stage integrator and a 1-stage comb with 6 differential delays, finishes filtering after down sampling by a pre-stage filter and provides a trap point of 50Hz and frequency multiplication thereof. Here, since the SINC1 filters have similar structures, the SINC1 filters SINC1_3, SINC1_4, and SINC1_5 adopt a multiplexing mode at the dashed line box in fig. 3, which saves area.
The FIR filter essentially multiplies each coefficient by the data output by the SINC1 filter, and finally adds all the products together, and the specific architecture is shown in fig. 5, and the whole filter design only needs 1 multiply-accumulate device and a storage unit for storing the filter coefficients, which is equivalent to adding a pipeline design, thereby greatly saving the circuit area. Since the two FIR filters have the same order, as shown in fig. 3, the two FIR filters MF1 and MF2 also adopt a multiplexing manner, which further reduces the hardware consumption of the circuit.
M1 to M6 shown in fig. 3 are commonly used decimation modules in multi-rate signal processing application, and can reduce the frequency of output data to the actually required frequency, and the circuit is usually implemented by using a counter, and only needs to adjust the count value according to the difference of the decimation number, so that the decimation modules M3 to M6 of the final output stage in fig. 3 also use a multiplexing mode.
Fig. 6 shows an implementation architecture of an averaging filter, which is cascaded after SINC1, and the interference suppression capability of 50Hz or 60Hz can be further improved.
Fig. 7 to 10 show the amplitude-frequency response simulation results of the power frequency suppression filter of the present invention at several output rates, and it can be known from fig. 10 that when the data output rate is at least 16.67Hz, the simultaneous suppression of power frequency interference of 50Hz ± 1Hz and 60Hz ± 1Hz can be realized, and the suppression capability is above 90 dB. The filter is particularly suitable for multi-rate signal processing systems such as a Sigma-delta ADC (analog to digital converter), and can realize 50Hz and 60Hz power frequency interference suppression while finishing down-sampling filtering output.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose of the embodiments is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All modifications made in accordance with the spirit of the main technical scheme of the invention are intended to be covered by the scope of the invention.

Claims (7)

1. A power frequency suppression filter suitable for a Sigma-delta ADC (analog to digital converter) is characterized by comprising SINC1 filters SINC1_ 1-SINC 1_6, FIR filters F1 and F2, extraction modules M1-M6, data selectors MUX1 and MUX2 and mean value filters MF1 and MF2;
the input end of an SINC1 filter SINC1_1 is the input end of a power frequency suppression filter, the output end of the SINC1_1 is respectively connected with the input ends of SINC1_2 and SINC1_5, and the output end of the SINC1_2 is respectively connected with the input ends of SINC1_3 and SINC1_ 4; the output end of the SINC1_3 is respectively connected with the input ends of the FIR filter F1 and the extraction module M3; the output ends of the SINC1_4 and the SINC1_5 are respectively connected with the input end of the extraction module M1, and the output end of the FIR filter F1 is connected with the input end of the extraction module M4; the output end of the extraction module M1 is respectively connected with the input ends of an FIR filter F2 and a data selector MUX1, the output end of the FIR filter F2 is connected with the other input end of the data selector MUX1, the output end of the data selector MUX1 is sequentially connected with the extraction modules M2, SINC1_6, the mean value filters MF1 and MF2 in a cascade mode, and the output ends of the mean value filters MF1 and MF2 are respectively connected with the input ends of the extraction modules M5 and M6; the output ends of the extraction modules M3 to M6 are respectively connected with the input end of the data selector MUX2, and the output end of the data selector MUX2 is the output end of the power frequency suppression filter.
2. The power frequency rejection filter for a Sigma-delta ADC of claim 1,
the SINC1_1 consists of a 1-stage integrator and a 1-stage 24-differential-delay comb, completes low-pass filtering of a preceding-stage output signal and provides a 50Hz notch point at a frequency doubling position;
the SINC1_2 and the SINC1_4 have the same structure and are both formed by a stage 1 integrator and a stage 1 comb with 2 differential delays, and the comb is used for further filtering and providing a trap wave point of 600Hz and frequency multiplication thereof;
the SINC1_3 consists of a 1-stage integrator and a 1-stage comb with 20 differential delays, and further provides a notch point of 60Hz and frequency multiplication thereof while filtering;
the SINC1_5 consists of a 1-stage integrator and a 1-stage 11-differential-delay comb, and provides a notch point of 110Hz and frequency multiplication thereof while further filtering;
the SINC1_6 consists of a 1-stage integrator and a 1-stage comb with 6 differential delays, finishes filtering after down sampling by a pre-stage filter and provides a trap point of 50Hz and frequency multiplication thereof.
3. The power frequency suppression filter suitable for a Sigma-delta ADC of claim 2, wherein the SINC1 filters SINC1_3, SINC1_4, SINC1_5 are multiplexed.
4. The power frequency suppression filter suitable for a Sigma-delta ADC of claim 2, wherein each of the FIR filters F1 and F2 comprises a multiplier-accumulator and a plurality of storage units for storing filter coefficients, the coefficients of each storage unit are multiplied by the data output from the corresponding SINC1 filter, and finally all the products are added.
5. The power frequency suppression filter suitable for the Sigma-delta ADC as recited in claim 4, wherein the FIR filters have the same F1 and F2 orders, and the two FIR filters are multiplexed.
6. The power frequency suppression filter suitable for the Sigma-delta ADC of claim 4, wherein the decimation modules M1 to M6 respectively reduce the frequency of the output data to the actually required frequency, and are implemented by using a counter in the circuit, and the count value is adjusted according to the difference of the decimation numbers.
7. The power frequency rejection filter for a Sigma-delta ADC of claim 6, wherein said decimation modules M3-M6 are multiplexed.
CN202211249026.0A 2022-10-12 2022-10-12 Power frequency suppression filter suitable for Sigma-delta ADC Pending CN115499013A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117828311A (en) * 2024-03-05 2024-04-05 上海海栎创科技股份有限公司 Noise frequency monitoring method and system based on LMS adaptive filter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117828311A (en) * 2024-03-05 2024-04-05 上海海栎创科技股份有限公司 Noise frequency monitoring method and system based on LMS adaptive filter

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