CN115498992A - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN115498992A CN115498992A CN202211102525.7A CN202211102525A CN115498992A CN 115498992 A CN115498992 A CN 115498992A CN 202211102525 A CN202211102525 A CN 202211102525A CN 115498992 A CN115498992 A CN 115498992A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
Abstract
A power-on-reset circuit, comprising: the circuit comprises an analog power supply judging unit, a digital power supply judging unit, a current converting unit and a logic unit; the analog power supply judging unit and the digital power supply judging unit respectively judge the power-on states of the analog power supply and the digital power supply through undervoltage locking logic and output analog power-on judging voltage and digital power-on judging voltage; the current conversion unit is connected with the digital power supply judgment unit, receives the digital power-on judgment voltage and generates digital power-on judgment current; the logic unit is respectively connected with the current conversion unit and the analog power supply judgment unit, and realizes the output of a chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a power-on reset circuit of a chip.
Background
At present, a power-on reset circuit is generally applied to an integrated circuit, and provides a control signal for a post-stage circuit in a chip in a stage where power-on of the chip is not completed and a power supply voltage is in a slow climbing state, so as to ensure that the chip executes a normal circuit program after the power supply is completed and the power supply voltage is stable, and prevent a logic error of the chip caused by a low power supply.
In a chip with multiple voltage domains, for example, a chip with both an analog power supply and a digital power supply, the power-on reset circuit needs to detect power-on states of multiple different power supplies at the same time, so that after all the power supplies are sufficiently powered on, normal logic of the chip is executed. In the prior art, an under-voltage lockout logic is usually adopted to determine whether a digital power supply is powered on, and a determination signal for powering on the digital power supply is input into a level shifter controlled by an analog power supply, so as to ensure that a power-on reset signal of a chip is output after an analog circuit is powered on as well.
However, the power-on reset circuit of this type still has some problems, for example, when the digital power supply is powered on and the analog power supply is not powered on, the level shifter receives the power-on signal of the digital power supply and then generates an unstable output, thereby causing the possibility of sending an erroneous power-on reset signal, so that the chip enters a normal working state in advance during the power-on process, and various errors or faults occur.
In order to solve the problems, the invention provides a novel power-on reset circuit.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a power-on reset circuit which respectively obtains the power-on states of a digital power supply and an analog power supply, converts a digital power-on judgment voltage into a digital power-on judgment current and then outputs a power-on reset signal of a chip through a logic module.
The invention adopts the following technical scheme.
The invention relates to a power-on reset circuit, which comprises an analog power supply judging unit, a digital power supply judging unit, a current converting unit and a logic unit, wherein the analog power supply judging unit is used for judging the power supply voltage of a power supply; the analog power supply judging unit and the digital power supply judging unit respectively judge the power-on states of the analog power supply and the digital power supply through the under-voltage locking logic and output analog power-on judging voltage and digital power-on judging voltage; the current conversion unit is connected with the digital power supply judgment unit and used for receiving the digital power-on judgment voltage and generating digital power-on judgment current; and the logic unit is respectively connected with the current conversion unit and the analog power supply judgment unit and realizes the output of the chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.
Preferably, the analog power supply judging unit and the digital power supply judging unit have the same circuit structure; the circuit structure comprises a band gap reference source, a voltage division branch circuit, a comparator and an inverter; the band-gap reference source generates a reference voltage Vref under the driving of a digital power supply or an analog power supply, and the voltage division branch divides the voltage of the digital power supply or the analog power supply and generates a divided voltage Vdiv; a comparator which compares the reference voltage Vref with the divided voltage Vdiv and outputs a comparison voltage to the inverter; the inverter outputs an analog power-on judgment voltage or a digital power-on judgment voltage.
Preferably, the power conversion unit includes first to third current sources, a first switch tube, a second switch tube, a first mirror tube, a second mirror tube and a capacitor; one end of the first current source is connected with the voltage of a digital power supply, the other end of the first current source is connected to the first image tube through a first switching tube, and the grid electrode of the first switching tube is connected with the output end of the digital power supply judging unit; the grid electrode and the drain electrode of the first mirror image tube are respectively connected to one end of a second current source and the grid electrode of the second mirror image tube; the source electrode of the first image tube, the source electrode of the second image tube and the other end of the second current source are all connected to the analog ground; one end of the third current source is connected with the analog power supply voltage, the other end of the third current source is connected with the drain electrode of the second image tube, the source drain electrode of the second switch tube is connected in parallel with the two ends of the third current source, and the grid electrode of the second switch tube is connected with the reverse signal of the output end of the analog power supply judgment unit; the capacitor is connected in parallel at two ends of the drain-source electrode of the second mirror tube.
Preferably, the logic unit comprises an inverter and an AND gate; one end of the NOT gate is connected with the digital power-on judgment current, and the other end of the NOT gate is connected to a first input end of the AND gate; and the second input end of the AND gate is connected with the analog power-on judgment voltage, and the output end generates a chip power-on reset signal.
Preferably, when the analog power supply is not powered on completely, the analog power-on judgment voltage is at a low level and the chip power-on reset signal is at a low level no matter whether the digital power supply is powered on completely or not.
Preferably, when the analog power supply is powered on, if the digital power supply is not powered on, the first switching tube is turned off, the digital power supply judges that the current enables the capacitor to be charged, a high-level signal is provided for a not gate input end in the logic unit, and a power-on reset signal of the chip is at a low level; if the digital power supply is electrified, the first switch tube is conducted, the digital electrification judgment current enables the capacitor to discharge, a low level signal is provided for the input end of the NOT gate in the logic unit, and the chip electrification reset signal is high level.
Preferably, when the analog power supply is powered on and the digital power supply is not powered on, the digital power-on judges that the current is I 1 (ii) a When the analog power supply and the digital power supply are powered on, the digital power-on judges that the current is N (I) pord -I 0 )-I 1 (ii) a Wherein, I pord 、I 0 And I 1 The current values of the first current source, the second current source and the third current source are respectively, and N is the current mirror image multiple of the first mirror image tube and the second mirror image tube.
Compared with the prior art, the power-on reset circuit has the advantages that the power-on reset circuit can respectively acquire the power-on states of a digital power supply and an analog power supply, converts the digital power-on judgment voltage into the digital power-on judgment current, and then outputs the power-on reset signal of the chip through the logic module. The method is simple and ingenious in thought, and effectively avoids the use of the level shifter, so that the circuit realizes the common inspection of the power-on states of a plurality of power supply voltages in different ranges in a voltage and current interchange mode.
The beneficial effects of the invention also include:
1. because the current conversion unit is added, the voltage range of the digital power supply is not required to be converted into the voltage range of the analog power supply through the level shifter, so that the problem of output error of the level shifter is avoided. In addition, the digital power-on judgment voltage is converted into the corresponding current, and the current is charged and discharged as the capacitor, so that the logic unit can acquire the capacitor voltage completely related to the current, and accurate logic output is realized.
2. In the invention, in order to prevent the possible abnormality of the current mirror in the current conversion unit, a smaller current source is connected to the grid electrodes of the two mirror image MOS tubes in the current mirror, and the grid voltage Vx of the two mirror image MOS tubes is limited on the basis of not influencing the basic logic of the current conversion unit, so that the Vx cannot be in a floating state under any condition, thereby further ensuring the accuracy of the logic.
Drawings
Fig. 1 is a schematic circuit diagram of a power-on reset circuit in a multi-power chip in the prior art;
fig. 2 is a schematic circuit diagram of a digital power determining unit in a power-on reset circuit according to the present invention;
fig. 3 is a schematic diagram of a circuit structure of an analog power determining unit, a power converting unit and a logic unit in a power-on reset circuit according to the present invention;
FIG. 4 is a schematic diagram of a digital power-on judgment current generated by a current conversion unit when power-on of a chip in a power-on reset circuit is completed according to the present invention;
fig. 5 is a schematic diagram of a digital power-on judgment current generated by the current conversion unit when power-on of a chip in the power-on reset circuit is not completed.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The embodiments described herein are only some embodiments of the invention, and not all embodiments. All other embodiments obtained by a person skilled in the art without any inventive step based on the spirit of the present invention are within the scope of the present invention.
Fig. 1 is a schematic circuit diagram of a power-on reset circuit in a multi-power chip in the prior art. As shown in fig. 1, in the multi-power chip in the prior art, in order to simultaneously determine whether each power supply in the chip is powered up, a level shifter is connected after an under-voltage lockout circuit for determining a Digital power supply DVDD (Digital VDD), and since the level shifter is controlled by an Analog power supply AVDD (Analog VDD), the circuit ideally provides a chip power-on reset signal aporb only when the Analog power supply is powered on.
However, in practice, when the digital power supply has been powered up and the analog power supply has not been sufficiently powered up, the circuit will provide a high dporb signal that, after input to the level shifter, will likely cause the output of the level shifter to go unstable.
To overcome this problem, the present invention provides a new power-on reset circuit.
Fig. 2 is a schematic circuit diagram of a digital power determining unit in a power-on reset circuit according to the present invention. As shown in fig. 2, a power-on reset circuit includes an analog power supply determining unit, a digital power supply determining unit, a current converting unit, and a logic unit; the analog power supply judging unit and the digital power supply judging unit respectively judge the power-on states of the analog power supply and the digital power supply through undervoltage locking logic and output analog power-on judging voltage and digital power-on judging voltage; the current conversion unit is connected with the digital power supply judgment unit and used for receiving the digital power-on judgment voltage and generating digital power-on judgment current; and the logic unit is respectively connected with the current conversion unit and the analog power supply judgment unit and realizes the output of the power-on reset signal of the chip based on the digital power-on judgment current and the analog power-on judgment voltage.
It can be understood that the analog power supply judging unit and the digital power supply judging unit in the invention can adopt the commonly used under-voltage locking logic in the prior art. Because the under-voltage locking logic circuit in the prior art is not unique, the structure and the mode of the circuit can be reasonably selected according to the specific condition of a chip. The essence of the under-voltage locking logic circuit provided in the embodiment of the present invention is that a relatively stable bandgap reference voltage is generated by a DVDD voltage at one end of a comparator, and the magnitude of the DVDD is sensed by dividing the DVDD voltage at the other end of the comparator. The comparator compares the divided voltage Vdiv of the DVDD with the reference voltage Vref with a constant magnitude to obtain a high level or a low level. Wherein a high level indicates that Vref is greater relative to Vdiv and therefore DVDD power up is incomplete, and a low level indicates that Vref is less relative to Vdiv and DVDD power up is complete. The comparison signal cmp generated by the comparator passes through the inverter again, and then is used as the digital power-on judgment voltage dporb in the present invention.
Preferably, the analog power supply judging unit and the digital power supply judging unit have the same circuit structure; the circuit structure comprises a band gap reference source, a voltage division branch circuit, a comparator and an inverter; the band-gap reference source generates a reference voltage Vref under the driving of a digital power supply or an analog power supply, and the voltage dividing branch divides the digital power supply or the analog power supply and generates a divided voltage Vdiv; a comparator which compares the reference voltage Vref with the divided voltage Vdiv and outputs a comparison voltage to the inverter; the inverter outputs an analog power-on judgment voltage or a digital power-on judgment voltage.
It is understood that the structures of the under-voltage lockout logic circuits for determining DVDD and AVDD in the present invention may be completely the same, and may be adjusted to some extent according to the actual conditions of the chip, such as the voltage ranges of DVDD and AVDD. However, the idea of determining whether power-on is completed through the under-voltage lockout logic remains unchanged.
Fig. 3 is a schematic circuit diagram of an analog power determining unit, a power converting unit and a logic unit in the power-on reset circuit according to the present invention. As shown in fig. 3, preferably, the power conversion unit includes first to third current sources, a first switch tube, a second switch tube, a first mirror tube, a second mirror tube and a capacitor; one end of the first current source is connected with the voltage of a digital power supply, the other end of the first current source is connected to the first image tube through a first switching tube, and the grid electrode of the first switching tube is connected with the output end of the digital power supply judging unit; the grid electrode and the drain electrode of the first mirror image tube are respectively connected to one end of a second current source and the grid electrode of the second mirror image tube; the source electrode of the first image tube, the source electrode of the second image tube and the other end of the second current source are all connected to the analog ground; one end of the third current source is connected with the analog power supply voltage, the other end of the third current source is connected with the drain electrode of the second image tube, the source drain electrode of the second switch tube is connected in parallel with the two ends of the third current source, and the grid electrode of the second switch tube is connected with the reverse signal of the output end of the analog power supply judgment unit; the capacitor is connected in parallel at two ends of the drain-source electrode of the second mirror tube.
It is understood that, in the present invention, although the analog power-on determination voltage and the digital power-on determination voltage can be separately obtained, the two voltages are not maintained at the same voltage value when they are in the high level state. In other words, due to the difference in voltage ranges of DVDD and AVDD, two voltage signals of different magnitudes cannot be directly compared by the logic unit. Due to the foregoing, level shifters should be avoided in the present invention to prevent errors in the output logic.
In this case, in the present invention, after one of the DVDD and AVDD voltages is converted into a reasonable current, the other voltage is converted back into a voltage having the same range as the other voltage by charging and discharging the capacitor, and then the logic unit performs logic conversion of the signal.
Therefore, the invention adds a new current conversion unit in the circuit of the prior art. In the unit, the first switch tube can sense the magnitude of the digital power-on judgment voltage and confirm whether to output corresponding digital power-on judgment current or not. After passing through the current mirror, the other end of the current conversion unit can realize the mirror image of the digital power-on judgment current, and simultaneously, the charge and discharge of the capacitor are influenced by the current.
On the other hand, if the first switch tube in the unit is in an off state, the third current source is connected into the circuit, the current mirror does not output any current, and the current of the third current source modifies the charging and discharging state of the capacitor through the flow direction opposite to the mirror current.
Under the combined action of the currents, the capacitor can realize charging or discharging according to the power-on state of the circuit, and correspondingly, reasonable capacitor voltage Vc is provided for the logic circuit.
Preferably, the logic unit comprises an inverter and an AND gate; one end of the NOT gate is connected with the digital power-on judgment current, and the other end of the NOT gate is connected to a first input end of the AND gate; and the second input end of the AND gate is connected with the analog power-on judgment voltage, and the output end generates a chip power-on reset signal.
It can be understood that the circuit of the logic unit in the invention can perform corresponding logic conversion on the converted digital power-on judgment voltage and the unconverted analog power-on judgment voltage, so as to generate an accurate chip power-on reset signal based on the two voltage signals.
Preferably, when the analog power supply is not powered on completely, the analog power-on judgment voltage is at a low level and the chip power-on reset signal is at a low level no matter whether the digital power supply is powered on completely or not.
As can be seen from the analysis of the circuits in fig. 2 and 3, when the analog power supply is not powered up, even if Ipord can input current into the current mirror through S1, the cmpa signal is still high, so that the aporb _ mid signal is low, and the aporb signal with low level is output after passing through the and gate.
Fig. 4 is a schematic diagram of a digital power-on judgment current generated by a current conversion unit when power-on of a chip in the power-on reset circuit is completed according to the present invention. Fig. 5 is a schematic diagram of a digital power-on judgment current generated by the current conversion unit when power-on of a chip in the power-on reset circuit is not completed. As shown in fig. 4 and fig. 5, preferably, when the analog power supply is powered on, if the digital power supply is not powered on, the first switching tube and the second switching tube are turned off, the digital power-on judgment current charges the capacitor, and provides a high-level signal to the not-gate input end in the logic unit, and the chip power-on reset signal is at a low level; if the digital power supply is electrified, the first switch tube and the second switch tube are conducted, the digital electrification judgment current enables the capacitor to discharge, a low level signal is provided for the input end of the NOT gate in the logic unit, and the chip electrification reset signal is high level.
Preferably, when the analog power supply is powered on and the digital power supply is not powered on, the digital power-on judges that the current is I 1 (ii) a When the analog power supply and the digital power supply are powered on, the digital power-on judges that the current is N (I) pord -I 0 )-I 1 (ii) a Wherein, I pord 、I 0 And I 1 Are respectively a first current sourceAnd the current values of the second current source and the third current source, wherein N is the current mirror image multiple of the first mirror image tube and the second mirror image tube.
It will be appreciated that if the AVDD has completed a sufficient power-up, then the output condition of the circuit can now be divided into two different conditions depending on the power-up state of the DVDD. First, as shown in fig. 4, when DVDD also completes the power-up, the switching tube S1 is in a conducting state, and the current Ipord of the first current source is inputted into the current mirror. In the present invention, a second current source I0 is added between the gates of the two current mirrors and the analog ground, taking into account the state of the stabilizing current mirror in each case. Under the action of the current source, not all the current Iford is input into the current mirror, and the current generated by the current mirror is only Iford-I0. When AVDD is fully powered on, cmpa is at a low level, so that the second switch tube is always in an off state, and the third current source can continuously provide current I1 for the current mirror.
Therefore, when the DVDD is completely powered up, the discharging current received by the capacitor side is N (I) pord -I 0 )-I 1 . It is easily conceivable that Ipord-I0 should be set to be larger than I1 by a suitable amount in order to make the capacitor discharge sufficiently in this case. Due to the discharge of the capacitor, the voltage of the Vc point is reduced, so that the aporb signal output by the logic unit is in a high level state.
On the other hand, if DVDD has not yet been powered up, the current mirror will not receive any input nor will it provide the output current I2, and therefore the discharge current received by the capacitor side should be equal to I1. At this time, the capacitor is charged by I1, and the voltage at Vc is increased, and the aporb signal is at a low level.
By the mode, the accurate output of the circuit is effectively realized, so that the chip can provide accurate execution logic according to the state of the power-on reset signal of the chip.
Compared with the prior art, the power-on reset circuit has the advantages that the power-on reset circuit respectively acquires the power-on states of a digital power supply and an analog power supply, converts the digital power-on judgment voltage into the digital power-on judgment current, and then outputs the power-on reset signal of the chip through the logic module.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (7)
1. A power-on-reset circuit, comprising:
the circuit comprises an analog power supply judging unit, a digital power supply judging unit, a current converting unit and a logic unit; wherein the content of the first and second substances,
the analog power supply judging unit and the digital power supply judging unit respectively judge the power-on states of the analog power supply and the digital power supply through undervoltage locking logic and output analog power-on judging voltage and digital power-on judging voltage;
the current conversion unit is connected with the digital power supply judgment unit, receives the digital power-on judgment voltage and generates digital power-on judgment current;
the logic unit is connected with the current conversion unit and the analog power supply judgment unit respectively, and outputs a chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.
2. A power-on-reset circuit as claimed in claim 1, wherein:
the analog power supply judging unit and the digital power supply judging unit have the same circuit structure; and the number of the first and second electrodes,
the circuit structure comprises a band gap reference source, a voltage division branch circuit, a comparator and an inverter;
the band-gap reference source generates a reference voltage Vref under the driving of a digital power supply or an analog power supply, and the voltage division branch divides the digital power supply or the analog power supply and generates a divided voltage Vdiv;
the comparator is used for comparing the reference voltage Vref with the divided voltage Vdiv and then outputting a comparison voltage to the inverter;
the inverter outputs an analog power-on judgment voltage or a digital power-on judgment voltage.
3. A power-on-reset circuit as claimed in claim 1, wherein:
the power supply conversion unit comprises first to third current sources, a first switch tube, a second switch tube, a first image mirror tube, a second image mirror tube and a capacitor; wherein the content of the first and second substances,
one end of the first current source is connected with a digital power supply voltage, the other end of the first current source is connected to the first image mirror tube through a first switching tube, and a grid electrode of the first switching tube is connected with the output end of the digital power supply judging unit;
the grid electrode and the drain electrode of the first mirror image tube are respectively connected to one end of a second current source and the grid electrode of the second mirror image tube;
the source electrode of the first image tube, the source electrode of the second image tube and the other end of the second current source are all connected to the analog ground;
one end of the third current source is connected with the voltage of an analog power supply, the other end of the third current source is connected with the drain electrode of the second image tube, the source drain electrode of the second switch tube is connected with the two ends of the third current source in parallel, and the grid electrode of the third current source is connected with the reverse signal of the output end of the analog power supply judging unit;
and the capacitor is connected in parallel at two ends of the drain-source electrode of the second mirror image tube.
4. A power-on-reset circuit as claimed in claim 3, wherein:
the logic unit comprises a NOT gate and an AND gate;
one end of the NOT gate is connected with the digital power-on judgment current, and the other end of the NOT gate is connected to a first input end of the AND gate;
and a second input end of the AND gate is connected with the analog power-on judgment voltage, and an output end of the AND gate generates a chip power-on reset signal.
5. A power-on-reset circuit as claimed in claim 4, wherein:
when the analog power supply is not powered on completely, whether the digital power supply is powered on completely or not, the analog power-on judgment voltage is at a low level, and the chip power-on reset signal is at a low level.
6. A power-on-reset circuit as claimed in claim 4, wherein:
when the analog power supply is powered on, if the digital power supply is not powered on, the first switching tube is turned off, the digital power-on judgment current enables the capacitor to be charged, a high-level signal is provided for a not gate input end in a logic unit, and a power-on reset signal of the chip is at a low level;
if the digital power supply is powered on, the first switch tube is conducted, the digital power-on judgment current enables the capacitor to discharge, a low-level signal is provided for a not gate input end in the logic unit, and a chip power-on reset signal is at a high level.
7. A power-on-reset circuit as claimed in claim 6, wherein:
when the analog power supply is electrified and the digital power supply is not electrified, the digital electrification judgment current is I 1 ；
When the analog power supply and the digital power supply are powered on, the digital power-on judgment current is N (I) pord -I 0 )-I 1 ；
Wherein, I pord 、I 0 And I 1 The current values of the first current source, the second current source and the third current source are respectively, and N is the current mirror image multiple of the first mirror image tube and the second mirror image tube.
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| CN202211102525.7A CN115498992A (en) | 2022-09-09 | 2022-09-09 | Power-on reset circuit |
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| CN202211102525.7A CN115498992A (en) | 2022-09-09 | 2022-09-09 | Power-on reset circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115981683A (en) * | 2023-03-20 | 2023-04-18 | 荣湃半导体（上海）有限公司 | Euse automatic programming circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115981683A (en) * | 2023-03-20 | 2023-04-18 | 荣湃半导体（上海）有限公司 | Euse automatic programming circuit |
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