CN115498967B - Amplifier bias circuit and radio frequency power amplifier - Google Patents
Amplifier bias circuit and radio frequency power amplifier Download PDFInfo
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- CN115498967B CN115498967B CN202211458371.5A CN202211458371A CN115498967B CN 115498967 B CN115498967 B CN 115498967B CN 202211458371 A CN202211458371 A CN 202211458371A CN 115498967 B CN115498967 B CN 115498967B
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- 238000005070 sampling Methods 0.000 claims abstract description 122
- 239000003990 capacitor Substances 0.000 claims description 15
- 230000000903 blocking effect Effects 0.000 claims description 9
- 230000003068 static effect Effects 0.000 abstract description 14
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 24
- 238000004891 communication Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
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- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The invention relates to an amplifier bias circuit and a radio frequency power amplifier, wherein the amplifier bias circuit comprises a sampling module, a control module and a node, and the sampling module comprises a sampling MOS (metal oxide semiconductor) tube and a bias voltage input end; the control module comprises a power input end, a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are connected with the power input end; the node is arranged between the second MOS tube and the sampling MOS tube and is connected with the input port of the amplifier circuit; when the drain current of the sampling MOS tube changes, a feedback is given to the first MOS tube to enable the first MOS tube to be conducted, the change of the first MOS tube is fed back to the sampling MOS tube through the second MOS tube, and the current of the sampling MOS tube is controlled. The invention can simultaneously solve the problems of stability and difference of the static bias current.
Description
Technical Field
The present invention relates to the field of radio frequency communication technologies, and in particular, to an amplifier bias circuit and a radio frequency power amplifier.
Background
The radio frequency power amplifier is widely applied to the field of wireless communication, and amplifies modulation signals of transmission information loaded on carrier signals through power to form radio frequency signals with certain bandwidth. Such as base station communications and handset communications. The linearity of the rf amplifier directly affects the signal integrity and error rate of wireless communications. Conventional rf power amplifiers use bias circuits to establish a quiescent bias current in the active die, keeping the input and output of the amplifier in a linear relationship. However, the static bias current fluctuates due to process errors and temperature changes, and the linearity of the radio frequency power amplifier deteriorates due to the changes of the static bias current.
The feedback technique introduces the quiescent bias current of the amplifier into the bias circuit, so that the quiescent current participates in the generation of the bias voltage, and the bias voltage drives the active die of the amplifier to generate the quiescent bias current, thereby forming a feedback closed loop and having proved to have certain quiescent bias current stability characteristics. The current main mode is based on negative feedback realization of an operational amplifier circuit, and the mode is to convert static bias current into voltage, compare the voltage with reference voltage through the operational amplifier and output corresponding control voltage, thereby controlling the output voltage of the bias circuit and realizing the characteristic of stabilizing the static bias current. Although the method can stabilize the quiescent bias current of a single amplifier product, the influence of an active process and temperature is large, and large quiescent bias current difference can be easily generated among a plurality of products.
Therefore, it is desirable to provide an amplifier bias circuit that simultaneously solves the problems of static bias current stability and diversity.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the technical defect that the stability and the difference of the static bias current cannot be considered simultaneously in the prior art.
In order to solve the above technical problem, the present invention provides an amplifier bias circuit configured to provide a bias current for a radio frequency power amplifier, where the radio frequency power amplifier includes an amplifier circuit including an input port and an amplifying MOS transistor connected to the input port, the amplifier bias circuit includes:
the sampling module comprises a bias voltage input end and a sampling MOS tube connected with the bias voltage input end;
the control module comprises a power input end, a first MOS tube and a second MOS tube which are connected with the power input end together, wherein the grid electrode of the first MOS tube is connected with the drain electrode of the sampling MOS tube, the source electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, and the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube;
a node arranged between the second MOS transistor and the sampling MOS transistor, the node being connected to an input port of the amplifier circuit;
when the drain current of the sampling MOS tube changes, a feedback is given to the first MOS tube, so that the first MOS tube is conducted, and the change of the first MOS tube is fed back to the sampling MOS tube through the second MOS tube to control the current of the sampling MOS tube.
In an embodiment of the present invention, the sampling MOS transistor and the amplifying MOS transistor have the same parameters except for different gate widths, and the gate width of the sampling MOS transistor is smaller than the gate width of the amplifying MOS transistor.
In an embodiment of the present invention, the control module includes a first resistor, a second resistor, a third resistor, and a capacitor, the source of the first MOS transistor is connected to the gate of the second MOS transistor through the first resistor, the gate of the second MOS transistor is grounded through the second resistor and the capacitor, respectively, and the source of the second MOS transistor is grounded through the third resistor.
In an embodiment of the invention, the sampling module includes a fourth resistor and a fifth resistor, the source of the second MOS transistor is connected to the gate of the sampling MOS transistor through the fourth resistor, and the drain of the sampling MOS transistor is connected to the bias voltage input terminal through the fifth resistor.
In one embodiment of the present invention, when the number of the radio frequency power amplifiers is more than one, at least two radio frequency power amplifiers are connected to the node in parallel.
In addition, the present invention also provides an amplifier bias circuit configured to provide a bias current for a radio frequency power amplifier, the radio frequency power amplifier including an amplifier circuit including an input port and an amplifying MOS transistor connected to the input port, the amplifier bias circuit including:
the sampling module comprises a bias voltage input end and a sampling MOS tube connected with the bias voltage input end;
the control module comprises a power input end, a first MOS tube and a second MOS tube which are connected with the power input end together, wherein the grid electrode of the first MOS tube is connected with the drain electrode of the sampling MOS tube, the source electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, and the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube;
the node is arranged between the second MOS tube and the sampling MOS tube and is connected with the input port of the amplifier circuit;
the dual-gate tube second gate voltage port is respectively connected with the second gate of the sampling MOS tube and the second gate of the amplifying MOS tube;
when the drain current of the sampling MOS tube changes, a feedback is given to the first MOS tube, so that the first MOS tube is conducted, the change of the first MOS tube is fed back to the sampling MOS tube through the second MOS tube to control the current of the sampling MOS tube, and the first grid electrode of the double-grid tube and the drain electrode of the double-grid tube are isolated by increasing the second grid voltage port of the double-grid tube.
In an embodiment of the present invention, the sampling MOS transistor and the amplifying MOS transistor have the same parameters except for different gate widths, and the gate width of the sampling MOS transistor is smaller than the gate width of the amplifying MOS transistor.
In an embodiment of the present invention, the control module includes a first resistor, a second resistor, a third resistor, and a capacitor, the source of the first MOS transistor is connected to the gate of the second MOS transistor through the first resistor, the gate of the second MOS transistor is grounded through the second resistor and the capacitor, respectively, and the source of the second MOS transistor is grounded through the third resistor; the sampling module comprises a fourth resistor and a fifth resistor, the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube through the fourth resistor, and the drain electrode of the sampling MOS tube is connected with the bias voltage input end through the fifth resistor.
In one embodiment of the present invention, when the number of the radio frequency power amplifiers is more than one, at least two radio frequency power amplifiers are connected to the node in parallel.
In addition, the invention also provides a radio frequency power amplifier, which comprises an amplifier circuit, wherein the amplifier circuit comprises an input port and an amplifying MOS (metal oxide semiconductor) tube connected with the input port, and also comprises the amplifier bias circuit, and a node of the amplifier bias circuit is connected with the input port of the amplifier circuit; the amplifier circuit further comprises an output port, a power port and an alternating current blocking circuit, wherein the output port is connected with the drain electrode of the amplifying MOS tube, and the drain electrode of the amplifying MOS tube is connected with the power port through the alternating current blocking circuit.
Compared with the prior art, the technical scheme of the invention has the following advantages:
1. the amplifier bias circuit and the radio frequency power amplifier only adopt the first MOS tube, the second MOS tube and the sampling MOS tube to realize the amplifier bias circuit which applies the feedback technology and the sampling technology, drain electrode current change of the sampling MOS tube is fed back to the grid electrode of the sampling MOS tube in real time through the first MOS tube and the second MOS tube so as to control the current of the sampling MOS tube, thereby realizing the stability of the quiescent current which is far superior to the prior amplifier and the bias circuit, simplifying the structure of the prior amplifier bias circuit, saving the circuit area, reducing the design difficulty and simultaneously solving the problems of the stability and the difference of the quiescent bias current;
2. according to the amplifier bias circuit and the radio frequency power amplifier, the characteristic that the process deviation directions in a small area are consistent when an integrated circuit is manufactured is utilized, the influence of process errors on the first MOS tube and the second MOS tube is used for compensating the influence of the process errors on the sampling MOS tube and the amplifying MOS tube, the fluctuation of quiescent current along with the process deviation is reduced, and the difference of the quiescent bias current among a plurality of amplifier products is greatly reduced;
3. the amplifier bias circuit and the radio frequency power amplifier utilize the characteristic that the temperature is consistent in a small area when an integrated circuit is manufactured, the influence of the temperature on the first MOS tube and the second MOS tube is used for compensating the influence of the temperature on the sampling MOS tube and the amplifying MOS tube, and the difference of the static bias current among a plurality of amplifier products is greatly reduced.
Drawings
In order that the present disclosure may be more readily and clearly understood, reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.
Fig. 1 is a schematic circuit diagram of an amplifier bias circuit according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of an amplifier bias circuit according to a second embodiment of the present invention.
FIG. 3 is a graph of quiescent current versus process error and temperature for the present invention.
Fig. 4 is a graph of the quiescent current of a prior art amplifier and bias circuit as a function of process error and temperature.
Wherein the reference numerals are as follows: 1. a first MOS transistor; 2. a first resistor; 3. a second resistor; 4. a capacitor; 5. a second MOS transistor; 6. a third resistor; 7. a fourth resistor; 8. a sixth resistor; 9. a fifth resistor; 10. sampling an MOS tube; 11. a power supply input terminal; 12. a bias voltage input terminal; 13. an amplifier circuit; 14. an AC blocking circuit; 15. amplifying the MOS tube; 16. a power port; 17. an input port; 18. an output port; 21. a dual gate voltage port.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
Example one
Referring to fig. 1, an embodiment of the present invention provides an amplifier bias circuit with a first structure, which is configured to provide a bias current for a radio frequency power amplifier, where the radio frequency power amplifier includes an amplifier circuit 13, and the amplifier circuit 13 includes an amplifying MOS transistor 15, an input port 17, an output port 18, a power supply port 16, and an ac blocking circuit 14; the amplifier bias circuit comprises a sampling module, a control module and a node, and the node of the amplifier bias circuit is connected with the input port 17 of the amplifier circuit 13.
The input port 17 of the amplifier circuit 13 is connected to the gate of the amplifying MOS transistor 15, the output port 18 is connected to the drain of the amplifying MOS transistor 15, the drain of the amplifying MOS transistor 15 is connected to the power port 16 through the ac blocking circuit 14, and the source of the amplifying MOS transistor 15 is grounded.
The sampling module of the amplifier bias circuit comprises a sampling MOS tube 10 and a bias voltage input end 12, wherein the drain electrode of the sampling MOS tube 10 is connected with the bias voltage input end 12; the control module comprises a first MOS tube 1, a second MOS tube 5 and a power input end 11, wherein the drain electrodes of the first MOS tube 1 and the second MOS tube 5 are commonly connected with the power input end 11, the grid electrode of the first MOS tube 1 is connected with the drain electrode of the sampling MOS tube 10, the source electrode of the first MOS tube 1 is connected with the grid electrode of the second MOS tube 5, and the source electrode of the second MOS tube 5 is connected with the grid electrode of the sampling MOS tube 10; the node is arranged between the second MOS tube 5 and the sampling MOS tube 10, and the node is connected with the input port 17 of the radio frequency power amplifier.
Specifically, the control module further includes a first resistor 2, a second resistor 3, a third resistor 6 and a capacitor 4, the source of the first MOS transistor 1 is connected to the gate of the second MOS transistor 5 through the first resistor 2, the gate of the second MOS transistor 5 is grounded through the second resistor 3 and the capacitor 4, respectively, and the source of the second MOS transistor 5 is grounded through the third resistor 6.
The sampling module further comprises a fourth resistor 7, a fifth resistor 9 and a sixth resistor 8, the source electrode of the second MOS tube 5 is connected with the grid electrode of the sampling MOS tube 10 through the fourth resistor 7, the drain electrode of the sampling MOS tube 10 is connected with the bias voltage input end 12 through the fifth resistor 9, and the sixth resistor 8 is arranged at the node and the input port 17 of the amplifier circuit 13.
Preferably, the sampling MOS tube 10 and the amplifying MOS tube 15 have the same parameters except for different gate widths, the gate width of the sampling MOS tube 10 is smaller than the gate width of the amplifying MOS tube 15, and the ratio of the quiescent currents of the sampling MOS tube 10 and the amplifying MOS tube 15 is the same as the gate width ratio of the sampling MOS tube 10 and the amplifying MOS tube 15.
When the drain current of the sampling MOS tube 10 changes, a feedback is given to the first MOS tube 1, so that the first MOS tube 1 is turned on, and the change is fed back to the sampling MOS tube 10 through the second MOS tube 5 to control the current of the sampling MOS tube 10, that is, the drain current of the sampling MOS tube 10 changes and is fed back to the gate of the sampling MOS tube 10 through the first MOS tube 1 and the second MOS tube 5 to control the current of the sampling MOS tube 10, thereby achieving the static current stability far superior to that of the conventional amplifier and bias circuit.
Preferably, when the number of the radio frequency power amplifiers is more than one, at least two radio frequency power amplifiers are connected to the node in parallel. The invention utilizes the characteristic that the process deviation directions in a small area are consistent when the integrated circuit is manufactured, the influence of the process error on the first MOS tube 1 and the second MOS tube 5 is used for compensating the influence of the process error on the sampling MOS tube 10 and the amplifying MOS tube 15, the fluctuation of the quiescent current along with the process deviation is reduced, and the difference of the quiescent bias current among a plurality of amplifier products is greatly reduced; the characteristic that the temperature is consistent in a small area when the integrated circuit is manufactured is utilized, the influence of the temperature on the first MOS tube 1 and the second MOS tube 5 is used for compensating the influence of the temperature on the sampling MOS tube 10 and the amplifying MOS tube 15, and the difference of the static bias current among a plurality of amplifier products is greatly reduced.
According to the amplifier bias circuit and the radio frequency power amplifier, the amplifier bias circuit which applies the feedback technology and the sampling technology is realized by only adopting 3 MOS tubes, 6 resistors and 1 capacitor, the structure of the existing amplifier bias circuit is simplified, the circuit area is saved, the design difficulty is reduced, the problems of stability and difference of static bias current can be solved at the same time, and the amplifier bias circuit and the radio frequency power amplifier are easy to popularize and use.
Example two
Corresponding to the first structure of the amplifier bias circuit described in the first embodiment, the second embodiment of the present invention provides a second structure of the amplifier bias circuit, please refer to fig. 2, which includes a structure configured to provide a bias current for a radio frequency power amplifier, where the radio frequency power amplifier includes an amplifier circuit 13, and the amplifier circuit 13 includes an amplifying MOS transistor 15, an input port 17, an output port 18, a power port 16, and an ac blocking circuit 14; the amplifier bias circuit comprises a sampling module, a control module and a node, and the node of the amplifier bias circuit is connected with the input port 17 of the amplifier circuit 13.
The input port 17 of the amplifier circuit 13 is connected to the gate of the amplifying MOS transistor 15, the output port 18 is connected to the drain of the amplifying MOS transistor 15, the drain of the amplifying MOS transistor 15 is connected to the power port 16 through the ac blocking circuit 14, and the source of the amplifying MOS transistor 15 is grounded.
The sampling module of the amplifier bias circuit comprises a sampling MOS tube 10 and a bias voltage input end 12, wherein the drain electrode of the sampling MOS tube 10 is connected with the bias voltage input end 12; the control module comprises a first MOS tube 1, a second MOS tube 5 and a power input end 11, the drains of the first MOS tube 1 and the second MOS tube 5 are connected with the power input end 11, the grid electrode of the first MOS tube 1 is connected with the drain electrode of the sampling MOS tube 10, the source electrode of the first MOS tube 1 is connected with the grid electrode of the second MOS tube 5, and the source electrode of the second MOS tube 5 is connected with the grid electrode of the sampling MOS tube 10; a node is disposed on a path between the second MOS transistor 5 and the sampling MOS transistor 10, and the node is connected to the input port 17 of the amplifier circuit 13.
Specifically, the control module further includes a first resistor 2, a second resistor 3, a third resistor 6 and a capacitor 4, the source of the first MOS transistor 1 is connected to the gate of the second MOS transistor 5 through the first resistor 2, the gate of the second MOS transistor 5 is grounded through the second resistor 3 and the capacitor 4, respectively, and the source of the second MOS transistor 5 is grounded through the third resistor 6.
The sampling module further comprises a fourth resistor 7, a fifth resistor 9 and a sixth resistor 8, the source electrode of the second MOS tube 5 is connected with the grid electrode of the sampling MOS tube 10 through the fourth resistor 7, the drain electrode of the sampling MOS tube 10 is connected with the bias voltage input end 12 through the fifth resistor 9, and the sixth resistor 8 is arranged at the node and the input port 17 of the radio frequency power amplifier.
Preferably, the sampling MOS tube 10 and the amplifying MOS tube 15 have the same parameters except for different gate widths, the gate width of the sampling MOS tube 10 is smaller than the gate width of the amplifying MOS tube 15, and the ratio of the quiescent currents of the sampling MOS tube 10 and the amplifying MOS tube 15 is the same as the gate width ratio of the sampling MOS tube 10 and the amplifying MOS tube 15.
When the drain current of the sampling MOS transistor 10 changes, a feedback is given to the first MOS transistor 1, so that the first MOS transistor 1 is turned on, and the change is fed back to the sampling MOS transistor 10 through the second MOS transistor 5 to control the current of the sampling MOS transistor 10, that is, the change in the drain current of the sampling MOS transistor 10 is fed back to the gate of the sampling MOS transistor 10 through the first MOS transistor 1 and the second MOS transistor 5 to control the current of the sampling MOS transistor 10, thereby realizing the stability of the quiescent current far superior to that of a conventional amplifier and a bias circuit.
Preferably, when the number of the radio frequency power amplifiers is more than one, at least two radio frequency power amplifiers are connected to the node in parallel. The invention utilizes the characteristic that the process deviation directions in a small area are consistent when the integrated circuit is manufactured, the influence of the process error on the first MOS tube 1 and the second MOS tube 5 is used for compensating the influence of the process error on the sampling MOS tube 10 and the amplifying MOS tube 15, the fluctuation of the quiescent current along with the process deviation is reduced, and the difference of the quiescent bias current among a plurality of amplifier products is greatly reduced; the characteristic that the temperature is consistent in a small area when the integrated circuit is manufactured is utilized, the influence of the temperature on the first MOS tube 1 and the second MOS tube 5 is used for compensating the influence of the temperature on the sampling MOS tube 10 and the amplifying MOS tube 15, and the difference of the static bias current among a plurality of amplifier products is greatly reduced.
The amplifier bias circuit further comprises a dual-gate-tube second gate voltage port 21, the dual-gate-tube second gate voltage port 21 is respectively connected with the second gate of the sampling MOS tube 10 and the second gate of the amplifying MOS tube 15, and the dual-gate-tube first gate and the drain thereof can be isolated by increasing the dual-gate-tube second gate voltage port 21 in this embodiment, so as to reduce the parasitic capacitance between the dual-gate-tube first gate and the drain thereof, thereby improving the applicable frequency of the circuit.
The invention can greatly reduce the deviation of static current along with the process and temperature on the premise of ensuring the simple structure. The following will explain the advantageous effects of the present invention in detail by taking the structure shown in fig. 2 as an example.
Referring to fig. 2, if the voltage of the power input terminal VCB and the bias voltage input terminal Vbias is set to 3V, the voltage of the dual-gate voltage port VG2 is set to 1.5V, and the voltage of the power port VDD is set to 5V, then the current flowing through the amplifying MOS transistor 15 is a static current ICQ, for example, ICQ =43mA. Setting a first resistor 2 to be 500 Ω, a second resistor 3 to be 10k Ω, a third resistor 6 and a fourth resistor 7 to be 400 Ω, a fifth resistor 9 to be 50 Ω, and a sixth resistor 8 to be 1000 Ω; the capacitor 4 is 2pF, and the inductor 14 is 10nH; a first MOS tube 1, a second MOS tube 5, a sampling MOS tube 10 and an amplifying MOS tube 15 are arranged to be 25-micron E-mode MOS tubes; the gate widths of the first MOS tube 1 and the second MOS tube 5 are 50 mu m; the gate width of the sampling MOS tube 10 is 166 μm, and the gate width of the amplifying MOS tube 15 is 4000 μm. Setting the process error of the third resistor 6, the fourth resistor 7 and the fifth resistor 9 to be Gaussian distribution with standard deviation of 1.5%, and setting the process error of the first resistor 2 and the second resistor 3 to be Gaussian distribution with standard deviation of 10%; setting the threshold voltages of a first MOS tube 1, a second MOS tube 5, a sampling MOS tube 10 and an amplifying MOS tube 15 to be Gaussian distribution with a standard deviation of 10 mV; the temperature was set to a uniform distribution of-40 to 125 ℃.
Referring to fig. 3, the quiescent current of the circuit of the present invention varies by ± 4.25mA with the above-mentioned process, temperature error, and the error percentage (erro) is less than ± 10%. Referring to fig. 4, in the case where the device parameters of the conventional amplifier and bias circuit are consistent with the above parameters of the present invention, the variation of the quiescent current with process error and temperature variation is ± 5.5mA, and the error percentage (erro) is greater than ± 12%, where the error percentage is calculated as Eqn erro = (abs (M1-M2)/(M1 + M2)) =100, and the average value is calculated as Eqn I _ mean =1000 (M1 + M2)/2, where abs represents an absolute value, M1 represents a maximum current value, and M2 represents a minimum current value.
Therefore, compared with the existing amplifier and the bias circuit, the circuit structure provided by the invention is simpler, and the fluctuation of the quiescent current along with the process and temperature deviation is smaller than that of the existing amplifier and the bias circuit.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (7)
1. An amplifier bias circuit configured to provide a bias current for a radio frequency power amplifier, the radio frequency power amplifier comprising an amplifier circuit including an input port and an amplifying MOS transistor connected to the input port, wherein: the amplifier bias circuit includes:
the sampling module comprises a bias voltage input end and a sampling MOS tube, wherein the drain electrode of the sampling MOS tube is connected with the bias voltage input end, and the source electrode of the sampling MOS tube is grounded;
the control module comprises a power input end, a first MOS tube, a second MOS tube, a first resistor, a second resistor, a third resistor and a capacitor, wherein the drain electrodes of the first MOS tube and the second MOS tube are commonly connected with the power input end, the grid electrode of the first MOS tube is connected with the drain electrode of the sampling MOS tube, the source electrode of the first MOS tube is connected with the grid electrode of the second MOS tube through the first resistor, the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube, the grid electrode of the second MOS tube is grounded through the second resistor and the capacitor respectively, and the source electrode of the second MOS tube is grounded through the third resistor;
the sampling module comprises a fourth resistor and a fifth resistor, the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube through the fourth resistor, and the drain electrode of the sampling MOS tube is connected with the bias voltage input end through the fifth resistor;
a node arranged between the second MOS transistor and the sampling MOS transistor, the node being connected to an input port of the amplifier circuit;
when the drain current of the sampling MOS tube changes, the current is fed back to the first MOS tube, so that the first MOS tube is conducted, and the change of the first MOS tube is fed back to the sampling MOS tube through the second MOS tube, so that the current of the sampling MOS tube is controlled.
2. The amplifier bias circuit of claim 1, wherein: the sampling MOS tube and the amplifying MOS tube have the same other parameters except for different gate widths, and the gate width of the sampling MOS tube is smaller than that of the amplifying MOS tube.
3. The amplifier biasing circuit of claim 1, wherein: when the number of the radio frequency power amplifiers is more than one, at least two radio frequency power amplifiers are connected to the node in parallel.
4. An amplifier bias circuit configured to provide a bias current for a radio frequency power amplifier, the radio frequency power amplifier comprising an amplifier circuit including an input port and an amplifying MOS transistor connected to the input port, wherein: the amplifier bias circuit includes:
the sampling module comprises a bias voltage input end and a sampling MOS tube, wherein the drain electrode of the sampling MOS tube is connected with the bias voltage input end, and the source electrode of the sampling MOS tube is grounded;
the control module comprises a power input end, a first MOS tube, a second MOS tube, a first resistor, a second resistor, a third resistor and a capacitor, wherein the drain electrodes of the first MOS tube and the second MOS tube are commonly connected with the power input end, the grid electrode of the first MOS tube is connected with the drain electrode of the sampling MOS tube, the source electrode of the first MOS tube is connected with the grid electrode of the second MOS tube through the first resistor, the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube, the grid electrode of the second MOS tube is grounded through the second resistor and the capacitor respectively, and the source electrode of the second MOS tube is grounded through the third resistor;
the sampling module comprises a fourth resistor and a fifth resistor, the source electrode of the second MOS tube is connected with the grid electrode of the sampling MOS tube through the fourth resistor, and the drain electrode of the sampling MOS tube is connected with the bias voltage input end through the fifth resistor;
the node is arranged between the second MOS tube and the sampling MOS tube and is connected with the input port of the amplifier circuit;
a second gate voltage port of the double-gate tube is respectively connected with a second gate of the sampling MOS tube and a second gate of the amplifying MOS tube;
when the drain current of the sampling MOS tube changes, a feedback is given to the first MOS tube, so that the first MOS tube is conducted, the change of the first MOS tube is fed back to the sampling MOS tube through the second MOS tube to control the current of the sampling MOS tube, and the first grid electrode of the double-grid tube and the drain electrode of the double-grid tube are isolated through the second grid voltage port of the double-grid tube.
5. The amplifier biasing circuit of claim 4, wherein: the sampling MOS tube and the amplifying MOS tube have the same other parameters except for different gate widths, and the gate width of the sampling MOS tube is smaller than that of the amplifying MOS tube.
6. The amplifier biasing circuit of claim 4, wherein: when the number of the radio frequency power amplifiers is more than one, at least two radio frequency power amplifiers are connected to the node in parallel.
7. A radio frequency power amplifier comprises an amplifier circuit, wherein the amplifier circuit comprises an input port and an amplifying MOS tube connected with the input port, and the radio frequency power amplifier is characterized in that: further comprising an amplifier bias circuit according to any of claims 1-3 or an amplifier bias circuit according to any of claims 4-6, a node of the amplifier bias circuit being connected to an input port of the amplifier circuit; the amplifier circuit further comprises an output port, a power port and an alternating current blocking circuit, wherein the output port is connected with the drain electrode of the amplifying MOS tube, and the drain electrode of the amplifying MOS tube is connected with the power port through the alternating current blocking circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211458371.5A CN115498967B (en) | 2022-11-21 | 2022-11-21 | Amplifier bias circuit and radio frequency power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211458371.5A CN115498967B (en) | 2022-11-21 | 2022-11-21 | Amplifier bias circuit and radio frequency power amplifier |
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| CN115498967A CN115498967A (en) | 2022-12-20 |
| CN115498967B true CN115498967B (en) | 2023-03-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009302781A (en) * | 2008-06-11 | 2009-12-24 | Toshiba Corp | Negative feedback amplifier |
| US8106712B2 (en) * | 2008-12-24 | 2012-01-31 | Georgia Tech Research Corporation | Systems and methods for self-mixing adaptive bias circuit for power amplifier |
| JP2012205289A (en) * | 2011-03-28 | 2012-10-22 | Asahi Kasei Electronics Co Ltd | Amplifier circuit |
| CN102364855B (en) * | 2011-06-30 | 2014-09-17 | 成都芯源系统有限公司 | Switch converter and control circuit and control method thereof |
| CN103441738A (en) * | 2013-08-28 | 2013-12-11 | 贵州中科汉天下电子有限公司 | Multimode radio frequency power amplifier circuit and current bias method thereof |
| CN103986425A (en) * | 2014-04-30 | 2014-08-13 | 无锡中普微电子有限公司 | Power amplifier based on radio-frequency direct current feedback |
| CN210428232U (en) * | 2019-04-21 | 2020-04-28 | 苏州源特半导体科技有限公司 | Starting circuit of band-gap reference voltage |
| CN111158423A (en) * | 2020-03-04 | 2020-05-15 | 广州致远微电子有限公司 | Protection circuit of linear regulator, linear regulation module and equipment |
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