CN115498102A

CN115498102A - Preparation method of graphene-based quantum resistor chip

Info

Publication number: CN115498102A
Application number: CN202211313444.1A
Authority: CN
Inventors: 王浩敏; 孔自强; 王慧山; 陈令修; 肖相生
Original assignee: Jiangsu Yunyong Electronic Technology Co ltd; Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Jiangsu Yunyong Electronic Technology Co ltd; Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2022-12-20

Abstract

The invention provides a preparation method of a quantum resistance chip based on graphene, which is characterized in that silicon carbide subjected to hydrogen annealing treatment is used as a substrate, silicon ethane is used as a gas catalyst, acetylene is used as a carbon source, a chemical vapor deposition method is adopted to epitaxially grow single-layer graphene, a graphene structure with good uniformity can be prepared, and the Hall resistance measurement accuracy of the prepared quantum resistance chip reaches 1.2 multiplied by 10 under the magnetic field intensity of 6T and the temperature of 4.5K ^‑8 While the relative uncertainty reaches 3 × 10 ^‑8 Reproducibility of 3 x 10 ^‑9 The quantum resistance chip has the advantages of miniaturization, high integration level, cost optimization, high economic benefit and strong applicability, can be directly integrated in a portable quantum resistance standard measurement system, and is favorable for promoting the further development of the precision measurement industry.

Description

Preparation method of quantum resistor chip based on graphene

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of a quantum resistor chip based on graphene.

Background

Graphene has high carrier mobility and mechanical strength, and has attracted extensive attention of researchers all over the world. The preparation of graphene thin films, especially on metal substrates, has made great progress in recent years. However, in order to facilitate the application of graphene in electronic devices, bypassing the transfer process, it is an important trend to synthesize high-quality graphene thin films directly on dielectric substrates.

At present, extensive research has been conducted on the preparation of graphene on non-metallic substrates, for example, on the surfaces of silicon carbide (SiC), hexagonal boron nitride (h-BN), silicon dioxide and sapphire substrates, and for these substrates, how to grow large-area graphene and minimize the influence of substrate morphology (surface relief, surface step height, etc.) on the performance of graphene devices remains an important issue to be further researched.

On the other hand, since the energy space between discrete landau levels of graphene is much wider than that of a gallium arsenide-based two-dimensional electron gas in a magnetic field, the graphene-based quantum resistance standard is promising in practical applications. Compared to gallium arsenide-based two-dimensional electron gases, graphene-based quantum resistance chips can work under more relaxed experimental conditions, such as convenient low temperature magnetic strips, lower magnetic field range, higher current and temperature, etc. So far, some research reports related to epitaxial growth of graphene on silicon carbide (SiC) exist, however, the current graphene-based quantum resistance chip has large performance difference, low accuracy and poor reproducibility, and thus application requirements are difficult to meet.

Therefore, it is necessary to provide a method for preparing a quantum resistor chip based on graphene.

Disclosure of Invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for preparing a graphene-based quantum resistor chip, which is used to solve the problem that the graphene-based quantum resistor chip prepared in the prior art is difficult to meet the application requirements.

In order to achieve the above and other related objects, the present invention provides a method for preparing a graphene-based quantum resistor chip, comprising the steps of:

providing a silicon carbide substrate;

annealing the silicon carbide substrate;

performing epitaxial growth on the surface of the annealed silicon carbide substrate by using a chemical vapor deposition method by using silicon ethane as a gas catalyst and acetylene as a carbon source to obtain single-layer graphene covering the silicon carbide substrate;

forming a patterned electrical contact layer on the single-layer graphene;

patterning the single-layer graphene to obtain a graphene structure, wherein the graphene structure is in contact with the electrical contact layer;

forming a patterned bonding electrode layer on the electric contact layer, wherein the bonding electrode layer is electrically connected with the electric contact layer;

carrying out carrier concentration regulation on the graphene structure;

and packaging the graphene structure.

Optionally, when the silicon carbide substrate is annealed, the processing atmosphere is a hydrogen atmosphere, and the processing temperature includes 1200 ℃ to 1400 ℃.

Optionally, when the single-layer graphene is prepared, the heating temperature is 1200 ℃ to 1400 ℃.

Optionally, the silicon carbide substrate includes a 4H-SiC substrate, and the step height of the annealed silicon carbide substrate includes 0.6nm to 1.0nm.

Optionally, the graphene structure comprises a graphene hall bar structure obtained by an ICP etching method, the etching gas comprises oxygen, the etching power comprises 180W-220W, and the etching time comprises 100 s-150 s.

Optionally, the channel length of the formed graphene structure is 100 μm to 800 μm, and the channel width is 50 μm to 300 μm.

Optionally, the cross-sectional area of the bonding electrode layer is larger than the cross-sectional area of the electrical contact layer; the electrical contact layer comprises a palladium/gold layer, and the bonding electrode layer comprises a titanium/gold layer; in the electric contact layer, the thickness of the palladium layer is 5-10 nm, and the thickness of the gold layer is 30-50 nm; in the bonding electrode layer, the thickness of the titanium layer is 5-10 nm, and the thickness of the gold layer is 50-100 nm.

Optionally, the step of forming the electrical contact layer, the graphene structure and the bonding electrode layer includes:

providing a mask plate and placing the mask plate on the surface of the single-layer graphene;

depositing a palladium/gold layer by adopting an electron beam evaporation method or a magnetron sputtering method to form an electric contact layer on the single-layer graphene;

removing the mask plate;

obtaining a graphene structure by adopting an ICP (inductively coupled plasma) etching method;

coating photoresist, exposing the photoresist by a laser direct writing method or an electron beam exposure method, and developing an exposure area to expose the electric contact layer;

depositing a titanium/gold layer by adopting an electron beam evaporation method or a magnetron sputtering method to form a bonding electrode layer on the electric contact layer;

and removing the photoresist.

Optionally, the method for adjusting the carrier concentration of the graphene structure includes modifying the graphene structure with nitric acid, and adjusting the carrier concentration of the graphene structure to a dirac point before encapsulation.

Optionally, the encapsulating material comprises MMA, PMMA.

As described above, according to the preparation method of the graphene-based quantum resistance chip, silicon carbide subjected to hydrogen annealing treatment is used as a substrate, silicon ethane is used as a gas catalyst, acetylene is used as a carbon source, and a chemical vapor deposition method is adopted to epitaxially grow single-layer graphene, so that a graphene structure with good uniformity can be prepared at 1200-1400 ℃, and the step height of the silicon carbide substrate is kept unchanged after graphene is grown.

The quantum resistance chip prepared by the invention has the Hall resistance measurement accuracy of 1.2 multiplied by 10 under the magnetic field intensity of 6T and the temperature of 4.5K ^-8 While the relative uncertainty reaches 3 x 10 ^-8 Reproducibility of 3 x 10 ^-9 The quantum resistance chip has the advantages of miniaturization, high integration level, cost optimization, high economic benefit and strong applicability, can be directly integrated in a portable quantum resistance standard measurement system, and is favorable for promoting the further development of the precision measurement industry.

Drawings

Fig. 1 shows a process flow diagram of a method for manufacturing a graphene-based quantum resistor chip according to an embodiment of the present invention.

Fig. 2 is a schematic structural view of a silicon carbide substrate provided in an embodiment of the present invention.

Fig. 3 shows a schematic structural diagram after a single-layer graphene is formed in an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an embodiment of the invention after forming an electrical contact layer.

Fig. 5 is a schematic structural diagram of the graphene structure formed in the embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a bonding electrode layer formed in an embodiment of the invention.

Fig. 7 is an atomic force microscope scan of single layer graphene formed on a silicon carbide substrate in an embodiment of the invention.

Fig. 8 is an optical microscope image of a quantum resistor chip in an embodiment of the invention.

Fig. 9 is a graph showing a comparison of magnetic transport measurement characteristics of the quantum resistance chip in the embodiment of the present invention.

FIG. 10 is a longitudinal resistivity scatter diagram of the quantum resistor chip in the embodiment of the invention under the magnetic field with the magnetic field strength of 4T-6T and different currents.

Fig. 11 shows a graph of the accuracy, relative uncertainty and reproducibility of the hall resistance Rxy over 15 days for a quantum resistance chip in an embodiment of the present invention.

Description of the element reference numerals

100. Silicon carbide substrate

200. Single-layer graphene

201. Graphene structure

300. Electrical contact layer

400. Bonding electrode layer

a channel length

b channel width

S1 to S8

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Where an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Expressions such as "between 8230 \\8230"; "between 8230"; "may be used herein, inclusive, and expressions such as" plurality "may be used, inclusive, and expressions such as two or more, unless specifically limited otherwise. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, this embodiment provides a method for manufacturing a graphene-based quantum resistor chip, including the following steps:

s1: providing a silicon carbide substrate;

s2: annealing the silicon carbide substrate;

s3: performing epitaxial growth on the surface of the annealed silicon carbide substrate by using a chemical vapor deposition method by using silicon ethane as a gas catalyst and acetylene as a carbon source to obtain single-layer graphene covering the silicon carbide substrate;

s4: forming a patterned electrical contact layer on the single-layer graphene;

s5: patterning the single-layer graphene to obtain a graphene structure, wherein the graphene structure is in contact with the electrical contact layer;

s6: forming a patterned bonding electrode layer on the electric contact layer, wherein the bonding electrode layer is electrically connected with the electric contact layer;

s7: carrying out carrier concentration regulation and control on the graphene structure;

s8: and packaging the graphene structure.

The following describes the preparation method of the quantum resistor chip with reference to fig. 2 to 6.

First, referring to fig. 2, step S1 is performed to provide a silicon carbide substrate 100.

Next, step S2 is performed to perform an annealing process on the silicon carbide substrate 100.

As an example, when the silicon carbide substrate 100 is annealed, the processing atmosphere is a hydrogen atmosphere, and the processing temperature may include 1200 ℃ to 1400 ℃.

Specifically, the steps of the silicon carbide substrate 100 provided initially are blurred, and when the silicon carbide substrate 100 is annealed in a hydrogen atmosphere at an annealing temperature of 1200 ℃ to 1400 ℃, for example, 1200 ℃, 1300 ℃, 1400 ℃, the steps of the silicon carbide substrate 100 are uniform and clear in height, so that the performance of the subsequently prepared graphene can be improved.

As an example, the silicon carbide substrate 100 may include a 4H-SiC substrate, and the step height of the silicon carbide after annealing treatment may include 0.6nm to 1.0nm, such as 0.6nm, 0.7nm, 0.8nm, 1.0nm, and the like.

Referring to fig. 7, in the embodiment, the silicon carbide substrate 100 is a 4H-SiC substrate, and after the annealing treatment, the step height of the silicon carbide substrate 100 is 0.7nm, but the type of the silicon carbide substrate 100 is not limited thereto.

Next, referring to fig. 3, step S3 is performed to perform epitaxial growth on the surface of the annealed silicon carbide substrate 100 by using silicon ethane as a gas catalyst and acetylene as a carbon source through a chemical vapor deposition method, so as to obtain single-layer graphene 200 covering the silicon carbide substrate 100.

As an example, the heating temperature may include 1200 ℃ to 1400 ℃ when preparing the single-layer graphene 200.

Specifically, the heating temperature in the CVD furnace may be 1200 ℃, 1250 ℃, 1300 ℃, 1400 ℃, or the like when the single-layer graphene 200 is prepared. In this example, the single-layer graphene 200 covering the entire surface of the silicon carbide substrate 100 is epitaxially grown on the silicon carbide substrate 100 by Chemical Vapor Deposition (CVD) at a temperature of 1300 ℃ in a low-pressure CVD furnace using ethyl silicon as a gas catalyst and acetylene as a carbon source, and the silicon carbide substrate 100 remaining after the growth is located below the single-layer graphene 200.

Next, referring to fig. 4, step S4 is performed to form a patterned electrical contact layer 300 on the single-layer graphene 200.

As an example, the electrical contact layer 300 may include a palladium/gold layer, wherein, in the electrical contact layer 300, the thickness of the palladium layer may be 5-10 nm, such as 5nm, 8nm, 10nm, etc., and the thickness of the gold layer may be 30-50 nm, such as 30, 45nm, 50nm, etc., but the material and thickness of each layer in the electrical contact layer 300 are not limited thereto, and may be selected as needed.

Next, referring to fig. 5, in step S5, the single-layer graphene 200 is patterned to obtain a graphene structure 201, and the graphene structure 201 is in contact with the electrical contact layer 300.

As an example, the graphene structure 201 may include a graphene hall bar structure obtained by using an ICP etching method, and the etching gas is oxygen, the etching power is 180W to 220W, such as 180W, 200W, 220W, and the like, and the etching time is 100s to 150s, such as 100s, 120s, 150s, and the like, but the graphene structure 201 is not limited to the graphene hall bar structure, and may be selected as needed, and is not limited herein.

As an example, the channel length of the formed graphene structure 200 includes 100 μm to 800 μm, and the channel width includes 50 μm to 300 μm.

Specifically, referring to fig. 7, which illustrates an atomic force microscope scanning diagram of the single-layer graphene 200 epitaxially grown on the silicon carbide substrate 100, in this embodiment, the silicon carbide substrate 100 employs semi-insulating 4H — SiC and has a step with a height of 0.7nm, and after the single-layer graphene 200 is grown, the step height remains unchanged.

Fig. 8 shows an optical microscope image of the patterned single-layer graphene 200 to form the graphene hall bar structure 201, where the channel length a is 600 micrometers, the channel width b is 200 micrometers, but not limited thereto, the channel length a may also be 100 μm, 200 μm, 400 μm, 800 μm, and the like, the channel width b may be 50 μm, 100 μm, 300 μm, and the like, and values of the channel length a and the channel length b may be specifically selected as needed, which is not limited herein.

Next, referring to fig. 6, step S6 is performed to form a patterned bonding electrode layer 400 on the electrical contact layer 300, and the bonding electrode layer 400 is electrically connected to the electrical contact layer 300.

Specifically, in this embodiment, the composite metal electrode having the electrical contact layer 300 and the bonding electrode layer 400 is adopted, so that the contact resistance of the single-layer graphene 200 can be improved, and the device performance can be improved.

As an example, the bonding electrode layer 400 may include a titanium/gold layer; in the bonding electrode layer 400, the thickness of the titanium layer may be 5 to 10nm, such as 5nm, 8nm, and 10nm, and the thickness of the gold layer may be 50 to 100nm, such as 50nm, 80nm, and 100nm, but the material and thickness of each layer in the bonding electrode layer 400 are not limited thereto, and may be selected according to needs.

As an example, the cross-sectional area of the bonding electrode layer 400 is larger than that of the electrical contact layer 300, so as to facilitate subsequent electrical connection.

In fig. 6, the bonding electrode layer 400 has a larger cross-sectional area than the electrical contact layer 300, so that the electrical contact layer 300 under the bonding electrode layer 400 is not shown.

As an example, the step of forming the electrical contact layer 300, the graphene structure 201 and the bonding electrode layer 400 may include:

providing a mask plate (not shown) and placing the mask plate on the surface of the single-layer graphene 200;

depositing a palladium/gold layer by using an electron beam evaporation method or a magnetron sputtering method to form an electrical contact layer 300 on the single-layer graphene 200;

removing the mask plate;

coating a photoresist (not shown), exposing the photoresist by a laser direct writing method or an electron beam exposure method, and developing the exposed region to expose the electrical contact layer 300;

depositing a titanium/gold layer by adopting an electron beam evaporation method or a magnetron sputtering method to form a bonding electrode layer 400 on the electric contact layer 300;

and removing the photoresist.

And then, executing step S7, and regulating and controlling the carrier concentration of the graphene structure.

As an example, the method for adjusting the carrier concentration of the graphene structure includes modifying the graphene structure with nitric acid, and adjusting the carrier concentration of the graphene structure to a dirac point, which is a position where a graphene resistance value is maximum, before packaging.

Next, step S8 is performed to encapsulate (not shown) the graphene structure to protect the graphene structure and improve device performance, wherein the encapsulating material may include, but is not limited to, MMA and PMMA.

Fig. 9 is a graph comparing the current magnetic transport measurement characteristic curve with the quantum resistance chip half year ago. The black solid line is the dependency relationship between the longitudinal resistance Rxx (a) measured half year ago and the magnetic field, the black dotted line is the dependency relationship between the hall resistance Rxx (a) measured half year ago and the magnetic field, the black dotted line is the dependency relationship between the longitudinal resistance Rxx (b) of the current chip and the magnetic field, and the black dash-dot line is the dependency relationship between the hall resistance Rxx (b) of the current chip and the magnetic field.

It can be seen that the magnetic transport properties of the chip maintain a high degree of stability for a period of half a year, and both half a year ago and the current measurement results can be seen: the quantum resistance chip enters complete quantization near 2T and is expressed as a longitudinal resistance R _xx The zero platform is started to enter near 2T, the platform is kept to 6T, the Hall resistor Rxy enters the quantum Hall platform at about 1.5T, and the value of the quantum Hall platform is h/2e ² The unit Ω, where h is the Planckian constant and e is the electronic charge value. At 4.5K, the carrier concentration of the quantum resistance chip reaches 7.8 multiplied by 10 ¹⁰ cm ^-2 . In the magnetic field range of 4T to 6T, the quantum resistance chip is in a fully quantized state, and the longitudinal resistivity is lower than 10m omega/\9633;, as shown in figure 10.

FIG. 11 illustrates the Hall resistance R of the quantum resistance chip within 15 days _xy With a magnetic field strength of 6T and a temperature of 4.5K, the hall resistance measurement accuracy of the chip (horizontal dashed line) reaches 1.2 × 10 ^-8 While the relative uncertainty (half of the vertical error bar) reaches 3 × 10 ^-8 The reproducibility within 15 days (standard deviation of Hall resistance value divided by mean value within 15 days) reached 3X 10 ^-9 。

In summary, according to the preparation method of the graphene-based quantum resistance chip, the silicon carbide subjected to hydrogen annealing treatment is used as the substrate, the silicon ethane is used as the gas catalyst, the acetylene is used as the carbon source, and the chemical vapor deposition method is adopted to epitaxially grow the single-layer graphene, so that the graphene structure with good uniformity can be prepared at 1200-1400 ℃, and the step height of the silicon carbide substrate is kept unchanged after the graphene is grown.

The accuracy of Hall resistance measurement of the quantum resistance chip prepared by the invention reaches 1.2 multiplied by 10 under the magnetic field intensity of 6T and the temperature of 4.5K ^-8 While the relative uncertainty reaches 3 × 10 ^-8 Reproducibility of 3 x 10 ^-9 The quantum resistance chip has the advantages of miniaturization, high integration level, cost optimization, high economic benefit and strong applicability, can be directly integrated in a portable quantum resistance standard measurement system, and is favorable for promoting the further development of the precision measurement industry.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A preparation method of a quantum resistance chip based on graphene is characterized by comprising the following steps:

providing a silicon carbide substrate;

annealing the silicon carbide substrate;

forming a patterned electrical contact layer on the single-layer graphene;

carrying out carrier concentration regulation and control on the graphene structure;

and packaging the graphene structure.

2. The method of claim 1, wherein the method comprises: when the silicon carbide substrate is annealed, the processing atmosphere is hydrogen atmosphere, and the processing temperature comprises 1200-1400 ℃.

3. The method of claim 1, wherein the method comprises: when the single-layer graphene is prepared, the heating temperature is 1200-1400 ℃.

4. The method of claim 1, wherein the method comprises: the silicon carbide substrate comprises a 4H-SiC substrate, and the step height of the annealed silicon carbide substrate comprises 0.6 nm-1.0 nm.

5. The method of claim 1, wherein the method comprises the steps of: the graphene structure comprises a graphene Hall bar structure obtained by adopting an ICP (inductively coupled plasma) etching method, etching gas is oxygen, etching power is 180W-220W, and etching time is 100 s-150 s.

6. The method of claim 1, wherein the method comprises: the channel length of the formed graphene structure is 100-800 microns, and the channel width is 50-300 microns.

7. The method of claim 1, wherein the method comprises: the cross sectional area of the bonding electrode layer is larger than that of the electric contact layer; the electric contact layer comprises a palladium/gold layer, and the bonding electrode layer comprises a titanium/gold layer; in the electric contact layer, the thickness of the palladium layer is 5-10 nm, and the thickness of the gold layer is 30-50 nm; in the bonding electrode layer, the thickness of the titanium layer is 5-10 nm, and the thickness of the gold layer is 50-100 nm.

8. The method of claim 7, wherein the method comprises: the steps of forming the electrical contact layer, the graphene structure and the bonding electrode layer include:

removing the mask plate;

coating a photoresist, exposing the photoresist by a laser direct writing method or an electron beam exposure method, and developing an exposure area to expose the electric contact layer;

and removing the photoresist.

9. The method of claim 1, wherein the method comprises: the method for regulating the carrier concentration of the graphene structure comprises the steps of modifying the graphene structure by using nitric acid, and regulating the carrier concentration of the graphene structure to a Dirac point before packaging.

10. The method of claim 1, wherein the method comprises the steps of: the packaging material comprises MMA and PMMA.