CN115496016A - Double-clock multi-core embedded concurrent time sequence simulation method and device - Google Patents
Double-clock multi-core embedded concurrent time sequence simulation method and device Download PDFInfo
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Abstract
The invention relates to the technical field of computer application, and particularly discloses a double-clock multi-core embedded concurrent time sequence simulation method and a device, wherein the method comprises the following steps: determining the kernel rate of each kernel in the multi-kernel embedded system and simulation events needing simulation; determining the global virtual clock rate of the global virtual clock according to the core rates of all the cores; dividing the global virtual clock rate by the kernel rate to obtain a kernel clock rate ratio of the local virtual clock of each kernel to the global virtual clock; and sequentially judging whether each core needs to execute simulation in each global virtual clock period according to the ratio of the current period number of the global virtual clock to the clock rate ratio of each core, so as to simulate the simulation event in each global virtual clock period through the core needing to execute simulation. The invention solves the problem of simulation error caused by the unmatched core speeds due to different frequencies of the core processors.
Description
Technical Field
The application relates to the technical field of computer application, in particular to a double-clock multi-core embedded concurrent time sequence simulation method and device.
Background
Embedded systems are widely used in various aspects of human life. With the rapid increase of the demand of the embedded system for computing power, the performance of the single-core processor gradually cannot support the real-time requirement of the system, and the multi-core processor is increasingly applied to the safety-critical embedded system. In a safety-critical embedded system, execution of each task in the system has strict time constraint, and a time sequence anomaly may cause destructive influence on the system, resulting in serious life and property loss, and the safety-critical embedded system needs to fully demonstrate the correctness of the time sequence. At present, a simulation tool for a multi-core embedded system mostly uses the same global clock as clocks of all cores, and does not consider the problem of core speed mismatching caused by different frequencies of core processors, thereby causing simulation errors. Meanwhile, the multi-core embedded system simulation also faces the problem of judging the occurrence sequence of events, two kernels with the same frequency observe that the occurrence time of the same event differs by a period, and due to the accumulation of synchronous errors and digital errors, the occurrence time of the events differs by a global virtual clock period, so that the time sequence of different events cannot be accurately represented. The kernels with different frequencies observe the same event, and the obtained time result error is larger. The problems lead to larger errors in the simulation process, the occurrence sequence of partial events cannot be accurately judged, and the simulation analysis conclusion is unreliable.
Disclosure of Invention
The application mainly aims to provide a double-clock multi-core embedded concurrent time sequence simulation method and device, so as to solve the problem that simulation errors caused by the fact that core speeds are not matched due to different frequencies of core processors are not considered in the prior art.
According to a first aspect of the embodiments of the present application, a dual-clock multi-core embedded concurrent timing simulation method is provided, including:
determining the kernel rate of each kernel in the multi-kernel embedded system and simulation events needing simulation;
determining the global virtual clock rate of a global virtual clock according to the core rates of all cores;
dividing the global virtual clock rate by the kernel rate to obtain a kernel clock rate ratio of the local virtual clock of each kernel to the global virtual clock;
and sequentially judging whether each kernel needs to execute simulation in each global virtual clock period according to the ratio of the current period number of the global virtual clock to the clock rate ratio of each kernel, so as to simulate the simulation event through the kernel needing to execute simulation in each global virtual clock period.
Further, the simulation method further comprises:
acquiring the release jitter time and preset release starting time of each simulation event, and acquiring the clock cycle length of a global virtual clock according to the global virtual clock rate;
determining the release time of the simulation event release simulation operation according to the release starting time and the release jitter time;
and determining a global virtual clock period release node corresponding to the release time according to the release time and the clock period length, wherein when a global virtual clock goes to the global virtual clock period release node, the simulation event releases the simulation operation, so that the kernel executes the simulation operation when simulating the simulation event.
Further, the sequentially judging whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the clock rate ratio of each core comprises:
acquiring total simulation time required by simulating all kernels;
and determining the ratio of the total simulation duration to the global virtual clock rate as the total simulation global clock period number, and if the current period number of the global virtual clock is less than the total simulation global clock period number, sequentially judging whether each core needs to execute simulation in each global virtual clock period according to the ratio between the current period number of the global virtual clock and the clock rate ratio of each core.
Further, when the kernel executes the simulation operation, the kernel advances the execution of the simulation operation through the local virtual clock.
Further, said facilitating execution of said simulation job by said local virtual clock comprises:
acquiring execution time jitter, preset execution time and kernel acceleration ratio of the kernel of each simulation event;
determining the expected execution time of the kernel for executing the simulation job according to the execution time jitter and the preset execution time;
determining the actual execution time of the kernel for executing the simulation operation according to the expected execution time and the kernel acceleration ratio;
and converting the actual execution time into the number of cycles of a local virtual clock according to the kernel speed, reducing the number of cycles of the local virtual clock obtained by conversion by one every time the local virtual clock advances by one cycle when the kernel executes the simulation operation, and finishing the simulation operation by the kernel when the number of cycles of the local virtual clock obtained by conversion is reduced to zero.
Further, in the process of simulating the simulation event by the kernel to be simulated in each global virtual clock cycle, the method further includes:
and acquiring a preset event occurrence time recording rule, and recording the occurrence time and the completion time of the simulation event based on the preset event occurrence time recording rule.
Further, the recording the occurrence time and the completion time of the simulation event based on the preset event occurrence time recording rule includes:
setting the first period of the local virtual clocks of all the kernels to start at the same moment, and recording the occurrence time and the completion time of the simulation event by adopting a global virtual clock period, wherein the recorded occurrence time of the simulation event is the global virtual clock period corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event is the global virtual clock period corresponding to the start of the next local virtual clock.
Further, the determining a global virtual clock rate of a global virtual clock according to the core rates of all cores includes:
determining the least common multiple of all the kernel rates, and determining the numerical value of the integral multiple of the least common multiple as the global virtual clock rate.
Further, after determining the numerical value of the integer multiple of the least common multiple as the global virtual clock rate, dividing the global virtual clock rate by the kernel rate to obtain the kernel clock rate ratio as an integer, and then sequentially determining whether each kernel needs to execute simulation in each global virtual clock cycle according to a ratio between a current cycle number of the global virtual clock and each kernel clock rate ratio, including:
and in each global virtual clock cycle, when the ratio of the current cycle of the global virtual clock to the core clock rate ratios which are integers is an integer, determining the core to which the core clock rate ratio belongs as the core to be simulated.
According to a second aspect of the embodiments of the present application, there is provided a dual-clock multi-core embedded concurrent timing simulation apparatus, including:
the first determining module is used for determining the kernel speed of each kernel in the multi-core embedded system and simulation events needing simulation;
the second determining module is used for determining the global virtual clock rate of the global virtual clock according to the kernel rates of all the kernels;
an obtaining module, configured to divide the global virtual clock rate by the kernel rate to obtain a kernel clock rate ratio of a local virtual clock of each kernel to a global virtual clock;
and the simulation operation module is used for sequentially judging whether each kernel needs to execute simulation in each global virtual clock period according to the ratio of the current period number of the global virtual clock to the clock rate ratio of each kernel, so as to simulate the simulation event through the kernel needing to execute simulation in each global virtual clock period.
Compared with the prior art, the technical scheme of the application has at least the following technical effects:
when the multi-core embedded system is simulated, the problem of core speed mismatching caused by different frequencies of the core processor is fully considered, the multi-core embedded system with different core frequencies can be simulated, when the simulation is carried out, the core clock rate ratio is obtained according to different core rates and the global virtual clock rate, when the multiple relation between the current period number of the global virtual clock and the core clock rate ratio is integral multiple, the core starts the simulation, otherwise, the core does not execute any operation in the global virtual clock period, and the core speed matching error caused by different core frequencies is solved.
Secondly, aiming at the problem that the occurrence time sequence of events on different cores of the multi-core processor is difficult to judge, the method provides an event occurrence time recording method, the method records the occurrence time and the completion time of the simulation events according to a preset event occurrence time recording rule, ensures that the occurrence sequence of all the events can be judged, reduces the observation error to a global virtual clock period, can accurately represent the time sequence of different events, and has accurate and reliable simulation analysis conclusion.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic flowchart of a dual-clock multi-core embedded concurrent timing simulation method according to a first embodiment of the present invention;
FIG. 2 is a schematic flow chart of the simulation method before step S14 in FIG. 1;
FIG. 3 is a flowchart illustrating a simulation event release simulation operation according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating a process of executing a simulation job using a local virtual clock by each core according to a first embodiment of the present invention;
fig. 5 is a schematic structural diagram of a dual-clock multi-core embedded concurrent timing simulation apparatus according to a second embodiment of the present invention;
fig. 6 is a schematic flowchart of a dual-clock multi-core embedded concurrent timing simulation method according to a third embodiment of the present invention;
fig. 7 is a flowchart of task release operation according to a third embodiment of the present invention.
Wherein the figures include the following reference numerals:
10. a first determination module; 20. a second determination module; 30. an acquisition module; 40. and a simulation operation module.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.
According to a first embodiment of the present application, a dual-clock multi-core embedded concurrent timing sequence simulation method is provided, please refer to fig. 1, which includes the following steps:
step S11: determining the kernel rate of each kernel in the multi-kernel embedded system and the simulation event to be simulated, such as gamma kernel i Is expressed as f i Here, the core rate may be a frequency of the core.
Step S12: determining global virtual clock rate f of global virtual clock according to kernel rates of all kernels g 。
Step S13: global virtual clock rate f g Divided by kernel rate f i Obtaining a core clock rate ratio s of the local virtual clock to the global virtual clock of each core i I.e. s i ＝f g /f i 。
Step S14: and sequentially judging whether each core needs to execute simulation in each global virtual clock period according to the ratio of the current period number of the global virtual clock to the clock rate ratio of each core, so as to simulate the simulation event in each global virtual clock period through the core needing to execute simulation.
Referring to fig. 2, step S14 sequentially determines whether each core needs to execute simulation in each global virtual clock cycle according to a ratio between the current cycle number of the global virtual clock and the clock rate ratio of each core, and includes the following steps:
step S21: acquiring total simulation time required by all kernels for simulation;
step S22: determining the ratio of the total simulation duration to the global virtual clock rate as the total simulation global clock period number, if the current period number of the global virtual clock is less than the total simulation global clock period number, indicating that the simulation is not finished, namely that the kernels are not simulated, and if the simulation is not finished, sequentially judging whether each kernel needs to execute the simulation in each global virtual clock period according to the ratio between the current period number of the global virtual clock and each kernel clock rate ratio.
Referring to fig. 3, if the simulation is not finished, step S14 sequentially determines whether each core needs to execute the simulation in each global virtual clock cycle according to a ratio between the current cycle number of the global virtual clock and the rate ratio of each core clock, and first releases the simulation operation for the simulation event (such as an interrupt and a task) according to the current cycle number of the global virtual clock, which specifically includes the following steps:
step S31: obtaining the release jitter time and the preset release starting time of each simulation event, and obtaining the clock period length p of the global virtual clock according to the global virtual clock rate g Length of clock cycle
Step S32: determining the release time of the simulation event release simulation operation according to the release starting time and the release jitter time;
step S33: and determining a global virtual clock period release node corresponding to the release time according to the release time and the clock period length, and when the global virtual clock goes to the global virtual clock period release node, releasing the simulation operation by the simulation event so as to execute the simulation operation when the kernel simulates the simulation event.
In order to make the embodiments of the present invention more clear, the above steps S31-S33 are further described by taking the simulation event as the periodic task release task, and it is assumed that the periodic task τ is i Has a period of T i The initial release time is srt i The release jitter is rj i Periodic task τ i Using a global variable rc i Recording the number of release operations, rc before starting simulation i Initialized to 0 and calculated tau using a periodic task arrival time calculation formula i Time rt of the first release job 1 ，rt 1 = srt + j, where j ~ U (-rj) i ,rj i ) The formula indicates that element j obeys the range U (-rj) i ,rj i ) Then, calculating a global virtual clock period gt corresponding to the release moment,
global virtual clock period corresponding to task first release operation
When the global virtual clock goes to the period, the periodic task tau i Release its first job (i.e., first simulation job), then rc i Is incremented by one, the system calculates the time rt at which the task next releases the job 2 ＝(srt+T i ) + j, wherein, j to U (-rj) i ,rj i ) Calculating the corresponding global virtual clock period when the second operation is released
Global virtual clock arrival gt 2 When, the task releases the job for the second time, rc i Is increased by one and the process is repeated until the simulation is finished.
And when the kernel executes the simulation operation, the kernel pushes the execution of the simulation operation through a local virtual clock of the kernel. The execution of the simulation job is advanced by a local virtual clock of the kernel, as shown in fig. 4, which includes the following steps:
step S41: acquiring execution time jitter, preset execution time and kernel acceleration ratio of each simulation event;
step S42: determining the expected execution time of the kernel for executing the simulation job according to the execution time jitter and the preset execution time;
step S43: determining the actual execution time of the kernel executing the simulation operation according to the expected execution time and the kernel acceleration ratio;
step S44: and converting the actual execution time into the number of cycles of the local virtual clock according to the kernel speed, reducing the number of cycles of the converted local virtual clock by one every time the local virtual clock advances by one cycle when the kernel executes the simulation operation, and finishing the simulation operation by the kernel when the number of cycles of the converted local virtual clock is reduced to zero. And when all the cores finish the simulation operation (namely all the cores finish the simulation), adding one to the current cycle of the global virtual clock until the current cycle of the global virtual clock is greater than the total cycle of the simulated global clock, and ending the simulation.
Inner check task tau in the embodiment of the invention i In releasing the kth simulation job
The content of the above steps S41-S44 is further explained by taking the time advance execution process as an example, and the task τ is i At release of the k-th job
Time-dependent jitter et i And the preset task execution time C i Determining execution time of job
Because the frequency and the speed of the processor cores are different, the execution time of the same task on different cores is also different, the core speed-up ratio sr is used for representing the difference of the processor core speeds, and the larger the speed-up ratio is, the faster the processing speed of the cores is. Job is being assigned to kernel γ n Then, according to the kernel acceleration ratio sr n Calculating the actual execution time of the job, equal to
Converting job execution time to number of cycles of local virtual clock lt k ，
When working
In kernel gamma n When doing so, every time γ n Forward one by the local virtual clockThe period of the time period is as follows,
is remaining number of execution cycles lt k Minus one, when lt k Operation is indicated when 0
The execution is complete. The execution process of the interrupt is similar to the job execution process, and is not described herein again.
In the process of executing the simulation operation flow to the simulation event to be simulated by the system simulation model through each kernel, the simulation method provided by the invention further comprises the following steps: acquiring a preset event occurrence time recording rule, recording the occurrence time and the completion time of the simulation event based on the preset event occurrence time recording rule, and specifically comprising the following steps:
setting the first periods of the local virtual clocks of all the cores to start at the same moment, ensuring that all the simulation events occur at the beginning of each local virtual clock, recording the occurrence time and the completion time of the simulation events by adopting a global virtual clock period, wherein the recorded occurrence time of the simulation events is the corresponding global virtual clock period when the local virtual clock starts, and the recorded completion time of the simulation events occurs in the corresponding global virtual clock period when the next local virtual clock starts.
In step S12, determining the global virtual clock rate of the global virtual clock according to the kernel rates of all the kernels includes:
and determining the least common multiple of all the kernel rates, and determining the integral multiple of the least common multiple as the global virtual clock rate. In the embodiment of the invention, the global virtual clock rate f g Equal to the least common multiple of all kernel rates (i.e., a value that is one time the least common multiple), i.e., f g ＝LCM(f 1 ,...,f n ). The resulting core clock rate ratio s i Is an integer, i.e. s i ＝f g /f i
At this time, in step S14, sequentially determining whether each core needs to execute simulation in each global virtual clock cycle according to a ratio between the current cycle number of the global virtual clock and the clock rate ratio of each core, including:
in each global virtual clock cycle, when the ratio of the current cycle number of the global virtual clock to one or more core clock rate ratios which are integers is an integer, one or more cores to which the one or more core clock rate ratios belong are determined as cores to be subjected to simulation. And only when the current cycle number of the global virtual clock is integral multiple of the rate ratio of the kernel, the kernel executes simulation in the current global virtual clock cycle, the kernel which does not satisfy the condition does not execute any operation in the cycle, waits for the coming of the next cycle until simulation can be performed, and finishes the simulation after all the kernels finish the simulation.
Therefore, when the multi-core embedded system is simulated, the problem of core speed mismatching caused by different frequencies of the core processor is fully considered, the multi-core embedded system with different core frequencies can be simulated, when the simulation is carried out, according to the core clock rate ratios obtained by different core rates and the global virtual clock rate, when the multiple relation between the current period number of the global virtual clock and the core clock rate ratio is integral multiple, the core starts to simulate, otherwise, the core does not execute any operation in the global virtual clock period, and the problem of core speed matching error caused by different core frequencies is solved.
Secondly, aiming at the problem that the occurrence time sequence of events on different cores of the multi-core processor is difficult to judge, the method provides an event occurrence time recording method, the method records the occurrence time and the completion time of the simulation events according to a preset event occurrence time recording rule, ensures that the occurrence sequence of all the events can be judged, reduces the observation error to a global virtual clock period, can accurately represent the time sequence of different events, and has accurate and reliable simulation analysis conclusion.
A second embodiment of the present application provides a dual-clock multi-core embedded concurrent timing simulation apparatus, please refer to fig. 5, which includes:
the first determining module 10 is configured to determine a kernel rate of each kernel in the multi-core embedded system and a simulation event to be simulated;
a second determining module 20, configured to determine a global virtual clock rate of the global virtual clock according to the core rates of all the cores;
an obtaining module 30, configured to divide the global virtual clock rate by the kernel rate to obtain a kernel clock rate ratio of the local virtual clock of each kernel to the global virtual clock;
and the simulation running module 40 is configured to sequentially determine whether each core needs to perform simulation in each global virtual clock cycle according to a ratio between the current cycle number of the global virtual clock and the clock rate ratio of each core, so as to perform simulation on a simulation event through the cores that need to perform simulation in each global virtual clock cycle.
In the embodiment of the present application, the simulation running module 40 further executes the following steps:
step S31: obtaining the release jitter time and the preset release starting time of each simulation event, and obtaining the clock period length p of the global virtual clock according to the global virtual clock rate g Length of clock cycle
Step S32: determining the release time of the simulation event release simulation operation according to the release starting time and the release jitter time;
step S33: and determining a global virtual clock period release node corresponding to the release time according to the release time and the clock period length, and when the global virtual clock goes to the global virtual clock period release node, releasing the simulation operation by the simulation event so as to execute the simulation operation when the kernel simulates the simulation event.
The simulation running module 40 sequentially judges whether each core needs to execute simulation in each global virtual clock cycle according to the ratio between the current cycle number of the global virtual clock and the clock rate ratio of each core, and the simulation running module 40 further executes the following steps of the method:
step S21: acquiring total simulation time required by all kernels for simulation;
step S22: and determining the ratio of the total simulation duration to the global virtual clock rate as the total simulated global clock cycle number, and if the current cycle number of the global virtual clock is less than the total simulated global clock cycle number, sequentially judging whether each kernel needs to execute simulation in each global virtual clock cycle by the simulation operation module 40 according to the ratio between the current cycle number of the global virtual clock and the clock rate ratio of each kernel.
When the simulation running module 40 makes the kernel execute the simulation job, the execution of the simulation job is advanced by the local virtual clock of the kernel, and the execution of the simulation job which is advanced by the simulation running module 40 by the local virtual clock of the kernel specifically includes the following steps:
step S41: acquiring execution time jitter, preset execution time and kernel acceleration ratio of each simulation event;
step S42: determining the expected execution time of the kernel for executing the simulation job according to the execution time jitter and the preset execution time;
step S43: determining the actual execution time of the kernel executing the simulation operation according to the expected execution time and the kernel acceleration ratio;
step S44: and converting the actual execution time into the number of cycles of the local virtual clock according to the kernel speed, reducing the number of cycles of the converted local virtual clock by one every time the local virtual clock advances by one cycle when the kernel executes the simulation operation, and finishing the simulation operation by the kernel when the number of cycles of the converted local virtual clock is reduced to zero. And when all the cores finish the simulation operation (namely all the cores finish the simulation), adding one to the current cycle number of the global virtual clock until the current cycle number of the global virtual clock is greater than the total simulation cycle number, and finishing the simulation.
In the process that the simulation running module 40 simulates the simulation event through the kernel to be simulated in each global virtual clock cycle, the following method steps are also executed:
and acquiring a preset event occurrence time recording rule, and recording the occurrence time and the completion time of the simulation event based on the preset event occurrence time recording rule.
Wherein, based on the record rule of the event occurrence time that is preserved, carry on the record to the occurrence time and the completion time of the simulation event, include: setting the first period of the local virtual clocks of all the kernels to be started at the same moment, and recording the occurrence time and the completion time of the simulation event by adopting a global virtual clock period, wherein the recorded occurrence time of the simulation event is the global virtual clock period corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event is the global virtual clock period corresponding to the start of the next local virtual clock.
When the second determining module 20 determines the global virtual clock rate of the global virtual clock according to the core rates of all the cores, the least common multiple of the core rates is determined, and the numerical value of the integral multiple of the least common multiple is determined as the global virtual clock rate.
After the second determining module 20 determines the integer multiple of the least common multiple as the global virtual clock rate, the obtaining module 30 divides the global virtual clock rate by the kernel rate to obtain a kernel clock rate ratio as an integer, at this time, the simulation running module 40 sequentially determines whether each kernel needs to execute simulation in each global virtual clock cycle according to a ratio between the current cycle number of the global virtual clock and each kernel clock rate ratio, and in each global virtual clock cycle, when a ratio between the current cycle number of the global virtual clock and a plurality of kernel clock rate ratios as integers is an integer, the kernel to which the kernel clock rate ratio belongs is determined as the kernel to be executed with simulation.
Therefore, the device provided by the invention can simulate the multi-core embedded system with different core frequencies, solves the problem that the occurrence time sequence of events on different cores of a multi-core processor is difficult to judge due to different core frequencies, and provides the event occurrence time recording method to ensure that the occurrence sequence of all events can be judged and reduce the observation error to a global virtual clock period.
In order to make the present invention more clearly understood, the third embodiment of the present application combines with an application embodiment provided in fig. 6 to 7 on the basis of the two embodiments, so as to specifically describe a specific implementation process of concurrent timing simulation of a dual-clock multi-core embedded system.
Referring to fig. 6, the embodiment of the present invention provides a method for implementing a dual-clock multi-core embedded concurrent timing simulation method, taking simulation events as interrupts and tasks as examples, including the following steps:
step one, defining a system model, and setting the speed of each kernel of the system, namely the kernel gamma i Is expressed as f i Here, the rate may be the frequency of the core;
step two, calculating the speed f of the global virtual clock of the simulation system g The rate of the global virtual clock is equal to the least common multiple of the rates of all cores, i.e., f g ＝LCM(f 1 ,...,f n ) (ii) a And calculates the period length of the global virtual clock g
Step three, calculating the rate ratio of the local virtual clock and the global virtual clock of each kernel, namely the kernel gamma i The ratio of the local virtual clock to the global virtual clock rate is represented as s i Equal to the global virtual clock rate divided by the kernel rate, i.e. s i ＝f g /f i ；
Step four, calculating the total simulation clock period number a according to the total simulation duration t, wherein a = t/f g ；
Step five, before the simulation begins, setting the current period C of the global virtual clock g To 0, set the local virtual clock current period C for each core 1 Is 0;
step six, in the simulation process, whether the simulation is finished or not is judged firstly when the global virtual clock period begins, and when C g >and a, finishing the simulation. If the simulation is not finished, firstly, the current period of the global virtual clock is determinedC g Releasing interrupt and task, judging whether kernel is simulated or not in sequence, and when the global virtual clock period number is integral multiple of kernel rate ratio, namely C g mods i =0, the core starts the simulation, otherwise the core does not perform any operation in this global virtual clock cycle. When all the kernels are executed, the current period C of the global virtual clock g And adding 1.
Referring to fig. 7, the release time of the interrupt and task is determined according to the global virtual clock. Suppose a periodic task τ i Has a period of T i The initial release time is srt i The release jitter is rj i Periodic task τ i Using a global variable rc i Recording the number of release operations, rc before starting simulation i Initialized to 0 and calculated tau using a periodic task arrival time calculation formula i Time rt of the first release job 1 ，rt 1 = srt + j, where j ~ U (-rj) i ,rj i ) The formula indicates that element j obeys the range U (-rj) i ,rj i ) Then, calculating a global virtual clock period gt corresponding to the release moment,
global virtual clock period corresponding to task first release operation
When the global virtual clock goes to the period, the task tau i Release its first job, then rc i Is incremented by one, the system calculates the time rt at which the task next releases the job 2 ＝(srt+T i ) + j, wherein, j to U (-rj) i ,rj i ) Calculating the corresponding global virtual clock period when the second operation is released
Global virtual clock arrival gt 2 When, the task releases the job for the second time, rc i Is increased by one and the process is repeated until the simulation is finished.
Releasing mode of accidental task and random taskBasically the same as the periodic task, the release times of the task are maintained by using a global variable, after the current task is released, the release time of the next task and the corresponding global virtual clock period are calculated, the calculation mode of the global virtual clock period is the same as that of the periodic task, and only the calculation mode of the release time is different, such as assuming an accidental task or a random task tau i Is srt i The release jitter is rj i Task τ i Using a global variable rc i Recording the number of release operations, rc before starting simulation i Initialized to 0, task τ i Time rt of the first release job 1 ，rt 1 = srt + j, where j ~ U (-rj) i ,rj i ) Then, calculating a global virtual clock period gt corresponding to the release moment,
global virtual clock period corresponding to task first release operation
The interrupt release flow is the same as the task release flow.
In order to be able to compare the order of occurrence of events on different kernels, the simulation is based on the following assumptions: the first period of all kernel local virtual clocks starts at the same time; the occurrence time of all events is recorded by using a global virtual clock; all events occur at the beginning of each local virtual clock, interrupts and job releases occur at the corresponding global virtual clock cycle at the beginning of the local virtual clock, and interrupts and job completions occur at the corresponding global virtual clock cycle at the beginning of the next local virtual clock.
After the tasks and the interrupts are distributed to different kernels by the global scheduler, the tasks and the interrupts are managed by the kernel local scheduler, and the execution of the tasks and the interrupts is promoted by the kernel local virtual clock. Task tau i At release of the k-th job
Time-dependent jitter et i And task execution time C i Determining execution time of job
Because the frequency and the speed of the processor cores are different, the execution time of the same task on different cores is also different, the core speed-up ratio sr is used for representing the difference of the processor core speeds, and the larger the speed-up ratio is, the faster the processing speed of the cores is. The job is distributed to the kernel gamma n Then, according to the kernel acceleration ratio sr n Calculating the actual execution time of the job, equal to
Converting job execution time to number of cycles of local virtual clock lt k ，
When working
In kernel gamma n When doing so, every time γ n The local virtual clock of (a) is advanced by one cycle,
is remaining number of execution cycles lt k Minus one, when lt k Operation is indicated when 0
The execution is complete. Similar to the job execution time simulation, other constrained simulations of a job also use local virtual clock pushing, and when a job is assigned to a kernel, the time related to execution, such as the message demand time, the message generation time, and the global variable modification time of the job, is first divided by the time actually required for simulation on the kernel calculated by the speed-up ratio of the kernel, and then each time is converted into the cycle number of the kernel local virtual clock. When the operation is executed by the kernel, the local virtual clock is increased by one, the relevant time for executing the operation is decreased by one, and when the time is decreased to 0, the corresponding action is executed according to the execution condition of the system. Of interruptionsThe execution process is similar to the job execution process.
Finally, the invention discloses a double-clock multi-core embedded concurrent time sequence simulation method. The method comprises six steps of defining a system model, setting the speed of each kernel of the system, calculating the speed of a global virtual clock of the simulation system, calculating the speed ratio of a local virtual clock and the global virtual clock of each kernel, determining the total number of the global clock cycles of the simulation, initializing the global virtual clock and the local virtual clock, and performing simulation operation. The invention can simulate a multi-core embedded system with different core frequencies, solves the problem that the core speed matching error caused by different core frequencies is difficult to judge the sequence of the event occurrence time on different cores of a multi-core processor, provides an event occurrence time recording method, ensures that the sequence of all events can be judged, and reduces the observation error to a global virtual clock period.
For ease of description, spatially relative terms such as "above … …", "above … …", "above … … upper surface", "above", etc. may be used herein to describe the spatial positional relationship of one device or feature to other devices or features as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A double-clock multi-core embedded concurrent time sequence simulation method is characterized by comprising the following steps:
determining the kernel rate of each kernel in the multi-kernel embedded system and simulation events needing simulation;
determining the global virtual clock rate of a global virtual clock according to the core rates of all cores;
dividing the global virtual clock rate by the kernel rate to obtain a kernel clock rate ratio of the local virtual clock of each kernel to the global virtual clock;
and sequentially judging whether each core needs to execute simulation in each global virtual clock period according to the ratio of the current period number of the global virtual clock to the clock rate ratio of each core, so as to simulate the simulation event in each global virtual clock period through the cores needing to execute simulation.
2. The dual-clock multi-core embedded concurrent timing simulation method according to claim 1, further comprising:
acquiring the release jitter time and preset release starting time of each simulation event, and acquiring the clock cycle length of a global virtual clock according to the global virtual clock rate;
determining the release time of the simulation event release simulation operation according to the release starting time and the release jitter time;
and determining a global virtual clock period release node corresponding to the release time according to the release time and the clock period length, wherein when a global virtual clock goes to the global virtual clock period release node, the simulation event releases the simulation operation, so that the kernel executes the simulation operation when simulating the simulation event.
3. The dual-clock multi-core embedded concurrent timing sequence simulation method according to claim 1 or 2, wherein the sequentially judging whether each core needs to execute simulation in each global virtual clock cycle according to a ratio between a current cycle number of the global virtual clock and a rate ratio of each core clock comprises:
acquiring total simulation time required by simulating all kernels;
and determining the ratio of the total simulation duration to the global virtual clock rate as the total simulation global clock period number, and if the current period number of the global virtual clock is less than the total simulation global clock period number, sequentially judging whether each core needs to execute simulation in each global virtual clock period according to the ratio between the current period number of the global virtual clock and the clock rate ratio of each core.
4. The dual-clock multi-core embedded concurrent timing simulation method according to claim 2, wherein when the kernel executes the simulation job, execution of the simulation job is advanced by the local virtual clock.
5. The dual-clock multi-core embedded concurrent timing simulation method according to claim 4, wherein the advancing execution of the simulation job by the local virtual clock comprises:
acquiring execution time jitter, preset execution time and kernel acceleration ratio of the kernel of each simulation event;
determining the expected execution time of the kernel for executing the simulation job according to the execution time jitter and the preset execution time;
determining the actual execution time of the kernel for executing the simulation operation according to the expected execution time and the kernel acceleration ratio;
and converting the actual execution time into the number of cycles of a local virtual clock according to the kernel speed, reducing the number of cycles of the local virtual clock obtained by conversion by one every time the local virtual clock advances by one cycle when the kernel executes the simulation operation, and finishing the simulation operation by the kernel when the number of cycles of the local virtual clock obtained by conversion is reduced to zero.
6. The dual-clock multi-core embedded concurrent timing simulation method according to claim 1, wherein in the process of simulating the simulation event by a kernel that needs to execute simulation in each global virtual clock cycle, the method further comprises:
and acquiring a preset event occurrence time recording rule, and recording the occurrence time and the completion time of the simulation event based on the preset event occurrence time recording rule.
7. The dual-clock multi-core embedded concurrent timing sequence simulation method according to claim 6, wherein the recording the occurrence time and completion time of the simulation event based on the preset event occurrence time recording rule comprises:
setting the first period of the local virtual clocks of all the kernels to start at the same moment, and recording the occurrence time and the completion time of the simulation event by adopting a global virtual clock period, wherein the recorded occurrence time of the simulation event is the global virtual clock period corresponding to the start of the local virtual clock, and the recorded completion time of the simulation event is the global virtual clock period corresponding to the start of the next local virtual clock.
8. The dual-clock multi-core embedded concurrent timing simulation method according to claim 1, wherein the determining a global virtual clock rate of a global virtual clock according to the core rates of all cores comprises:
determining the least common multiple of all the kernel rates, and determining the numerical value of the integral multiple of the least common multiple as the global virtual clock rate.
9. The dual-clock multi-core embedded concurrent timing sequence simulation method according to claim 8, wherein after determining the numerical value of the integer multiple of the least common multiple as the global virtual clock rate, the core clock rate ratio obtained by dividing the global virtual clock rate by the core rate is an integer, and then sequentially determining whether each core needs to execute simulation in each global virtual clock cycle according to a ratio between the current cycle number of the global virtual clock and each core clock rate ratio comprises:
and in each global virtual clock cycle, when the ratio of the current cycle of the global virtual clock to the core clock rate ratios which are integers is an integer, determining the core to which the core clock rate ratio belongs as the core to be simulated.
10. A dual-clock multi-core embedded concurrent timing sequence simulation device is characterized by comprising:
the first determining module (10) is used for determining the kernel rate of each kernel in the multi-core embedded system and simulation events needing simulation;
a second determining module (20) for determining a global virtual clock rate of a global virtual clock from the core rates of all cores;
an obtaining module (30) for dividing the global virtual clock rate by the core rate to obtain a core clock rate ratio of the local virtual clock to the global virtual clock of each core;
and the simulation running module (40) is used for sequentially judging whether each kernel needs to execute simulation in each global virtual clock period according to the ratio of the current period number of the global virtual clock to the clock rate ratio of each kernel, so that the simulation event is simulated in each global virtual clock period through the kernels needing to execute simulation.
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