CN115495801B

CN115495801B - USB (universal serial bus) channel disconnection protection method, electronic equipment, self-destruction circuit and medium

Info

Publication number: CN115495801B
Application number: CN202211442690.7A
Authority: CN
Inventors: 李智勇; 张小亮; 郭轶尊
Original assignee: Beijing Superred Technology Co Ltd
Current assignee: Beijing Superred Technology Co Ltd
Priority date: 2022-11-18
Filing date: 2022-11-18
Publication date: 2023-03-10
Anticipated expiration: 2042-11-18
Also published as: CN115495801A

Abstract

The present application relates to the field of data transmission, and in particular, to a USB channel disconnection protection method, an electronic device, a self-destruction circuit, and a medium. The method is performed by an electronic device, the electronic device comprising: the self-destruction circuit comprises a processor, a self-destruction circuit, a self-destruction resistor and a bare communication interface, wherein one end of the processor is connected to one end of the self-destruction resistor, the other end of the self-destruction resistor is connected to the bare communication interface, the other end of the processor is also connected to the self-destruction circuit, and the self-destruction circuit is connected with the self-destruction resistor; the exposed communication interface is used for information interaction with external equipment; the method comprises the following steps: when the processor detects that a first preset condition is met, a starting command is sent to the self-destruction circuit, so that the self-destruction circuit controls the self-destruction of the self-destruction resistor. The application has the effect of improving the safety of the electronic equipment.

Description

USB (universal serial bus) channel disconnection protection method, electronic equipment, self-destruction circuit and medium

Technical Field

The present application relates to the field of data transmission, and in particular, to a USB channel disconnection protection method, an electronic device, a self-destruction circuit, and a medium.

Background

The USB path refers to a path for transmitting data. After electronic equipment, such as a mobile phone, is produced, the electronic equipment needs to be tested, in a machine testing link, the tested equipment is placed on a work station to perform testing, recording, exporting a machine Log, refreshing and other operations, in the operation processes, a USB channel in the tested equipment needs to be utilized, data is uploaded into the tested equipment by a testing machine or downloaded from the tested equipment, data transmission between the tested equipment and a testing machine is realized, and when data transmission is not needed, the USB channel needs to be disconnected.

At present, a controlled circuit is mostly used to control the disconnection and conduction of a USB channel, the controlled circuit is usually implemented by a software control method, a device under test outputs a start instruction to the controlled circuit, the controlled circuit controls the USB channel to be conducted, the device under test outputs a disconnection instruction to the controlled circuit, and the controlled circuit controls the USB channel to be disconnected, so as to control the USB channel.

However, in the above-described method, when data exchange is not required, the controlled circuit is in an off state, and the controlled circuit can be controlled by another rogue device to turn on the USB channel, so that the rogue device can import unauthorized information into the electronic device through the USB channel or export information in the electronic device through the USB channel, and the information security of the electronic device is low.

Disclosure of Invention

In order to improve the information security of the electronic device, the application provides a USB channel disconnection protection method, an electronic device, a self-destruction circuit and a medium.

In a first aspect, the present application provides a USB path disconnection protection method, which adopts the following technical solution:

a USB path disconnection protection method performed by an electronic device, the electronic device comprising: the self-destruction circuit comprises a processor, a self-destruction circuit, a self-destruction resistor and a bare communication interface, wherein one end of the processor is connected to one end of the self-destruction resistor, the other end of the self-destruction resistor is connected to the bare communication interface, the other end of the processor is also connected to the self-destruction circuit, and the self-destruction circuit is connected with the self-destruction resistor; the exposed communication interface is used for information interaction with external equipment;

wherein the method comprises the following steps:

when the processor detects that a first preset condition is met, the processor sends a starting command to the self-destruction circuit, so that the self-destruction circuit controls the self-destruction of the self-destruction resistor.

By adopting the technical scheme, when the processor detects that the first preset condition is met, the starting command is sent to the self-destruction circuit, so that the self-destruction circuit controls the self-destruction resistor to carry out self-destruction, the self-destruction resistor is arranged between the exposed communication interface of the electronic equipment for carrying out information interaction with the external equipment and the processor, and after the self-destruction resistor is self-destroyed, an information interaction channel between the external equipment and the processor is completely disconnected, so that the external equipment is difficult to introduce unsafe information into the electronic equipment and lead the information out of the electronic equipment, and the information safety of the electronic equipment can be improved.

In one possible implementation manner, the electronic device further includes: the change-over switch comprises a first connecting port and a second connecting port, one end of the processor is connected to the first connecting port, and the second connecting port is connected to one end of the self-destruction resistor; wherein, the first and the second end of the pipe are connected with each other,

the processor sends a starting command to the self-destruction circuit, and the method comprises the following steps:

acquiring the state of the selector switch;

wherein the processor sends a turn-on command to the self-destruction circuit, including:

and if the state of the change-over switch is an off state, the processor sends a starting command to the self-destruction circuit, and the off state represents that the processor and the self-destruction resistor are in an off state.

In another possible implementation manner, the obtaining the state of the switch further includes:

and if the state of the change-over switch is a first conduction state, controlling the change-over switch to be switched to the disconnection state, wherein the first conduction state represents that the processor and the self-destruction resistor are in conduction state.

In another possible implementation manner, the self-destruction circuit comprises a boosting unit and a load switch;

the boosting unit comprises an input end, an output end and a backflow ground, the input end is connected to the processor, and the processor is used for controlling the boosting unit to boost according to a preset rule;

the load switch comprises a first port, a second port, a third port and a fourth port, wherein the first port is connected to the output end, the second port is connected to the backflow ground, the third port is connected to one end, connected with the change-over switch, of the self-destruction resistor, the fourth port is connected to the other end of the self-destruction resistor, and the load switch is used for enabling the voltage after the boosting unit is boosted to act on the self-destruction resistor.

In another possible implementation manner, the self-destruction circuit further includes a protection unit, one end of the protection unit is connected to the third port, the other end of the protection unit is connected to one end of the self-destruction resistor connected to the change-over switch, and the protection unit is configured to disconnect a path where the protection unit is located when a current higher than a preset current threshold flows through the protection unit.

In another possible implementation manner, the manner of controlling the boosting unit to boost according to the preset rule includes any one of the following:

controlling the boosting unit to boost voltage, wherein the boosted voltage is in direct proportion to self-destruction duration, and the starting time of the self-destruction duration is the time when the self-destruction resistor starts self-destruction;

and controlling the boosting unit to boost the voltage based on the corresponding relation between the self-destruction duration and the voltage.

In another possible implementation manner, the method further includes:

when the processor sends a starting command to the self-destruction circuit, a timer is started;

determining whether the self-destruction resistance is successfully self-destroyed;

if the self-destruction is not successful and the timing duration of the timer reaches the preset self-destruction duration, the processor sends a self-destruction termination instruction to the self-destruction circuit so that the self-destruction circuit controls the self-destruction resistor to terminate the self-destruction;

if the self-destruction is not successful and the timing duration of the timer does not reach the preset self-destruction duration, circularly executing to determine whether the self-destruction of the resistor is successful or not until a second preset condition is met;

the second preset condition includes any one of:

the self-destruction of the self-destruction resistor is successful, and the timing duration of the timer does not reach the preset self-destruction duration;

the self-destruction resistor is not successfully self-destroyed, and the timing duration of the timer reaches the preset self-destruction duration;

the self-destruction of the self-destruction resistor is successful, and the timing duration of the timer reaches the preset self-destruction duration.

In another possible implementation manner, the determining whether the self-destruction resistance is successful in self-destruction includes:

if a notification message sent by the self-destruction circuit is received, determining that the self-destruction of the self-destruction resistor is successful, wherein the notification message is used for notifying the processor that the current value of the self-destruction resistor in a first preset time period is abnormal;

wherein the self-destruction circuit further comprises: a current detection unit and a detection resistor;

one end of the detection resistor is connected to the fourth port, and the other end of the detection resistor is connected to one end of the self-destruction resistor connected with the exposed communication interface;

the current detection unit comprises a first input port, a second input port and an output port, the first input port is connected to one end of the detection resistor, the second input port is connected to the other end of the detection resistor, the output port is connected to the processor and used for detecting the current value of the detection resistor so as to determine whether the current value of the self-destruction resistor in a first preset time period is abnormal or not, and when the current value is abnormal, the notification message is sent to the processor.

In another possible implementation manner, the method further includes:

if the self-destruction is successful, controlling the switch to be switched to the first conduction state;

obtaining a detection result sent by a preset test tool, wherein the detection result is obtained by detecting a path between the exposed communication interface and the processor by the preset test tool;

and if the detection result represents that the path is disconnected, feeding the detection result back to the server.

In another possible implementation manner, the first preset condition includes any one of the following:

receiving a self-destruction instruction input by a user, wherein the self-destruction instruction is used for indicating self-destruction of the self-destruction resistor;

detecting that no data is written and/or read in a second preset time period;

detecting that the time from the last self-destruction termination reaches a preset time interval.

In another possible implementation manner, the electronic device further includes a dedicated module, and the switch further includes a third connection port, where the third connection port is connected to the dedicated module;

the special module is used for carrying out information transmission with the processor when the change-over switch is in a second conduction state, and the second conduction state represents that the special module and the processor are in a conduction state.

In a second aspect, the present application provides an electronic device, which adopts the following technical solutions:

an electronic device, comprising: the system comprises a processor, a self-destruction circuit, a self-destruction resistor and a bare communication interface;

one end of the processor is connected to one end of the self-destruction resistor;

the other end of the self-destruction resistor is connected to the exposed communication interface, the other end of the processor is also connected to the self-destruction circuit, and the self-destruction circuit is connected with the self-destruction resistor;

the exposed communication interface is used for information interaction with external equipment; the processor is configured to execute the USB path disconnection protection method shown in the first aspect.

By adopting the technical scheme, in order to disconnect the USB channel between the exposed communication interface and the processor, the self-destruction resistor is arranged on the USB channel, the processor controls the self-destruction circuit to drive the self-destruction resistor to carry out self-destruction so as to realize disconnection of the USB channel, and then external equipment is difficult to steal data or introduce unsafe data through the USB channel, so that the information security of the electronic equipment is improved.

In one possible implementation, the electronic device further includes: the self-destruction resistor comprises a self-destruction resistor, a processor and a change-over switch, wherein the change-over switch comprises a first connecting port and a second connecting port, one end of the processor is connected to the first connecting port, and the second connecting port is connected to one end of the self-destruction resistor.

the load switch comprises a first port, a second port, a third port and a fourth port, wherein the first port is connected to the output end, the second port is connected to the backflow ground, the third port is connected to one end of the self-destruction resistor connected with the change-over switch, the fourth port is connected to the other end of the self-destruction resistor, and the load switch is used for enabling the voltage after the boosting unit is boosted to act on the self-destruction resistor.

In another possible implementation manner, the self-destruction circuit further includes: a current detection unit and a detection resistor;

In a third aspect, the present application provides a self-destruction circuit, which adopts the following technical scheme:

a self-destruction circuit comprises a boosting unit, wherein the boosting unit comprises an input end, an output end and a backflow ground, and the input end is connected to a processor and used for boosting according to a preset rule under the control of the processor;

the output end is connected to one end of a self-destruction resistor, the output end is connected to the other end of the self-destruction resistor in a backflow mode, the boosted voltage acts on the self-destruction resistor to enable the self-destruction resistor to be self-destroyed, the self-destruction resistor is used for disconnecting the connection between the processor and the exposed communication interface after being self-destroyed, and the exposed communication interface is used for information interaction between the processor and external equipment.

By adopting the technical scheme, when the self-destruction circuit controls the self-destruction resistor to carry out self-destruction, the processor controls the boosting unit to boost according to a preset rule, then the boosted voltage acts on two ends of the self-destruction resistor, the self-destruction resistor continuously accumulates heat under the action of the voltage until fusing, the self-destruction is completed, the self-destruction resistor is arranged between the processor and the exposed communication interface, after the self-destruction is completed, a USB (universal serial bus) channel between the processor and the exposed communication interface is disconnected, external equipment is difficult to realize information interaction with the processor through the exposed communication interface, the safety of electronic equipment is improved, secondly, in the self-destruction process of the self-destruction resistor, the boosting unit is utilized to continuously boost, the heat accumulation rate of the self-destruction resistor is accelerated, and the self-destruction process of the self-destruction resistor is accelerated.

In a possible implementation manner, the self-destruction circuit further includes a current detection unit and a detection resistor, one end of the detection resistor is connected to the output end, and the other end of the detection resistor is connected to one end of the self-destruction resistor;

the current detection unit comprises a first input port, a second input port and an output port, the first input port is connected to one end of the detection resistor, the second input port is connected to the other end of the detection resistor and used for detecting the current value of the detection resistor so as to determine whether the current value of the self-destruction resistor in a first preset time period is abnormal or not, and a notification message is sent when the current value of the self-destruction resistor in the first preset time period is abnormal;

the output port is connected with the processor and is used for sending the notification message to the processor.

In another possible implementation manner, the self-destruction circuit further comprises a load switch;

the load switch comprises a first port, a second port, a third port and a fourth port, the first port is connected to the output end, the second port is connected to the reflux ground, the third port is connected to one end of the self-destruction resistor, and the fourth port is connected to the other end of the self-destruction resistor;

the load switch further comprises a fifth port, and the fifth port is connected to the processor and is used for applying the voltage boosted by the boosting unit to the self-destruction resistor after receiving a starting command sent by the processor.

In another possible implementation manner, the self-destruction circuit further includes a protection unit;

one end of the protection unit is connected with the output end, and the other end of the protection unit is connected with one end of the self-destruction resistor, which is used for being connected with the output end, and is used for disconnecting the path when current higher than a preset current threshold flows.

In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solutions:

a computer-readable storage medium, comprising: a computer program is stored which can be loaded by a processor and which implements the USB path disconnection protection method described above.

To sum up, the application comprises the following beneficial technical effects:

1. when the processor detects that a first preset condition is met, a starting command is sent to the self-destruction circuit, so that the self-destruction circuit controls the self-destruction resistor to carry out self-destruction, the self-destruction resistor is arranged between a naked communication interface of the electronic equipment, which is used for carrying out information interaction with external equipment, and the processor, and after the self-destruction resistor is self-destroyed, an information interaction channel between the external equipment and the processor is completely disconnected, so that the external equipment is difficult to introduce unsafe information into the electronic equipment and to derive the information from the electronic equipment, and the information safety of the electronic equipment can be improved.

2. When the self-destruction resistor is not successfully self-destroyed for a long time, the self-destruction resistor is characterized to be abnormal and not successfully self-destroyed within a normal time range, and meanwhile, the voltage raised by the boosting unit is possibly in a higher level, so that other components are easily impacted.

Drawings

FIG. 1 is a block diagram of an electronic device according to an embodiment of the present application;

FIG. 2 is a flow chart illustrating a USB channel disconnection method according to an embodiment of the present disclosure;

FIG. 3 is a block diagram of an electronic device including a switch according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a self-destruct circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a load switch connected to a processor according to an embodiment of the present application;

FIG. 6 is a flowchart of a first example of the program according to the embodiment of the present application;

FIG. 7 is a flowchart of a second example of the program according to the embodiment of the present application;

fig. 8 is a schematic connection diagram of a self-destruct circuit according to an embodiment of the present application.

Description of reference numerals:

1. a processor; 2. a switch; 3. a self-destruction circuit; 31. a voltage boosting unit; 32. a load switch; 33. a current detection unit; 34. detecting a resistance; 35. a protection unit; 4. a self-destruction resistor; 5. a bare communication interface; 6. a filter; 7. and (5) a special module.

Detailed Description

The present application is described in further detail below with reference to figures 1-8.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

After electronic devices such as a computer, a mobile phone and a tablet are produced, the electronic devices need to be subjected to a station passing test, for example, tests such as a CPU performance test, a network card test, a lead-out machine LOG and a machine-flushing test are performed at a station, and after each test is completed, the tested data needs to be uploaded to a server, so that when problems occur, the source tracing can be performed in time. In the testing process, the electronic device also needs to receive data issued by the server, for example, in the flash test, the server needs to transmit the operating system of the machine to the electronic device, so that the electronic device can download and install the operating system.

As shown in fig. 1, the electronic device includes a processor 1 and a bare communication interface 5, the bare communication interface 5 is used for externally connecting an external device, the bare communication interface 5 is connected with the processor 1 inside the electronic device, and a path between the processor 1 and the bare communication interface 5 is a USB path. The exposed communication interface 5 comprises a USB interface, a TYPE-C interface, a debug port and a secret key port.

During testing, the server realizes data interaction with the USB channel through the exposed communication interface 5. After the test is finished, data interaction with external equipment is not needed any more. However, lawless persons may steal data in the processor 1 or introduce unsafe data into the processor 1 through the exposed communication interface 5, and therefore the USB channel needs to be disconnected after the test is completed, so as to block a path for stealing information or introducing unsafe information by external equipment, and improve data security of the electronic equipment.

In order to realize the on-off control of the USB channel, a controlled switch may be implemented in the form of a switching tube (e.g., a MOS tube, a BJT, or other switching element), or a relay switch, where the controlled switch is connected to the USB channel in series and controlled by the processor 1 in the electronic device, and the processor 1 controls the switch of the controlled switch to be turned off, so as to turn off the USB channel.

However, the switch of the controlled switch is always in a controllable state, that is, when the switch controlling the controlled switch is closed again, the disconnected USB channel is then turned on again, so that it is possible to upload unsafe data into the electronic device or export data from the electronic device through the turned-on USB channel to threaten the safety of the electronic device.

Therefore, the USB channel can be completely disconnected after the electronic equipment is tested, so that the safety of the electronic equipment is improved. An embodiment of the present application provides a USB path disconnection protection method, which may be executed by an electronic device, as shown in fig. 1, where the electronic device may include: the system comprises a processor 1, a self-destruction circuit 3, a self-destruction resistor 4 and an exposed communication interface 5, wherein one end of the processor 1 is connected with one end of the self-destruction resistor 4, the other end of the self-destruction resistor 4 is connected with the exposed communication interface 5, the other end of the processor 1 is also connected with the self-destruction circuit 3, and the self-destruction circuit 3 is connected with the self-destruction resistor 4; the exposed communication interface 5 is used for information interaction with external equipment.

Specifically, in order to control the on-off of the USB channel (the channel between the processor 1 and the exposed communication interface 5), the self-destruction resistor 4 is connected in series with the USB channel, when the USB channel needs to be disconnected, the self-destruction resistor 4 will perform self-destruction, and when the self-destruction succeeds, the position of the self-destruction resistor 4 will become an open circuit and cannot be recovered, and then the external device cannot send unsafe information to the processor 1 of the electronic device or derive data from the processor 1 through the exposed communication interface 5, so that the safety of the electronic device can be improved. The self-destruction circuit 3 is used for controlling the self-destruction resistor 4 to perform self-destruction, and is used for receiving an instruction of the processor 1, and when the processor 1 needs to self-destroy the USB channel, the self-destruction circuit 3 controls the self-destruction resistor 4 to self-destroy, so as to realize disconnection control of the USB channel.

Further, on the basis of the internal structure of the electronic device shown in fig. 1, an embodiment of the present application further provides a method for controlling disconnection of a USB channel, as shown in fig. 2, the method may include:

step S201, when the processor 1 detects that the first preset condition is met, the processor 1 sends a turn-on command to the self-destruction circuit 3, so that the self-destruction circuit 3 controls the self-destruction resistor 4 to self-destroy.

The first preset condition is used for representing the condition when the USB channel needs to be disconnected.

Specifically, when the processor 1 detects that the first preset condition is met, that is, the processor 1 needs to disconnect the USB channel at this time is characterized, at this time, the processor 1 outputs a start command to the self-destruction circuit 3, and the self-destruction circuit 3 controls the self-destruction resistor 4 to perform self-destruction after receiving the start command. The self-destruction resistor 4 after self-destruction becomes open circuit, information can not circulate through a channel where the self-destruction resistor 4 is located, then disconnection control of the USB channel is achieved, and if external equipment attempts to steal information through the exposed communication interface 5 at the moment, the USB channel of data interaction is disconnected due to the fact that the self-destruction resistor 4 in the electronic equipment is self-destroyed, and bad attempts of the external equipment are difficult to achieve.

Furthermore, since the self-destruction resistor 4 cannot be recovered after self-destruction, external devices cannot steal information data and import illegal information in a manner of recovering the self-destruction resistor 4, and thus the information security of the electronic device is improved, and the reliability of the security can be improved.

However, in the self-destruction process of the self-destruction resistor 4, a high voltage impact may be generated on the processor 1, which may cause an unnecessary EOS problem of the processor 1, and therefore, in order to reduce the influence on the processor 1 when the self-destruction resistor 4 is self-destroyed, referring to fig. 3, the switch 2 is connected between the processor 1 and the self-destruction resistor 4, the switch 2 includes a first connection port and a second connection port, the first connection port is connected to one end of the processor 1 for connecting with the self-destruction resistor 4, and the second connection port is connected to one end of the self-destruction resistor 4.

In step S201, the processor 1 sends a turn-on command to the self-destruction circuit 3, and the method further includes: the state of the changeover switch 2 is acquired.

The states of the switch 2 include a first on state and an off state, the first on state represents that the self-destruction resistor 4 and the processor 1 are in an on state, and the off state represents that the self-destruction resistor 4 and the processor 1 are in an off state.

Specifically, the change-over switch 2 is arranged between the self-destruction resistor 4 and the processor 1, and when the switch is turned off (i.e. the path between the self-destruction resistor 4 and the processor 1 is in an off state), the state of the change-over switch 2 is in an off state; when the switch is closed (i.e. the path between the self-destruction resistor 4 and the processor 1 is in a conducting state), the state of the switch 2 is switched to the first conducting state.

Specifically, the manner in which the processor 1 obtains the state of the switch 2 may include: in a normal state of the self-destruction circuit 3, a small voltage acts on two ends of the self-destruction resistor 4, when the processor 1 can detect a small current, the current state of the switch 2 is represented as a first on state, and if the processor 1 does not detect the current, the state of the switch 2 is represented as an off state.

Further, the manner of acquiring the state of the switch 2 by the processor 1 may further include: the processor 1 may determine the state after the last switching of the control switch 2 by accessing an internal memory and determining the state as the current state of the switch 2, for example: the last time the processor 1 controls the switch 2 to switch to the off state, the processor 1 accesses the memory to determine that the current state of the switch 2 is the off state.

Further, after the processor 1 acquires the state of the switch 2, the processor 1 sends a turn-on command to the self-destruction circuit 3, which may specifically include: if the state of the change-over switch 2 is off, the processor 1 sends a turn-on command to the self-destruction circuit 3. When the state of the switch 2 acquired by the processor 1 is a disconnected state, the processor 1 sends a turn-on command to the self-destruction circuit 3 to enable the self-destruction circuit 3 to control the self-destruction resistor 4 to carry out self-destruction, and because the switch 2 is arranged between the processor 1 and the self-destruction resistor 4, when the self-destruction resistor 4 carries out self-destruction, the generated high-voltage impact is difficult to be transmitted into the processor 1 through the disconnected switch 2, so that the probability of generating an unnecessary EOS problem caused by the fact that the processor 1 receives a high-voltage signal is reduced, and the safety of the processor 1 is further improved.

If the state of the changeover switch 2 acquired by the processor 1 is the first on state, it is indicated that the self-destruction of the self-destruction resistor 4 is necessary at this time, but if the processor 1 is directly self-destroyed, there is a risk that the processor 1 is damaged. Therefore, in order to avoid the processor 1 from being impacted by the high voltage of the self-destruction circuit 3 as much as possible, the method for acquiring the state of the change-over switch 2 may further include the following steps: if the state of the change-over switch 2 is the first on state, the change-over switch 2 is controlled to be switched to the off state.

That is to say, when the processor 1 self-destructs the self-destruction resistor 4, if the switch 2 is in the on state of the processor 1 and the self-destruction resistor 4, the processor 1 can also control the switch 2 to switch to the off state, that is, when the processor 1 and the self-destruction resistor 4 are disconnected, then the processor 1 sends a self-destruction circuit 3 start command to the self-destruction circuit 3 to control the self-destruction of the self-destruction resistor 4.

Specifically, in the embodiment of the present application, the manner of controlling the switch 2 to switch to the off state may include: the processor 1 sends a corresponding type of trigger signal to the switch 2 to trigger the switch 2 to switch the state, for example: the state of the switch 2 acquired by the processor 1 is a first on state, at this time, a low-level trigger signal is sent to the switch 2, and after receiving the low-level trigger signal, the switch 2 is disconnected so that the connection between the processor 1 and the self-destruction resistor 4 is in an open circuit state.

In another possible implementation manner, if the state of the switch 2 acquired by the processor 1 is the first on state, that is, when the self-destruction resistor 4 is turned on with the processor 1, the sending of the start command to the self-destruction circuit 3 is stopped, so that the self-destruction circuit 3 does not perform the self-destruction operation of the self-destruction resistor 4, and further the safety of the processor 1 is improved until the processor 1 or a person switches the state of the switch 2 to the off state, and then when a first preset condition is met, the processor 1 sends the start command again, so that the self-destruction circuit 3 controls the self-destruction resistor 4 to perform self-destruction.

In the above embodiment, a scheme of using the self-destruction circuit 3 to control the self-destruction resistor 4 to perform self-destruction when the switch 2 is in the off state or the first on state is described; in any of the above-described embodiments, in order to self-destruct the self-destruction circuit 3 with reference to fig. 4, the self-destruction circuit 3 includes a boosting unit 31 and a load switch 32; the boosting unit 31 comprises an input end, an output end and a reflux ground, wherein the input end is connected to the processor 1 and is used for receiving a starting command sent by the processor 1 and boosting according to a preset rule after receiving the starting command; the load switch 32 includes a first port, a second port, a third port and a fourth port, wherein the first port is connected to the output end, the second port is connected to the backflow ground, the third port is connected to one end of the self-destruction resistor 4 connected to the switch 2, the fourth port is connected to the other end of the self-destruction resistor 4, and the load switch 32 is configured to apply the voltage boosted by the voltage boosting unit 31 to the self-destruction resistor 4.

Specifically, referring to fig. 5, the load switch 32 is also connected to the processor 1, and is configured to receive a start command sent by the processor 1, and is closed after receiving the start command, so that a path between the voltage boosting unit 31 and the self-destruction resistor 4 is turned on, and further, in a process that the self-destruction resistor 4 is not self-destroyed, a voltage boosted by the voltage boosting unit 31 is transmitted into a circuit to affect data transmission of the processor 1.

The processor 1 controls the boosting unit 31 to boost according to a preset rule, and applies the boosted voltage to two ends of the self-destruction resistor 4. According to the heat effect of the resistor, the self-destruction resistor 4 continuously accumulates heat under the action of voltage, and when the accumulated heat reaches a preset heat value, the self-destruction resistor 4 is fused, so that circuit breaks are formed at two ends of the self-destruction resistor 4, and self-destruction of the self-destruction resistor 4 is realized. Fusing belongs to the condition of being irreversible, will unable the recovery after self-destruction resistance 4 is fused, consequently when there is external equipment to attempt to steal data, be difficult to make disconnected USB route reconon, consequently, external equipment will be difficult to realize stealing the illegal attempt of data or uploading illegal data, furthermore, the voltage at self-destruction resistance 4 both ends grow gradually, the heat that accumulates in the unit interval increases gradually, be favorable to accelerating the rate of heat accumulation, and then accelerate self-destruction resistance 4, the duration of waiting for self-destruction resistance 4 self-destruction has been reduced, convenience is improved.

Further, when the self-destruction resistor 4 is fused, fine sparks may be generated, so that in order to reduce the influence of the self-destruction resistor 4 on other components during self-destruction, when the self-destruction circuit 3 and the PCB of the self-destruction resistor 4 are designed, the setting position of the self-destruction resistor 4 needs to avoid flammable materials, and the situation that the flammable materials contact the sparks to start burning when sparks are generated is reduced; meanwhile, the setting position of the self-destruction resistor 4 should also avoid a temperature sensitive region, for example, in a preset region near the processor 1, when the temperature is too high, the pin of the processor 1 may be damaged, and an unnecessary EOS problem is generated; further in order to reduce the possibility of burning, shielding cases can be added at two ends of the self-destruction resistor 4 on the PCB, when the self-destruction resistor 4 is fused, if other materials near the self-destruction resistor 4 are caused to burn, the shielding cases can be blocked, so that the burning area is limited in the area surrounded by the shielding cases, the burning area is not enlarged, and the influence on other components and parts when the self-destruction resistor 4 is self-destroyed is further reduced.

Further, in order to reduce the interference signal during data transmission by using the USB channel and improve the quality of data transmission, referring to fig. 3, a filter 6 may be further disposed between the switch 2 and the exposed communication interface 5, and the filter 6 may be used to filter out a noise signal during data transmission, and further, the filter 6 may be a common mode filter for suppressing EMI noise of the electronic device. The filter 6 may be disposed between the switch 2 and the self-destruction resistor 4, or between the self-destruction resistor 4 and the exposed communication interface 5, which is not limited herein, and fig. 3 is a schematic diagram of disposing the filter 6 between the switch 2 and the self-destruction resistor 4.

Furthermore, in order to fuse the self-destruction resistor 4, a resistor with a small package size may be used as the self-destruction resistor 4, for example, a resistor with an actual package size of 01005, 0201, or the like is selected, the power that the resistor with a small package size can bear is small, the corresponding preset heat value is small, that is, the heat that needs to be accumulated during fusing is small, and the resistor with a small package size is easier to fuse.

In order to accelerate the heat accumulation rate of the self-destruction resistor 4 and enable the self-destruction resistor 4 to be successfully self-destroyed as soon as possible, in the self-destruction process of the self-destruction resistor 4, the voltage across the self-destruction resistor 4 needs to be controlled to be continuously increased, wherein the processor 1 controls the boosting unit 31 to boost according to a preset rule, and the boosting mode includes any one of a first mode and a second mode, wherein:

the first method is as follows: the boosting unit 31 is controlled to boost.

The boosted voltage is in direct proportion to the self-destruction duration, and the starting time of the self-destruction duration is the time when the self-destruction resistor 4 starts self-destruction. That is, when the self-destruction resistor 4 starts self-destruction, the voltage boosting unit 31 gradually boosts the voltage across the self-destruction resistor 4 along with the self-destruction time.

For example, the time when the processor 1 issues the turn-on command (i.e. the time when the self-destruction resistor 4 turns on the self-destruction) is 08. In the embodiment of the present application, the voltage boosting unit 31 boosts the voltage step by step until the self-destruction resistor 4 is self-destroyed, or the voltage boosting unit 31 boosts the voltage step by step until the self-destruction resistor 4 is self-destroyed successfully or is pressurized to the preset voltage threshold.

Further, in a possible implementation manner, the boosted voltage has a direct proportional relationship with a self-destruction duration, where the self-destruction duration represents a duration counted from zero from an initial time, for example, the initial time is 08 00: if k is equal to 20 (as shown in table 1 below), the self-destruction duration is 2 seconds, and the corresponding increased voltage value is 40V; after 1 second, when the current time is 08 00.

TABLE 1

If a coordinate system is established by taking the self-destruction duration as a horizontal axis and the increased voltage as a vertical axis, boosting is carried out in a first mode, and the corresponding image of the increased voltage-the self-destruction duration is a line segment which is continuously increased by taking an original point as a starting point.

It should be noted that the relationship between the boosted voltage and the self-destruction time period K times shown in the above embodiments is only an example, and is not a limitation to the embodiments of the present application.

The second method comprises the following steps: and controlling the boosting unit 31 to boost the voltage based on the corresponding relation between the self-destruction duration and the voltage.

Specifically, the boosting period is determined based on the self-destruction duration, each boosting period corresponds to one voltage value, and in any one boosting period, the voltage boosted by the boosting unit 31 is controlled to be the voltage value corresponding to the any one boosting period.

Before the processor 1 controls the boosting unit 31 to boost the voltage based on the correspondence relationship of the boosting period and the voltage value, the processor 1 creates the correspondence relationship of the boosting period and the voltage. In this embodiment, a voltage boosting cycle may correspond to a voltage value, for example, a self-destruction duration is counted from 0 second to 1 second as a voltage boosting cycle, the corresponding voltage value is 20 volts (V), and may also correspond to a voltage value, where the voltage value may form a preset relationship with a corresponding time period, and may also correspond to a preset voltage value, for example, the voltage boosting cycle corresponding to the self-destruction duration from 0 second to 1 second may correspond to 10V-20V.

Further, in the above embodiment, each boosting cycle may have a voltage value, and the voltage values corresponding to different boosting cycles may be the same or different. In order to increase the speed of the self-destruction resistor 4 fusing, it is preferable that the voltage value corresponding to the subsequent boosting period is higher than the voltage value corresponding to the previous boosting period in chronological order. For example: as shown in table 2, when the starting time is 08 00, and the preset boosting period is 2 seconds, then the boosting period between the first node and the second node is a time period from 0 second to 2 seconds, corresponding to 08.

TABLE 2

In a preset boosting duration (corresponding to a first boosting period) after the processor 1 sends a starting command, the output voltage is kept as a voltage value corresponding to the first boosting period; and entering a second boosting period after the preset boosting duration, wherein the output voltage is boosted to a voltage value corresponding to the second boosting period and is kept at the voltage value in the second boosting period, and so on, and in the nth boosting period, the voltage boosted by the boosting unit 31 is kept at the voltage value corresponding to the nth boosting period.

Further, if the voltage boosting unit 31 generates a high voltage during voltage boosting, and the self-destruction resistor 4 has not been successfully self-destroyed, it is easy to damage other devices, so as to reduce the probability of damage of other devices due to overvoltage or overcurrent, referring to fig. 4, the self-destruction circuit 3 further includes a protection unit 35, one end of the protection unit 35 is connected to the third port of the load switch 32, and the other end of the protection unit 35 is connected to the end of the self-destruction resistor 4 connected to the switch 2, and the protection unit 35 is configured to disconnect the path where the self-destruction resistor 35 is located when a current higher than a preset current threshold flows through the self-destruction resistor, and/or the voltage at the two ends of the protection unit 35 exceeds the preset voltage threshold.

Because the boosting unit 31 can gradually boost the voltage, if the boosting unit 31 generates an extremely high voltage, the heat of the self-destruction resistor 4 is not accumulated to a preset heat value, that is, the self-destruction is not successful, the overvoltage and the overcurrent generated by the boosting unit 31 easily flow into other components at the moment, and damage is caused to other components, at the moment, the protection unit 35 detects that the current exceeds a preset current value, and protects the circuit to be disconnected, and in addition, if the voltages at the two ends of the protection power supply exceed a preset voltage threshold, the circuit to be disconnected is also protected, so that the overvoltage and/or the overcurrent are effectively prevented from flowing into a loop, and damage is caused to other components.

After the processor 1 sends a turn-on command to the self-destruction circuit 3, on one hand, the self-destruction circuit 3 is driven to control the self-destruction resistor 4 to perform self-destruction, and on the other hand, the processor 1 is further configured to perform a step Sa1 (not shown), a step Sa2 (not shown), and a step Sa3 (not shown), wherein:

in step Sa1, when the processor 1 sends a start command to the self-destruction circuit 3, a timer is started.

For the embodiment of the application, when the voltage of the boosting unit 31 is continuously boosted, after the preset self-destruction duration, the voltage output by the boosting unit 31 is very large, which may affect other components, and if the heat accumulated by the self-destruction resistor 4 is still insufficient to support the self-destruction by fusing the self-destruction resistor 4, the self-destruction is stopped at this time, so as to reduce the threat of the high voltage to other components. When the processor 1 sends a start command to the self-destruction circuit 3, the self-destruction circuit 3 starts to control the self-destruction of the self-destruction resistor 4, and simultaneously starts a timer to time, wherein the time length measured by the timer is the time length from the self-destruction resistor 4 to the current time when the self-destruction resistor starts to self-destruct.

For example, at 08.

And step Sa2, determining whether the self-destruction resistor 4 is successfully self-destroyed.

If the self-destruction resistor 4 can be successfully self-destroyed within the preset self-destruction duration, the current self-destruction process is represented as a normal process; if the self-destruction resistor 4 fails to be successfully self-destroyed within the preset self-destruction duration, the current self-destruction process is represented to be abnormal, and the self-destruction needs to be terminated. Therefore, the processor 1 needs to determine whether the self-destruction resistor 4 is successfully self-destroyed, and determine whether the self-destruction needs to be terminated by combining the timing duration of the timer.

Further, in order to detect whether the self-destruction resistor 4 is successfully self-destroyed, referring to fig. 4, the self-destruction circuit 3 further includes a current detection unit 33 and a detection resistor 34, one end of the detection resistor 34 is connected to the fourth port, and the other end is connected to one end of the self-destruction resistor 4 connected to the exposed communication interface 5; the current detection unit 33 includes a first input port, a second input port, and an output port, where the first input port is connected to one end of the detection resistor 34, the second input port is connected to the other end of the detection resistor 34, and the output port is connected to the processor 1, and is configured to detect a current value of the detection resistor 34, determine whether the current value of the self-destruction resistor 4 in a first preset time period is abnormal, and send a notification message to the processor 1 when the abnormality occurs.

The notification message is used to notify the processor 1 that the current value of the self-destruction resistor 4 is abnormal within a first preset time period. The first preset time period may include one detection period (the definition of the detection period is detailed in the following embodiments, and is not described herein), and may further include at least two detection periods, where the current detection unit 33 detects whether the current value in the first preset time period is abnormal, and may specifically detect whether the current value in the at least one detection period is abnormal, or whether the current value in the at least two detection periods is abnormal, and is detailed in the following embodiments, and is not described herein.

Specifically, when the self-destruction resistor 4 is successfully self-destroyed, the current cannot flow, and the current of the self-destruction resistor 4 changes abruptly, which is different from the normally increased current. Therefore, it is possible to determine whether the self-destruction resistance 4 has succeeded in self-destruction based on the current flowing through the self-destruction resistance 4. However, in the self-destruction process of the self-destruction resistor 4, the self-destruction resistor 4 continuously accumulates heat to gradually self-destroy, and the resistance value of the self-destruction resistor 4 changes in the process, so that it is difficult to directly detect the voltage at the two ends of the self-destruction resistor 4 to determine the current of the self-destruction resistor 4.

In order to determine whether the self-destruction resistor 4 is successfully self-destroyed, referring to fig. 4, a detection resistor 34 is disposed in the self-destruction circuit 3, the detection resistor 34 is connected in series between the self-destruction resistor 4 and the fourth port of the load switch 32, and the current flowing through the detection resistor 34 is equal to the current flowing through the self-destruction resistor 4, that is, the current flowing through the self-destruction resistor 4 is detected according to the detection resistor 34.

Therefore, the current detection unit 33 can determine the current flowing through the self-destruction resistor 4 by collecting the voltages at the two ends of the detection resistor 34, and further determine whether the current value flowing through the self-destruction resistor 4 is abnormal, if so, the current value represents that the self-destruction of the self-destruction resistor 4 is successful, and send a notification message to the processor 1 to indicate that the current self-destruction of the self-destruction resistor 4 of the processor 1 is successful.

As can be seen from the foregoing embodiment, the first preset time period may include at least two detection cycles, and when the current detection unit 33 detects current values of the at least two detection cycles, the method specifically includes: the current detection unit 33 sequentially sets detection periods in a segmented manner, the first detection period starts from the time when the self-destruction resistor 4 starts self-destruction, ends after a preset time interval, and enters the next detection period, and the start of the next detection period is the time when the first detection period ends, and so on. The current detection unit 33 detects whether the current value in the first detection period is abnormal, if no abnormality occurs, that is, the self-destruction resistor 4 is not successfully self-destroyed, the current detection unit detects whether the current value in the second detection period is abnormal, and so on, until the current value in the nth detection period is detected to be abnormal, the self-destruction resistor 4 is successfully self-destroyed. For example: the time when the self-destruction resistor 4 starts self-destruction is 08.

Wherein, when the first preset time period includes at least two detection cycles, for example: after the self-destruction resistor 4 starts to be self-destroyed, taking the first detection period and the second detection period as a first preset time period, respectively judging whether the current values in the first detection period and the second detection period are abnormal, and if the current values in the first detection period and the second detection period are not abnormal, representing that the self-destruction resistor 4 is not self-destroyed successfully.

Further, when the first preset time period includes at least two detection cycles, in any one of the detection cycles, a mode of determining whether the current value of the self-destruction resistor 4 is abnormal includes any one of a mode one and a mode two, where:

the first method is as follows: and judging whether the current value of the self-destruction resistor 4 in any detection period is in a preset current range.

When the current value of the self-destruction resistor 4 in any detection period is within a preset current range, the self-destruction resistor 4 is represented to be not self-destroyed successfully; when the current value of the self-destruction resistor 4 is not within the preset current range, the self-destruction of the self-destruction resistor 4 is represented to be successful.

When the self-destruction of the self-destruction resistor 4 succeeds, the self-destruction resistor 4 is in an open circuit state, so that when the self-destruction succeeds, the value of the current flowing through the self-destruction resistor 4 should be theoretically zero, or when the value of the current flowing through the self-destruction resistor 4 is zero, the self-destruction success of the self-destruction resistor 4 can be judged. In consideration of the problems of the detection accuracy, the error and the like of the current detection unit 33, in practical application, when the self-destruction of the self-destruction resistor 4 is successful, the measured current value of the self-destruction resistor 4 may not be zero, so a preset current range is set, and when the current detection unit 33 detects that the current value of the self-destruction resistor 4 is not within the preset current range, the self-destruction of the self-destruction resistor 4 is represented to be successful. For example: the preset current range is set to be (5 mA, infinity), and when the current value of the self-destruction resistor 4 is below 5mA, the self-destruction of the self-destruction resistor 4 can be considered to be successful.

Since the current value of the self-destruction resistor 4 increases with time, the normal current value standard corresponding to each detection period is different, for example, the current value is generally 5A in the first detection period and 10A in the second detection period. Therefore, in the embodiment of the present application, each detection period is set to have a corresponding preset current range. Wherein each preset current range may be the same or different. Preferably, the preset current ranges corresponding to each detection period are different.

On one hand, before judging whether the self-destruction of the self-destruction resistor 4 is successful, a preset current range corresponding to any one detection period is determined, for example: the time when the self-destruction resistor 4 starts self-destruction is taken as the beginning, and according to the time sequence, each detection period is a first detection period, a second detection period and a third detection period … … nth detection period in sequence, wherein the first detection period corresponds to a preset current range 1, the second detection period corresponds to a preset current range 2, the third detection period corresponds to a preset current range 3, the nth detection period corresponds to a preset current range n, if any detection period is a fifth detection period, the detection period corresponds to a preset current range 5, and when the current value in any detection period is determined to be in the preset current range, whether the current value is in the preset current range 5 is judged.

Specifically, the manner of determining the preset current range corresponding to the any one detection period by the current detection unit 33 may include: a simulation circuit is arranged on the basis of the self-destruction circuit 3 to carry out a self-destruction simulation experiment, and the simulation circuit comprises a boosting unit 31, a load switch 32, a detection resistor 34, a self-destruction resistor 4 and the connection relation among all devices, wherein the boosting unit 31 has the same parameters as the self-destruction circuit 3; and performing a self-destruction simulation experiment, namely self-destroying the self-destruction resistor 4 in the same self-destruction mode as the self-destruction circuit 3, determining the current change of the self-destruction resistor 4 in the self-destruction process, and generating a standard current change curve. It should be noted that the standard current variation curve may also be preset, and is not limited in the embodiment of the present application.

If the boosting mode of the boosting unit 31 is a boosting mode in which boosting is performed in a direct proportional relationship with the self-destruction time (that is, the first mode described above), according to the standard current variation curve, the current value at the start time of any one detection period is taken as the lower limit of the preset current range, and the current value at the end time of any one detection period is taken as the upper limit of the preset current range, so as to determine the preset current range corresponding to any one detection period.

If the boosting mode of the boosting unit 31 is a mode of boosting based on the corresponding relationship between the time period and the voltage (i.e., the above-mentioned mode two), the preset time interval corresponding to any one detection period may be equal to the preset boosting time of the boosting unit 31, or may be a multiple of the preset boosting time, preferably, the preset time interval corresponding to the first preset time period is equal to the preset boosting time, and then in the standard current change curve, the current of any one detection period is a fixed value, so that the preset current range may be a range within the error allowable range with the current as the reference. For example: if the resistance of the detection resistor 34 is 2 ohms, in the example shown in table 2, the time period from 2 seconds to 4 seconds during the self-destruction period corresponds to a first preset time period, the corresponding boosted voltage in the first preset time period is 40V, the allowable error range is 2V, and the preset current range is { 42/resistance of the detection resistor 34, 38/resistance of the detection resistor 34 }, that is, the preset current range is {24, 19}.

On the other hand, after determining the preset current range corresponding to the any one detection period, the current detection unit 33 determines whether the current value in the any one detection period is in the corresponding preset current range. Whether the current value in any one detection period is abnormal or not can be detected in real time, or a target current value is extracted according to a preset frequency in any one detection period, and whether the target current value is in a corresponding preset current range or not is judged, for example: and after the detection period starts, selecting a target current value every 1 second, judging whether the target current value is within a preset current range, if so, extracting the target current value again two seconds after the start, and carrying out detection judgment until the detection period is finished, or judging that the target current value is not within the preset current range in the detection period.

The second method comprises the following steps: and integrating the current value in any detection period according to the current value in any detection period, and judging whether the integrated electric quantity value is lower than a preset electric quantity threshold value or not, wherein if the integrated electric quantity value is lower than the preset electric quantity threshold value, the self-destruction of the self-destruction resistor 4 is represented to be successful, and if the integrated electric quantity value is not lower than the preset electric quantity threshold value, the self-destruction resistor 4 is represented to be unsuccessful.

Specifically, the method for detecting the self-destruction success of the self-destruction resistor 4 may also be a segmented integration method, where each detection period corresponds to a preset electric quantity threshold, and the preset electric quantity thresholds corresponding to each detection period may be the same or different. And integrating the current in each detection period based on a standard current change curve obtained by the simulation experiment in the first mode and the preset time interval of each detection period, and obtaining a standard electric quantity value after integration, wherein the standard electric quantity value can be used as a preset electric quantity threshold value.

And integrating the actual current value in the any detection period according to time to obtain the actual electric quantity value in the any detection period, then determining a preset electric quantity threshold corresponding to the any detection period, and if the self-destruction resistor 4 is successfully self-destroyed in the any detection period, judging whether the self-destruction resistor 4 is successfully self-destroyed or not if the electric quantity consumed by the resistor in the any detection period is less, namely the actual electric quantity value is less than the preset electric quantity threshold.

In the above embodiment, the way that the processor 1 represents that the self-destruction of the self-destruction resistor 4 is successful when receiving the notification message sent by the current detection unit 33 is described, and represents that the self-destruction resistor 4 is not successful when the processor 1 does not receive the notification message.

Step Sa3, if the self-destruction is not successful and the timing duration of the timer reaches the preset self-destruction duration, the processor 1 sends a self-destruction termination instruction to the self-destruction circuit 3, so that the self-destruction circuit 3 controls the self-destruction resistor 4 to terminate the self-destruction.

Specifically, when the timing duration of the timer reaches the preset self-destruction duration, the representation of the current self-destruction duration is longer, and in order to improve the security of other components in the electronic device, if the self-destruction has not been successful at this time, the processor 1 will not perform self-destruction again, and at this time, the processor 1 will send a self-destruction termination instruction to the self-destruction circuit 3, so that the self-destruction circuit 3 controls the self-destruction resistor 4 to terminate the self-destruction, and further, the threat of high voltage to other components in the electronic device is reduced.

Specifically, the step of determining whether the counted time length of the timer reaches the preset self-destruction time length may be executed before the step (step Sa 2) of determining whether the self-destruction of the self-destruction resistor 4 is successful, may be executed after the step Sa2, and may be executed simultaneously with the step Sa 2.

In a possible implementation manner, the step of judging whether the timing duration of the timer reaches the preset self-destruction duration is executed before the step Sa2, specifically, after the processor 1 sends a start command, the timer starts timing, when the timing duration of the timer reaches the preset self-destruction duration, the processor 1 determines whether the self-destruction of the self-destruction resistor 4 is successful, if it is determined that the self-destruction of the self-destruction resistor 4 is successful, the self-destruction is represented to be normal, and the self-destruction is ended; if it is determined that the self-destruction resistor 4 is not successfully self-destroyed at this time, the characterization of the self-destruction is abnormal, the self-destruction is terminated, a self-destruction termination instruction is sent to the self-destruction circuit 3, and the self-destruction circuit 3 terminates the self-destruction of the self-destruction resistor 4.

In another possible implementation manner, the step of determining whether the timing duration of the timer reaches the preset self-destruction duration is executed after step Sa2, when the processor 1 sends the start command, the timer starts timing, and simultaneously determines whether the self-destruction of the self-destruction resistor 4 succeeds in real time, if the self-destruction does not succeed, whether the timing duration of the timer reaches the preset self-destruction duration is detected, and if the timing duration of the timer reaches the preset self-destruction duration, the self-destruction is characterized to be abnormal, and the self-destruction needs to be terminated.

In another possible implementation manner, the step of determining whether the timing duration of the timer reaches the preset self-destruction duration occurs simultaneously with the step Sa2, specifically, after the processor 1 sends the start command, it is determined whether the self-destruction resistor 4 is successfully self-destroyed every other preset duration, and it is determined whether the timing duration of the timer reaches the preset self-destruction duration, if the preset self-destruction duration is reached and the self-destruction resistor 4 is not successfully self-destroyed, it is indicated that the self-destruction is abnormal, the self-destruction needs to be terminated, and the processor 1 sends a self-destruction termination command to the self-destruction circuit 3 to control the self-destruction circuit 3 to terminate the self-destruction of the self-destruction resistor 4.

Further, when the self-destruction is not successful and the timing duration of the timer does not reach the preset self-destruction duration, it represents that the self-destruction resistor 4 may be in the normal self-destruction process at this time, and the self-destruction should be continued. For this purpose, after determining whether the self-destruction resistor 4 has succeeded in self-destruction, a step Sa4 (not shown in the figure) is further included:

and step Sa4, if the self-destruction is not successful and the timing duration of the timer does not reach the preset self-destruction duration, circularly executing to determine whether the self-destruction of the resistor is successful or not until a second preset condition is met. That is, if the self-destruction is not successful, the step Sa2 is executed in a loop until the second preset condition is met.

Wherein the second preset condition comprises any one of:

the self-destruction resistor 4 is successfully self-destroyed, and the timing duration of the timer does not reach the preset self-destruction duration;

the self-destruction resistor 4 is not self-destroyed successfully, and the timing duration of the timer reaches the preset self-destruction duration;

the self-destruction resistor 4 is successfully self-destroyed, and the timing duration of the timer reaches the preset self-destruction duration.

Specifically, if the self-destruction resistor 4 is not self-destroyed successfully and the timing duration of the timer does not reach the preset self-destruction duration, that is, the self-destruction resistor 4 is in the normal self-destruction process at this time, it is continuously determined whether the self-destruction of the resistor is successful or not, and it is determined whether the timing duration of the timer reaches the preset self-destruction duration or not.

When the self-destruction resistor 4 completes the self-destruction within the preset self-destruction duration, that is, the processor 1 detects that the self-destruction of the self-destruction resistor 4 is successful, the timing duration of the timer does not reach the preset self-destruction duration, or the self-destruction of the self-destruction resistor 4 is successful when the timing duration of the timer just reaches the preset self-destruction duration, the self-destruction resistor 4 is represented to be successfully self-destroyed, whether the self-destruction of the self-destruction resistor 4 is successful or not is not determined, the cycle is ended, and the processor 1 outputs an end command to the self-destruction circuit 3 and the timer, so that the self-destruction circuit 3 ends the self-destruction of the self-destruction resistor 4, and the timer ends the timing and resets.

When the self-destruction resistor 4 does not complete self-destruction within the preset self-destruction duration, that is, the processor 1 detects that the self-destruction resistor 4 is not successfully self-destroyed, and the timing duration of the timer reaches the preset self-destruction duration, which represents that the self-destruction of the self-destruction resistor 4 fails, the self-destruction of the self-destruction resistor 4 needs to be terminated at this moment, and the processor 1 outputs a self-destruction termination command to the self-destruction resistor 4 and the timer to terminate the cycle, so that the self-destruction circuit 3 terminates the self-destruction of the self-destruction resistor 4, and the timer terminates the timing and clears.

For example: the preset self-destruction duration is 5 seconds, when the timing duration of the timer is 1 second, the processor 1 does not receive the notification message, the self-destruction resistance 4 is represented to be not successfully self-destroyed at the moment, and the timing duration of the timer does not reach the preset self-destruction duration at the moment, so that whether the self-destruction is successful or not is continuously judged. If the timing duration of the timer is 3 seconds, the processor 1 receives the notification message, the self-destruction of the self-destruction resistor 4 is represented to be successful, the timing duration of the timer does not reach the preset self-destruction duration, the processor 1 outputs an end command, the timing duration of the timer is reset, and the self-destruction circuit 3 ends the self-destruction; if the notification message is not received when the timing duration of the timer is 3 seconds, continuously judging whether the self-destruction is successful, and then if the notification message is received when the timing duration of the timer is 5 seconds, representing that the self-destruction is successful, wherein within the preset self-destruction duration, the processor 1 finishes the circulation and outputs an end command to the self-destruction circuit 3 and the timer so as to enable the self-destruction circuit 3 to stop controlling the self-destruction of the self-destruction resistor 4 and simultaneously enable the timing duration of the timer to be reset; if the notification message is not received when the timing duration of the timer is 5 seconds, it is represented that the self-destruction resistor 4 is abnormal at this time, the self-destruction is not successful within the preset self-destruction duration, at this time, the self-destruction to the self-destruction resistor 4 is terminated, the cycle of determining whether the self-destruction of the self-destruction resistor 4 is successful is ended, and a self-destruction termination command is output to the self-destruction circuit 3 and the timer, so that the self-destruction circuit 3 terminates the self-destruction operation to the self-destruction resistor 4, and clears the timing of the timer to end the timing.

Further, after the self-destruction of the self-destruction resistor 4 is successful, it is necessary to verify whether the self-destruction resistor 4 is successfully self-destroyed, so as to further verify the self-destruction result of the self-destruction resistor 4, and therefore, in step Sa2, it is determined whether the self-destruction resistor 4 is successfully self-destroyed, and then step Sb1 (not shown), step Sb2 (not shown), and step Sb3 (not shown) may be further included, in which:

and step Sb1, if the self-destruction is successful, controlling the selector switch 2 to be switched to a first conduction state.

Specifically, in order to verify the self-destruction result of the self-destruction resistor 4, an external test tool needs to be used to verify the on-off state of the USB channel, and when the switch 2 is in the off state, the test results of testing the USB channel are all results representing the disconnection of the USB channel, but it cannot be determined whether the disconnection of the USB channel is the disconnection caused by the self-destruction of the self-destruction resistor 4 or the disconnection caused by the switch 2. Therefore, the switch 2 needs to be switched to the first conducting state before the start command is issued, and then the self-destruction result of the self-destruction resistor 4 needs to be verified. That is, the selector switch 2 is switched to the on state in which the processor 1 communicates with the self-destruction resistor 4. And then testing the on-off of the USB channel, wherein if the tested result represents that the USB channel is disconnected, the representation self-destruction resistor 4 is successfully self-destroyed at the moment, and if the tested result represents that the USB channel is connected, the representation self-destruction resistor 4 is not successfully self-destroyed.

And Sb2, obtaining a detection result sent by a preset test tool.

Wherein, the detection result is obtained by detecting the path between the exposed communication interface 5 and the processor 1 by a preset test tool.

Specifically, the preset test tool is a tool for detecting the on-off state of a USB channel, that is, a tool for detecting the on-off state of a channel between the exposed communication interface 5 and the processor 1, the exposed communication interface 5 of the electronic device includes a USB interface, when the USB channel is in an off state, the USB interface cannot perform data transmission, at this time, the preset test tool is used for detecting the on-off state of the USB channel of the electronic device by using D + and ground and the conduction condition between D-and ground to represent the on-off state of the USB channel, and D + and D-are two ends of the USB interface used for data transmission; if the USB channel is in a conducting state, the D + is conducted with the ground, the D-is also conducted with the ground, the output detection result represents that the channel is conducted, if the USB channel is in a disconnecting state, the D + is disconnected with the ground, the D-is also disconnected with the ground, and the output detection result represents that the channel is disconnected.

The device comprises a preset testing tool, a TYPE-C male interface, an TYPE-C female interface, a Bluetooth, WLAN or 5G and other wireless communication modes are utilized when the testing tool is preset to test whether a USB channel is disconnected or not, the processor 1 of the electronic device is wirelessly connected with the preset testing tool, the TYPE-C male interface of the preset testing tool is inserted into the TYPE-C female interface of the electronic device, whether the USB channel is connected or not starts to be detected, and a detection result is sent to the electronic device through the wireless communication mode so that the electronic device can obtain a detection result of the preset testing tool.

And step Sb3, if the detection result represents that the path is disconnected, feeding back the detection result to the server.

Specifically, if the detection result of the anti-verification by using the preset test tool also represents that the USB channel is disconnected, the characterization self-destruction resistor 4 has been successfully self-destroyed, and at this time, the detection result is fed back to the server, and the server can store the detection result.

The method for verifying the self-destruction success result of the self-destruction resistor 4 may further include: after the change-over switch 2 is switched to the first conduction state, the external equipment is manually connected with the exposed communication interface 5 of the electronic equipment, whether a prompt message of 'USB connected' is displayed in the electronic equipment is checked, if the prompt message is displayed, the self-destruction of the self-destruction resistor 4 is represented to be failed, and if the prompt message is not displayed, the self-destruction of the self-destruction resistor 4 is represented to be successful.

In order to further improve the security of the data inside the electronic device, referring to fig. 3, a dedicated module 7 is further disposed in the electronic device, and the dedicated module 7 is configured to perform specific processing on the data received from the processor 1, for example, the dedicated module 7 may be an encryption/decryption module configured to encrypt and transmit the data, or configured to perform decryption processing after receiving the encrypted data.

Referring to fig. 3, the switch 2 further includes a third connection port, and the third connection port is connected to the dedicated module 7; the special module 7 is configured to send data to the processor 1 for specific processing when the switch 2 is in the second on state, and transmit the data to the processor 1 after the specific processing, or the special module 7 may also directly transmit the data processed inside the special module 7 to the processor 1 when the switch 2 is in the second on state, where the second on state represents that the special module 7 and the processor 1 are in the on state.

Specifically, the change-over switch 2 is a three-port component, a single-pole double-throw switch may be adopted, a double-pole four-throw switch or other types of switches may also be adopted, and the single-pole double-throw switch is taken as an example for illustration, wherein the single-pole double-throw switch includes a fixed end and two movable ends, respectively being a movable end a and a movable end b, and the single-pole double-throw switch may enable the fixed end to be communicated with the movable end a, or enable the fixed end to be communicated with the movable end b, wherein the fixed end is connected to the processor 1, the movable end a is connected to the self-destruction resistor 4, the movable end b is connected to the dedicated module 7, and when the processor 1 detects that a first preset condition is met, the single-pole double-throw switch is controlled to be located at a position where the fixed end is disconnected from the movable end a, and the fixed end is communicated with the movable end b.

The change-over switch 2 is in the second conducting state, and the fixed end and the movable end b of the representation change-over switch 2 are conducted, that is, the representation processor 1 and the special module 7 are in a connected state, and the processor 1 and the self-destruction resistor 4 are in a disconnected state.

After the self-destruction resistor 4 completes self-destruction, the change-over switch 2 is switched to the second conduction state, data stored in the electronic equipment can be specifically processed by using the special module 7, external equipment is difficult to acquire the specifically processed data in the special module 7 through a USB channel corresponding to the exposed communication interface 5, and then the safety of the data is improved.

The above embodiment describes a flow and steps of the processor 1 controlling the self-destruction resistor 4 to perform self-destruction when detecting that a first preset condition is met, where the processor 1 detects that the first preset condition in the first preset condition is met, and includes: receiving a self-destruction instruction input by a user, wherein the self-destruction instruction is used for indicating self-destruction of the self-destruction resistor 4; or detecting that no data is written and/or read in the second preset time period; or, detecting that the time from the last self-destruction termination reaches a preset time interval.

The preset time interval is a preset criterion for the processor 1 to send a start command again to control the self-destruction of the self-destruction resistor 4, that is, the processor 1 starts timing from zero when the self-destruction is terminated last time, when the timing duration reaches the preset time interval, the processor 1 starts to control the self-destruction resistor 4 to self-destroy again, for example, the preset time interval is 5min, the self-destruction is terminated at the self-destruction resistor 4, the preset time interval is reached after 5min, and the processor 1 sends a start command to the self-destruction circuit 3 at this time, so that the self-destruction circuit 3 starts to control the self-destruction resistor 4 to self-destroy again.

In a possible implementation manner, after the electronic device completes all test works on the workstation, the processor 1 is no longer required to perform data interaction with external devices, and therefore the USB channel needs to be disconnected after all test works are completed, so that when it is detected that no data is written in and/or read from the electronic device within a second preset time period, it is characterized that data transmission is not performed for a long time, that is, it is characterized that all test works of the current electronic device have been completed, and at this time, the processor 1 automatically detects that a first preset condition is met, and starts to perform disconnection work of USB connection and disconnection.

In another possible implementation manner, when the user determines that the electronic device has completed self-destruction, the user may also input a self-destruction instruction into the electronic device through an operation device such as a keyboard and a mouse, and the processor 1 receives the self-destruction instruction, that is, when the processor 1 receives the self-destruction instruction, it is detected that the first preset condition is met.

In another possible implementation manner, when the processor 1 determines that the self-destruction resistor 4 is not successfully self-destructed and determines that the timing duration of the timer reaches the preset self-destruction duration, that is, when the self-destruction resistor 4 still does not complete self-destruction within the preset self-destruction duration, the processor 1 sends a self-destruction termination instruction to the self-destruction circuit 3, and the self-destruction circuit 3 controls the self-destruction resistor 4 to terminate self-destruction. After the processor 1 fails to self-destruct once, in order to automatically control the self-destruct resistor 4 to self-destruct again, the self-destruct can be restarted after the self-destruct fails, but if the processor is restarted immediately after the self-destruct fails, the probability of the self-destruct failure is higher, therefore, after the preset time interval, the processor 1 detects that the time from the last self-destruct termination reaches the preset time interval, namely waits for the preset time interval again, the processor 1 detects that the first preset condition is met again, at this moment, the state of the switch 2 is restarted to obtain, and then a starting command is sent to enable the self-destruct circuit 3 to start to control the self-destruct resistor 4 to self-destruct. For example: the time when the processor 1 sends the self-destruction termination command is 08.

Based on the foregoing embodiments, an example is provided in this application to describe a process of USB channel disconnection protection, referring to fig. 6, an electronic device is disposed in a workstation to perform various tests, a test result is uploaded to a server, a processor 1 of the electronic device detects that there is no data write-in and/or data read in a second preset time period after the various tests are completed, the processor 1 detects that a first preset condition is met, obtains a state of a switch 2 to determine whether the switch 2 is in a disconnected state, and starts a process of a self-destruction circuit 3 at this time (that is, the self-destruction circuit 3 controls a self-destruction resistor 4 to perform self-destruction) if the state of the switch 2 is in the disconnected state at this time; if the state of the switch 2 is not disconnected (i.e. the first on state), that is, the processor 1 and the exposed communication interface 5 are in the on state, the processor 1 controls the switch 2 to be switched to the off state, that is, the processor 1 and the exposed communication interface 5 are disconnected, and then the process of the self-destruction circuit 3 is started; then after starting the self-destruction circuit 3 for a period of time, judging whether the self-destruction of the self-destruction resistor 4 is successful, if the self-destruction of the self-destruction resistor 4 is successful, the processor 1 feeds back to the server to prompt that the self-destruction is completed; if the self-destruction is not successful, judging whether the self-destruction is overtime (namely judging whether the timing duration of the timer reaches the preset self-destruction duration or not), if the self-destruction is overtime, terminating the self-destruction process, and after the self-destruction is terminated, detecting that the duration after the self-destruction is terminated by the processor 1 reaches a preset time interval, and then restarting the self-destruction, namely restarting the self-destruction process after a period of waiting time after the self-destruction failure is terminated; if not, returning to the step of judging whether the self-destruction of the self-destruction resistor 4 is successful or not.

Further, in another example, referring to fig. 7, after the processor 1 detects that the first preset condition is met, the state of the switch 2 is obtained, if the state of the switch 2 does not belong to the off state between the self-destruction resistor 4 and the processor 1, but is the on state between the self-destruction resistor 4 and the processor 1, at this time, self-destruction is not performed any more, the self-destruction process is disabled, that is, no start command is sent to the self-destruction circuit 3, and the self-destruction circuit 3 does not perform any self-destruction operation in this state, which is beneficial to preventing the processor 1 from being interfered by an interference signal generated by the self-destruction resistor 4 when the self-destruction resistor 4 is self-destroyed, so that the processor 1 generates problems such as EOS, and the like, thereby improving the safety of the processor 1; if the state of the selector switch 2 belongs to the disconnection state between the self-destruction resistor 4 and the processor 1, starting the process of the self-destruction circuit 3, judging whether the self-destruction resistor 4 is successfully self-destroyed or not according to the above mode, and if so, feeding back to the server to prompt that self-destruction is completed; if not, judging whether the self-destruction is overtime or not, if so, terminating the self-destruction process and executing the waiting time; if not, the self-destruction circuit 3 process is continued to be returned.

An embodiment of the present application also introduces an electronic device from the perspective of a physical device, as shown in fig. 1, the electronic device including: the system comprises a processor 1, a self-destruction circuit 3, a self-destruction resistor 4 and an exposed communication interface 5; one end of the processor 1 is connected with one end of the self-destruction resistor 4; the other end of the self-destruction resistor 4 is connected with the exposed communication interface 5, the other end of the processor 1 is also connected with the self-destruction circuit 3, and the self-destruction circuit 3 is connected with the self-destruction resistor 4; the exposed communication interface 5 is used for information interaction with external equipment; the processor 1 is configured to execute the USB path disconnection protection method described above.

Specifically, in order to disconnect the USB channel between the exposed communication interface 5 and the processor 1, the self-destruction resistor 4 is arranged on the USB channel, and the processor 1 controls the self-destruction circuit 3 to further drive the self-destruction resistor 4 to perform self-destruction, so as to disconnect the USB channel, and further, external devices are difficult to steal data or introduce unsafe data through the USB channel, thereby improving the security of the electronic device.

Referring to fig. 3, a possible implementation manner of the embodiment of the present application, the electronic device further includes: the processor comprises a selector switch 2, wherein the selector switch 2 comprises a first connecting port and a second connecting port, one end of the processor 1 is connected with the first connecting port, and the second connecting port is connected with one end of a self-destruction resistor 4.

Specifically, when the self-destruction resistor 4 is self-destroyed, the path between the processor 1 and the self-destruction resistor 4 can be disconnected through the switch 2, so that the occurrence of the situation that an interference signal generated when the self-destruction resistor 4 is self-destroyed enters the processor 1 is effectively reduced, and the safety of the processor 1 can be further improved on the basis of improving the safety of the electronic device.

Referring to fig. 4, a self-destruction circuit 3 includes a voltage boosting unit 31 and a load switch 32; the boosting unit 31 comprises an input end, an output end and a reflux ground, wherein the input end is connected to the processor 1, and the processor 1 is used for controlling the boosting unit 31 to boost according to a preset rule; the load switch 32 includes a first port, a second port, a third port and a fourth port, wherein the first port is connected to the output end, the second port is connected to the backflow ground, the third port is connected to one end of the self-destruction resistor 4 connected to the switch 2, the fourth port is connected to the other end of the self-destruction resistor 4, and the load switch 32 is configured to apply the voltage boosted by the voltage boosting unit 31 to the self-destruction resistor 4.

Referring to fig. 4, the self-destruction circuit 3 further includes a protection unit 35, one end of the protection unit 35 is connected to the third port, the other end of the protection unit 35 is connected to one end of the self-destruction resistor 4 connected to the switch 2, and the protection unit 35 is configured to disconnect a path where the current flows when the current is higher than a preset current threshold.

Referring to fig. 4, a possible implementation manner of the embodiment of the present application, the self-destruction circuit 3 further includes: a current detection unit 33 and a detection resistor 34; one end of the detection resistor 34 is connected to the fourth port, and the other end is connected to one end of the self-destruction resistor 4 connected with the exposed communication interface 5; the current detection unit 33 includes a first input port connected to one end of the detection resistor 34, a second input port connected to the other end of the detection resistor 34, and an output port connected to the processor 1, and is configured to detect a current value of the detection resistor 34, determine whether the current value of the self-destruction resistor 4 in a first preset time period is abnormal, and send a notification message to the processor 1 when the abnormality occurs.

Referring to fig. 3, the electronic device further includes a special module 7, the switch 2 further includes a third connection port, and the third connection port is connected to the special module 7; the special module 7 is configured to perform information transmission with the processor 1 when the switch 2 is in a second on state, where the second on state represents that the special module 7 and the processor 1 are in an on state.

Among them, electronic devices include but are not limited to: mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like.

As shown in fig. 8, the self-destruction circuit 3 includes a voltage boosting unit 31, where the voltage boosting unit 31 includes an input end, an output end, and a backflow ground, where the input end is connected to the processor 1 and is used for boosting voltage according to a preset rule under the control of the processor 1; the output end of the voltage boosting unit 31 is connected to one end of the self-destruction resistor 4, and is connected to the other end of the self-destruction resistor 4 in a backflow manner, so that the boosted voltage acts on the self-destruction resistor 4 to cause the self-destruction resistor 4 to be self-destroyed, the self-destruction resistor 4 is used for disconnecting the connection between the processor 1 and the exposed communication interface 5 after being self-destroyed, and the exposed communication interface 5 is used for information interaction between the processor 1 and external equipment.

Specifically, when the self-destruction circuit 3 controls the self-destruction resistor 4 to perform self-destruction, the processor 1 controls the voltage boosting unit 31 to boost voltage according to a preset rule, then the boosted voltage acts on two ends of the self-destruction resistor 4, the self-destruction resistor 4 continuously accumulates heat under the action of the voltage until fusing, self-destruction is completed, the self-destruction resistor 4 is arranged between the processor 1 and the exposed communication interface 5, after self-destruction is completed, a USB channel between the processor 1 and the exposed communication interface 5 is disconnected, external equipment is difficult to realize information interaction with the processor 1 through the exposed communication interface 5, so that the safety of electronic equipment is improved, secondly, in the self-destruction process of the self-destruction resistor 4, the voltage boosting unit 31 is utilized to continuously boost voltage, the speed of heat accumulation of the self-destruction resistor 4 is facilitated to accelerate the self-destruction process of the self-destruction resistor 4.

Referring to fig. 4, the self-destruction circuit 3 further includes a current detection unit 33 and a detection resistor 34, one end of the detection resistor 34 is connected to the output end of the voltage boosting unit 31, and the other end is connected to one end of the self-destruction resistor 4;

the current detection unit 33 includes a first input port connected to one end of the detection resistor 34, a second input port connected to the other end of the detection resistor 34, and an output port, where the second input port is used to detect a current value of the detection resistor 34 to determine whether a current value of the self-destruction resistor 4 in a first preset time period is abnormal, and when the current value is abnormal, send a notification message, and the output port is connected to the processor 1 and is used to send the notification message to the processor 1.

Referring to fig. 4, the self-destruction circuit 3 further includes a load switch 32;

the load switch 32 includes a first port, a second port, a third port and a fourth port, the first port is connected to the output end of the voltage boosting unit 31, the second port is connected to the return ground, the third port is connected to one end of the self-destruction resistor 4, and the fourth port is connected to the other end of the self-destruction resistor 4;

referring to fig. 5, the load switch 32 further includes a fifth port, connected to the processor 1, for applying the boosted voltage of the voltage boosting unit 31 to the self-destruction resistor 4 after receiving the turn-on command sent by the processor 1.

Referring to fig. 4, in a possible implementation manner of the embodiment of the present application, the self-destruction circuit 3 further includes a protection unit 35;

one end of the protection unit 35 is connected to the output end of the voltage boosting unit 31, and the other end of the protection unit 35 is connected to one end of the self-destruction resistor 4, which is used for being connected to the output end of the voltage boosting unit 31, and is used for disconnecting the path where the self-destruction resistor is located when current higher than a preset current threshold flows.

The present application provides a computer-readable storage medium, on which a computer program is stored, which, when running on a computer, enables the computer to execute the corresponding content in the foregoing method embodiments. In this embodiment of the application, when the processor 1 detects that the first preset condition is met, and when the processor 1 and the self-destruction resistor 4 are in a disconnected state, a turn-on command is sent to the self-destruction circuit 3, so that the self-destruction circuit 3 controls the self-destruction resistor 4 to perform self-destruction, the self-destruction resistor 4 is disposed between the exposed communication interface 5 of the electronic device for performing information interaction with the external device and the processor 1, and after the self-destruction resistor 4 is self-destroyed, an information interaction path between the external device and the processor 1 is completely disconnected, so that the external device is difficult to introduce unsafe information into the electronic device and to derive information from the electronic device, and thus the security of the electronic device is improved.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A USB path disconnection protection method, performed by an electronic device, the electronic device comprising: the self-destruction circuit comprises a processor, a self-destruction circuit, a self-destruction resistor and a bare communication interface, wherein one end of the processor is connected to one end of the self-destruction resistor, the other end of the self-destruction resistor is connected to the bare communication interface, the other end of the processor is also connected to the self-destruction circuit, and the self-destruction circuit is connected with the self-destruction resistor; the exposed communication interface is used for information interaction with external equipment;

wherein the method comprises the following steps:

when the processor detects that a first preset condition is met, the processor sends a starting command to the self-destruction circuit, so that the self-destruction circuit controls the self-destruction of the self-destruction resistor;

the electronic device further includes: the change-over switch comprises a first connecting port and a second connecting port, one end of the processor is connected to the first connecting port, and the second connecting port is connected to one end of the self-destruction resistor; wherein the content of the first and second substances,

acquiring the state of the selector switch;

wherein the processor sends a turn-on command to the self-destruction circuit, comprising:

2. The method of claim 1, wherein obtaining the state of the switch further comprises:

3. The method of claim 1 or 2, wherein the self-destruction circuit comprises a boost unit and a load switch;

the boosting unit comprises an input end, an output end and a reflux ground, wherein the input end is connected to the processor, and the processor is used for controlling the boosting unit to boost according to a preset rule;

4. The method according to claim 3, wherein the step-up unit is controlled to step up according to a preset rule, and the method comprises any one of the following steps:

5. The method of claim 4, further comprising:

if the self-destruction is not successful and the timing duration of the timer does not reach the preset self-destruction duration, circularly executing to determine whether the self-destruction of the self-destruction resistor is successful or not until a second preset condition is met;

the second preset condition includes any one of:

the self-destruction resistor is not self-destroyed successfully, and the timing duration of the timer reaches the preset self-destruction duration;

the self-destruction resistor is successfully self-destroyed, and the timing duration of the timer reaches the preset self-destruction duration.

6. The method of claim 5, wherein the determining whether the self-destruction resistance is successful comprises:

7. The method of claim 1, wherein the electronic device further comprises a dedicated module, and wherein the switch further comprises a third connection port connected to the dedicated module;

8. An electronic device, comprising: the system comprises a processor, a self-destruction circuit, a self-destruction resistor and a bare communication interface;

the exposed communication interface is used for information interaction with external equipment;

the processor is used for executing the USB channel disconnection protection method of any one of claims 1 to 7.

9. A self-destruction circuit is characterized by comprising a boosting unit, wherein the boosting unit comprises an input end, an output end and a backflow ground, the input end is connected to a processor and boosts voltage according to a preset rule under the control of the processor;

the output end is connected with one end of a self-destruction resistor, the output end is connected with the other end of the self-destruction resistor in a backflow mode, the boosted voltage is used for acting on the self-destruction resistor so as to enable the self-destruction resistor to be self-destroyed, the self-destruction resistor is used for disconnecting the connection between the processor and the exposed communication interface after being self-destroyed, and the exposed communication interface is used for information interaction between the processor and external equipment;

the processor is further connected with a change-over switch, the change-over switch comprises a first connection port and a second connection port, one end of the processor is connected to the first connection port, the second connection port is connected to one end of the self-destruction resistor, the processor is further used for obtaining the state of the change-over switch, and the processor is further used for sending a starting command to the self-destruction circuit when sending the starting command to the self-destruction circuit and specifically used for sending the starting command to the self-destruction circuit when the state of the change-over switch is a disconnection state, and the disconnection state represents that the processor is in a disconnection state with the self-destruction resistor.

10. The self-destruction circuit of claim 9, further comprising a current detection unit and a detection resistor, wherein one end of the detection resistor is connected to the output terminal, and the other end of the detection resistor is connected to one end of the self-destruction resistor;

11. The self-destruct circuit of claim 9, further comprising a load switch;

12. A computer-readable storage medium having stored thereon a computer program, which, when executed in a computer, causes the computer to execute the USB path disconnection protection method of any one of claims 1 to 7.