CN115494908B - Temperature-tracking current source mismatch foreground calibration circuit and method - Google Patents

Temperature-tracking current source mismatch foreground calibration circuit and method Download PDF

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Publication number
CN115494908B
CN115494908B CN202211268826.7A CN202211268826A CN115494908B CN 115494908 B CN115494908 B CN 115494908B CN 202211268826 A CN202211268826 A CN 202211268826A CN 115494908 B CN115494908 B CN 115494908B
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current
calibration
drain
pmos transistor
transistor
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CN115494908A (en
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杨卫东
刘军
马世碧
温显超
朱璨
藏剑栋
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Chongqing Jixin Technology Co ltd
CETC 24 Research Institute
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Chongqing Jixin Technology Co ltd
CETC 24 Research Institute
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Abstract

The invention provides a current source mismatch foreground calibration circuit and a method for tracking temperature, wherein the circuit comprises the following components: a current source to be calibrated; a reference current source; the current generating module containing temperature information generates working current containing temperature information; tracking the temperature calibration module. In the invention, working current containing temperature information is generated firstly, and then calibration compensation is carried out on the mismatch between the current source to be calibrated and the reference current source according to the working current, so that target calibration current is provided for the current source to be calibrated, and the obtained target calibration current automatically tracks temperature change. During calibration compensation, a universal stable target calibration current can be found out through repeated iterative adjustment, and the accuracy of foreground calibration is improved.

Description

Temperature-tracking current source mismatch foreground calibration circuit and method
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a current source mismatch foreground calibration circuit and a current source mismatch foreground calibration method for tracking temperature.
Background
The matching of devices is one of the most critical characteristics of analog integrated circuits, and advanced manufacturing process technology brings about the reduction of the feature size of transistors, the reduction of parasitic parameters of transistors and the improvement of the operating speed of devices. Meanwhile, the problem of transistor current source array mismatch caused by transistor size reduction is also brought, and in many analog or mixed signal integrated circuits, a large-scale current source array needs to be designed in a circuit architecture, for example, a high-speed high-precision current rudder D/A converter, and the static linearity error of the circuit and the spurious emission of an output frequency spectrum of the circuit are seriously dependent on the matching performance of the transistor current source array. Therefore, due to the continuous improvement of the conversion rate of the D/a converter, an advanced nanoscale process with smaller feature size must be adopted, and the mismatch problem of the transistor current source array caused by the advanced nanoscale process is more remarkable, so that in order to ensure the performance index of the high-speed D/a converter, the current source array of the high-speed current rudder D/a converter must be calibrated.
The calibration method of the D/A converter current source array is divided into a foreground calibration mode and a background calibration mode. Background calibration is performed when the D/A converter works normally, and changes of working temperature can be tracked timely. However, background calibration circuits such as sensing and control circuits consume additional power, resulting in degradation of the performance of the D/a converter due to noise and glitches introduced into the calibration behavior. Therefore, the calibration method of the high-performance high-speed high-precision current rudder D/a converter is generally focused on the foreground calibration method. The front stage calibration is to complete the calibration before the current rudder D/A converter normally works, and is suitable for the D/A converter to be in a non-working state, for example, the D/A converter is in a power-on, standby or test stage, so that the defects caused by the back stage calibration can be avoided. However, since the foreground calibration is performed before the D/a converter normally operates, there is mainly a change in the state at the time of calibration (for example, the ambient temperature, etc.) and the state at the time of operation. These changes can result in a calibrated and compensated current source array mismatch current that varies with temperature, thereby affecting calibration accuracy.
Therefore, a current source mismatch foreground calibration scheme capable of eliminating the influence of temperature variation on calibration accuracy is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a current source mismatch foreground calibration method capable of automatically tracking temperature, generating a calibration current by a working current containing temperature information, and performing calibration compensation on mismatch between a current source to be calibrated and a reference current source based on the calibration current, wherein the calibration current can automatically track temperature variation of the current source mismatch without performing calibration again after additionally changing ambient temperature, and thus, the temperature stability of foreground calibration of a transistor current source array is improved under the condition of reducing calibration time and cost.
In order to achieve the above object and other related objects, the present invention provides the following technical solutions.
A temperature tracking current source mismatch foreground calibration circuit comprising:
a current source to be calibrated;
a reference current source;
the current generating module containing temperature information generates working current containing temperature information;
and the tracking temperature calibration module is connected with the current source to be calibrated, the reference current source and the temperature information-containing current generation module, and is used for calibrating and compensating the mismatch between the current source to be calibrated and the reference current source according to the working current, so as to provide a target calibration current for the current source to be calibrated, and the target calibration current automatically tracks the temperature change.
Optionally, the temperature information-containing current generating module includes a first bias current generating unit, a second bias current generating unit, a first bias voltage generating unit, a second bias voltage generating unit, a third bias voltage generating unit, a first current mirror, and a second current mirror, where an input end of the first bias current generating unit is connected to a first bias voltage, a first output end of the first bias current generating unit is connected to a first input end of the first bias voltage generating unit, a second output end of the first bias current generating unit is connected to a second input end of the first bias voltage generating unit, a first output end of the first bias voltage generating unit is connected to a first input end of the first current mirror, a second output end of the first bias voltage generating unit is connected to a second input end of the first current mirror, a second output end of the first bias voltage generating unit is connected to a third input end of the first current mirror, a first output end of the first bias current mirror is connected to a second output end of the second bias voltage generating unit, a second output end of the first bias voltage generating unit is connected to a second output end of the second current mirror, and a second output end of the first bias voltage generating unit is connected to a third input end of the first current mirror, the voltage input end of the third bias voltage generating unit is connected with a second bias voltage, the first voltage output end of the third bias voltage generating unit is connected with the first input end of the second bias current generating unit, the second voltage output end of the third bias voltage generating unit is connected with the second input end of the second bias current generating unit, the third input end of the second bias current generating unit is connected with the third bias voltage, and the output end of the second bias current generating unit outputs the working current.
Optionally, the first bias current generating unit includes an amplifier, a first NMOS tube, a second NMOS tube, a first resistor and a second resistor, where the non-inverting input end of the amplifier is connected to the first bias voltage, the inverting input end of the amplifier is connected to the source of the second NMOS tube, the source of the first NMOS tube is grounded after being connected in series to the first resistor, the source of the second NMOS tube is grounded after being connected in series to the second resistor, and the output end of the amplifier is connected to the gate of the first NMOS tube and the gate of the second NMOS tube respectively, where the non-inverting input end of the amplifier is the input end of the first bias current generating unit, the drain of the first NMOS tube is the first output end of the first bias current generating unit, and the drain of the second NMOS tube is the second output end of the first bias current generating unit.
Optionally, the first bias voltage generating unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, where a source of the first PMOS tube is connected to a working voltage, a drain of the first PMOS tube is connected to a source of the second PMOS tube, a drain of the second PMOS tube is connected to a gate of the second PMOS tube, a source of the third PMOS tube is connected to the working voltage, a drain of the third PMOS tube is connected to a source of the fourth PMOS tube, a drain of the fourth PMOS tube is connected to a gate of the third PMOS tube, a gate of the first PMOS tube, a gate of the second PMOS tube and a gate of the fourth PMOS tube are shorted, a drain of the second PMOS tube is a first input end of the first bias voltage generating unit, a drain of the fourth PMOS tube is a second input end of the first bias voltage generating unit, a gate of the first PMOS tube is a first output end of the first bias voltage generating unit, and a drain of the fourth PMOS tube is a second output end of the first bias voltage generating unit.
Optionally, the second bias voltage generating unit includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube, where a drain of the third NMOS tube is connected to a gate of the third NMOS tube, a source of the third NMOS tube is connected to a drain of the fourth NMOS tube, a gate of the fourth NMOS tube is connected to a gate of the third NMOS tube, a source of the fourth NMOS tube is grounded, a drain of the fifth NMOS tube is connected to a gate of the sixth NMOS tube, a gate of the fifth NMOS tube is connected to a gate of the fourth NMOS tube, a source of the fifth NMOS tube is connected to a drain of the sixth NMOS tube, and a source of the sixth NMOS tube is grounded, where a drain of the third NMOS tube is a first input terminal of the second bias voltage generating unit, a drain of the fifth NMOS tube is a second input terminal of the second bias voltage generating unit, a gate of the fourth NMOS tube is a second output terminal of the second bias voltage generating unit, and a drain of the fourth NMOS tube is a second bias voltage generating unit.
Optionally, the first current mirror includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor, where a source of the fifth PMOS transistor is connected to the operating voltage, a gate of the fifth PMOS transistor is connected to a gate of the third PMOS transistor, a gate drain of the fifth PMOS transistor is connected to a source of the sixth PMOS transistor, a gate of the sixth PMOS transistor is connected to a gate of the fourth PMOS transistor, a source of the seventh PMOS transistor is connected to the operating voltage, a gate of the seventh PMOS transistor is connected to a gate of the third PMOS transistor, a drain of the seventh PMOS transistor is connected to a source of the eighth PMOS transistor, a gate of the eighth PMOS transistor is connected to a gate of the fourth PMOS transistor, a source of the ninth PMOS transistor is connected to the operating voltage, a gate of the fifth PMOS transistor is connected to a gate of the third PMOS transistor, a gate of the ninth PMOS transistor is connected to a drain of the PMOS transistor, a drain of the fourth PMOS transistor is connected to a drain of the fourth PMOS transistor, a current of the fourth PMOS transistor is output to a fourth PMOS transistor, and a drain of the fourth PMOS transistor is connected to a drain of the fourth PMOS transistor.
Optionally, the third bias voltage generating unit includes a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third resistor and a fourth resistor, where a drain of the tenth PMOS transistor is connected to a drain of the seventh NMOS transistor after passing through the third resistor and the fourth resistor that are sequentially connected in series, a gate of the seventh NMOS transistor is connected to a gate of the fifth NMOS transistor, a source of the seventh NMOS transistor is connected to a drain of the eighth NMOS transistor, a gate of the eighth NMOS transistor is connected to a gate of the sixth NMOS transistor, and a source of the eighth NMOS transistor is grounded, a drain of the tenth PMOS transistor is a first current input terminal of the third bias voltage generating unit, a drain of the seventh NMOS transistor is a second current input terminal of the third bias voltage generating unit, a common terminal of the third resistor and the fourth resistor is a voltage input terminal of the third bias voltage generating unit, a drain of the tenth PMOS transistor is a third bias voltage generating unit, and a drain of the seventh NMOS transistor is a third bias voltage generating unit.
Optionally, the second current mirror includes the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor, where a gate of the fifth NMOS transistor is the first input end of the second current mirror, a gate of the sixth NMOS transistor is the second input end of the second current mirror, a drain of the fifth NMOS transistor is the third input end of the second current mirror, and a drain of the seventh NMOS transistor is the output end of the second current mirror.
Optionally, the second bias current generating unit includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor, where a source of the ninth NMOS transistor is grounded, a gate of the ninth NMOS transistor is connected to a drain of the tenth PMOS transistor, a drain of the ninth NMOS transistor is connected to a source of the eleventh NMOS transistor, a gate of the eleventh NMOS transistor is connected to the third bias voltage, a drain of the eleventh NMOS transistor is connected to a drain of the twelfth PMOS transistor, a gate of the twelfth PMOS transistor is connected to a drain of the twelfth PMOS transistor, a source of the twelfth PMOS transistor is connected to a drain of the eleventh PMOS transistor, a gate of the eleventh PMOS transistor is connected to a drain of the eleventh PMOS transistor, a source of the eleventh PMOS transistor is connected to the operating voltage, a source of the tenth NMOS transistor is grounded, the grid electrode of the tenth NMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the tenth NMOS tube is connected with the source electrode of the twelfth NMOS tube, the grid electrode of the twelfth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube, the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the twelfth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with the drain electrode of the thirteenth PMOS tube, the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the eleventh PMOS tube, the source electrode of the thirteenth PMOS tube is connected with the working voltage, wherein the grid electrode of the ninth NMOS tube is the first input end of the second bias current generating unit, the grid electrode of the tenth NMOS tube is the second input end of the second bias current generating unit, the grid electrode of the eleventh NMOS tube is the third input end of the second bias current generating unit, the drain electrode of the fourteenth PMOS tube is the output end of the second bias current generating unit.
Optionally, the tracking temperature calibration module includes a single-pole double-throw switch, a comparator, a tracking temperature calibration unit, a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, and a fourth digital-to-analog converter, where one of the double-throw ends of the single-pole double-throw switch is connected to a control end of an operating branch of the current source to be calibrated, the other of the double-throw ends of the single-pole double-throw switch is connected to a control end of the calibration branch of the current source to be calibrated, a single-pole of the single-pole double-throw switch is connected to the third bias voltage, an in-phase input of the comparator is connected to the reference current source, an inverting input of the comparator is connected to an output end of the calibration branch of the current source to be calibrated, an output of the comparator is connected to an input end of the tracking temperature calibration unit, an address output of the tracking temperature calibration unit is connected to a single-pole end of the single-pole double-throw switch, a first data output of the tracking temperature calibration unit is connected to an input end of the first digital-to-analog converter, a second data output of the tracking temperature calibration unit is connected to an input of the second digital-to-analog converter, a second data output of the tracking temperature calibration unit is connected to the fourth digital-to the output of the bias current calibration unit, a third output of the tracking temperature calibration unit is connected to the fourth digital-to the output of the digital-analog converter, a fourth output of the calibration unit is connected to the output of the calibration current, the output end of the first digital-to-analog converter outputs a first calibration current, the first calibration current and the second calibration current are overlapped to form the target calibration current, and the target calibration current is fed back to the current source to be calibrated.
A method of calibrating a current source mismatch foreground that tracks temperature, comprising:
providing a calibration bias current and an operating current containing temperature information;
generating a first calibration current by the calibration bias current and a second calibration current by the operating current;
carrying out superposition summation on the first calibration current and the second calibration current to obtain a target calibration current capable of automatically tracking temperature change;
and feeding the target calibration current back to a current source to be calibrated, and performing calibration compensation for automatically tracking temperature change on mismatch between the current source to be calibrated and a reference current source.
Optionally, before feeding back the target calibration current to the current source to be calibrated, iteratively adjusting the magnitude of the first calibration current and the magnitude of the second calibration current, so that the target calibration current obtained by each adjustment is equal to a mismatch value between the current source to be calibrated and the reference current source, and adopting a successive comparison algorithm when each adjustment.
Optionally, the number of iterations of the iterative adjustment is related to calibration compensation accuracy.
As described above, the current source mismatch foreground calibration circuit and method for tracking temperature provided by the invention have at least the following beneficial effects:
Based on the structural design of a temperature information-containing current generation module and a tracking temperature calibration module, working current containing temperature information is generated through the temperature information-containing current generation module, calibration compensation is carried out on mismatch between a current source to be calibrated and a reference current source according to the working current through the tracking temperature calibration module, target calibration current is provided for the current source to be calibrated, and the obtained target calibration current automatically tracks temperature change.
Drawings
Fig. 1 shows a schematic block diagram of a conventional current source array mismatch front calibration.
Fig. 2 shows a circuit diagram of a current source mismatch front calibration circuit for tracking temperature in the present invention.
Fig. 3 is a circuit diagram of the current generating module with temperature information in fig. 2.
Fig. 4 shows a flow chart of iterative adjustment of the tracking temperature calibration unit of fig. 2.
Fig. 5 is a schematic diagram showing steps of a current source mismatch foreground calibration method for tracking temperature in the present invention.
Description of the embodiments
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the claims, but rather by the claims.
As described in the foregoing background, the inventors have studied to find: for the traditional current source array mismatch foreground calibration technology as shown in fig. 1, under the action of a comparator A, the bias current I is calibrated according to bias Generating a calibration current I_cal for compensation, and treating the calibration current source I and the reference current source I according to the working current ref The mismatch between the two current sources is calibrated and compensated to obtain the current source I_cal+I after calibration, but the calibration is only suitable for the non-working state of the D/A converter, such as the power-on, standby or test stage of the D/A converter, and the front calibration is completed before the D/A converter normally works, so that the state of the front calibration and the state of the front calibration are changed, and the change (especially the change of the temperature) can cause the mismatch current I_cal+I of the current source array after calibration and compensation to change along with the different temperatures, thereby influencing the calibration precision.
Wherein, the resistor R and the NMOS transistors N100, N101, N102, N103, N104, N105 and N106 are partial structures of the current steering D/A converter, the NMOS transistors N100, N101 and N102 are current source array transistors, the sources of the NMOS transistors N100, N101 and N102 are all grounded, and the gates of the NMOS transistors N100, N101 and N102 are all connected with the bias voltage V bias0 The NMOS transistor N100 is a current source transistor to be calibrated, the corresponding drain current is a current source I to be calibrated, the NMOS transistor N101 is a reference current source transistor, and a reference current I is provided ref NMOS transistor N103 is a complementary current source transistor providing a calibration bias current I for calibration bias The NMOS tubes N103 and N104 are Casode level bias tubes, the grids of the NMOS tubes N103 and N104 are respectively connected with two ends of the double-throw end of the single-pole double-throw switch S, and the single-pole end of the single-pole double-throw switch S is connected with a bias voltage V bias1 The NMOS transistors N105 and N106 are current steering switching transistors, the grid electrode of the NMOS transistor N105 is connected with a control signal D, the drain electrode of the NMOS transistor N105 is connected with a working voltage VCC through a serially connected resistor R, and the grid electrode of the NMOS transistor N106 is connected with a control signal DB; the logic module of the comparator A, SAR and the analog-to-digital converter DAC form a calibration circuit, and the detailed structure is shown in fig. 1, which is not repeated here.
Therefore, the invention provides a current source mismatch foreground calibration technical scheme for tracking temperature: the working current containing temperature information is generated firstly, then target calibration current which automatically changes along with temperature is generated according to the working current, and finally calibration compensation is carried out on mismatch between a current source to be calibrated and a reference current source through the target calibration current, so that the calibration compensation automatically tracks temperature change, and calibration is carried out again after the environment temperature is not required to be additionally changed, thereby reducing the calibration time and the calibration cost, and improving the temperature stability of foreground calibration.
First, as shown in fig. 2, the present invention provides a current source mismatch foreground calibration circuit for tracking temperature, which includes:
a current source I to be calibrated;
a reference current source Iref;
the current generation module containing temperature information generates working current Ibias_4 containing temperature information;
the tracking temperature calibration module receives the calibration current source I, the reference current source Iref and the current generation module containing temperature information, performs calibration compensation on mismatch between the calibration current source I and the reference current source Iref according to the working current Ibias_4, provides a target calibration current Ical_3 for a current source I to be calibrated, and automatically tracks temperature change by the target calibration current Ical_3.
In detail, in an alternative embodiment of the present invention, as shown in fig. 3, the temperature information-containing current generating module includes a first bias current generating unit, a second bias current generating unit, a first bias voltage generating unit, a second bias voltage generating unit, a third bias voltage generating unit, a first current mirror, and a second current mirror, wherein an input end of the first bias current generating unit is connected to a first bias voltage V 1 The first output end of the first bias current generating unit is connected with the first input end of the first bias voltage generating unit, the second output end of the first bias current generating unit is connected with the second input end of the first bias voltage generating unit, the first output end of the first bias voltage generating unit is connected with the first input end of the first current mirror, and the second output end of the first bias voltage generating unit is connected with the first The second output end of the first bias current generating unit is connected with the third input end of the first current mirror, the first output end of the first current mirror is connected with the first input end of the second bias voltage generating unit, the second output end of the first current mirror is connected with the second input end of the second bias voltage generating unit, the third output end of the first current mirror is connected with the first current input end of the third bias voltage generating unit, the first output end of the second bias voltage generating unit is connected with the first input end of the second current mirror, the second output end of the second bias voltage generating unit is connected with the second input end of the second current mirror, the third input end of the second current mirror is connected with the second output end of the first current mirror, the output end of the second current mirror is connected with the second current input end of the third bias voltage generating unit, the voltage input end of the third bias voltage generating unit is connected with the second bias voltage Vbs 0, the first voltage output end of the third bias voltage generating unit is connected with the first input end of the second bias voltage generating unit, and the second bias voltage generating unit is connected with the second current output end of the second bias unit is connected with the second bias voltage generating unit, and the second current is connected with the second input end of the second bias unit is connected with the second voltage generating unit.
In more detail, as shown in fig. 3, the first bias current generating unit includes an amplifier A1, a first NMOS transistor N 1 Second NMOS tube N 2 A first resistor R 1 A second resistor R 2 The non-inverting input end of the amplifier A1 is connected with the first bias voltage V 1 The inverting input end of the amplifier A1 is connected with the second NMOS tube N 2 Source electrode of the first NMOS transistor N 1 A first resistor R connected in series with the source electrode of (C) 1 Rear grounded, second NMOS tube N 2 A second resistor R connected in series with the source electrode of the transistor 2 The output end of the amplifier A1 is respectively connected with the first NMOS tube N 1 Gate of (2) and second NMOS transistor N 2 Wherein the non-inverting input terminal of the amplifier A1 is the input terminal of the first bias current generating unit, the first NMOS transistor N 1 The drain electrode of the first bias current generating unit is a first output end for outputting a current I 1 Second NMOS tubeN 2 The drain electrode of the first bias current generating unit is a second output end of the first bias current generating unit, and outputs a current I 2 。
In more detail, as shown in FIG. 3, the first bias voltage generating unit includes a first PMOS tube P 1 A second PMOS tube P 2 Third PMOS tube P 3 Fourth PMOS tube P 4 First PMOS tube P 1 The source electrode of the first PMOS tube P is connected with the working voltage VCC 1 The drain electrode of the transistor is connected with the second PMOS tube P 2 Source electrode of the second PMOS tube P 2 The drain electrode of the transistor is connected with the second PMOS tube P 2 Gate electrode of the third PMOS tube P 3 The source electrode of the third PMOS tube P is connected with the working voltage VCC 3 The drain electrode of the transistor is connected with a fourth PMOS tube P 4 Source electrode of the fourth PMOS tube P 4 The drain electrode of the transistor is connected with a third PMOS tube P 3 A grid electrode of the first PMOS tube P 1 Gate electrode of (C), second PMOS tube P 2 Gate of (d) and fourth PMOS transistor P 4 Wherein the second PMOS tube P 2 The drain electrode of the first PMOS tube is a first input end of the first bias voltage generating unit 4 The drain electrode of the first PMOS tube P is a second input end of the first bias voltage generating unit 1 The grid electrode of the first bias voltage generating unit is a first output end for outputting bias voltage V P1 Third PMOS tube P 3 The grid electrode of the first bias voltage generating unit is a second output end of the first bias voltage generating unit and outputs bias voltage V P2 。
In more detail, as shown in FIG. 3, the second bias voltage generating unit includes a third NMOS transistor N 3 Fourth NMOS tube N 4 Fifth NMOS tube N 5 Sixth NMOS transistor N 6 Third NMOS tube N 3 The drain electrode of (C) is connected with a third NMOS tube N 3 Gate of the third NMOS transistor N 3 The source electrode of (C) is connected with the fourth NMOS tube N 4 Drain electrode of the fourth NMOS transistor N 4 The grid electrode of (C) is connected with a third NMOS tube N 3 Gate of the fourth NMOS transistor N 4 The source electrode of the fifth NMOS tube N is grounded 5 The drain electrode of (C) is connected with a sixth NMOS tube N 6 Gate of the fifth NMOS transistor N 5 The grid electrode of (C) is connected with a fourth NMOS tube N 4 Gate of the fifth NMOS transistor N 5 The source electrode of (C) is connected with a sixth NMOS tube N 6 Drain electrode of the sixth NMOS transistor N 6 The source electrode of the third NMOS transistor N is grounded 3 The drain electrode of the fifth NMOS transistor N is used as the first input end of the second bias voltage generating unit 5 The drain electrode of the second bias voltage generating unit is the second input end of the fourth NMOS transistor N 4 The gate of (2) is the first output end of the second bias voltage generating unit and outputs the bias voltage V N1 Sixth NMOS tube N 6 The gate of (2) is a second output end of the second bias voltage generating unit and outputs a bias voltage V N2 。
In more detail, as shown in FIG. 3, the first current mirror includes a third PMOS tube P 3 Fourth PMOS tube P 4 Fifth PMOS tube P 5 Sixth PMOS tube P 6 Seventh PMOS tube P 7 Eighth PMOS tube P 8 Ninth PMOS tube P 9 Tenth PMOS tube P 10 Fifth PMOS tube P 5 The source electrode of the fifth PMOS tube P is connected with the working voltage VCC 5 The grid electrode of the transistor is connected with a third PMOS tube P 3 Gate of (v), fifth PMOS tube P 5 The grid drain electrode of the transistor is connected with a sixth PMOS tube P 6 Source electrode of the sixth PMOS tube P 6 The grid electrode of the transistor is connected with a fourth PMOS tube P 4 Gate of (d), seventh PMOS tube P 7 The source electrode of the (V) is connected with the working voltage VCC, the seventh PMOS tube P 7 The grid electrode of the transistor is connected with a third PMOS tube P 3 Gate of (d), seventh PMOS tube P 7 The drain electrode of the transistor is connected with an eighth PMOS tube P 8 Source electrode of the eighth PMOS tube P 8 The grid electrode of the transistor is connected with a fourth PMOS tube P 4 Gate electrode of the ninth PMOS tube P 9 The source electrode of the P-channel metal oxide semiconductor (PMOS) tube is connected with the working voltage VCC, the P-channel metal oxide semiconductor (PMOS) tube P 9 The grid electrode of the transistor is connected with a third PMOS tube P 3 Gate electrode of the ninth PMOS tube P 9 The drain electrode of the transistor is connected with a tenth PMOS tube P 10 Source electrode of the tenth PMOS tube P 10 The grid electrode of the transistor is connected with a fourth PMOS tube P 4 Wherein, the fourth PMOS tube P 4 The grid electrode of the third PMOS tube P is the first input end of the first current mirror 3 The grid electrode of the transistor is the second input end of the first current mirror, and the fourth PMOS transistor P 4 The drain electrode of the transistor is the third input end of the first current mirror, and the sixth PMOS transistor P 6 The drain electrode of (a) is the first output end of the first current mirror and mirrors the output current I 3 Eighth PMOS tube P 8 The drain electrode of (a) is the second output end of the first current mirror and is mirroredOutput current I 4 Tenth PMOS tube P 10 The drain electrode of the first current mirror is a third output end of the first current mirror, and the output current I is mirrored 5 。
In more detail, as shown in FIG. 3, the third bias voltage generating unit includes a ninth PMOS tube P 9 Tenth PMOS tube P 10 Seventh NMOS tube N 7 Eighth NMOS tube N 8 Third resistor R 3 Fourth resistor R 4 Tenth PMOS tube P 10 The drain electrode of the capacitor is sequentially connected in series with a third resistor R 3 Fourth resistor R 4 The rear is connected with a seventh NMOS tube N 7 Drain electrode of the seventh NMOS transistor N 7 The grid electrode of (C) is connected with a fifth NMOS tube N 5 Gate of (d), seventh NMOS transistor N 7 The source electrode of (a) is connected with the eighth NMOS tube N 8 Drain electrode of eighth NMOS transistor N 8 The grid electrode of (C) is connected with a sixth NMOS tube N 6 Gate electrode of the eighth NMOS transistor N 8 The source electrode of the tenth PMOS tube P is grounded 10 The drain electrode of the third bias voltage generating unit is the first current input end of the seventh NMOS transistor N 7 The drain electrode of the third bias voltage generating unit is a second current input end for inputting current I 6 Third resistor R 3 And a fourth resistor R 4 The common end of the third PMOS transistor P is the voltage input end of the third bias voltage generating unit 10 The drain electrode of the third bias voltage generating unit is a first voltage output end for outputting a voltage V 2 Seventh NMOS tube N 7 The drain electrode of the third bias voltage generating unit is a second voltage output end for outputting a voltage V 3 。
In more detail, as shown in FIG. 3, the second current mirror includes a fifth NMOS transistor N 5 Sixth NMOS transistor N 6 Seventh NMOS tube N 7 Eighth NMOS tube N 8 Wherein, the fifth NMOS tube N 5 The grid electrode of the second current mirror is the first input end of the sixth NMOS transistor N 6 The grid electrode of the fifth NMOS transistor N is the second input end of the second current mirror 5 The drain electrode of the second transistor is the third input end of the second current mirror, and the seventh NMOS transistor N 7 The drain electrode of the (a) is the output end of the second current mirror, and outputs current I 6 。
In more detail, as shown in FIG. 3, the second bias current flows The raw unit comprises a ninth NMOS tube N 9 Tenth NMOS tube N 10 Eleventh NMOS tube N 11 Twelfth NMOS transistor N 12 Eleventh PMOS tube P 11 Twelfth PMOS tube P 12 Thirteenth PMOS tube P 13 Fourteenth PMOS tube P 14 Ninth NMOS tube N 9 The source electrode of the ninth NMOS tube N is grounded 9 The grid electrode of the transistor is connected with a tenth PMOS tube P 10 Drain electrode of the ninth NMOS transistor N 9 The drain electrode of (a) is connected with an eleventh NMOS tube N 11 Source electrode of the eleventh NMOS transistor N 11 The gate of the (N) is connected with the third bias voltage Vbias1, the eleventh NMOS transistor N 11 The drain electrode of the transistor is connected with a twelfth PMOS tube P 12 Drain electrode of the twelfth PMOS tube P 12 The grid electrode of the transistor is connected with a twelfth PMOS tube P 12 Drain electrode of the twelfth PMOS tube P 12 The source electrode of (C) is connected with the eleventh PMOS tube P 11 Drain electrode of the eleventh PMOS tube P 11 The grid electrode of the transistor is connected with an eleventh PMOS tube P 11 Drain electrode of the eleventh PMOS tube P 11 The source electrode of the tenth NMOS transistor N is connected with the working voltage VCC 10 A tenth NMOS transistor N with the source electrode grounded 10 The grid electrode of (C) is connected with a seventh NMOS tube N 7 Drain electrode of tenth NMOS transistor N 10 The drain electrode of (C) is connected with the twelfth NMOS tube N 12 A twelfth NMOS transistor N 12 The grid electrode of (C) is connected with an eleventh NMOS tube N 11 Gate of twelfth NMOS transistor N 12 The drain electrode of the transistor is connected with a fourteenth PMOS tube P 14 Drain electrode of the fourteenth PMOS tube P 14 The grid electrode of the transistor is connected with a twelfth PMOS tube P 12 Gate of fourteenth PMOS tube P 14 The source electrode of (C) is connected with the thirteenth PMOS tube P 13 Drain electrode of thirteenth PMOS tube P 13 The grid electrode of the transistor is connected with an eleventh PMOS tube P 11 Gate electrode of thirteenth PMOS tube P 13 The source electrode of the ninth NMOS transistor N is connected with the working voltage VCC 9 The gate of the (a) is the first input end of the second bias current generating unit, the tenth NMOS transistor N 10 The gate of the second bias current generating unit is the second input end of the eleventh NMOS transistor N 11 The gate of the (B) is a third input end of the second bias current generating unit, and the fourteenth PMOS tube P 14 The drain electrode of the second bias current generating unit outputs an operating current Ibias_4 containing temperature information.
In detail, as shown in fig. 2, the tracking temperature calibration module includes a single-pole double-throw switch S1, a comparator A0, a tracking temperature calibration unit, a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a third digital-to-analog converter DAC3, and a fourth digital-to-analog converter DAC4, one end of the double-throw end of the single-pole double-throw switch S1 is connected to the control end of the working branch of the current source I to be calibrated, the other end of the double-throw end of the single-pole double-throw switch S1 is connected to the control end of the calibration branch of the current source I to be calibrated, the single-pole end of the single-pole double-throw switch S1 is connected to the third bias voltage Vbias1, the in-phase input end of the comparator A0 is connected to the reference current source Iref, the inverting input end of the comparator A0 is connected to the output end of the calibration branch of the current source I to be calibrated, the output end of the comparator A0 is connected to the input end of the tracking temperature calibration unit, the address output of the tracking temperature calibration unit is connected to the single-pole double-throw switch S1, the output of the tracking temperature calibration unit is connected to the input end of the first digital-to-analog converter DAC2, the output of the tracking temperature calibration unit is connected to the output of the digital-to-analog converter DAC4, the output of the digital-to-analog converter is connected to-analog converter 3, the output of the digital-to-analog converter is connected to the output end of the digital-to-analog converter 2 is connected to the output of the digital-analog converter 3, the digital-to-analog converter 2 is connected to the output of the digital-to-analog converter 3, the bias end of the first digital-to-analog converter DAC1 is connected with the output end of the third digital-to-analog converter DAC3, the output end of the first digital-to-analog converter DAC1 outputs a first calibration current Ical_1, the first calibration current Ical_1 and the second calibration current Ical_2 are overlapped to form a target calibration current Ical_3, and the target calibration current Ical_3 is fed back to the current source I to be calibrated.
In detail, as shown in fig. 2, the to-be-calibrated current steering DAC core circuit includes current steering switching transistors N105 and N106, current switching transistor load resistors R, cascode, level bias transistors N103 and N104, to-be-calibrated current source transistor N100, reference current source transistor N101, and transistor N102 providing a bias current source for the third DAC3 of the calibration portion, wherein gates of the current steering DAC switching transistors N105 and N106 are respectively connected to differential CMOS logic levels D and DB, drains of N105 and N106 are respectively connected to one end of a resistor R, the other end of the resistor R is connected to an operating voltage VCC, sources of N105 and N106 are connected together, and are connected to drains of a Cascode stage bias transistor N103, drains of the Cascode stage bias transistor N104 are connected to inverting input terminals of a comparator A0 of the calibration circuit portion, gates of the Cascode stage bias transistor N103 and N104 are connected to double throw terminals of a single-knife double throw switch S1, sources of the Cascode stage bias transistors N103 and N104 are connected together, and sources of the Cascode stage bias transistors N100 and the drain of the current source bias transistor DAC1 are connected to the inverting input terminals of the comparator A0 of the comparator portion, and the drain of the current source bias transistor N101 are connected to the drain terminal of the comparator N101, and the drain of the current source bias transistor is connected to the drain of the comparator 1 of the comparator portion is connected to the drain terminal of the comparator N101.
In more detail, as shown in fig. 2, the switching of the single-pole double-throw switch S1 is controlled by the calibration address cal_add which is tracked by the output of the temperature calibration unit, the single-pole termination of the single-pole double-throw switch S1 is connected with the Cascode stage bias voltage Vbias1, the input digital codes of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 which provide the target calibration current, the input digital codes of the third digital-to-analog converter DAC3 which provide the operating bias current of the first digital-to-analog converter DAC1 and the fourth digital-to-analog converter DAC4 which provide the operating bias current of the second digital-to-analog converter DAC2 are both provided by the drain current of the current source transistor N102 in the current steering DAC unit circuit (or the output current ibias_1 of the third digital-to-analog converter DAC3 is provided by the output current ibias_1 of the third digital-to-analog converter DAC 3), the operating bias current of the first digital-to-analog converter DAC1 is provided by the output current ibias_1 of the fourth digital-to-analog converter DAC2, and the operating bias current of the fourth digital-to-analog converter DAC4 is provided by the drain current of the current cell transistor i_102 (i_as_3) of the fourth digital-to-analog converter DAC 4).
In more detail, as shown in fig. 2 and 3, the working principle of the current source mismatch foreground calibration circuit for tracking temperature in the present invention is analyzed as follows:
NMOS transistors (neglecting channel length modulation effect) N100, N101, and N102 operating in the saturation state are designed as current sources, and are obtained from the transfer characteristics of the MOS transistors operating in the saturation region:
（1）
wherein,，is the current factor of the MOS tube, W/L is the width-to-length ratio of the MOS tube, V GS Is the grid source bias voltage of the MOS tube, V TH Is the threshold voltage of the MOS tube, C OX Is the capacitance of the gate oxide layer per unit area,is carrier mobility.
Differentiating the formula (1), the absolute error of the unit current is obtained as follows:
（2）
equation (3) is further derived from equation (2) as follows:
（3）
substituting the formula (3) into the formula (1) can obtain the relative error of the unit current as follows:
（4）
when the sizes of the two MOS transistors are equal, the bias voltage V GS Equality, then further result from equation (4):
（5）
the random mismatch between the current sources of the two MOS tubes with the same size and the same bias voltage can be obtained by the formula (5) and consists of two parts, namely the mismatch of threshold voltageMismatch with current factorCan be simplified as:
（6）
wherein,i is the current of MOS tube in operation, g m Is the transconductance of the MOS tube during working.
Based on the advanced nano-scale CMOS process platform, the working current of the MOS tube can be designed to have smaller temperature dependence,is also generally almost constant with respect to temperature variations,depending on the type of transistor, long channel NMOS transistorHas relatively low temperature dependence. Therefore, the transistors of the current source array are designed as long channel NMOS transistors N100, N101 and N102, which have wide and long lengthsThe ratio is designed to be 1/1.7, which is negligibleTemperature dependence of the term.
From the above, the mismatch temperature dependence of the long-channel NMOS transistor current source array can be simply considered as transconductance g m One factor, known from equation (6), is the transconductance g m Is the bias current I and carrier mobility of the transistor in operationDue to carrier mobility of MOS transistorIs a factor dependent on temperature, g m Exhibiting a strong temperature-dependent characteristic. In general, in equation (6)Ratio of values of (2)Much larger, which plays a key role in the mismatch of the MOS transistor current sources.
In the temperature information-containing current generation module shown in FIG. 3, the first bias current generation unit generates a current (or current source) I 1 And I 2 The first bias voltage generating unit generates bias voltage V of PMOS constant current source P1 And V P2 By a first current mirror current I 2 Generating a current (or current source) I 3 、I 4 And I 5 . Wherein, PMOS tube P 1 、P 3 、P 5 、P 7 And P 9 The width and the length of the PMOS tube P are designed to be consistent and are designed according to the proportion of 2:1 2 、P 4 、P 6 、P 8 And P 10 The width and the length of the resistor R are designed to be consistent, and the resistor R is designed according to the proportion of 10:1 1 And R is 2 The resistance value of (a) is equal to 5kΩ, and the NMOS transistor N 1 、N 2 The width and the length are designed to be consistent, and are designed according to the proportion of 4:1, the firstBias voltage V 1 Obtained from the bandgap reference voltage, designed to be 1.2V. Thus, it is possible to obtain:
（7）
current I 3 And I 4 The second bias voltage generating unit generates bias voltage V of NMOS constant current source N1 And V N2 Then pass through the second current mirror current I 4 Generating a current I 6 Wherein, NMOS tube N 5 And N 7 The width and the length of the NMOS tube are designed to be consistent, and are designed according to the proportion of 8:1, and the NMOS tube N is formed by the two parts 6 And N 8 The width and the length of the resistor R are designed to be consistent, and the resistor R is designed according to the proportion of 1:1 3 And R is 4 The resistance of (2) is equal to 1kΩ. Due to NMOS tube N 5 /N 6 Size and N 7 /N 8 The tubes are identical and the gate bias voltages are identical, thus the current I 4 And current I 6 Equal, thereby obtaining current I 5 And current I 6 Equal.
（8）
Then, the bias voltage V generated by the third bias voltage generating unit can be obtained 2 、V 3 The expression is as follows:
（9）
（10）
due to the bias voltage V 2 、V 3 Is NMOS tube N in the second bias current generating unit 9 And N 10 V of (2) GS Bias voltage, therefore, NMOS transistor N can be obtained 9 And N 10 Leakage current I of (2) 7 、I 8 The following are provided:
（11）
（12）
due to PMOS tube P 11 /P 12 And P 13 /P 14 Is the same in size and bias voltage, and thus, current I 7 And current I 9 Equal, then:
（13）
as can be seen from equation (13), the operating current ibias—4 is equal to the transistor transconductance g m Multiplied by (2R 4 ×V 1 ）/ R 2 And (2R) 4 ×V 1 ）/ R 2 Under temperature variation, it can be regarded as a constant, and thus the operating current Ibias_4 can be regarded as the transistor transconductance g m And the transistor transconductance g m With a strong temperature dependence, we can design the bias current ibias—4 to represent the temperature information of the chip during operation.
Generating an operating current Ibias_4 containing temperature information by using a current generating module containing temperature information, generating a second calibration current Ical_2 by the operating current Ibias_4, providing a calibration bias current Ibias_3 by using a current source transistor N102, and generating a first calibration current Ical_1 by using the calibration bias current Ibias_3; performing superposition summation on the first calibration current Ical_1 and the second calibration current Ical_2 to obtain a target calibration current Ical_3 capable of automatically tracking temperature change; and feeding back the target calibration current ical_3 to the current source I to be calibrated, and performing calibration compensation for automatically tracking temperature change on mismatch between the current source I to be calibrated and the reference current source Iref.
Then, the target calibration current ical_3 that compensates for the mismatch can be obtained:
（14）
thus, the equation (14) can be further derived:
（15）
it should be noted that, before the target calibration current ical_3 is fed back to the current source I to be calibrated, under the control of the tracking temperature calibration unit, the magnitude of the first calibration current ical_1 and the magnitude of the second calibration current ical_2 need to be iteratively adjusted (reduced or amplified), wherein one of the first calibration current ical_1 and the second calibration current ical_2 is amplified, and the other one of the first calibration current ical_2 and the second calibration current ical_3 is amplified, so that the universal and stable target calibration current ical_3 is found, and the final target calibration current ical_3 is equal to the mismatch value between the current source I to be calibrated and the reference current source Iref, and each adjustment adopts a successive comparison algorithm, and the iteration number of iterative adjustment is related to the calibration compensation precision.
In more detail, the detailed procedure based on the iterative adjustment of the tracking temperature calibration unit to find the final target calibration current ical_3 is shown in fig. 4:
firstly, starting calibration, and starting a calibration algorithm;
secondly, selecting the address cal_add of the calibrated current source, and once the address is selected, switching on the current source to be calibrated by the single pole double throw switch S1 in FIG. 2;
setting the input digital codes data_3 and data_4 of the third digital-to-analog converter DAC3 and the fourth digital-to-analog converter DAC4 to be set values 1 (designated first set values), setting the input digital code data_1 of the first digital-to-analog converter DAC1 to be all 0, and enabling the final target calibration current Ical_3 to be equal to the mismatch current I_mis through a successive comparison algorithm to obtain the input digital code data_2 of the second digital-to-analog converter DAC 2;
Fourth, changing the input digital codes data_3 and data_4 of the third digital-to-analog converter DAC3 and the fourth digital-to-analog converter DAC4 to a set value 2 (designated second set value), keeping the input digital code data_2 of the second digital-to-analog converter DAC2 unchanged, and making the final target calibration current ical_3 equal to the mismatch current i_mis by a successive comparison algorithm to obtain the input digital code data_1 of the first digital-to-analog converter DAC 1;
fifthly, restoring the input digital codes data_3 and data_4 of the third digital-to-analog converter DAC3 and the fourth digital-to-analog converter DAC4 to be set values 1 (designated first set values), keeping the input digital code data_1 of the first digital-to-analog converter DAC1 unchanged, and enabling the final target calibration current Ical_3 to be equal to the mismatch current I_mis through a successive comparison algorithm to obtain the input digital code data_2 of the second digital-to-analog converter DAC 2;
a sixth step of changing the input digital codes data_3 and data_4 of the third digital-to-analog converter DAC3 and the fourth digital-to-analog converter DAC4 to the set value 2 (specified second set value);
and seventh, judging whether the iteration times are set values (such as 9 times), if the iteration times are not reached, returning to the fourth step, continuing the iteration work, and if the iteration times are reached, finishing the calibration of the mismatch current of the current source.
Secondly, based on the design thought of the temperature tracking current source mismatch foreground calibration circuit, the invention also provides a temperature tracking current source mismatch foreground calibration method, as shown in fig. 5, which comprises the following steps:
s1, providing a calibration bias current and an operating current containing temperature information;
s2, generating a first calibration current through calibration bias current, and generating a second calibration current through working current;
s3, carrying out superposition summation on the first calibration current and the second calibration current to obtain a target calibration current capable of automatically tracking temperature change;
and S4, feeding back a target calibration current to the current source to be calibrated, and performing calibration compensation for automatically tracking temperature change on mismatch between the current source to be calibrated and the reference current source.
In detail, before executing the step S4 of feeding back the target calibration current to the current source to be calibrated, steps S2-S3 are repeated, the magnitude of the first calibration current and the magnitude of the second calibration current are iteratively adjusted, one of them is amplified and the other is reduced, a universal and stable target calibration current is found, so that the target calibration current obtained by each adjustment is equal to the mismatch value between the current source to be calibrated and the reference current source, and a successive comparison algorithm is adopted during each adjustment. The number of iterations of the iterative adjustment is related to the calibration compensation accuracy, and is not limited herein.
In summary, in the calibration circuit and method for the current source mismatch foreground with temperature tracking provided by the invention, based on the structural design of the temperature information-containing current generation module and the tracking temperature calibration module, the working current containing temperature information is generated by the temperature information-containing current generation module, and then the calibration compensation is carried out by the tracking temperature calibration module according to the mismatch between the current source to be calibrated and the reference current source, so as to provide the target calibration current for the current source to be calibrated, and the obtained target calibration current automatically tracks the temperature change. During calibration compensation, a universal stable target calibration current can be found out through repeated iterative adjustment, and the accuracy of foreground calibration is improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (12)

1. A temperature tracking current source mismatch foreground calibration circuit, comprising:
a current source to be calibrated;
a reference current source;
the current generating module containing temperature information generates working current containing temperature information;
the tracking temperature calibration module is connected with the current source to be calibrated, the reference current source and the temperature information-containing current generation module, and is used for calibrating and compensating the mismatch between the current source to be calibrated and the reference current source according to the working current, providing a target calibration current for the current source to be calibrated, and automatically tracking temperature change by the target calibration current;
the temperature information-containing current generation module comprises a first bias current generation unit, a second bias current generation unit, a first bias voltage generation unit, a second bias voltage generation unit, a third bias voltage generation unit, a first current mirror and a second current mirror, wherein the input end of the first bias current generation unit is connected with a first bias voltage, the first output end of the first bias current generation unit is connected with the first input end of the first bias voltage generation unit, the second output end of the first bias current generation unit is connected with the second input end of the first bias voltage generation unit, the first output end of the first bias voltage generation unit is connected with the first input end of the first current mirror, the second output end of the first bias voltage generation unit is connected with the third input end of the first current mirror, the first output end of the first bias current mirror is connected with the first input end of the second bias voltage generation unit, the first output end of the first bias voltage generation unit is connected with the first output end of the second current mirror, the second output end of the first bias voltage generation unit is connected with the second output end of the first current mirror, and the second output end of the first current mirror is connected with the second input end of the first current mirror, the voltage input end of the third bias voltage generating unit is connected with a second bias voltage, the first voltage output end of the third bias voltage generating unit is connected with the first input end of the second bias current generating unit, the second voltage output end of the third bias voltage generating unit is connected with the second input end of the second bias current generating unit, the third input end of the second bias current generating unit is connected with the third bias voltage, and the output end of the second bias current generating unit outputs the working current.
2. The current source mismatch foreground calibration circuit according to claim 1, wherein the first bias current generating unit comprises an amplifier, a first NMOS tube, a second NMOS tube, a first resistor and a second resistor, wherein the non-inverting input terminal of the amplifier is connected with the first bias voltage, the inverting input terminal of the amplifier is connected with the source of the second NMOS tube, the source of the first NMOS tube is grounded after being connected with the first resistor in series, the source of the second NMOS tube is grounded after being connected with the second resistor in series, and the output terminal of the amplifier is connected with the gate of the first NMOS tube and the gate of the second NMOS tube respectively, wherein the non-inverting input terminal of the amplifier is the input terminal of the first bias current generating unit, the drain of the first NMOS tube is the first output terminal of the first bias current generating unit, and the drain of the second NMOS tube is the second output terminal of the first bias current generating unit.
3. The temperature-tracking current source mismatch foreground calibration circuit of claim 2, wherein the first bias voltage generating unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, wherein a source of the first PMOS transistor is connected to an operating voltage, a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, a drain of the second PMOS transistor is connected to a gate of the second PMOS transistor, a source of the third PMOS transistor is connected to the operating voltage, a drain of the third PMOS transistor is connected to a source of the fourth PMOS transistor, a drain of the fourth PMOS transistor is connected to a gate of the third PMOS transistor, a gate of the first PMOS transistor, a gate of the second PMOS transistor and a gate of the fourth PMOS transistor are shorted, wherein a drain of the second PMOS transistor is a first input terminal of the first bias voltage generating unit, a drain of the fourth PMOS transistor is a second input terminal of the first bias voltage generating unit, and a drain of the first PMOS transistor is a first output terminal of the first bias voltage generating unit.
4. The current source mismatch foreground calibration circuit according to claim 3, wherein said second bias voltage generating unit comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, a drain of said third NMOS transistor is connected to a gate of said third NMOS transistor, a source of said third NMOS transistor is connected to a drain of said fourth NMOS transistor, a gate of said fourth NMOS transistor is connected to a gate of said third NMOS transistor, a source of said fourth NMOS transistor is grounded, a drain of said fifth NMOS transistor is connected to a gate of said sixth NMOS transistor, a source of said fifth NMOS transistor is connected to a drain of said sixth NMOS transistor, a source of said sixth NMOS transistor is grounded, a drain of said third NMOS transistor is a first input terminal of said second bias voltage generating unit, a drain of said fifth NMOS transistor is a second input terminal of said second bias voltage generating unit, and a drain of said fourth NMOS transistor is a second bias voltage generating unit is a second output terminal of said second bias voltage generating unit.
5. The temperature tracking current source mismatch front calibration circuit according to claim 4, wherein the first current mirror comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, the source of the fifth PMOS transistor is connected to the operating voltage, the gate of the fifth PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor, the source of the seventh PMOS transistor is connected to the operating voltage, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, the source of the eighth PMOS transistor is connected to the gate of the fourth PMOS transistor, the source of the ninth PMOS transistor is connected to the operating voltage, the gate of the ninth PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the fourth PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor.
6. The temperature-tracking current source mismatch foreground calibration circuit according to claim 5, wherein the third bias voltage generating unit comprises a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third resistor and a fourth resistor, wherein a drain of the tenth PMOS transistor is connected to a drain of the seventh NMOS transistor after passing through the third resistor and the fourth resistor which are sequentially connected in series, a gate of the seventh NMOS transistor is connected to a gate of the fifth NMOS transistor, a source of the seventh NMOS transistor is connected to a drain of the eighth NMOS transistor, a gate of the eighth NMOS transistor is connected to a gate of the sixth NMOS transistor, a source of the eighth NMOS transistor is grounded, a drain of the tenth PMOS transistor is a first current input terminal of the third bias voltage generating unit, a drain of the seventh PMOS transistor is a second current input terminal of the third bias voltage generating unit, a common terminal of the third resistor and the fourth resistor is a drain of the third NMOS voltage generating unit, and a drain of the seventh NMOS voltage generating unit is a drain of the third bias voltage generating unit.
7. The temperature-tracking current source mismatch foreground calibration circuit of claim 6, wherein said second current mirror comprises said fifth NMOS transistor, said sixth NMOS transistor, said seventh NMOS transistor, and said eighth NMOS transistor, wherein a gate of said fifth NMOS transistor is a first input of said second current mirror, a gate of said sixth NMOS transistor is a second input of said second current mirror, a drain of said fifth NMOS transistor is a third input of said second current mirror, and a drain of said seventh NMOS transistor is an output of said second current mirror.
8. The temperature-tracking current source mismatch front calibration circuit according to claim 6, wherein said second bias current generating unit comprises a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor, a source of said ninth NMOS transistor is grounded, a gate of said ninth NMOS transistor is connected to a drain of said tenth PMOS transistor, a drain of said ninth NMOS transistor is connected to a source of said eleventh NMOS transistor, a gate of said eleventh NMOS transistor is connected to said third bias voltage, a drain of said eleventh NMOS transistor is connected to a drain of said twelfth PMOS transistor, a gate of said twelfth PMOS transistor is connected to a drain of said PMOS transistor, a source of said twelfth PMOS transistor is connected to a drain of said eleventh PMOS transistor, a source of said eleventh PMOS transistor is connected to said operating voltage, a source of said NMOS transistor is connected to a drain of said NMOS PMOS transistor, a source of said NMOS transistor is connected to a ground, a drain of said NMOS transistor is connected to a drain of said PMOS transistor, a drain of said PMOS transistor is connected to a drain of said PMOS transistor, a drain of said NMOS transistor is biased, a drain of said NMOS transistor is connected to a drain of said NMOS transistor, a drain of said NMOS transistor is connected to a PMOS transistor, a drain of said NMOS transistor is biased, a source of said NMOS transistor is connected to said NMOS transistor, a drain of said NMOS transistor is connected to said NMOS transistor, and a source of said NMOS transistor is biased to drain of said NMOS transistor is connected to said NMOS transistor. The grid of the eleventh NMOS tube is a third input end of the second bias current generating unit, and the drain electrode of the fourteenth PMOS tube is an output end of the second bias current generating unit.
9. The temperature tracking current source mismatch front calibration circuit according to claim 8, wherein the temperature tracking calibration module comprises a single-pole double-throw switch, a comparator, a temperature tracking calibration unit, a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, and a fourth digital-to-analog converter, one of the double-throw ends of the single-pole double-throw switch is connected with the control end of the working branch of the current source to be calibrated, the other of the double-throw ends of the single-pole double-throw switch is connected with the control end of the calibration branch of the current source to be calibrated, the single-pole of the single-pole double-throw switch is connected with the third bias voltage, the non-inverting input of the comparator is connected with the output end of the calibration branch of the current source to be calibrated, the output of the comparator is connected with the input end of the temperature tracking calibration unit, the address output of the temperature tracking calibration unit is connected with the single-pole-to-analog converter end of the single-temperature tracking calibration unit, the first data output end of the tracking temperature calibration unit is connected with the input end of the first digital-to-analog converter, the other end of the tracking temperature calibration unit is connected with the control end of the calibration branch of the current source to be calibrated, the non-inverting input of the calibration unit is connected with the output of the reference current source to the calibration unit, the output of the calibration unit is connected with the output of the digital-to the calibration unit, the bias end of the first digital-to-analog converter is connected with the output end of the third digital-to-analog converter, the output end of the first digital-to-analog converter outputs a first calibration current, the first calibration current and the second calibration current are overlapped to form a target calibration current, and the target calibration current is fed back to the current source to be calibrated.
10. A temperature-tracking current source mismatch foreground calibration method applied to a temperature-tracking current source mismatch foreground calibration circuit according to any one of claims 1 to 9, comprising:
providing a calibration bias current and an operating current containing temperature information;
generating a first calibration current by the calibration bias current and a second calibration current by the operating current;
carrying out superposition summation on the first calibration current and the second calibration current to obtain a target calibration current capable of automatically tracking temperature change;
and feeding the target calibration current back to a current source to be calibrated, and performing calibration compensation for automatically tracking temperature change on mismatch between the current source to be calibrated and a reference current source.
11. The method of claim 10, wherein the magnitude of the first calibration current and the magnitude of the second calibration current are iteratively adjusted prior to feeding back the target calibration current to the current source to be calibrated such that the target calibration current resulting from each adjustment is equal to the mismatch value between the current source to be calibrated and the reference current source, and wherein a successive comparison algorithm is employed for each adjustment.
12. The temperature-tracking current source mismatch foreground calibration method according to claim 11, wherein the number of iterations of said iterative adjustment is related to calibration compensation accuracy.
CN202211268826.7A 2022-10-17 2022-10-17 Temperature-tracking current source mismatch foreground calibration circuit and method Active CN115494908B (en)

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