CN115473572B - Method and system for realizing signal arrival detection based on double correlation algorithm - Google Patents
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Abstract
The invention discloses a method and a system for realizing signal arrival detection based on a double correlation algorithm. The method comprises the steps of receiving a unique code signal, and shunting the unique code signal, wherein one path of the unique code signal is filtered to obtain a filtered signal; constructing an autocorrelation module, performing signal autocorrelation operation on the filtering signals, outputting a preset number of storage results, and storing the storage results; taking a preset storage result, and carrying out XOR operation and summation operation in sequence to obtain a signal correlation value; a decision module is constructed, the signal correlation value is received, whether the signal reaches the decision module or not is judged, and a decision result is output; and delaying the judgment result and outputting the result. The invention reduces the algorithm complexity, provides a method for judging the threshold value of the signal correlation value, effectively reduces the false alarm probability and the missed detection probability and reduces the processing time.
Description
Technical Field
The invention belongs to the technical field of satellite communication, and particularly relates to a method and a system for realizing signal arrival detection based on a double correlation algorithm.
Background
In recent years, the field of satellite communication is rapidly developed, the manufacturing and transmitting cost and bandwidth cost of the satellite are reduced, and high-flux synchronous satellites and low-orbit satellites also enter the field of view of the general public. The low earth orbit satellite has an operating angular velocity of 3.6 degrees per minute, i.e., an orbital rate of about 7.8 kilometers per second. However, the doppler shift problem caused by the high-speed motion of the low-earth orbit satellite provides a challenge for the signal arrival detection of satellite communication.
The existing arrival detection method is a single correlation operation, that is, a signal at a receiving end is correlated with a known local unique code, but the detection accuracy is reduced along with the increase of frequency offset. To solve this problem, the skilled person proposes a double correlation algorithm, but it is not widely used. The reason for this is that the calculation of the method is too complex, complex multiplication needs to be performed on the filtering signals with different lengths, then the multiplication needs to be performed on the filtering signals, the results are multiplied by the results after the correlation with the local unique codes, the obtained results are summed up and modulo according to different numerical values, and finally the summed results are accumulated to calculate the correlation value of the current filtering signal. Therefore, this method not only requires a lot of resources, but also increases the processing time and the requirement for the timing is increased.
Therefore, a new technology is needed to solve the above problems.
Disclosure of Invention
The purpose of the invention is as follows: a method for realizing signal arrival detection based on a double correlation algorithm is provided to solve the problems in the prior art. And further provides a system for implementing the method.
The technical scheme is as follows: a method for realizing signal arrival detection based on a double correlation algorithm comprises the following steps:
s1, receiving a unique code signal, and shunting the unique code signal, wherein one path is filtered to obtain a filtered signal;
s2, constructing an autocorrelation module, performing signal autocorrelation operation on the filtering signals, outputting a preset number of storage results, and storing the storage results;
s3, taking a preset storage result, and carrying out XOR operation and summation operation in sequence to obtain a signal correlation value;
s4, constructing a judgment module, receiving the signal correlation value, judging whether the signal reaches the judgment result, and outputting the judgment result;
and S5, delaying the judgment result and outputting the result.
Further, the specific steps in S2 include:
s21, combining at least a symbol delay module, a complex multiplication module and a storage module into the autocorrelation module;
s22, correcting the sampling point at the previous moment into the sampling point at the current moment by using a symbol delay module;
s23, inputting the sampling point at the previous moment and the sampling point at the current moment to a complex multiplication module for operation, and outputting a storage result;
and S24, inputting the storage result into a storage module for storage.
Further, the sampling point at the previous moment and the sampling point at the current moment are obtained based on the biphase Guan Suanfa; the formula of the double correlation algorithm is as follows:
wherein,
in order for the parameters to be known,UW*(k)in order to select the unique code signal,r(n)for filtering the signal, the parameter N represents the oversampling multiple of the received signal, D represents the maximum correlation interval, L represents the length of the unique code signal, r (N + kN + Nd) is the current time instant sample, r (N + kN) is the previous time instant sample, r represents the conjugate, and i represents the modulus.
Further, the specific step of S3 includes:
s31, selecting the data stored in the step S24 to form a group of new data, carrying out XOR operation on the new data and the corresponding data in the known parameters, and outputting the result of the XOR operation;
s32, counting the number of 0 in the XOR operation result, reducing the calculation amount by changing the accumulation of the number L into the number of 0 judgment, and summing the calculation result toNum0－(L－Num0)＋N_padding(d)；
And S33, generating a preset amount of data after the calculation is finished, and calculating again according to a preset calculation method to obtain the signal correlation value of the sampling point at the corresponding moment.
Further, the decision process of the decision module includes:
s41, outputting the signal correlation value in the S33 to a judgment module, wherein the judgment module at least comprises a sliding window module and a comparison module;
s42, the sliding window module judges whether the position of the maximum value of the signal correlation value in the current window is located at the tail position of the window; if the signal is at the tail position, the comparison module judges the proportion between the value of the signal and the value of the window starting position, namely 0, and judges that the signal arrives after the preset proportion relation is met.
A system for realizing signal arrival detection based on a double correlation algorithm at least comprises a radio frequency receiving module, a filtering module, a signal autocorrelation module, a UW module, a judgment module and a delay module based on the application of the method for realizing the signal arrival detection based on the double correlation algorithm, wherein the output end of the radio frequency receiving module is respectively connected with the input end of a matched filtering module and the input end of the delay module, the matched filtering module outputs to a signal autocorrelation operation module, the result of the signal autocorrelation module outputs to the UW module, the UW module carries out XOR and summation operation, the UW module is connected with the judgment module, when the output result at the current moment of the UW meets the judgment condition of the judgment module, the signal arrival is judged, the judgment result is fed back to the delay module, and the signal arrival detection is finished.
The function and operation data of the relevant modules are as described in the above embodiments.
Has the advantages that:
1. for the signal of the high frequency offset signal, the signal arrival detection is carried out by using a double correlation algorithm, the influence of the frequency offset is eliminated by the autocorrelation operation of the first layer signal, and the autocorrelation result of the second layer signal and the autocorrelation result of the local unique code are subjected to the correlation operation to obtain a correlation value and judge.
2. The invention optimizes the autocorrelation operation of the first layer signal, reduces the consumption of storage resources, reduces the processing time and is suitable for the data processing with high symbol rate; and aiming at the second-layer correlation operation, the accumulated summation of the data is converted into the number of 0 in the calculation register, so that the calculation complexity is greatly reduced, the resource consumption is also reduced, and the processing time is also greatly reduced.
3. For the judgment of the correlation value, a judgment mode is given, and the processing time depends on the length of the sliding window Lw. In general, the processing time of all modules except the decision module is about 3D sampling periods, and for a high symbol rate, the processing time is much shorter than the time of L data accumulation sums in the formula, so that the resource consumption is reduced, and the calculation amount is simplified.
Drawings
Fig. 1 is a schematic diagram of a physical frame structure model at a transmitting end according to the present invention.
FIG. 2 is a block diagram of an algorithm implementation of the present invention.
FIG. 3 is a flow chart of a signal autocorrelation module according to the present invention.
Fig. 4 is a flow chart of a decision module of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
The invention realizes the resistance to the influence of Doppler frequency shift brought by high-speed motion of a receiving and transmitting end by a method for realizing signal arrival detection based on a double correlation algorithm in satellite communication, and optimizes the realization process of the double correlation algorithm on the basis, thereby reducing the resource consumption and the processing time. The present invention will be further described in detail with reference to the following examples and accompanying drawings.
The method mainly comprises the following steps:
dividing the received signal, delaying one path and filtering the other path;
performing signal autocorrelation operation on the filtered signal;
local unique code operation and summation operation;
and (5) judging a signal correlation value.
As shown in fig. 1, in the present invention, a method for implementing signal arrival detection based on a double correlation algorithm is proposed, which includes a schematic model diagram of a physical frame structure of a transmitting end. The physical frame structure of the transmitting end is composed of a synchronization code (unique code) and transmission data. The unique code adopts an m sequence with good correlation, the m sequence is generated by a multi-stage shift register through linear feedback, and a primitive polynomial of the m sequence adopted by the invention is as follows:
the initial state is as follows: 0000_0001, the period length is 255, in order to ensure that probabilities such as 0,1 and the like occur, the unique code length adopted by the invention is 256 bits (L = 256), and UW = [ m,0] is formed by adding 0 to an m sequence of one period. And the physical frame is sent to a radio frequency sending end through a forming filter, and the oversampling multiple N =4. At the receiving end, the maximum correlation interval D =8 in the two-correlation algorithm,
as shown in fig. 2, the implementation principle of the double correlation algorithm at the receiving end is described. The output end of the radio frequency receiving module is respectively connected with the input end of the matched filtering module and the input end of the delay module. The matched filtering module outputs the signals to the signal autocorrelation operation module, the signal autocorrelation module optimizes and stores calculated 2D =16 signal autocorrelation values, the result of the signal autocorrelation module is output to the UW module, and the UW module performs XOR, peace and summation operation. The UW module is connected with the judgment module, when the output result at the current moment of the UW meets the judgment condition of the judgment module, the signal arrival can be judged, and the judgment result is fed back to the delay module, so that the signal arrival detection is completed.
The method specifically comprises the following steps:
the method comprises the following steps: the received signal is divided, one path is delayed, and the other path is filtered:
whether the single correlation calculation or the double correlation calculation is carried out, whether a signal arrives or not can be judged after a complete synchronous code signal, namely a local unique code signal, is received, and when the judgment signal arrives, the received unique code signal data is already passed in time, so that other calculations, such as frequency offset estimation, of a subsequent module according to the received unique code signal are inconvenient, and time delay is needed to be carried out, and the time of the time delay is at least longer than the time of the arrival of the judgment signal. Meanwhile, in order to reduce the influence of noise on the detection result, the received signal needs to pass through a matched filter and then the signal arrival detection is performed.
The coefficients of the matched filter are the same as those of the transmit-side shaping filter. The delay module is composed of FIFO, the depth of FIFO is 2048bit, the write enable of FIFO is driven by Valid, the read enable is decided by Valid, threshold and feedback enable of decision module. When the read enable is asserted, the data read from the FIFO begins to count, sampleCount [31 ] plus 1. When the data in the FIFO of the delay module is greater than the threshold value, the feedback enable of the decision module is still not received, the FIFO read enable is driven by Valid, the read data are invalid and do not need to be transmitted to the next module, and the read data are Valid until the feedback of the decision module is received and the feedback count is equal to the SampleCount. The data at this time may be transferred to the next module.
Step two: and performing signal autocorrelation operation on the filtered signal:
as shown in fig. 3, the input signal of the signal autocorrelation module is composed of a master clock Clk, a reset signal reset, I-way data Idat [11 [ 0], Q-way data Qdat [11 [ 0], and data enable composition Valid.
In normal operation, every time a Valid pulse arrives, 1 is added to Rth _ counter [31 ] to represent the serial number of the current sampling point. The total number of the delayers in the symbol delay module is 8, each delay Shi Qiyan is 4 Valid, the input and output bit number of the delayer is 24bit, the input of the first delay is { -Qdat, idat }, and the first delay is conjugate complex multiplication operation, so that conjugation is performed. The delay of the delayer is driven by Valid. The number of complex multipliers in the complex multiplication module is 8, which are also driven by Valid. Whenever Valid and data arrive, the first complex multiplier is multiplied by Qdat, idat and the output of the first delay, the second complex multiplier is multiplied by Qdat, idat and the output of the second delay, and the eighth complex multiplier is multiplied by Qdat, idat and the output of the eighth delay. The input bit number of the complex multiplier is 24 bits, sign bits of a real part and an imaginary part of an output result are respectively taken and stored in a corresponding 1024-bit shift register. The storage module has 16 1024-bit shift registers. The shift is performed, for example, by shifting the value of reg _ I1[1023 0] by 1 bit to the right, storing the output result of the first complex multiplier, result1[32], in the register reg _ I1[1023], shifting the value of reg _ Q1[1023] by 1 bit to the right, and storing the output result of the first complex multiplier, result1[72], in the register reg _ Q1[1023 ]. The memory module is still driven by Valid, and every time Valid and data arrive, the shift register shifts right by one bit, and simultaneously, the corresponding sign bit is stored in the high bit of the shift register.
The processing time of the whole signal autocorrelation module comprises the processing time of the complex multiplier and the delay of 1 stored sampling point. Pipeline of the complex multiplier =6, so the overall delay is 7 sample points in time.
Step three: local unique code operation and summation operation:
the transmission signal is composed of a synchronization code, i.e., a local unique code, and transmission data. The local unique code is a known m-sequence with good correlation, i.e.UW(k)Is a known sequence consisting of 0,1. So in the formula of the double correlation algorithm
Can be directly stored as a known parameter inIn the UW module, registers that can be expressed as D L-bit wide are notedUW reg(d) . Some of the invalid bits are countedN_padding(d)And sets the value corresponding to the invalid bit to 1.
Every time a sampling point comes, a signal autocorrelation module is used for sampling a signal in each memory [0]Form a new set of data andUW reg(d) in which the registers corresponding to the same d value are XOR-operated, and the data of the I path and the Q path are XOR-operatedUW reg(d) The values are the same. The exclusive-or operation can be completed in 1 main clock period, and the total output results of the exclusive-or operation are 2D.
The sequence of UW is known and can be determined according to
And directly calculating the result of the autocorrelation operation of the unique code. For example, 255 pieces of data are generated when d =1, and 254 pieces of data are generated when d = 2. Similarly, at d =8, 248 data are generated, and less data are invalid data than 256 data of the unique code itself, all of which are set to 1, and the number of which is recorded to be equal to d. The data of the 8 rows and 256 columns are stored in 8 256-bit registers UW1[255]、UW2[255:0]、......UW8[255:0]It is shown that data with k =1 is low, and data with k as the maximum value is high.
The 16 1024bit registers of the signal autocorrelation module are decimated into data in the manner of 0. Registers reg _ Ix _256 and UWx corresponding to the same value d are subjected to exclusive-or operation, and UWx obtained by performing exclusive-or operation on data of the I path and the Q path is the same. The exclusive-or operation can be completed in 1 cycle of the main clock, and is also driven by Valid for the sake of uniformity. The output of the exclusive-or operation is 16 in total, and is represented by UW _ sx [ 255. Delaying by 1 sample period.
And then, summing operation is carried out, the number of 0 in the result register output by the exclusive-or operation can be counted, and as can be seen from the step two, 0 represents a positive number, and 1 carries a negative number. Therefore, through the optimization in the step two, the accumulation of the L numbers is changed into the number of judgment 0, and the calculation amount is greatly reduced. All summation operations can be performed simultaneously, and after the calculation is completed, 2D data are generated. And then the 2D data squares are summed, and the signal correlation value of the sampling point at the corresponding moment can be calculated. It should be noted that there is a time difference between the calculated signal correlation value and the sampling point at the corresponding time, and the time of the difference is determined by the processing time, so that the corresponding relationship needs to be determined.
For example, as can be seen from step two, the number of 0 s in W _ sx is a positive number, and 1 is a negative number. The actual summation results are:Num0-(256-Num0) + d is equivalent to an increase of 1 at the invalid position 1, and therefore needs to be compensated for in the actual calculation. All summation operations can be performed simultaneously, and after the computation is completed, 16 data are generated. And then, summing the square of the 16 data, so as to calculate the signal correlation value Rth [21]. The sum and square operation is also driven by Valid for a total delay of 9 sample periods. Therefore, at this time, there is a difference of 17 counts between Rth _ Counter corresponding to Valid at the current time and Rth _ Counter corresponding to Rth.
Step four: and (3) signal correlation value judgment:
and after the sampling points and the corresponding signal correlation values are determined, the signal correlation values are output to a judgment module. The judgment module consists of a sliding window module and a comparison module. The length of the sliding window is Lw (odd number), the window slides once every sampling point comes, and whether the position of the maximum value of the signal correlation value in the current window is located at the tail position of the window, namely Lw, is judged once. If the signal is at the end, the comparison module judges the proportion between the value and the value at the window starting position, namely 0, and can judge that the signal arrives after a certain proportion relation is met, and the processing time at the moment is Lw sampling point time.
For example, the Rth value and the corresponding Rth _ Counter in step three are sent to the sliding window module of the decision module. The length of the sliding window is 33, the window slides once every Valid, the maximum value Rth _ max of the signal correlation value in the current window and the size of the current Rth are judged once, if the Rth _ max > Rth, the value of the counting max _ cnt [5:0] plus 1 Rth _maxat the position of the maximum value is kept unchanged; conversely, if Rth _ max ≦ Rth, the value of max _ cnt [5:0] becomes 1,Rth _max = Rth. After the comparison is completed, whether the value of max _ cnt is 33 or not is confirmed, if the value is 33, when the comparison module judges that the value comes from the new Valid of the window, the proportion between Rth _ max and Rth is satisfied, and after Rth _ max > 4 × Rth, the signal can be judged to arrive, and the whole judgment process is shown in fig. 4. The processing time at this time is 34 sampling point times, and there is a difference of 51 sampling counts between Rth _ Counter corresponding to Valid at the current time and the sampling point where the actual signal arrives. Then the Count Rth _ Valid _ Count [31 ] = Rth _ counter-51-255 × 4 of the actual unique code start sample point. At this time, the values of the feedback enable Rth _ Valid and Rth _ Valid _ Count are output to the delay module.
In summary, in order to improve the detection side precision, the invention provides a method for detecting signal arrival based on a double correlation algorithm, the signal arrival detection is carried out by using the double correlation algorithm, the influence of frequency deviation is eliminated by the autocorrelation operation of a first layer signal, the autocorrelation result of a second layer signal and the autocorrelation result of a local unique code are subjected to the correlation operation, a correlation value is obtained, and the judgment is carried out. The invention optimizes the autocorrelation operation of the first layer signal, reduces the consumption of storage resources, reduces the processing time and is suitable for the data processing with high symbol rate; for the second layer of correlation operation, the accumulated summation of the data is converted into the number of 0 in the solution register, so that the calculation complexity is greatly reduced, the resource consumption is also reduced, and the processing time is also greatly reduced; for the judgment of the correlation value, a judgment mode is given, and the processing time depends on the length of the sliding window Lw.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (5)
1. The method for realizing signal arrival detection based on the double correlation algorithm is characterized by comprising the following steps of:
s1, receiving a unique code signal, and shunting the unique code signal, wherein one path is filtered to obtain a filtered signal;
s2, constructing an autocorrelation module, performing signal autocorrelation operation on the filtering signals, outputting a preset number of storage results, and storing the storage results;
s3, taking a preset storage result, and carrying out XOR operation and summation operation in sequence to obtain a signal correlation value;
s4, constructing a judgment module, receiving the signal correlation value, judging whether the signal reaches the judgment result, and outputting the judgment result;
s5, delaying the judgment result and outputting the result;
the S2 comprises the following specific steps:
s21, combining at least a symbol delay module, a complex multiplication module and a storage module into the autocorrelation module;
s22, correcting the sampling point at the previous moment into the sampling point at the current moment by using a symbol delay module;
s23, inputting the sampling point at the previous moment and the sampling point at the current moment to a complex multiplication module for operation, and outputting a storage result;
and S24, inputting the storage result into a storage module for storage.
2. The method for achieving signal arrival detection based on the dual correlation algorithm as claimed in claim 1, wherein the sampling points at the previous time and the current time are obtained based on a dual phase Guan Suanfa; the formula of the double correlation algorithm is as follows:
wherein,
is a known parameter, whereinUW(k)In order to select the unique code signal,r (n)for filtering signals, parametersNRepresenting an over-sampled multiple of the received signal,Dindicating the maximum correlation interval, L indicating the unique codeThe length of the signal(s) is,r*(n+kN+Nd)is a sample point at the current time,r(n+kN)the samples at the previous time are the conjugates and the symbol represents the modulus.
3. The method for achieving signal arrival detection based on the double correlation algorithm as claimed in claim 2, wherein the step S3 comprises:
s31, selecting the storage result stored in the step S24 to form a group of new data, carrying out XOR operation on the new data and the corresponding data in the known parameters, and outputting the XOR operation result;
s32, counting the number of 0 in the XOR operation result, reducing the calculation amount by changing the accumulation of the number L into the number of judgment 0, and summing the calculation result to obtainNum0－(L－Num0)＋N_padding(d)；
And S33, generating a preset amount of data after the calculation is finished, and calculating again according to a preset calculation method to obtain the signal correlation value of the sampling point at the corresponding moment.
4. The method for signal arrival detection based on the double correlation algorithm as claimed in claim 3, wherein the decision process of the decision module comprises:
s41, outputting the signal correlation value in the S33 to a judgment module, wherein the judgment module at least comprises a sliding window module and a comparison module;
s42, the sliding window module judges whether the position of the maximum value of the signal correlation value in the current window is located at the tail position of the window; if the signal is at the tail position, the comparison module judges the proportion between the value of the signal and the value of the window starting position, namely 0, and judges that the signal arrives after the preset proportion relation is met.
5. A system for realizing signal arrival detection based on a double correlation algorithm is characterized by at least comprising a radio frequency receiving module, a filtering module, a signal autocorrelation module, a UW module, a judgment module and a delay module, wherein the output end of the radio frequency receiving module is respectively connected with the input end of a matched filtering module and the input end of the delay module, the matched filtering module outputs to a signal autocorrelation operation module, the result of the signal autocorrelation module outputs to the UW module, the UW module carries out XOR and summation operation, the UW module is connected with the judgment module, when the output result of the UW at the current moment meets the judgment condition of the judgment module, the signal arrival is judged, and the judgment result is fed back to the delay module to finish the detection of the signal arrival.
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| CN108063738B (en) * | 2017-11-22 | 2020-08-25 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Convergence decision method for digital equalizer |
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