CN115473537A - Improved ES-SCL decoding method in polarization code - Google Patents

Improved ES-SCL decoding method in polarization code Download PDF

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CN115473537A
CN115473537A CN202211140736.XA CN202211140736A CN115473537A CN 115473537 A CN115473537 A CN 115473537A CN 202211140736 A CN202211140736 A CN 202211140736A CN 115473537 A CN115473537 A CN 115473537A
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袁建国
张降龙
余林峰
游薇
张丰果
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Chongqing University of Post and Telecommunications
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Abstract

The invention relates to an improved ES-SCL decoding method in a polarization code. The invention belongs to the technical field of channel coding, and the method comprises the steps of firstly constructing an error set according to the channel characteristics of a polar code, setting a Parity Check (PC) bit according to elements in the error set during the coding of the polar code, placing an information bit and a freezing bit at the rest positions, obtaining bit estimation of the PC bit by each path through a check function when a decoder decodes the PC bit, not executing path splitting and pruning, and executing Serial Cancellation List (SCL) decoding at the rest positions. Simulation results show that the ES-SCL decoding method provided by the invention obtains certain performance gain compared with a CA-SCL decoding algorithm and a PC-PSCL decoding algorithm; in addition, the ES-SCL decoding method adopting the partial bit splitting decoding can reduce about 50% of sequencing times and has lower decoding complexity under the condition that the block error rate is almost the same as that of a PC-PSCL decoding algorithm.

Description

Improved ES-SCL decoding method in polarization code
Technical Field
The invention belongs to the technical field of channel coding, and relates to an improved ES-SCL (subsequent Cancellation List based on the Error Set, ES-SCL) decoding method in channel coding. The method is mainly based on the principles of Error Set (ES) construction, parity Check (PC) code and polar code Serial Cancellation List (SCL) decoding algorithm to improve the defect of Error correction performance of the polar code at medium and short code length.
Background
The polar code proposed by Arikan is a first kind of code word that can be proven to achieve the channel capacity of binary input memoryless symmetric channels, and is an important technology of a new generation of mobile communication systems. The polar code has successfully selected into the 5G standard, becomes a coding scheme of a control channel in a 5G enhanced mobile broadband scene, and is a research hotspot in the current channel coding field. In addition to the channel capacity accessibility feature, the polar code has the outstanding advantage that no error floor exists under the serial cancellation decoding algorithm. However, in the case of limited code length, the Block Error Rate (BLER) performance of the actual SC decoding algorithm is far worse than that of the Turbo code and the LDPC code due to incomplete channel polarization.
Thus, researchers have proposed a Sequential Cancellation List (SCL) decoding algorithm capable of retaining a plurality of decoding paths, and a CA-SCL (CRC Aid SCL) decoding algorithm using a CRC-Polar code concatenated with a Cyclic Redundancy Check (CRC) code. The CA-SCL decoding algorithm selects the Path with the minimum Path Metric value (PM) from the paths passing through CRC check as decoding output when the decoding is finished, and the decoding performance of the SCL is improved. Under the CA-SCL decoder, compared with the LDPC code with the same code length and code rate, the BLER performance of the polarization code can exceed that of the existing LDPC code.
Because the CRC code is generally added at the end of the information sequence and cannot detect errors occurring in the decoding process, some researchers have proposed a scheme of a concatenated Parity Check (PC) code to correct errors occurring in the decoding process in time, thereby further improving the error correction capability of the polar code. The key of the parity check code cascade polarization code scheme is the selection of the position of the PC (personal computer) bit and the determination of the check function of the PC bit. The scholars propose a Parity Check code assisted serial Cancellation List (PC-SCL) decoding algorithm, which calculates the error probability P of each channel by Gaussian approximation e Selecting P e The largest non-frozen bit is used as the position of the PC codes, and each PC code only checks part P e The larger information bits. Another scholarly proposed serial cancellation partial list (Parity Check addressed Par) based on Parity code concatenated polar codesPartial Cancellation List, PC-PSCL) decoding algorithm, which calculates the error probability P of each channel though also by Gaussian approximation e But choose P in the partially split bits e The minimum position is used as the position of the PC codes, and each PC code also verifies part P e The larger information bits. Because the two parity check code cascade polarization code schemes only depend on Gaussian approximation to select the position of the PC code, and the channel characteristics of the polarization code are not fully considered, the performance improvement is not obvious compared with a CA-SCL decoding algorithm. Aiming at the problem, the invention constructs an Error Set by analyzing the characteristics of a polarization channel in the polarization code, and sets a PC bit according to elements in the Error Set, thereby providing an improved ES-SCL (successful registration List based on Error Set, ES-SCL) decoding method with lower block Error rate.
Disclosure of Invention
Accordingly, the present invention is directed to an improved method for decoding ES-SCL in a polar code. The method comprises the steps of firstly constructing an error set according to the channel characteristics of a polar code, setting PC bits according to elements in the error set during the coding of the polar code, placing information bits and frozen bits at other positions, obtaining bit estimation of the PC bits by each path through a check function when a decoder decodes the PC bits, not executing path splitting and pruning, and executing SCL decoding at other positions.
In order to achieve the purpose, the invention provides the following technical scheme:
firstly, selecting the length N of a polarization code to be designed, the number k of information bits, the number m of parity check code bits and the number r of CRC (cyclic redundancy check) codes, calculating the reliable measurement value of each channel by using a Gaussian approximation method, and obtaining a split channel position index value sequence after sequencing from high to low
Figure BDA0003853483280000021
And selecting better k + m + r channels from N polarized channels to transmit a non-frozen bit set A, and transmitting the frozen bit set A by the rest N-k-m-r channels c 。
Then passing through A and A c Determining a Rate 1 (Rate-1, R1) node and a Single-Parity-Check (SPC) nodeWherein the R1 node is a sub-polar code block containing only information bits, and the SPC node is a sub-polar code block in which all bits are information bits except for the first bit which is a frozen bit. And then arranging the R1 and SPC nodes in descending order according to the lengths of the nodes, arranging the nodes with low channel sequence numbers in the front when the lengths of the two nodes are equal, and finally sequentially adding the first non-frozen bits of the ordered R1 node and the SPC node into an error set ES.
Then selecting k positions of PC codes and calculating the value of each PC position to complete PC code coding to obtain the coded sequence at the moment
Figure BDA0003853483280000022
Then to
Figure BDA0003853483280000023
CRC coding is carried out to obtain
Figure BDA0003853483280000024
Finally will be
Figure BDA0003853483280000025
Coding the polarization code as a non-frozen bit set in the polarization code to obtain a code word
Figure BDA0003853483280000026
And when the receiving end adopts a corresponding decoding method, namely, the decoder decodes the PC bit, each decoding path obtains a decoding estimation value of the PC bit through check function calculation according to respective decoding result, and the PM is updated according to the LLR at the moment. When the decoder decodes other positions, SCL decoding is executed, and a path with the minimum PM is selected from paths passing CRC check after decoding is finished to serve as an output result of the decoder.
And finally, under the same simulation environment, carrying out simulation comparative analysis on an improved ES-SCL decoding method in the polarization code proposed by the patent and other decoding methods of the same type.
The invention has the beneficial effects that:
an improved ES-SCL decoding method in polar codes is proposed. The method comprises the steps of firstly constructing an error set according to the channel characteristics of the polar code, setting parity check PC bits according to elements in the error set when the polar code is coded, placing information bits and freezing bits at other positions, obtaining bit estimation of the PC bits by each path through a check function when a decoder decodes the PC bits, not executing path splitting and pruning, and executing SCL decoding at other positions. So that the method has the following advantages: 1. the condition that the correct path is lost in the SCL decoding process is improved; 2. the code word difference between decoding paths is increased in the decoding process, so that the correct path can be better distinguished from the wrong path in the decoding process.
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In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:
FIG. 1 is a technical scheme of the process of the present invention;
FIG. 2 is a diagram of a binary tree with a code length of 16 for a polar code;
fig. 3 is a comparison graph of block error rate performance of five polar code decoding methods when the code length N = 512;
fig. 4 is a comparison graph of block error rate performance of five polar code decoding methods when the code length N = 256;
FIG. 5 shows the average decoding rank of different decoding methods.
Detailed Description
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(1) With reference to fig. 1, an improved ES-SCL decoding method in the polar code is specifically implemented as follows:
in the coding stage of the polarization code, firstly, the length N of the polarization code to be designed, the number k of information bits, the number m of parity check code bits and the number r of CRC (cyclic redundancy check) codes are selected, the reliable measurement value of each channel is calculated by utilizing a Gaussian approximation method, and a split channel position index value sequence is obtained after the reliable measurement value is sequenced from high to low
Figure BDA0003853483280000031
And selecting one of N polarized channelsThe good k + m + r channels transmit the non-frozen bit set A, and the remaining N-k-m-r channels transmit the frozen bit set A c Then through A and A c An R1 node and an SPC node are determined, wherein the R1 node is a sub-polar code block containing only information bits, and the SPC node is a sub-polar code block in which all bits are information bits except for the first bit which is a frozen bit. And then, the R1 and the SPC nodes are arranged in a descending order according to the node lengths, when the two node lengths are equal, the node with the low channel sequence number is arranged in the front, and finally, the first non-frozen bits of the R1 node and the SPC node after the ordering are sequentially added into the error set ES.
Then selecting k positions of PC codes and calculating the value of each PC bit as shown in formula (1) to complete PC code coding, and obtaining the coded sequence at the moment
Figure BDA0003853483280000032
Then to
Figure BDA0003853483280000033
CRC coding is carried out to obtain
Figure BDA0003853483280000034
Finally will be
Figure BDA0003853483280000035
The code word is obtained by carrying out polar code coding as the non-frozen bit set in the polar code
Figure BDA0003853483280000036
Figure BDA0003853483280000041
Wherein S i Representing the set of information bits in the middle of the i-1 st to ith PC bits.
At the receiving end, the value of the received signal is first converted into a Log Likelihood Ratio (LLR), as shown in equation (2).
Figure BDA0003853483280000042
Y in formula (2) i Representing the received signal value, σ, of each bit 2 Representing the variance of the channel noise. Each path then obtains a decision LLR for each bit by performing a corresponding f and g operation.
L≈sign(L 1 )sign(L 2 )min{|L 1 ||L 2 |} (3)
L＝(1-2U 1 )L 1 +L 2 (4)
Equation (3) represents f operation for easy hardware implementation, equation (4) represents g operation, where L represents LLR of operation output, L 1 ，L 2 LLR, U representing an input operation 1 Representing the decoded estimate of the previous bit of the input operation.
When the decoder decodes the PC bit, each decoding path obtains a decoding estimation value of the PC bit through the check function shown in the formula (1) according to the respective decoding result, the PM is updated according to the LLR at the moment according to the formula (5), when the decoder decodes other positions, SCL decoding is executed, and the path with the minimum PM is selected from the paths passing through the CRC check after the decoding is finished as the output result of the decoder.
Figure BDA0003853483280000043
Wherein
Figure BDA0003853483280000044
Represents the path metric value of the ith decoding path after decoding the ith bit,
Figure BDA0003853483280000045
indicating the decoded estimate of the ith bit in the ith decoding path,
Figure BDA0003853483280000046
representing decoding judgment of ith bit in ith decoding pathThe LLR of the block.
(2) The construction of the error set is explained with reference to fig. 2:
the polar code can be seen as consisting of a number of sub-polar code blocks, where the white leaf nodes represent the frozen bits, the black leaf nodes represent the information bits, and the grey nodes represent sub-blocks containing both the frozen bits and the information bits, where the sub-blocks { a, B, C, D, E } containing only the information bits are referred to as R1 nodes, the sub-blocks { F } containing only the first bit as the frozen bits and the remaining bits as all the information bits are referred to as SPC nodes. With non-frozen bit set A, frozen bit set A c Determining an R1 node and an SPC node in a polar code, then arranging the lengths of the R1 node and the SPC node in a descending order, when the lengths of the two nodes are equal, arranging the node with a low channel sequence number in the front, and finally sequentially adding the first non-frozen bits of the arranged R1 node and the arranged SPC node to an error set ES.
(3) The advantages of the proposed decoding method are demonstrated in conjunction with fig. 3,4, and 5, which are as follows:
the CA-SCL Decoding algorithm is a scheme proposed in the document [1] "Niu Kai, chen Kai. CRC-aid Decoding of Polar Codes [ J ]. IEEE Communications Letters,2012,16 (10): 1668-1671.";
the PSS-SS-SCL decoding Algorithm is a scheme proposed in the document [2] "Gao chenyu, liu Rongke, dai Bin, et al, path Splitting Selecting Stratagy-aid successful Cancellation List Algorithm for Polar Codes [ J ]. IEEE Communications Letters,2019,23 (3): 422-425.";
the PC-PSCL decoding algorithm is a scheme proposed by a document [3] "a low-complexity decoding algorithm [ J ] based on parity check code cascade polarization codes, the journal of electronics and informatics, 2022,44 (02): 637-645 ];
due to document [3]]Zhongpc-PSCL decoding algorithm and literature [2]]The PSS-SS-SCL decoding algorithm only partially performs path splitting on non-frozen bits during decoding, so that a document [2] is adopted on the basis of the ES-SCL decoding method provided by the invention]The search set carries out partial bit splitting decoding, namely, the decoder only carries out path splitting when decoding elements in the key set and decodes the ES-SCL (PS-ES-SCL for short) of partial splitting decodingMethods and documents [3]Middle PC-PSCL decoding algorithm and literature [2]]And carrying out comparative analysis on the PSS-SS-SCL decoding algorithm. Analyzing the decoding process of SCL can see that when the number of decoding paths is greater than the maximum decoding list number L, PM needs to be sorted, L paths with smaller PM are reserved, and because the number of paths grows exponentially, at the (1 + log) of decoding 2 L) non-frozen bits are required to be sequenced, and the sequencing work is almost the part with the highest complexity when each bit is decoded, so the invention describes the decoding complexity of each method by counting the sequencing times of decoding by each method on average. FIG. 3 shows the code length N =512 and the code rate
Figure BDA0003853483280000051
(k is the number of transmitted information bits) block error rate simulation results of each algorithm, and fig. 4 shows that the code length N =256 and the code rate
Figure BDA0003853483280000052
And (4) a simulation result graph of the block error rate of each algorithm. The other simulation parameters are set to be the same, namely the maximum decoding list number L =8, CA-SCL, and a PSS-SS-SCL decoding algorithm adopts 16-bit CRC check codes; the PC-PSCL, ES-SCL decoding algorithm and the ES-SCL decoding algorithm of partial splitting all adopt 8-bit PC codes and 8-bit CRC check codes, each algorithm adopts BPSK modulation, and the channel adopts an additive white Gaussian noise channel. Fig. 5 counts the sorting times of each method for averaging one decoding under different code lengths.
As can be seen from fig. 3 and 4, the block error rate of the ES-SCL decoding method proposed by the present invention is lower than that of other decoding algorithms, when BLER =10 -5 When N =512, the ES-SCL decoding method has about 0.15dB gain compared with the CA-SCL decoding algorithm, when BLER =10 -5 And when N =256, the ES-SCL coding method has about 0.3dB gain compared with the CA-SCL coding algorithm. And it can be seen from fig. 5 that the decoding complexity of the ES-SCL decoding method proposed herein is almost the same as that of the CA-SCL decoding algorithm, and since the calculation of the PC bit value only involves modulo two addition, the total decoding complexity is not greatly affected, and the ES-SCL decoding method only increases the average time complexity once to O (N + tlog) compared to the CA-SCL decoding algorithm 2 Error of t)Set construction step already (N is the length of the polar code, t represents the total number of R1 nodes and SPC nodes). It can also be seen from FIGS. 3-5 that the PS-ES-SCL decoding method has a block error rate similar to that of the document [3]]The block error rate of the PC-PSCL decoding algorithm in the method is almost consistent, but the required sorting times are reduced by 50%, and the decoding complexity is lower. And the PS-ES-SCL decoding method is compared with the literature [2]]The PSS-SS-SCL decoding algorithm in the method has lower block error rate under the condition of more or less sorting times, and further embodies the advantage of the invention in improving the error correction performance of the polar code.

Claims (1)

1. An improved ES-SCL (successful Cancellation List based on the Error Set, ES-SCL) decoding method in the polar code, which is characterized in that: aiming at the problem of insufficient Error correction performance of a polar code at medium and short code lengths, firstly, constructing an Error Set (ES) according to the channel characteristics of the polar code, setting Parity Check (PC) bits according to elements in the Error Set when the polar code is coded, placing information bits and freezing bits at other positions, obtaining bit estimation of the PC bits through a Check function by a decoder when the decoder decodes the PC bits, not executing path splitting and pruning, and executing Serial Cancellation List (SCL) decoding at other positions; the method specifically comprises the following steps:
the method comprises the following steps: selecting the length N of a polarization code to be designed, the number k of information bits, the number m of parity Check code bits and the number r of Cyclic Redundancy Check (CRC) codes, calculating a reliability measurement parameter of each split channel by using a Gaussian approximation method, sequencing all split channels according to the channel reliability from high to low to obtain a sequenced split channel position index value sequence
Figure FDA0003853483270000011
Step two: the first k + m + r split channels with the highest reliability are selected, i.e.
Figure FDA0003853483270000012
Splitting corresponding to middle and front k + m + r index valuesThe channel is used to transmit a set A of non-frozen bits, the remaining N-k-m-r split channels are used to transmit a set A of frozen bits (usually set to 0) c ；
Step three: with non-frozen bit set A, frozen bit set A c Determining a code Rate 1 (Rate-1, R1) node and a Single-Parity-Check (SPC) node, wherein the R1 node is a sub-polar code block only containing information bits, the SPC node is a sub-polar code block except the first bit which is a frozen bit, the rest bits are all information bits, then arranging the R1 and the SPC node in descending order according to the length of the nodes, when the lengths of the two nodes are equal, arranging the node with the low channel number in the front, and finally adding the first non-frozen bits of the ordered R1 node and the SPC node to an error set ES in sequence;
step four: selecting the first k elements in the error set ES as the positions for placing PC codes, and then aligning the information sequence
Figure FDA0003853483270000013
Segmenting and adding m-bit parity check codes to obtain a segmented sequence
Figure FDA0003853483270000014
Step five: to the sequence
Figure FDA0003853483270000015
Performing CRC coding on
Figure FDA0003853483270000016
Is used for checking all the previous bits to obtain a sequence
Figure FDA0003853483270000017
Step six: to the sequence
Figure FDA0003853483270000018
Performing polar code encoding to obtain a sequence
Figure FDA0003853483270000019
Inputting the non-frozen bits into a polar code encoder to carry out polar code encoding to obtain a polar code encoded code word
Figure FDA00038534832700000110
Then will be
Figure FDA00038534832700000111
Transmitting the data through an incoming channel;
step seven: decoding, a receiving end firstly converts a received signal into a log-Likelihood Ratio (LLR) during decoding, then calculates a decision LLR of each bit, if a current bit is a PC bit, each decoding Path obtains a decoding estimation value of the PC bit through check function calculation according to respective decoding results, and updates a Path Metric (PM) value according to the LLR at the moment, when a decoder decodes other positions, SCL decoding is executed, and a Path with the minimum PM is selected from paths passing through CRC check as an output result of the decoder after decoding is finished.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115987302A (en) * 2023-02-03 2023-04-18 中国传媒大学 Parity check supported dynamic serial offset list flip decoding method and system
CN117792407A (en) * 2024-02-23 2024-03-29 南京邮电大学 Hardware ordering system for decoding polarization code serial offset list

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115987302A (en) * 2023-02-03 2023-04-18 中国传媒大学 Parity check supported dynamic serial offset list flip decoding method and system
CN115987302B (en) * 2023-02-03 2023-11-21 中国传媒大学 Parity-check-supported dynamic serial cancellation list overturning decoding method and system
CN117792407A (en) * 2024-02-23 2024-03-29 南京邮电大学 Hardware ordering system for decoding polarization code serial offset list
CN117792407B (en) * 2024-02-23 2024-05-24 南京邮电大学 Hardware ordering system for decoding polarization code serial offset list

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