CN115469816A - Read-write switching method, device and equipment of memory and storage medium - Google Patents

Read-write switching method, device and equipment of memory and storage medium Download PDF

Info

Publication number
CN115469816A
CN115469816A CN202211359720.8A CN202211359720A CN115469816A CN 115469816 A CN115469816 A CN 115469816A CN 202211359720 A CN202211359720 A CN 202211359720A CN 115469816 A CN115469816 A CN 115469816A
Authority
CN
China
Prior art keywords
read
command buffer
command
write
write command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202211359720.8A
Other languages
Chinese (zh)
Other versions
CN115469816B (en
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Moore Threads Technology Co Ltd
Original Assignee
Moore Threads Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Moore Threads Technology Co Ltd filed Critical Moore Threads Technology Co Ltd
Priority to CN202211359720.8A priority Critical patent/CN115469816B/en
Publication of CN115469816A publication Critical patent/CN115469816A/en
Application granted granted Critical
Publication of CN115469816B publication Critical patent/CN115469816B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The application provides a read-write switching method, a device, equipment and a storage medium of a memory, wherein the method comprises the following steps: by detecting the first command message column in the read command buffer, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty. By adopting the technical scheme, the problem of long time consumption of a read-write conversion mode of the memory can be solved, so that the occupancy rate of the bandwidth is improved, and the command delay is reduced.

Description

Read-write switching method, device and equipment of memory and storage medium
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method, an apparatus, a device, and a storage medium for switching read and write of a memory.
Background
Extra conversion time is needed for the transition from read to write or from write to read of a DDR SDRAM (Double Data Rate SDRAM), which occupies DDR bandwidth, and meanwhile, systems such as CPU or GPU have different requirements for read and write latency.
However, the read-write conversion method of the current DDR is time-consuming, and further causes a large bandwidth loss.
Therefore, a method for switching between reading and writing of a memory is needed to solve the above problems.
Disclosure of Invention
The application provides a method, a device, equipment and a storage medium for switching read and write of a memory, which can solve the problem of time consumption of a read-write conversion mode of the memory and further improve the occupancy rate of bandwidth.
In a first aspect, the present application provides a method for switching read and write of a memory, applied to a scheduler, including:
detecting a first column of command messages in a read command buffer;
if there is at least one timeout maximum read latency sensitive command in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
In one optional example, the method further comprises:
detecting a second column of command messages in the write command buffer;
determining whether to execute the operation of switching from the read command buffer to the write command buffer according to the quantity of the write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In an optional example, determining whether to perform an operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column includes:
if the number of the write command messages in the second command message column exceeds a first threshold and the first command message column does not include the overtime maximum read delay sensitive command, executing the operation of switching from the read command buffer to the write command buffer;
if the number of write command messages in the second command message column does not exceed the first threshold, then no switching operation of the read command buffer needs to be performed.
In an optional example, if the number of the write command messages in the second command message column does not exceed the first threshold, after the switching operation on the read command buffer does not need to be performed, the method further includes:
if the first command message column is empty, the second command message column is not empty, and the condition that the read command buffer is switched to the write command buffer is met, executing the operation of switching from the read command buffer to the write command buffer;
and if the first command message column is not empty, the second command message column is empty or the condition for switching the read command buffer to the write command buffer is not met, the switching operation of the read command buffer is not required to be executed.
In an optional example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In one optional example, the method further comprises:
executing an operation of switching from a read command buffer to a write command buffer in case an alarm message sent by the write command buffer is received and the first command message queue does not include a maximum read delay sensitive command which is overtime; wherein the alarm message is used to instruct to execute the operation of switching from the read command buffer to the write command buffer.
In one optional example, the method further comprises:
executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
In an optional example, after the operation of switching from the read command buffer to the write command buffer is performed, the method further includes:
and if the second command message column is empty and the condition that the write command buffer is switched to the read command buffer is met, executing the operation of switching from the write command buffer to the read command buffer.
In an optional example, if the read command buffer is not empty, the scheduler stays in the write command buffer for more than a third preset time, and then switches to the read command buffer.
In a second aspect, the present application provides a read/write switching apparatus for a memory, applied to a scheduler, the apparatus including:
a first detection unit for detecting a first command message column in the read command buffer;
a first executing unit, configured to execute each of the maximum read delay sensitive commands that are overtime if at least one of the maximum read delay sensitive commands that are overtime exists in the first command message column until the maximum read delay sensitive command that is overtime is empty.
In an optional example, the apparatus further comprises:
a second detection unit for detecting a second command message column in the write command buffer;
a second execution unit, configured to determine whether to execute an operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In an optional example, the second execution unit includes:
a first determining module, configured to execute an operation of switching from the read command buffer to the write command buffer if the number of the write command messages in the second command message column exceeds a first threshold and the first command message column does not include a maximum read delay sensitive command that is overtime;
a second determining module, configured to not perform a switching operation on the read command buffer if the number of the write command messages in the second command message column does not exceed the first threshold.
In an optional example, after the second determining module, the method further includes:
a third determining module, configured to execute an operation of switching from the read command buffer to the write command buffer if the first command message column is empty, the second command message column is not empty, and a condition for switching from the read command buffer to the write command buffer is met;
a fourth determining module, configured to not perform a switching operation on the read command buffer if the first command message column is not empty, the second command message column is empty, or a condition for switching the read command buffer to the write command buffer is not satisfied.
In an optional example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In one optional example, the apparatus further comprises:
the sending module is used for executing the operation of switching from the read command buffer to the write command buffer under the condition that an alarm message sent by the write command buffer is received and the first command message queue does not comprise a maximum read delay sensitive command which is overtime; wherein the alarm message is used to instruct to execute the operation of switching from the read command buffer to the write command buffer.
In one optional example, the apparatus further comprises:
an execution module, configured to execute the write command messages in the write command buffer until a number of the write command messages is lower than a second threshold; wherein the first threshold is greater than the second threshold.
In an optional example, the apparatus further comprises:
a third executing unit, configured to execute an operation of switching from the write command buffer to the read command buffer if the second command message is empty and a condition for switching from the write command buffer to the read command buffer is satisfied.
In an optional example, the apparatus further comprises:
and the fourth execution unit is used for switching to the read command buffer if the read command buffer is not empty and the time of the scheduler staying in the write command buffer exceeds a third preset time.
In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer execution instructions;
the processor executes computer-executable instructions stored by the memory to implement the method of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium having stored thereon computer-executable instructions for implementing the method according to the first aspect when executed by a processor.
In a fifth aspect, the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the method according to the first aspect.
According to the read-write switching method, device, equipment and storage medium of the memory, by detecting a first command message column in a read command buffer, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty. By adopting the technical scheme, the problem of long time consumption of a read-write conversion mode of the memory can be solved, so that the occupancy rate of the bandwidth is improved, and the command delay is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic diagram of a framework of a read/write switching method for a memory according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a read/write switching method of a memory according to a second embodiment of the present application;
fig. 3 is a schematic flowchart of a read/write switching method for a memory according to a third embodiment of the present application;
FIG. 4 is a schematic diagram of a read command buffer and a schematic diagram of a write command buffer according to a third embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a read/write switching method for a memory according to a fourth embodiment of the present application;
fig. 6 is a schematic diagram of a read/write switching device of a memory according to a fifth embodiment of the present application;
fig. 7 is a schematic diagram of a read/write switching device of a memory according to a sixth embodiment of the present application;
FIG. 8 is a block diagram of an electronic device shown in accordance with an example embodiment.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The application provides a read-write switching method of a memory, which aims to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a frame of a read/write switching method for a memory according to an embodiment of the present application, in which a plurality of master controllers issue a plurality of read command messages and a plurality of write command messages to a scheduler, and the scheduler issues the read command messages and the write command messages to a DDR SDRAM (Double Data Rate SDRAM). The scheduler includes two storage structures, which are a Read Command Buffer (RCB) and a Write Command Buffer (WCB).
Fig. 2 is a schematic flowchart of a read/write switching method for a memory according to a second embodiment of the present application, where the method is applied to a scheduler, and the second embodiment includes the following steps:
s201, detecting a first command message column in the read command buffer.
In one example, the first command message column includes a plurality of read command messages to be read and at least one maximum read latency sensitive command that times out, and further, the read command messages include a maximum latency sensitive command and a general read command message.
The maximum read latency sensitive command is generated after the maximum latency sensitive command has reached an upper limit of time that must be processed. Specifically, each maximum delay sensitive command stores a timer, the timer can time the maximum delay sensitive command, and when the maximum delay sensitive command exceeds a preset time, the maximum delay sensitive command is changed into an overtime maximum read delay sensitive command. The preset time can be set according to needs, and the set preset time can be smaller than the delay time which can be actually accepted by the command.
The maximum read delay sensitive command is the highest priority, and when the maximum read delay sensitive command exists, the maximum read delay sensitive command must be switched to the read command buffer to process the maximum read delay sensitive command in the read command buffer, so that the delay of the maximum read delay sensitive command is ensured to be controllable.
S202, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
If the first command message column is not empty, it indicates that the first command message column includes a plurality of read command messages, or further includes a maximum read delay sensitive command that is overtime.
In this embodiment, if at least one overtime maximum read delay sensitive command exists in the first command message column, each overtime maximum read delay sensitive command is preferentially executed until all the overtime maximum read delay sensitive commands are empty.
According to the read-write switching method of the memory, by detecting the first command message column in the read command buffer, if the overtime maximum read delay sensitive command exists in the first command message column, the overtime maximum read delay sensitive command is processed preferentially, and all the overtime maximum read delay sensitive commands are processed completely. By adopting the technical scheme, all the maximum read delay sensitive commands which need to be processed urgently can be processed preferentially, and the first priority of the read command buffer is further realized.
Fig. 3 is a schematic flowchart of a read/write switching method for a memory according to a third embodiment of the present application, where the method is applied to a scheduler, and the third embodiment includes the following steps:
s301, detecting a first command message column in the read command buffer.
For example, this step may refer to step S201 described above, and is not described again.
S302, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
For example, this step may refer to step S202, which is not described again.
S303, detecting a second command message column in the write command buffer.
In one example, a second command message column is stored in the write command buffer. Specifically, a schematic diagram of a read command buffer and a schematic diagram of a write command buffer may be seen in fig. 4, and as can be seen from fig. 4, the read command buffer includes a plurality of read command messages and a maximum read delay sensitive command that is timed out. The write command buffer includes a plurality of write command messages.
S304, determining whether to execute the operation of switching from the read command buffer to the write command buffer according to the number of the write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In this embodiment, the number of write command messages in the second command message column is obtained, and if the number meets a preset requirement, the read command buffer is switched to the write command buffer, and the read command message is processed to the write command message.
According to the read-write switching method of the memory, by detecting a first command message column in a read command buffer, if the first command message column has a maximum overtime read delay sensitive command, processing the maximum overtime read delay sensitive command preferentially, and after all the maximum overtime read delay sensitive commands are processed, detecting a second command message column in a write command buffer, and according to the number of write command messages in the second command message column, switching the read command buffer to the write command buffer, and executing the write command messages in the write command buffer. By adopting the technical scheme, the read delay can be reduced as much as possible on the premise that the write command message is not blocked, and the delay is controllable to the maximum extent by using the read command message which is very sensitive to the delay.
Fig. 5 is a schematic flowchart of a read/write switching method for a memory according to a fourth embodiment of the present application, where the method is applied to a scheduler, and the fourth embodiment includes the following steps:
s501, detecting a first command message column in the read command buffer.
For example, this step may refer to step S201 described above, and is not described again.
S502, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
For example, this step may refer to step S202, which is not described again.
S503, detecting a second command message column in the write command buffer.
For example, this step may refer to step S303 described above, and is not described again.
S504, if the number of the write command messages in the second command message column exceeds a first threshold and the first command message column does not include the overtime maximum read delay sensitive command, the operation of switching from the read command buffer to the write command buffer is executed.
In this embodiment, the first threshold is the upper limit value of the write command messages set in the write command buffer, and if the first threshold is exceeded, it indicates that the number of write command messages in the second command message column is too large, and the scheduler needs to process the write command messages in the write command buffer, so that the read command buffer needs to be switched to the write command buffer. In the present embodiment, the exceeding means greater than or equal to.
In one optional example, the method further comprises:
executing an operation of switching from a read command buffer to a write command buffer when an alarm message sent by the write command buffer is received and the first command message queue does not include a maximum read delay sensitive command which is overtime; wherein the alarm message is used to instruct to execute the operation of switching from the read command buffer to the write command buffer.
In this embodiment, when the number of write command messages in the write command buffer exceeds the first threshold, an alarm message is issued to prompt the scheduler to process the write command messages in the write command buffer.
In one optional example, the method further comprises:
executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
In this embodiment, the second threshold is a lower limit value of the write command messages in the second command message column, and if the second threshold is lower than the second threshold, it indicates that the second command message column already has a certain redundancy for the newly issued write command message, and the alarm message is released after the number of the write command messages is lower than the second threshold.
And S505, if the number of the write command messages in the second command message column does not exceed the first threshold, the switching operation of the read command buffer does not need to be executed.
In this embodiment, if the second command message column is empty, it indicates that no write command message needs to be processed in the write command buffer, and if the number of write command messages in the second command message column does not exceed the first threshold, it indicates that the write command buffer further has a storage space available for the write command message to be issued.
S506, if the first command message sequence is empty, the second command message sequence is not empty, and the condition that the read command buffer is switched to the write command buffer is met, the operation that the read command buffer is switched to the write command buffer is executed.
In this embodiment, if the first command message column is empty, it indicates that no read command message needs to be processed in the read command buffer, and if the second command message column is not empty, it indicates that a write command message needs to be processed in the write command buffer, at this time, if a condition for switching from the read command buffer to the write command buffer is satisfied, the read command buffer may be switched to the write command buffer, and then the write command message in the write command buffer is processed.
S507, if the first command message column is not empty, the second command message column is empty or the condition for switching the read command buffer to the write command buffer is not satisfied, the switching operation of the read command buffer is not required to be executed.
In this embodiment, there may be several cases without performing the switching operation on the read command buffer:
the first case is that the first command message column is not empty;
in the second case, the second command message column is empty;
the third condition is that the condition for switching the read command buffer to the write command buffer is not satisfied;
the fourth case is that the first command message column is not empty and the second command message column is empty;
the fifth case is that the first command message column is not empty and does not satisfy the operation of switching from the read command buffer to the write command buffer;
the sixth case is that the second command message is listed as empty and does not satisfy the operation of switching the read command buffer to the write command buffer;
the seventh case is that the first command message column is not empty, the second command message column is empty, and the condition for switching from the read command buffer to the write command buffer is not satisfied.
In an alternative example, the condition for switching the read command buffer to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In this embodiment, the first preset time is a time for switching the read command buffer to the write command buffer, which is preset by a user, and a specific first preset time may be represented by an identifier t _ r2w _ delay. Wherein, the value of the first preset time is not 0 value.
In an optional example, if the read command buffer is not empty, the scheduler stays in the write command buffer for more than a third preset time, and then switches to the read command buffer.
In this embodiment, when the read command buffer is not empty, the controller does not switch to the read command buffer, that is, the scheduler stays in the write command buffer for a time period exceeding a third preset time period, and then the scheduler is forced to switch to the read command buffer.
In this embodiment, a timer is configured in the read command buffer, and may calculate the unprocessed time of the scheduler in the read command buffer, and if the staying time of the scheduler in the write command buffer exceeds a third preset time, the scheduler is forced to move to the read command buffer. Wherein the value of the unprocessed time in the read command buffer is equal to the value of the third preset time.
In an optional example, after performing the operation of switching from the read command buffer to the write command buffer, the method further includes:
if the second command message queue is empty and the condition for switching from the write command buffer to the read command buffer is satisfied, the operation for switching from the write command buffer to the read command buffer is performed.
In one example, if the second command message is listed as empty and the condition for switching the write command buffer to the read command buffer is satisfied, it is stated that the write command message in the write command buffer has not been processed, and therefore, the write command buffer may be switched to the read command buffer at this time. And switching the write command buffer to the read command buffer on the condition that the dwell time in the write command buffer exceeds a second preset time. Wherein, the second preset time may be represented by an identifier t _ w2r _ delay. The specific value of the second preset time may be 0.
According to the read-write switching method of the memory, the read command buffer and the write command buffer can be free from the influence of the sequence of the input read-write command message by setting the switching condition between the read command buffer and the write command buffer, the read command message and the write command message are selected and executed in a self-adaptive manner, the read-write conversion times are greatly reduced, and the bandwidth utilization rate is improved.
Fig. 6 is a schematic diagram of a read/write switching device of a memory according to a fifth embodiment of the present application, where the device 60 in the fifth embodiment includes:
the first detection unit 601 is configured to detect a first command message column in the read command buffer.
If at least one overtime maximum read delay sensitive command exists in the first command message column, the first execution unit 602 executes each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Fig. 7 is a schematic diagram of a read/write switching apparatus for a memory according to a sixth embodiment of the present application, where an apparatus 70 in the sixth embodiment includes:
a first detection unit 701 for detecting a first command message column in the read command buffer;
a first executing unit 702, configured to execute each of the maximum read latency sensitive commands that are overtime if at least one maximum read latency sensitive command that is overtime exists in the first command message column until the maximum read latency sensitive command that is overtime is empty.
In an optional example, the apparatus further comprises:
a second detection unit 703 for detecting a second command message column in the write command buffer;
a second execution unit 704, configured to determine whether to execute an operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In an optional example, the second execution unit 704 includes:
a first determining module 7041, configured to execute an operation of switching from the read command buffer to the write command buffer if the number of the write command messages in the second command message row exceeds a first threshold and the first command message row does not include a maximum read delay sensitive command that is overtime;
a second determining module 7042, configured to not perform a switching operation on the read command buffer if the number of the write command messages in the second command message queue does not exceed the first threshold.
In an optional example, after the second determining module 7042, the method further comprises:
a third determining module 7043, configured to execute an operation of switching from the read command buffer to the write command buffer if the first command message column is empty, the second command message column is not empty, and a condition that the read command buffer is switched to the write command buffer is met;
a fourth determining module 7044, configured to not perform the switching operation on the read command buffer if the first command message column is not empty, the second command message column is empty, or a condition for switching the read command buffer to the write command buffer is not met.
In an optional example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In one optional example, the apparatus further comprises:
an issuing module 7045, configured to, when an alarm message issued by a write command buffer is received and the first command message queue does not include a maximum read delay sensitive command that is overtime, execute an operation of switching from the read command buffer to the write command buffer; wherein the alarm message is used for indicating to execute the operation of switching from the read command buffer to the write command buffer.
In one optional example, the apparatus further comprises:
an executing module 7046, configured to execute the write command messages in the write command buffer until the number of write command messages is lower than a second threshold; wherein the first threshold is greater than the second threshold.
In an optional example, the apparatus further comprises:
a third executing unit 705, configured to execute an operation of switching from the write command buffer to the read command buffer if the second command message is empty and a condition for switching from the write command buffer to the read command buffer is met.
In an optional example, the apparatus further comprises:
a fourth executing unit 706, configured to switch to the read command buffer if the read command buffer is not empty and the time that the scheduler stays in the write command buffer exceeds a third preset time.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
FIG. 8 is a block diagram illustrating an electronic device, which may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like, in accordance with one exemplary embodiment.
The apparatus 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input/output (I/O) interface 812, a sensor component 814, and a communication component 816.
The processing component 802 generally controls overall operation of the device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operations at the apparatus 800. Examples of such data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
Power components 806 provide power to the various components of device 800. The power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the apparatus 800.
The multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the device 800 is in an operating mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 810 is configured to output and/or input audio signals. For example, audio component 810 includes a Microphone (MIC) configured to receive external audio signals when apparatus 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the device 800. For example, the sensor assembly 814 may detect the open/closed status of the device 800, the relative positioning of components, such as a display and keypad of the device 800, the sensor assembly 814 may also detect a change in the position of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration/deceleration of the device 800, and a change in the temperature of the device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 816 is configured to facilitate communications between the apparatus 800 and other devices in a wired or wireless manner. The device 800 may access a wireless network based on a communication standard, such as WiFi,2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the apparatus 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic components for performing the above-described methods.
In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as the memory 804 comprising instructions, executable by the processor 820 of the device 800 to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer-readable storage medium, wherein instructions of the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform a read-write switching method of a memory of the electronic device.
The application also discloses a computer program product comprising a computer program which, when executed by a processor, performs the method as described in the embodiments.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or electronic device.
In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data electronic device), or that includes a middleware component (e.g., an application electronic device), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.
The computer system may include a client and an electronic device. The client and the electronic device are generally remote from each other and typically interact through a communication network. The relationship of client and electronic device arises by virtue of computer programs running on the respective computers and having a client-electronic device relationship to each other. The electronic device may be a cloud electronic device, which is also called a cloud computing electronic device or a cloud host, and is a host product in a cloud computing service system, so as to solve the defects of high management difficulty and weak service extensibility in a traditional physical host and a VPS service ("Virtual Private Server", or "VPS" for short). The electronic device may also be a distributed system of electronic devices or an electronic device incorporating a blockchain. It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present application may be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present application can be achieved, and the present invention is not limited herein.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (13)

1. A method for switching read and write of a memory is applied to a scheduler, and the method comprises the following steps:
detecting a first column of command messages in a read command buffer;
if at least one overtime maximum reading delay sensitive command exists in the first command message column, executing each overtime maximum reading delay sensitive command until the overtime maximum reading delay sensitive command is empty.
2. The method of claim 1, further comprising:
detecting a second command message column in the write command buffer;
determining whether to execute the operation of switching from the read command buffer to the write command buffer according to the quantity of the write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
3. The method of claim 2, wherein determining whether to perform the operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column comprises:
if the number of the write command messages in the second command message column exceeds a first threshold and the first command message column does not include the overtime maximum read delay sensitive command, executing the operation of switching from the read command buffer to the write command buffer;
if the number of write command messages in the second command message column does not exceed the first threshold, then no switching operation of the read command buffer needs to be performed.
4. The method of claim 3, wherein if the number of write command messages in the second command message column does not exceed the first threshold, after performing the switch operation on the read command buffer, the method further comprises:
if the first command message column is empty, the second command message column is not empty, and the condition that the read command buffer is switched to the write command buffer is met, executing the operation of switching from the read command buffer to the write command buffer;
and if the first command message column is not empty, the second command message column is empty or the condition for switching the read command buffer to the write command buffer is not met, the switching operation of the read command buffer is not required to be executed.
5. The method of claim 4, wherein the condition for the read command buffer to switch to the write command buffer comprises: the dwell time in the read command buffer exceeds a first preset time.
6. The method of claim 1, further comprising:
executing an operation of switching from a read command buffer to a write command buffer in case an alarm message sent by the write command buffer is received and the first command message queue does not include a maximum read delay sensitive command which is overtime; wherein the alarm message is used to instruct to execute the operation of switching from the read command buffer to the write command buffer.
7. The method of claim 3, further comprising:
executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
8. The method of any of claims 2-4, wherein after performing the operation of switching from the read command buffer to the write command buffer, further comprising:
and if the second command message column is empty and the condition that the write command buffer is switched to the read command buffer is met, executing the operation of switching from the write command buffer to the read command buffer.
9. The method of claim 1, further comprising:
and if the read command buffer is not empty, the time that the scheduler stays in the write command buffer exceeds a third preset time, and the read command buffer is switched to.
10. A read/write switching device for a memory, applied to a scheduler, the device comprising:
a first detection unit for detecting a first command message column in the read command buffer;
a first executing unit, configured to execute each of the maximum read delay sensitive commands that are overtime if at least one of the maximum read delay sensitive commands that are overtime exists in the first command message column until the maximum read delay sensitive command that is overtime is empty.
11. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored by the memory to implement the method of any of claims 1-9.
12. A computer-readable storage medium having computer-executable instructions stored therein, which when executed by a processor, are configured to implement the method of any one of claims 1-9.
13. A computer program product, comprising a computer program which, when executed by a processor, implements the method of any one of claims 1-9.
CN202211359720.8A 2022-11-02 2022-11-02 Method, device, equipment and storage medium for switching reading and writing of memory Active CN115469816B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211359720.8A CN115469816B (en) 2022-11-02 2022-11-02 Method, device, equipment and storage medium for switching reading and writing of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211359720.8A CN115469816B (en) 2022-11-02 2022-11-02 Method, device, equipment and storage medium for switching reading and writing of memory

Publications (2)

Publication Number Publication Date
CN115469816A true CN115469816A (en) 2022-12-13
CN115469816B CN115469816B (en) 2024-01-30

Family

ID=84336327

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211359720.8A Active CN115469816B (en) 2022-11-02 2022-11-02 Method, device, equipment and storage medium for switching reading and writing of memory

Country Status (1)

Country Link
CN (1) CN115469816B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115934002A (en) * 2023-03-08 2023-04-07 阿里巴巴（中国）有限公司 Solid state disk access method, solid state disk, storage system and cloud server

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101694610A (en) * 2009-10-16 2010-04-14 成都市华为赛门铁克科技有限公司 Command processing method, device and memory device
WO2020077495A1 (en) * 2018-10-15 2020-04-23 华为技术有限公司 Command scheduling method and device and storage medium
CN112578999A (en) * 2019-09-27 2021-03-30 英特尔公司 Dynamic change between read operations devoted to latency and read operations devoted to bandwidth
WO2022155970A1 (en) * 2021-01-25 2022-07-28 华为技术有限公司 Memory control method and memory control apparatus
CN114844844A (en) * 2022-04-25 2022-08-02 平安普惠企业管理有限公司 Delay message processing method, device, equipment and storage medium

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101694610A (en) * 2009-10-16 2010-04-14 成都市华为赛门铁克科技有限公司 Command processing method, device and memory device
WO2020077495A1 (en) * 2018-10-15 2020-04-23 华为技术有限公司 Command scheduling method and device and storage medium
CN112578999A (en) * 2019-09-27 2021-03-30 英特尔公司 Dynamic change between read operations devoted to latency and read operations devoted to bandwidth
WO2022155970A1 (en) * 2021-01-25 2022-07-28 华为技术有限公司 Memory control method and memory control apparatus
CN114844844A (en) * 2022-04-25 2022-08-02 平安普惠企业管理有限公司 Delay message processing method, device, equipment and storage medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115934002A (en) * 2023-03-08 2023-04-07 阿里巴巴（中国）有限公司 Solid state disk access method, solid state disk, storage system and cloud server
CN115934002B (en) * 2023-03-08 2023-08-04 阿里巴巴（中国）有限公司 Solid state disk access method, solid state disk, storage system and cloud server

Also Published As

Publication number Publication date
CN115469816B (en) 2024-01-30

Similar Documents

Publication Publication Date Title
EP3382520B1 (en) Method and apparatus for operating a display of a mobile terminal
EP2993584B1 (en) Method and device for controlling background application
US20170322709A1 (en) Split-screen display method, apparatus and medium
EP3046016A1 (en) Method and apparatus for switching display mode
EP2677415A2 (en) Terminal and Method of Operating the Terminal
EP3382527A1 (en) Method and apparatus for managing a shared storage system
EP3015983A1 (en) Method and device for optimizing memory
EP3828832B1 (en) Display control method, display control device and computer-readable storage medium
EP3249505A1 (en) Method and device for controlling state of touch screen, electronic device
CN105511777B (en) Session display method and device on touch display screen
EP3232325B1 (en) Method and device for starting application interface
CN108829475B (en) UI drawing method, device and storage medium
EP3236355A1 (en) Method and apparatus for managing task of instant messaging application
US9678868B2 (en) Method and device for optimizing memory
CN115469816B (en) Method, device, equipment and storage medium for switching reading and writing of memory
CN109547782B (en) MPM candidate list construction method and device, electronic equipment and storage medium
CN108874450B (en) Method and device for waking up voice assistant
CN110968523A (en) Memory defragmentation method and device
EP4134793A1 (en) Method and apparatus for controlling input function, and storage medium
CN111722919B (en) Method and device for running background application program, storage medium and electronic equipment
CN112988105A (en) Playing state control method and device, electronic equipment and storage medium
US10572308B2 (en) Method and apparatus for monitoring virtual document object model
CN111124099A (en) State control method, device and storage medium
CN115348478B (en) Equipment interactive display method and device, electronic equipment and readable storage medium
EP4361785A1 (en) Screen split control method and apparatus, and storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant