CN115460145A - Forwarding rule issuing method, intelligent network card and storage medium - Google Patents
Forwarding rule issuing method, intelligent network card and storage medium Download PDFInfo
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Abstract
The embodiment of the application provides a forwarding rule issuing method, an intelligent network card and a storage medium, wherein the method comprises the following steps: generating a forwarding rule of the message; loading the forwarding rule in an information structure of the message; generating a message carrying the forwarding rule according to an information structure bearing the forwarding rule; and sending the generated message by using a data channel. The embodiment of the application utilizes a data channel between the on-chip processor and the hardware acceleration engine to issue the forwarding rule; and the forwarding rule is carried in the information structure of the message, so that the forwarding rule and the message can be synchronously issued to the hardware acceleration engine, and the issuing performance and reliability of issuing the forwarding rule can be improved.
Description
Technical Field
The embodiment of the application relates to the technical field of cloud computing, in particular to a forwarding rule issuing method, an intelligent network card and a storage medium.
Background
With the development of cloud computing and virtualization technologies, in order to cope with the increasing network bandwidth and realize the support of the virtualization function at a lower cost, the virtualization function such as network virtualization can be offloaded (offload) to the smart network card. For example, a Virtual switch (Vswitch) running on the host may be offloaded onto a smart network card to enable high-performance forwarding of messages. The offloading referred to herein may be understood as a process of offloading software functions to hardware for implementation by hardware.
In the virtualization technology, a virtual switch may be used to be responsible for packet forwarding of a virtual machine. For example, sending and receiving messages by the virtual machines may be implemented by the virtual switches based on forwarding rules. One of the key technologies for offloading the virtual switch to the intelligent network card is to issue the forwarding rule of the virtual switch to the hardware part of the intelligent network card, so that the intelligent network card can accelerate the hardware for forwarding the message. Under this background, how to improve the issuing performance and reliability of the forwarding rule issued to the intelligent network card becomes a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of this, embodiments of the present application provide a forwarding rule issuing method, an intelligent network card, and a storage medium, so as to improve issuing performance and reliability of issuing a forwarding rule to an intelligent network card.
In order to achieve the above object, the embodiments of the present application provide the following technical solutions.
In a first aspect, an embodiment of the present application provides a forwarding rule issuing method, including:
generating a forwarding rule of the message;
loading the forwarding rule in an information structure of the message;
generating a message carrying the forwarding rule according to an information structure bearing the forwarding rule;
and sending the generated message by using a data channel.
In a second aspect, an embodiment of the present application provides a method for issuing a forwarding rule, including:
acquiring a transmitted message by using a data channel; the message carries the forwarding rule of the message;
analyzing the information structure of the message to determine the forwarding rule carried in the message; wherein, the forwarding rule is carried in the information structure of the message;
and recording the forwarding rule of the message.
In a third aspect, an embodiment of the present application provides an intelligent network card, including: an on-chip processor and a hardware acceleration engine; the on-chip processor is configured to execute the forwarding rule issuing method according to the first aspect; the hardware acceleration engine is configured to execute the forwarding rule issuing method according to the second aspect.
In a fourth aspect, an embodiment of the present application provides a storage medium, where the storage medium stores one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the forwarding rule issuing method according to the first aspect described above is implemented, or the forwarding rule issuing method according to the second aspect described above is implemented.
In the forwarding rule issuing method provided by the embodiment of the application, the on-chip processor can generate the forwarding rule of the message and bear the generated forwarding rule in the information structure of the message; therefore, the on-chip processor can generate a message according to the information structure bearing the forwarding rule, so that the generated message carries the forwarding rule of the message; furthermore, the on-chip processor can issue the generated message by using a data channel for data message transmission with the hardware acceleration engine, so that the hardware acceleration engine can obtain a message carrying a forwarding rule through the data channel, and the on-chip processor can issue the forwarding rule of the message to the hardware acceleration engine.
When the data channel is used for sending the message to the hardware acceleration engine, the forwarding rule can be synchronously carried in the message, so that the forwarding rule can be sent through the data channel, and the sending performance of the forwarding rule sent through the data channel is equal to the sending performance of the on-chip processor and the hardware acceleration engine on the data message level, and the sending performance of the on-chip processor and the hardware acceleration engine on the data message level is far greater than the sending performance of configuration information and commands of the configuration channel, so that the sending performance of the forwarding rule can be greatly improved; meanwhile, the forwarding rule is issued along with the message, so that the issuing of the forwarding rule belongs to a synchronous event, the problem of reliability caused by asynchronous issuing of the forwarding rule can be solved, the issuing mode of the forwarding rule can meet the requirements of service scenes such as network short link and the like, and the issuing reliability of the forwarding rule is improved. Therefore, the embodiment of the application utilizes the data channel between the on-chip processor and the hardware acceleration engine to issue the forwarding rule; and the forwarding rule is carried in the information structure of the message, so that the forwarding rule and the message can be synchronously issued to the hardware acceleration engine, and the issuing performance and reliability of issuing the forwarding rule can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a diagram showing an example of a system configuration having a virtual switch.
Fig. 2A is a diagram illustrating an exemplary structure of the intelligent network card.
Fig. 2B is another exemplary diagram of the structure of the intelligent network card.
Fig. 3 is a diagram illustrating a forwarding rule issuing scenario.
Fig. 4 is a flowchart of a forwarding rule issuing method provided in an embodiment of the present application.
Fig. 5 is another flowchart of a forwarding rule issuing method according to an embodiment of the present application.
Fig. 6 is a diagram showing a structure example of the flow table.
Fig. 7 is an exemplary diagram of an information structure of a message.
Fig. 8 is a diagram illustrating a process example of issuing a forwarding rule according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a diagram illustrating an exemplary structure of a system with a virtual switch, and as shown in fig. 1, the system may include a plurality of virtual machines 101 to 10n (n is the number of virtual machines, which may be determined according to actual situations) and a virtual switch 110. The message transceiving of the plurality of virtual machines 101 to 10n can be realized by the virtual switch 110; for example, the virtual switch may forward the message of the virtual machine to the destination port based on the forwarding rule; the virtual switch may forward the message received by the host to the virtual machine based on the forwarding rule.
The virtual switch 110 is originally running on a host. For example, a processor (e.g., CPU) of the host may virtualize a plurality of virtual machines 101 to 10n by a virtualization technique, and implement the virtual switch 110 by a software function; thus, the virtual switch 110 may be responsible for the messaging of multiple virtual machines 101 to 10 n.
With the continuous development of cloud computing and network technologies, the requirements of users on network performance are higher and higher, and the message forwarding performance of a virtual switch running on a host cannot meet the performance requirements; to achieve high performance forwarding of the message, the virtual switch 110 running on the host can be offloaded onto the smart card 120 to achieve high performance forwarding of the message.
Besides the network transmission function of the standard network card, the intelligent network card can also improve the application performance and greatly reduce the consumption of a processor (such as a CPU) in communication through a built-in programmable and configurable hardware acceleration engine. When the virtual switch is offloaded to the intelligent network card, the intelligent network card can be understood as a network card which completes the message forwarding operation of the virtual switch by using hardware and has an on-chip processor (such as an on-chip CPU). Fig. 2A is a diagram illustrating an example structure of an intelligent network card, which may include an on-chip processor 210 and a hardware acceleration engine 220, as shown in fig. 2A.
The on-chip processor 210 may be understood to be a processor (e.g., a CPU) of an intelligent network card and part of an operating system. Under the condition that virtualization functions such as network virtualization are offloaded to the intelligent network card, the on-chip processor 210 may be responsible for functions such as network management and configuration that originally run on the host; in addition, the on-chip processor 210 may also be responsible for processing traffic that does not require high performance. When the virtual switch is unloaded onto the intelligent network card, the process of the virtual switch can run on an on-chip processor of the intelligent network card, and the message forwarding work and configuration management of the virtual switch can be realized through a processor core of the on-chip processor; as further shown in fig. 2A, the processor core of the on-chip processor 210 may include at least one data core 211 and at least one control core 212, where the data core 211 is responsible for packet forwarding work of the virtual switch, and the control core 212 is responsible for configuration management work of the virtual switch.
The hardware acceleration engine 220 is a hardware component of the intelligent network card, and the hardware acceleration engine 220 has higher performance than the on-chip processor 210, but has lower flexibility, and can be used for processing high-performance services. In one example, the hardware acceleration engine 220 may include a hardware processing device such as an NP (Network Processor), an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit). When the virtual switch is unloaded onto the intelligent network card, the hardware acceleration engine 220 (e.g., a hardware processing device such as an FPGA, an ASIC, etc.) of the intelligent network card may set the forwarding rule table 221, and the forwarding rule table 221 may be used to record the forwarding rule of the packet, so that the packet is accelerated and forwarded on a hardware layer, and the forwarding performance of the packet is improved.
One packet forwarding method based on the forwarding rule table 221 may be: when the intelligent network card obtains a message, the hardware acceleration engine 220 in the intelligent network card can inquire whether a forwarding rule matched with the message is recorded in the forwarding rule table 221; if yes, forwarding the message according to the recorded forwarding rule; if not, the message is transmitted to the on-chip processor 210 of the intelligent network card. After obtaining the message transmitted by the hardware acceleration engine 220 (corresponding to the case that the forwarding rule table 221 does not record the forwarding rule of the message), the on-chip processor 210 may query multiple forwarding configuration information of the virtual switch, thereby generating the forwarding rule of the message; further, the on-chip processor 210 may issue the generated forwarding rule to the hardware acceleration engine 220, and the hardware acceleration engine 220 records the forwarding rule in the forwarding rule table 221, so as to implement that the forwarding rule of the virtual switch is issued to the hardware portion of the intelligent network card. Subsequently, when the message hits the forwarding rule table (that is, the forwarding rule table records the forwarding rule of the message), the hardware acceleration engine 220 may forward the message according to the forwarding rule hit in the forwarding rule table, without transmitting the message to the on-chip processor 210, thereby accelerating the forwarding of the message in a hardware manner and improving the forwarding performance of the message.
It can be seen that, when a message does not match a forwarding rule in a hardware acceleration engine (for example, a forwarding rule table of the hardware acceleration engine, a forwarding rule of the message is not recorded), the on-chip processor needs to generate the forwarding rule and issue the forwarding rule to the hardware acceleration engine, so that the hardware acceleration engine records the forwarding rule of the message (for example, records the forwarding rule of the message in the forwarding rule table). The process relates to the process that the on-chip processor issues the forwarding rule to the hardware acceleration engine; that is, the process of issuing the forwarding rule of the virtual switch to the hardware part of the intelligent network card in the embodiment of the present application.
After the on-chip processor generates the forwarding rule, one way of issuing the forwarding rule to the hardware acceleration engine may be: and transmitting the forwarding rule generated by the on-chip processor to the hardware acceleration engine by using a configuration channel between the on-chip processor and the hardware acceleration engine. For ease of understanding, fig. 2B schematically illustrates another exemplary structure diagram of the smart network card, and as shown in fig. 2A and fig. 2B, a configuration channel 231 and a data channel 232 exist between the on-chip processor 210 and the hardware acceleration engine 220. Wherein, the configuration channel 231 is used for configuration management between the on-chip processor 210 and the hardware acceleration engine 220; for example, software running on the on-chip processor 210 may issue various configuration commands and information to the hardware of the hardware acceleration engine 220 via the configuration channel 231. The data channel 232 is used for data, message transmission between the on-chip processor 210 and the hardware acceleration engine 220.
Based on the attribute of the configuration channel 231 for transmitting the configuration command and information, the forwarding rule as the configuration information may be issued to the hardware acceleration engine 220 by the on-chip processor 210 through the configuration channel 231, so that the forwarding rule of the virtual switch may be issued to the hardware portion of the intelligent network card. For example, in the on-chip processor, the control core or the data core of the virtual switch may generate a forwarding rule, and then, through the configuration channel, the forwarding rule is issued to the hardware acceleration engine of the intelligent network card.
However, in the research process, the inventors of the present application find that the way in which the on-chip processor issues the forwarding rule to the hardware acceleration engine by using the configuration channel has at least the following problems:
the transmission rate of the configuration channel is low, so that the issuing performance of the forwarding rule is low; for example, the transmission rate of the configuration channel is generally 1 million per second, and when facing a service scenario of network short link such as CPS (Cyber Physical Systems ), the lower transmission rate of the configuration channel cannot meet the issuing requirement of the forwarding rule, and may also cause a large number of forwarding rules to have the possibility of issuing failure; for example, in a service scenario of a network short link, a forwarding rule needs to be recorded in a short time at a hardware level of an intelligent network card, and a low transmission rate of a configuration channel cannot meet the requirement, which may cause a large number of forwarding rules to be failed to be issued;
the configuration channel issues the forwarding rule in an asynchronous manner, for example, when the configuration channel is used for issuing the forwarding rule, the forwarding rule is stored in a shared memory space shared with the hardware acceleration engine, which requires the hardware acceleration engine to acquire the forwarding rule one by one from the shared memory space and record the forwarding rule into a forwarding rule table; in the above asynchronous forwarding rule issuing manner, when a service scenario of a short link of a network is faced, the short link of the network may be terminated when the forwarding rule is actually issued to the hardware acceleration engine (for example, when the forwarding rule is actually recorded in a forwarding rule table of the hardware acceleration engine), which not only results in that the hardware acceleration engine cannot perform an accelerated forwarding effect of a message, but also may waste overhead used for issuing the forwarding rule.
To facilitate understanding of the above-mentioned problems, taking a TCP (Transmission Control Protocol) Protocol as an example, fig. 3 exemplarily shows an example of issuing a forwarding rule in a network short link scenario. As shown in fig. 3, a connection is established between the client and the server through a three-step handshake, for example, the client sends a SYN (synchronization Sequence number) request to the server, the server sends SYN ACK (acknowledgement Character) information to the client, and the client sends ACK information to the server, so that the three-step handshake is completed between the client and the server. After the client and the server complete the three-step handshake, the software of the on-chip processor of the intelligent network card starts to issue the forwarding rule, because the issuing performance of the configuration channel is low, and because of the delay caused by asynchronous issuing, when the forwarding rule is really successfully issued (for example, when the forwarding rule is really recorded in the forwarding rule table), the link between the client and the server already enters a completion state or a state to be completed, which causes that the issued forwarding rule cannot be used in the current network short link, that is, the hardware acceleration engine of the intelligent network card cannot accelerate the forwarding of the message in the process of the current network short link. Referring to fig. 3, when the forwarding rule is issued from the beginning to the success of issuing the forwarding rule, k times of interactions have been performed between the client and the server, and the client sends the interaction completion information to the server, which means that when the forwarding rule is actually issued successfully, the link between the client and the server has already entered a completion state or a state to be completed. It should be further noted that when the client and the server complete the interaction, the client may send interaction completion information to the server, and the server sends an interaction completion confirmation to the client; when the server completes the interaction with the client, the server sends interaction completion information to the client, and the client sends an interaction completion confirmation to the server.
Therefore, the issue of the forwarding rule issued by using the configuration channel has the problems of lower issuing performance and lower reliability; for example, in a service scenario of a network short link, unreliable conditions such as a failure of forwarding rule issuing, and an inability of forwarding rule to be used in the network short link may be caused.
Based on this, the embodiment of the application provides an improved forwarding rule issuing scheme to improve the issuing performance and reliability of the forwarding rule. In order to achieve the above object, in the embodiment of the present application, a forwarding rule is issued by using a data channel between an on-chip processor and a hardware acceleration engine; and the forwarding rule is carried in the information structure of the message, so that the forwarding rule can be synchronously issued to the hardware layer (namely the layer of the hardware acceleration engine) of the intelligent network card from the software layer (namely the layer of the on-chip processor) of the intelligent network card with the message, thereby improving the issuing performance and reliability of the forwarding rule.
Based on the above thought, fig. 4 exemplarily shows an optional flowchart of the forwarding rule issuing method provided in the embodiment of the present application, and the flow of the method may be implemented by an intelligent network card, for example, by an on-chip processor and a hardware acceleration engine of the intelligent network card; referring to fig. 4, the method flow may include the following steps.
In step S410, the on-chip processor generates a forwarding rule for the packet.
In some embodiments, after obtaining the message, the intelligent network card may first query whether a forwarding rule matching the message exists in a hardware acceleration engine of the intelligent network card; if the forwarding rule matched with the message does not exist in the hardware acceleration engine, the hardware acceleration engine can transmit the message to the on-chip processor of the intelligent network card; therefore, the on-chip processor can generate a forwarding rule matched with the message according to the forwarding configuration information of the virtual switch, so that the generated forwarding rule is issued to the hardware acceleration engine, and the hardware acceleration engine can record the forwarding rule and forward the message.
As an optional implementation, the hardware acceleration engine may store a forwarding rule table, and the forwarding rule table may record a forwarding rule of the packet; after the hardware acceleration engine acquires the message, the hardware acceleration engine can inquire whether a forwarding rule matched with the message is recorded in a forwarding rule table or not so as to inquire whether the forwarding rule matched with the message exists in the hardware acceleration engine or not; if the forwarding rule matched with the message is not recorded in the forwarding rule table, the hardware acceleration engine can transmit the message to the on-chip processor of the intelligent network card; therefore, the on-chip processor can generate a forwarding rule matched with the message according to the forwarding configuration information of the virtual switch, so that the generated forwarding rule is issued to the hardware acceleration engine, and the hardware acceleration engine can record the forwarding rule and forward the message.
It should be noted that the forwarding rule may be a rule for describing a message forwarding behavior, and includes matching information of the message, such as a five-tuple (source IP, destination IP, source port, destination port, and protocol number), other necessary information that can distinguish a data flow of the message, and information such as a forwarding action. The forwarding action includes NAT (Network Address Translation), encapsulation and/or decapsulation of the tunnel, port (port) of the forwarded message, and so on.
As an optional implementation, the forwarding configuration information of the virtual switch, which is used by the on-chip processor when generating the forwarding rule, may be, for example, access Control Lists (ACL) information, quality of Service (Qos) information, and routing information. In an implementation example of generating a forwarding rule matched with a message by an on-chip processor, the on-chip processor may obtain a query result of the query message in each forwarding table by querying each forwarding table, so as to use a set of the query results of each forwarding table as the forwarding rule matched with the message; that is, the forwarding rule of the packet may be regarded as a set of query results of the packet in each forwarding table.
In one example, it is assumed that forwarding tables such as ACL tables, routing tables, etc. exist, examples of ACL tables are:
192.168.0.0/24 accept;
192.168.1.0/24 drop (discard).
Examples of routing tables are:
192.168.0.0/24 port1；
192.168.1.0/24 port2。
then for the message: 1.1.1.1 > 1111- >192.168.0.1, 80, tcp (transmission control protocol), after querying the query result of the packet in the ACL table and the routing table, the set of the query result may be used as the forwarding rule of the packet, for example, the forwarding rule of the packet is: 1.1.1.1.
In step S411, the on-chip processor loads the forwarding rule in the information structure of the packet.
The requirement of message interaction through a data channel exists between the on-chip processor of the intelligent network card and the hardware acceleration engine. For example, when determining that a forwarding rule is not recorded in a message, the hardware acceleration engine needs to transmit the message to the on-chip processor (for example, transmit the message to the on-chip processor through a data channel), and then, after generating the forwarding rule of the message, the on-chip processor needs to transmit the message transmitted by the hardware acceleration engine back to the hardware acceleration engine (for example, transmit the message back to the hardware acceleration engine through the data channel) in addition to transmitting the forwarding rule to the hardware acceleration engine, so that the hardware acceleration engine performs hardware acceleration forwarding on the message by using the forwarding rule transmitted by the on-chip processor.
Based on the above situation, in some embodiments, the on-chip processor needs to carry data information of the packet (e.g., information such as data content of the packet) in an information structure of the packet, so as to generate the packet that the on-chip processor delivers to the hardware acceleration engine based on the information structure. In the embodiment of the application, the on-chip processor issues the forwarding rule of the message to the hardware acceleration engine not by configuring a channel, but by using a data channel; in order to enable the forwarding rule of the message to be issued to the hardware acceleration engine through the data channel, the embodiment of the application may carry the forwarding rule generated by the on-chip processor in the message transmitted on the data channel, so that the forwarding rule generated by the on-chip processor is transmitted to the hardware acceleration engine along with the message.
In some embodiments, in order to implement that a forwarding rule is carried in a message, an information structure of the message may be called in the embodiments of the present application, so that the forwarding rule of the message generated by the on-chip processor is carried in the information structure; furthermore, the on-chip processor may generate the packet based on an information structure of the forwarding rule of the bearer packet, so that the packet generated by the on-chip processor can carry the forwarding rule of the packet generated by the on-chip processor.
In some embodiments, the forwarding rule may be carried in a head room (head room) field of an information structure of the packet. The header space field may be located between a header field and a data field of an information structure of the message. As an optional implementation, the size of the head space field may be set, and on this basis, the size of the head space field may be set to correspond to a preset length of the forwarding rule in the embodiment of the present application; therefore, the embodiment of the application can bear the forwarding rule with the preset length in front of the data field of the information structure, so as to realize that the forwarding rule is borne in the head space field of the information structure.
In step S412, the on-chip processor generates a packet carrying the forwarding rule according to the information structure carrying the forwarding rule.
In step S413, the on-chip processor sends the generated message to the hardware acceleration engine by using the data channel.
After the on-chip processor bears the forwarding rule of the message in the information structure of the message, the message can be generated based on the information structure bearing the forwarding rule, so that the generated message carries the forwarding rule. Furthermore, the on-chip processor can send the generated message to the hardware acceleration engine by using the data channel, so that the hardware acceleration engine can synchronously obtain the forwarding rule carried in the message while obtaining the message.
In some further embodiments, in order to enable the hardware acceleration engine to determine that the message transmitted by the on-chip processor carries the forwarding rule, when the on-chip processor issues the message to the hardware acceleration engine through the data channel, the on-chip processor may transmit preset flag (flag) information at the same time to indicate that the message issued by the hardware acceleration engine carries the forwarding rule. The preset mark information can be realized by mark information which can be directly transmitted between software and hardware of the intelligent network card, namely, the mark information can be directly transmitted between the on-chip processor and the hardware acceleration engine.
It should be noted that the preset flag (flag) information is flag information, which may be a bit, a number, or flag information in any form, and may tell the hardware acceleration engine that a currently transmitted packet carries a forwarding rule, and the preset flag (flag) information may be transmitted to the hardware acceleration engine by the on-chip processor through a data channel.
In step S414, the hardware acceleration engine analyzes the information structure of the packet to determine the forwarding rule carried in the packet.
In step S415, the hardware acceleration engine records the forwarding rule of the packet.
After obtaining the message sent by the on-chip processor through the data channel, the hardware acceleration engine can analyze the message, so as to determine a forwarding rule from the message. In some embodiments, the hardware acceleration engine may parse a head space (head room) field of an information structure of the message to determine the forwarding rule carried in the head space field.
As an alternative implementation, the spatial size of the head space field may be set, for example, the spatial size of the head space field may be set to correspond to a preset length of the forwarding rule; therefore, the hardware acceleration engine can separate the forwarding rule from the front of the data field of the information structure of the message according to the preset length of the forwarding rule so as to determine the forwarding rule loaded in the head space field. It should be noted that, in the information structure of the message, the header space field is located between the header field and the data field of the information structure and in front of the data field, so that the information of the preset length in front of the data field is separated based on the preset length of the forwarding rule, and the forwarding rule carried in the message can be obtained.
In some further embodiments, the hardware acceleration engine may determine that the packet carries the forwarding rule based on preset flag information transmitted by the on-chip processor, so as to perform a step of parsing the packet to determine the forwarding rule carried in the packet. Further, if the on-chip processor does not directly transmit the preset flag information while issuing the message, the hardware acceleration engine may determine that the message issued by the on-chip processor does not carry the forwarding rule, and the hardware acceleration engine may not execute determining the forwarding rule carried in the message.
After determining the forwarding rule from the message, the hardware acceleration engine can record the forwarding rule of the message. In some further embodiments, the hardware acceleration engine may also forward the message based on a forwarding rule of the message. Subsequently, after the hardware acceleration engine obtains the message, the hardware acceleration engine can also directly forward the message based on the forwarding rule recorded by the hardware acceleration engine under the condition that the forwarding rule of the message is recorded.
In some embodiments, the hardware acceleration engine may set a forwarding rule table in which the hardware acceleration engine may record the forwarding rule determined from the message. As an optional implementation, the forwarding rule table may record a corresponding relationship between a packet identifier of the packet and a forwarding rule of the packet; in one example, the packet identifier is, for example, five-tuple information, which may also be considered as part of the forwarding rule; the hardware acceleration engine may record a corresponding relationship between a packet identifier of the packet and a forwarding rule of the packet in a forwarding rule table based on a packet identifier of the packet issued by the on-chip processor and the forwarding rule carried in the packet, so as to implement the hardware acceleration engine to record the forwarding rule of the packet. As an alternative implementation, the message identifier of the message may be determined from the information structure of the message.
In one implementation example, if the packet is a packet of a data flow, the packet identifier of the packet may be indicated by a data flow identifier of the data flow corresponding to the packet; the forwarding rule of the message may be a forwarding rule corresponding to a data stream of the message; correspondingly, the forwarding rule table may be a flow table (flow table) for recording the forwarding rule of each data flow; therefore, the hardware acceleration engine may record, in the flow table, a forwarding rule of the data flow corresponding to the packet (for example, record a flow identifier of the data flow corresponding to the packet, and a corresponding relationship between the flow identifier and the forwarding rule), so as to implement recording of the forwarding rule of the packet in the forwarding rule table.
It should be noted that the preset flag (flag) information and the packet identifier (e.g. match) in the forwarding rule table (e.g. flow table) are different, the flow table is divided into match and action, the match, i.e. information such as the five-tuple of the packet, is used to distinguish the data stream to which the packet belongs, and the action is used to specify how the data stream to which the packet belongs should be forwarded.
In the forwarding rule issuing method provided by the embodiment of the application, the on-chip processor can generate the forwarding rule of the message and bear the generated forwarding rule in the information structure of the message; therefore, the on-chip processor can generate a message according to the information structure bearing the forwarding rule, so that the generated message carries the forwarding rule of the message; furthermore, the on-chip processor can issue the generated message by using a data channel for data message transmission with the hardware acceleration engine, so that the hardware acceleration engine can obtain a message carrying a forwarding rule through the data channel, and the on-chip processor can issue the forwarding rule of the message to the hardware acceleration engine.
When the data channel is used for sending the message to the hardware acceleration engine, the forwarding rule can be synchronously carried in the message, so that the forwarding rule can be sent through the data channel, and the sending performance of the forwarding rule sent through the data channel is equal to the sending performance of the on-chip processor and the hardware acceleration engine on the data message level, and the sending performance of the on-chip processor and the hardware acceleration engine on the data message level is far greater than the sending performance of configuration information and commands of the configuration channel, so that the sending performance of the forwarding rule can be greatly improved; meanwhile, the forwarding rule is issued along with the message, so that the issuing of the forwarding rule belongs to a synchronous event, the problem of reliability caused by asynchronous issuing of the forwarding rule can be solved, the issuing mode of the forwarding rule can meet the requirements of service scenes such as network short link and the like, and the issuing reliability of the forwarding rule is improved. Therefore, the embodiment of the application utilizes the data channel between the on-chip processor and the hardware acceleration engine to issue the forwarding rule; and the forwarding rule is carried in the information structure of the message, so that the forwarding rule and the message can be synchronously issued to the hardware acceleration engine, and the issuing performance and reliability of issuing the forwarding rule can be improved.
As an optional implementation, the forwarding rule issuing method provided in this embodiment is described below by taking a message as a data flow message as an example. As an alternative implementation, fig. 5 exemplarily shows another alternative flowchart of the forwarding rule issuing method provided in the embodiment of the present application, and the flow of the method may be implemented by an on-chip processor and a hardware acceleration engine, and referring to fig. 5, the flow of the method may include the following steps.
In step S510, the hardware acceleration engine obtains a message of the data flow.
After the intelligent network card obtains the data stream message sent by the virtual machine or the data stream message sent to the virtual machine, the intelligent network card can perform hardware acceleration forwarding on the data stream message through a hardware acceleration engine of the intelligent network card, so that the hardware acceleration engine can correspondingly obtain the data stream message. The packets of the data stream obtained by the hardware acceleration engine may be regarded as packets of the data stream to be forwarded (e.g., packets of the data stream to be forwarded by a hardware acceleration manner).
In step S511, the hardware acceleration engine queries whether a flow entry matching the data flow of the packet is recorded in the flow table, if so, step S512 is executed, otherwise, step S513 is executed.
In step S512, the hardware acceleration engine forwards the packet of the data flow based on the flow entry matching with the data flow of the packet.
In step S513, the hardware acceleration engine transfers the message of the data flow to the on-chip processor through the data channel.
After obtaining the packet of the data flow, the hardware acceleration engine may query whether a flow entry (flow table) that matches the data flow of the packet is recorded in the flow table (the flow entry in the flow table may indicate a forwarding rule of the data flow). If the flow table records the flow table entry matched with the data flow of the message, the hardware acceleration engine can perform hardware acceleration forwarding on the message of the data flow based on the flow table entry matched with the data flow of the message, which is recorded in the flow table, so that the message forwarding performance of the data flow is improved. If no flow table entry matched with the data flow of the message is recorded in the flow table, the hardware acceleration engine needs to transmit the message of the data flow to the on-chip processor through the data channel; thereby generating, by the on-chip processor, flow entries that match the data flow of the message.
In some embodiments, a data stream may be formed by a set of packets (e.g., packets) of the same type, and the type distinction of the packets may be determined by the value of the match field of the packets, which may be regarded as the value of the match field in the packets.
In some embodiments, the flow table may record a plurality of flow entries (flow entries), and one flow entry may be used to indicate a forwarding rule of one data flow. In one example, a flow entry may record a data flow identification for a data flow and a forwarding rule corresponding to the data flow. For convenience of understanding, as an implementation example, fig. 6 exemplarily shows a structure example of the flow table, as shown in fig. 6, a plurality of flow entries 601 to 60m (m is the number of flow entries, which may be determined according to actual situations) are recorded in the flow table, and one flow entry may record a data flow identifier of one data flow and a forwarding rule corresponding to the data flow.
As an optional implementation of step S511, the hardware acceleration engine may query, according to the data stream identifier corresponding to the data stream of the packet, whether a stream table entry matching the data stream identifier of the data stream is recorded in the stream table; if yes, the hardware acceleration engine records a forwarding rule matched with the data flow of the message; if not, the hardware acceleration engine does not record the forwarding rule matched with the data stream of the message.
In step S514, the on-chip processor generates a flow entry matching the data flow of the packet according to the forwarding configuration information of the virtual switch.
In step S515, the on-chip processor carries the generated flow entry in the header space field of the information structure of the packet.
After obtaining the message of the data flow transmitted by the hardware acceleration engine through the data channel, the on-chip processor may query various forwarding configuration information of the virtual switch (for example, query ACL information, qos information, routing information, etc. of the virtual switch), so as to generate a flow table entry matched with the data flow of the message according to the forwarding configuration information of the virtual switch (the flow table entry matched with the data flow of the message may be used for indicating, and a forwarding rule matched with the data flow of the message).
After generating the flow entry matched with the data flow of the message, the on-chip processor may carry the flow entry in a header space field of an information structure of the message, so that the flow entry can be carried in the message.
In some embodiments, the on-chip processor is configured to run a data core of the virtual switch, and may generate the forwarding rule and carry the forwarding rule in a header space field of an information structure of the packet. For example, the data core may generate flow entries that match the data flow of the packet and carry the flow entries in the header space field of the information structure of the packet.
In one example, fig. 7 is an exemplary diagram illustrating an information structure of a packet, and as shown in fig. 7, a data (data) field for carrying packet data is included in the information structure of the packet. A head space (head room) field is arranged in front of the data field, and the size of the head space field can be set, so that the embodiment of the present application can set the size of the head space field according to a preset length of a forwarding rule (for example, a preset length of a flow entry); in turn, a forwarding rule of a preset length (e.g., a flow entry of a preset length) is carried in front of the data field to carry the forwarding rule in a header space field in front of the data field. The front of the header space field is a private (private) field, and the front of the private field is a structure (structure) field of the information structure. Private and structural fields can be considered as header fields in the information structure of the message.
In an implementation example, taking an example that an information structure of a message adopts an mbuf (memory buffer) structure, a data field in the mbuf structure may store data information of the message, a partial head space (head room) field may be further provided at a front portion of the data field in the mbuf structure for storing control information of the message, and a space size of the head space field may be set; thus, the embodiment of the present application may carry the forwarding rule (e.g., the flow entry) in the head room field of the mbuf structure. As an optional implementation, the mbuf structure may be applied to a scene such as a DPDK (Data Plane Development Kit).
In step S516, the on-chip processor generates a packet carrying the flow table entry according to the information structure of the bearer flow table entry.
In step S517, the on-chip processor issues the generated packet to the hardware acceleration engine through the data channel; and transmitting preset mark information to the hardware acceleration engine to indicate that the issued message carries the flow table entry.
After the on-chip processor loads the flow table entry in the information structure of the message, the on-chip processor can generate the message carrying the flow table entry; and the generated message is sent to the hardware acceleration engine through the data channel, so that the hardware acceleration engine can obtain the message carrying the flow table entry through the data channel. Further, in order to indicate to the hardware acceleration engine that the issued message carries the flow table entry, the on-chip processor may also transmit preset flag information to the hardware acceleration engine while issuing the message; the preset flag information may be used to indicate that a message sent by the on-chip processor carries a flow entry.
In step S518, the hardware acceleration engine determines that the flow entry is carried in a message sent by the on-chip processor through the data channel according to the preset flag information; and determining an outflow table entry from a head space field of an information structure of the message.
After obtaining the message sent by the on-chip processor through the data channel and the preset mark information transmitted by the on-chip processor, the hardware acceleration engine can determine that the sent message carries the flow table item based on the preset mark information; the hardware acceleration engine may thus determine an egress entry (i.e., a flow entry that matches the data flow of the message) from the header space field of the message's information structure. In some embodiments, the hardware acceleration engine may separate information of a preset length from a front of a data field of an information structure of the packet according to the preset length of the flow entry, so as to obtain the flow entry carried in the packet.
In step S519, the hardware acceleration engine records the flow entry in the flow table; and based on the flow table item, forwarding the message issued by the on-chip processor.
After determining a flow table entry matched with the data flow of the message in the message sent from the on-chip processor, the hardware acceleration engine may record the flow table entry in a flow table (e.g., insert the flow table entry in the flow table); and the hardware acceleration engine can forward the message sent by the on-chip processor based on the forwarding rule of the data flow indicated by the flow table item.
In some further embodiments, after obtaining the same data stream packet subsequently, the hardware acceleration engine may query a stream entry matching the data stream identifier of the data stream from the stream table, so as to implement accelerated forwarding of the data stream packet at the hardware layer based on the queried stream entry, thereby improving packet forwarding performance of the data stream. That is, if the message hits the flow entry in the hardware acceleration engine, the message is not transmitted to the on-chip processor, and the hardware acceleration engine can directly forward the message based on the flow entry hit by the message; and only when the message does not hit the flow table entry in the hardware acceleration engine, the hardware acceleration engine transmits the message to the on-chip processor, and the on-chip processor generates the flow table entry of the message. The flow table items generated by the on-chip processor can be carried in the message and sent to the hardware acceleration engine through the data channel.
In further some embodiments, if the hardware acceleration engine fails to insert a flow entry into the flow table due to some abnormal reasons (for example, hash collision exists between a flow entry to be inserted and a flow entry recorded in the flow table, which results in a failure in inserting the flow entry), the packet of the subsequent data flow cannot hit the flow entry recorded in the flow table, and the packet of the data flow may continue to be transferred to the on-chip processor, and the on-chip processor generates a flow entry matched with the data flow of the packet, and issues the flow entry according to the scheme provided in the embodiment of the present application.
In an implementation example, fig. 8 exemplarily shows an example of a process issued by a forwarding rule provided in the embodiment of the present application, and as shown in fig. 8, taking a packet of a data flow as an example of a data packet form, the process may be as follows:
(1) after obtaining the data packet sent by the virtual machine or the data packet sent to the virtual machine, the intelligent network card can be sent to the hardware acceleration engine for processing; the hardware acceleration engine determines that a flow table item matched with the data flow of the data packet is not inquired in the flow table;
(2) the hardware acceleration engine transmits a data packet to the on-chip processor through a data channel;
(3) the on-chip processor (for example, a data core in the on-chip processor) may generate a flow table entry matching the data flow of the data packet based on the forwarding configuration information of the virtual switch, and carry the flow table entry in the data packet that needs to be delivered to the intelligent network card; the data packet may carry a flow table entry, data information of the data packet, and the like;
(4) the on-chip processor sends a data packet carrying a flow table entry to the hardware acceleration engine through the data channel (further, the on-chip processor can simultaneously transmit preset mark information);
(5) the hardware acceleration engine can determine the carried flow table items from the data packet sent by the on-chip processor and record the flow table items in the flow table;
(6) the hardware acceleration engine forwards the data packet based on the flow table entry.
According to the forwarding rule issuing scheme provided by the embodiment of the application, the forwarding rule is carried in the message, so that the on-chip processor can synchronously issue the message to the hardware acceleration engine through the data channel while issuing the message to the hardware acceleration engine through the data channel; the embodiment of the application realizes the issuing of the forwarding rule by using the data channel, and improves the issuing performance of the forwarding rule; and because the forwarding rule is synchronously issued to the hardware acceleration engine along with the message and belongs to a synchronous event, the problem of reliability caused by asynchronous issuing of the forwarding rule can be solved, and the issuing reliability of the forwarding rule is improved. The forwarding rule issuing scheme provided by the embodiment of the application can improve the issuing performance of the forwarding rule, improve the issuing reliability of the forwarding rule, can be effectively applied to service scenes such as network short links and the like, and improve the application value of cloud computing and virtualization technology.
In the following, the intelligent network card provided by the embodiment of the present application is introduced, and the functions of the intelligent network card described below may be referred to in correspondence with the contents described above. As shown in fig. 2A and fig. 2B, the intelligent network card provided in the embodiment of the present application may include an on-chip processor and a hardware acceleration engine. As an alternative implementation, the functions of the on-chip processor described below may be implemented by means of software functions; the functions of the hardware acceleration engine described below may be implemented by hardware functions or software functions programmed by the hardware acceleration engine based on the programmability of the hardware acceleration engine.
In the embodiment of the application, the on-chip processor can be used for generating a forwarding rule of the message; the forwarding rule is carried in the information structure of the message; generating a message carrying the forwarding rule according to an information structure bearing the forwarding rule; and sending the generated message to a hardware acceleration engine by using a data channel.
The hardware acceleration engine can be used for acquiring a message issued by the on-chip processor by using a data channel, wherein the message carries a forwarding rule of the message; analyzing the information structure of the message to determine the forwarding rule carried in the message, wherein the forwarding rule is carried in the information structure of the message; and recording the forwarding rule of the message.
In some embodiments, the on-chip processor is configured to, in carrying the forwarding rule in the information structure of the packet, include:
in the head space field of the information structure, carrying the forwarding rule; the header space field is located between a header field and a data field of the information structure.
In some embodiments, the head space field is sized in space to correspond to a preset length of the forwarding rule; the on-chip processor is configured to, in a header space field of the information structure, carry the forwarding rule, including:
the forwarding rule with a preset length is borne in front of a data field of the information structure; wherein the head space field is located forward of the data field.
In some further embodiments, while issuing the generated packet to the hardware acceleration engine by using the data channel, the on-chip processor may be further configured to: and transmitting preset mark information to the hardware acceleration engine, wherein the preset mark information indicates that the issued message carries forwarding rules.
In some further embodiments, the on-chip processor may be further configured to: when the forwarding rule of the message is not recorded in the hardware acceleration engine, obtaining the message transmitted by the hardware acceleration engine through a data channel so as to enable the on-chip processor to enter the step of generating the forwarding rule of the message;
in some embodiments, the on-chip processor is configured to generate the forwarding rule of the packet, including:
and generating a forwarding rule of the message according to the forwarding configuration information of the virtual switch.
In some embodiments, the hardware acceleration engine is configured to parse an information structure of the packet to determine that the forwarding rule carried in the packet includes:
parsing a header space field of the information structure to determine the forwarding rules carried in the header space field; the header space field is located between a header field and a data field of the information structure.
In some embodiments, the head space field is sized in space to correspond to a preset length of the forwarding rule; the hardware acceleration engine is configured to parse a header space field of the information structure to determine that the forwarding rule carried in the header space field includes:
separating the forwarding rule with the preset length from the front of the data field of the information structure according to the preset length; wherein the head space field is located forward of the data field.
In some further embodiments, when the hardware acceleration engine acquires the delivered packet through the data channel, the hardware acceleration engine may be further configured to: and acquiring transmitted preset mark information, wherein the preset mark information indicates that a transmitted message carries a forwarding rule.
In some further embodiments, the hardware acceleration engine may be further configured to: and when the forwarding rule of the message is not recorded, transmitting the message to the on-chip processor through the data channel so that the on-chip processor generates the message carrying the forwarding rule.
In some embodiments, the packets are packets of a data stream; the forwarding rule of the message is a flow entry matched with the data flow of the message; the flow table entry is recorded in the flow table, and a plurality of flow table entries are recorded in the flow table, one flow table entry being used to indicate a forwarding rule of one data flow.
Correspondingly, the hardware acceleration engine is configured to record a forwarding rule of the packet, and includes:
and inserting the flow table entry matched with the data flow of the message into the flow table.
The embodiment of the present application further provides a storage medium, where the storage medium stores one or more computer-executable instructions, and when the one or more computer-executable instructions are executed, the method for issuing the forwarding rule executed by the on-chip acceleration engine according to the embodiment of the present application is implemented, or the method for issuing the forwarding rule executed by the hardware acceleration engine according to the embodiment of the present application is implemented.
The embodiment of the present application further provides a computer program, and when the computer program is executed, the method for issuing the forwarding rule executed by the on-chip acceleration engine according to the embodiment of the present application is implemented, or the method for issuing the forwarding rule executed by the hardware acceleration engine according to the embodiment of the present application is implemented.
While various embodiments provided by the embodiments of the present application have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in the embodiments of the present application.
Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and it is intended that the scope of the present disclosure be defined by the appended claims.
Claims (12)
1. A forwarding rule issuing method is applied to an on-chip processor, and comprises the following steps:
generating a forwarding rule of the message;
the forwarding rule is carried in the information structure of the message;
generating a message carrying the forwarding rule according to an information structure bearing the forwarding rule;
and sending the generated message by using a data channel.
2. The method of claim 1, wherein the carrying the forwarding rule in an information structure of the packet comprises:
in the head space field of the information structure, carrying the forwarding rule; the header space field is located between a header field and a data field of the information structure.
3. The method of claim 2, wherein the head-space field is set to a spatial size corresponding to a preset length of the forwarding rule; the carrying the forwarding rule in a head space field of the information structure includes:
the forwarding rule with a preset length is borne in front of a data field of the information structure; wherein the header space field is located in front of the data field.
4. The method of claim 1, wherein when the generated packet is transmitted using a data channel, the method further comprises:
transmitting preset mark information, wherein the preset mark information indicates that a transmitted message carries a forwarding rule;
the method further comprises the following steps:
when the forwarding rule of the message is not recorded in the hardware acceleration engine, obtaining the message transmitted by the hardware acceleration engine through a data channel so as to enter the step of generating the forwarding rule of the message;
the forwarding rule for generating the message comprises:
and generating a forwarding rule of the message according to the forwarding configuration information of the virtual switch.
5. The method according to any of claims 1-4, wherein the packets are packets of a data flow; the forwarding rule of the message is a flow entry matched with the data flow of the message; the flow table entry is recorded in a flow table stored in the hardware acceleration engine, and a plurality of flow table entries are recorded in the flow table, one flow table entry being used to indicate a forwarding rule of one data flow.
6. A forwarding rule issuing method is applied to a hardware acceleration engine, and comprises the following steps:
acquiring a transmitted message by using a data channel; the message carries the forwarding rule of the message;
analyzing the information structure of the message to determine the forwarding rule carried in the message; wherein, the forwarding rule is carried in the information structure of the message;
and recording the forwarding rule of the message.
7. The method of claim 6, wherein the parsing the information structure of the packet to determine the forwarding rule carried in the packet comprises:
parsing a header space field of the information structure to determine the forwarding rules carried in the header space field; the header space field is located between a header field and a data field of the information structure.
8. The method of claim 7, wherein the head-space field is set to a spatial size corresponding to a preset length of the forwarding rule; said parsing the header space field of the information structure to determine the forwarding rule carried in the header space field comprises:
separating the forwarding rule with the preset length from the front of the data field of the information structure according to the preset length; wherein the header space field is located in front of the data field.
9. The method of claim 6, wherein when the data channel is used to obtain the delivered message, the method further comprises:
acquiring transmitted preset mark information, wherein the preset mark information indicates that a transmitted message carries a forwarding rule;
the method further comprises the following steps:
and when the forwarding rule of the message is not recorded, transmitting the message to the on-chip processor through the data channel so that the on-chip processor generates the message carrying the forwarding rule.
10. The method according to any of claims 6-9, wherein the packets are packets of a data flow; the forwarding rule of the message is a flow table item matched with the data flow of the message; the flow table entry is recorded in the flow table, and a plurality of flow table entries are recorded in the flow table, and one flow table entry is used for indicating a forwarding rule of one data flow; the recording of the forwarding rule of the message comprises:
and inserting a flow table entry matched with the data flow of the message into the flow table.
11. An intelligent network card, comprising: an on-chip processor and a hardware acceleration engine; the on-chip processor is configured to execute the forwarding rule issuing method according to any one of claims 1-5; the hardware acceleration engine is configured to perform the forwarding rule issuing method according to any one of claims 6-10.
12. A storage medium, wherein the storage medium stores one or more computer-executable instructions that, when executed, implement the forwarding rule issuing method of any one of claims 1-5 or the forwarding rule issuing method of any one of claims 6-10.
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| CN202210981665.XA CN115460145A (en) | 2022-08-15 | 2022-08-15 | Forwarding rule issuing method, intelligent network card and storage medium |
| PCT/CN2023/111395 WO2024037366A1 (en) | 2022-08-15 | 2023-08-07 | Forwarding rule issuing method, and intelligent network interface card and storage medium |
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