CN115459621A - Space vector modulation method and system of asymmetric quasi-Z-source three-level inverter - Google Patents

Space vector modulation method and system of asymmetric quasi-Z-source three-level inverter Download PDF

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CN115459621A
CN115459621A CN202211198260.5A CN202211198260A CN115459621A CN 115459621 A CN115459621 A CN 115459621A CN 202211198260 A CN202211198260 A CN 202211198260A CN 115459621 A CN115459621 A CN 115459621A
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vector
flag
ppp
sequence
nnn
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秦昌伟
李晓艳
褚志元
张焕君
李兆余
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Shandong Jianzhu University
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Shandong Jianzhu University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4833—Capacitor voltage balancing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

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Abstract

The invention provides a space vector modulation method and a space vector modulation system of an asymmetric quasi-Z-source three-level inverter, which relate to the technical field of power electronic power conversion, and are used for judging a sector of a reference voltage vector in a space vector diagram according to the amplitude and the phase angle of the reference voltage vector; selecting corresponding basic voltage vectors by combining the voltage deviation of the two capacitors in the sector where the reference voltage vector is located and the quasi-Z source network, and calculating a switch sequence zone bit; adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller; based on the switch sequence zone bit, selecting and injecting different types of direct-through states, and calculating the duty ratio of the basic voltage vector; designing a switching sequence according to the switching sequence flag bit and the duty ratio of the basic voltage vector; the invention can overcome the influence of the asymmetry of the topological structure on the system output, ensures three-phase symmetrical output current and has the capacity of boosting and neutral voltage balance active control.

Description

Space vector modulation method and system of asymmetric quasi-Z-source three-level inverter
Technical Field
The invention belongs to the technical field of power electronic power conversion, and particularly relates to a space vector modulation method and system of an asymmetric quasi-Z-source three-level inverter.
Background
The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
The quasi-Z-source three-level inverter has the advantages of single-stage power conversion, continuous input current, small capacity of passive devices, no need of dead time and the like, and is widely applied to the fields of solar photovoltaic power generation, energy storage systems, motor driving and the like. The quasi-Z source Neutral Point Clamped (NPC) and T-Type (T-Type) three-level inverters are the two most commonly used topologies of quasi-Z source three-level inverters, but both of them need to use a large number of power switching tubes, which inevitably increases the system cost and volume.
In order to further reduce the number of power switching tubes and reduce the volume and cost of a system, an asymmetric quasi-Z-source three-level inverter topological structure can be adopted, namely, one phase bridge arm of the quasi-Z-source three-level inverter is replaced by a bridge arm of a two-level inverter topology; however, the three-phase bridge arm of the topological structure is not symmetrical any more, and the existing modulation method for the quasi-Z-source three-level inverter cannot be applied.
The inventor finds that the number of basic voltage vectors of the asymmetrical quasi-Z source three-level inverter is limited, which brings great difficulty to the design of a space vector modulation strategy; therefore, a space vector modulation method suitable for the asymmetric quasi-Z source three-level inverter needs to be researched.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a space vector modulation method and a space vector modulation system of an asymmetric quasi-Z-source three-level inverter, which can overcome the influence of the asymmetry of a topological structure on the output of the system, ensure three-phase symmetric output current and have the capacity of boosting and neutral voltage balance active control.
To achieve the above object, one or more embodiments of the present invention provide the following technical solutions:
the invention provides a space vector modulation method of an asymmetric quasi-Z-source three-level inverter.
The space vector modulation method of the asymmetric quasi-Z source three-level inverter comprises the following steps:
judging the sector of the reference voltage vector in the space vector diagram according to the amplitude and the phase angle of the reference voltage vector;
selecting corresponding basic voltage vectors by combining the sector where the reference voltage vector is located and the voltage deviation of two capacitors in the quasi-Z source network, and generating a switch sequence flag bit;
adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller;
based on the switch sequence zone bit, selecting and injecting different types of through states, calculating the duty ratio of a basic voltage vector, and limiting the output quantity of the direct current side capacitor voltage balance controller according to the calculated duty ratio;
and designing a switching sequence according to the mark bit of the switching sequence and the duty ratio of the basic voltage vector, converting the switching sequence into a PWM (pulse-width modulation) driving signal of a power switching tube, and controlling the work of the asymmetric quasi-Z-source three-level inverter.
Further, according to the requirement of the midpoint voltage balance control of the system, a midpoint voltage balance control threshold value delta V is set np_th Combining the Sector in which the reference voltage vector is located and the capacitor C 2 、C 3 Voltage deviation Δ V of np And selecting corresponding basic voltage vectors according to a rule to synthesize a reference voltage vector, and generating a Flag of a switch sequence.
Further, the voltage deviation delta V of two capacitors in the quasi-Z source network np And sending the voltage to a proportional-integral (PI) regulator, and further taking absolute value to operate to obtain the output quantity of the DC side capacitor voltage balance controller.
Further, determining a basic voltage vector duty ratio calculation mode according to the value condition of the switch sequence flag bit; and (4) writing an equation set by using a volt-second balance principle, and solving the duty ratio of the basic voltage vector.
Further, the selective injection of different types of pass-through states is specifically performed as follows: when the Flag bit Flag of the switching sequence is =5 or 14, a lower through state is injected into the P-type small vector, and an upper through state is injected into the N-type small vector, so that the boosting function is realized, and the normal output alternating voltage of the system is not influenced; when the Flag bit Flag of the switching sequence takes other values, a full-through state is injected into the zero vector [ PPP ] or [ NNN ], so that the boosting function is realized, and the normal output alternating voltage of the system is not influenced.
Furthermore, the output quantity of the DC side capacitor voltage balance controller is subjected to amplitude limiting processing, the duty ratio of each basic voltage vector is ensured to be larger than 0 and smaller than 1, the duty ratio of each basic voltage vector is updated, and neutral point voltage balance control is achieved.
Further, a switch sequence is designed according to the value situation of the switch sequence flag bit.
Furthermore, the designed switching sequence is converted into a PWM driving signal of a power switching tube, and then the work of the asymmetric quasi-Z source three-level inverter system is controlled.
The invention provides a space vector modulation system of an asymmetric quasi-Z-source three-level inverter.
The space vector modulation system of the asymmetric quasi-Z source three-level inverter comprises a sector judgment module, a zone bit calculation module, a direct-current side capacitance voltage balance control module, a duty ratio calculation module and a switch design module;
a sector determination module configured to: judging the sector of the reference voltage vector in the space vector diagram according to the amplitude and the phase angle of the reference voltage vector;
a flag bit calculation module configured to: selecting corresponding basic voltage vectors by combining the voltage deviation of the two capacitors in the sector where the reference voltage vector is located and the quasi-Z source network, and calculating a switch sequence zone bit;
a DC side capacitance voltage balance control module configured to: adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller;
a duty cycle calculation module configured to: based on the switch sequence zone bit, selecting and injecting different types of through states, calculating the duty ratio of a basic voltage vector, and limiting the output quantity of the direct current side capacitor voltage balance controller according to the calculated duty ratio;
a switch design module configured to: and designing a switching sequence according to the duty ratio of the switch sequence zone bit and the basic voltage vector, converting the switching sequence into a PWM (pulse-width modulation) driving signal of a power switch tube, and controlling the work of the asymmetric quasi-Z-source three-level inverter.
A third aspect of the present invention provides a computer readable storage medium having stored thereon a program which, when being executed by a processor, realizes the steps in the space vector modulation method of an asymmetric quasi-Z-source three-level inverter according to the first aspect of the present invention.
A fourth aspect of the present invention provides an electronic device, comprising a memory, a processor and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the space vector modulation method of the asymmetric quasi-Z-source three-level inverter according to the first aspect of the present invention.
The above one or more technical solutions have the following beneficial effects:
1. in different sectors, the boosting function is realized by injecting a full-through state in a zero vector or injecting an upper through state and a lower through state in a small vector.
2. And selecting a corresponding basic voltage vector according to the sector where the reference voltage vector is located and the voltage deviation value of the capacitor at the direct current side, effectively controlling the midpoint voltage balance and having small fluctuation amplitude of the voltage of the capacitor.
3. When the midpoint voltage is deviated due to abnormal factors, the method has the capability of active control of midpoint voltage balance, and realizes the recovery of the midpoint voltage balance state, thereby improving the operation reliability of the system.
4. The influence of the asymmetry of the topological structure on the system output is overcome, and the three-phase symmetrical output current is ensured.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a circuit topology diagram of an asymmetric quasi-Z-source three-level inverter in a first embodiment;
FIG. 2 is a spatial vector diagram in a first embodiment;
FIG. 3 is a control block diagram in the first embodiment;
fig. 4 (a) and 4 (b) are waveform diagrams illustrating the operation of the method of the present embodiment in the non-boost operation mode.
Fig. 5 (a) and 5 (b) are waveform diagrams illustrating the operation of the method of the present embodiment in the boost operation mode.
Fig. 6 (a) is an operating waveform diagram of the method of the present embodiment when the modulation degree is changed from 0.6 to 0.8 in a step-by-step mode of operation.
Fig. 6 (b) is an operation waveform diagram of the method of the present embodiment when the modulation degree is changed from 0.6 to 0.8 in the step-up operation mode.
Fig. 7 (a) is a waveform diagram illustrating the operation of the method of the present embodiment from enabling to cancelling the midpoint voltage balance control in the non-boost operation mode.
Fig. 7 (b) is a waveform diagram of the operation of the method of the present embodiment in the boost operation mode from enabling to cancelling the midpoint voltage balance control.
Detailed Description
The invention is further described with reference to the following figures and examples.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention; unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention; as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Example one
The embodiment discloses a space vector modulation method of an asymmetric quasi-Z-source three-level inverter.
Fig. 1 is a circuit topology diagram of an asymmetric quasi-Z source three-level inverter, which includes the following components: the system comprises a direct current power supply, a quasi-Z source network, an asymmetric three-level inverter and a load. The quasi-Z source network is connected between the direct-current power supply and the asymmetric three-level inverter and used for realizing a boosting function; having an input voltage of V in Output voltage of V dc (ii) a The asymmetric three-level inverter consists of three-phase bridge arms A, B and C, wherein the bridge arm A comprises 2 power switching tubes, and the bridge arms B and C respectively comprise 4 power switching tubes.
The switching states of the asymmetric quasi-Z source three-level inverter can be divided into two types: a Non-Shoot-Through state and a Shoot-Through state.
The same as a common three-level inverter, the non-through state of the asymmetric quasi-Z source three-level inverter comprises three states: [ P ]]、[O]And [ N](ii) a Selecting a neutral point (i.e., point O in fig. 1) of the quasi-Z source network as a reference point; when the switch state is [ P ]]The output voltage of the bridge arm is + V dc 2; when the switch state is [ O ]]When the output voltage of the bridge arm is 0; when the switch state is [ N ]]When the output voltage of the bridge arm is-V dc /2。
TABLE 1A phase switching state and power switching tube
Figure BDA0003871398070000061
TABLE 2 switching state of B-phase and C-phase and power switch tube turned on
Figure BDA0003871398070000062
The through state of the asymmetric quasi-Z source three-level inverter comprises three states: an Up-Shoot-Through (UST) state (abbreviated as [ U ]), a Down-Shoot-Through (DST) state (abbreviated as [ D ]), and a Full-Shoot-Through (FST) state (abbreviated as [ F ]); the switching states and the turned-on power switch tubes of the A phase are shown in the table 1, and the switching states and the turned-on power switch tubes of the B phase and the C phase are shown in the table 2.
Controlling the on and off of each power switch tube by adopting a Pulse Width Modulation (PWM) mode; it can be understood that the power switch tube is an insulated-Gate Bipolar Transistor (IGBT); the power switch tube can also be realized by adopting other forms of transistors.
Fig. 2 is a space vector diagram of an asymmetric quasi-Z source three-level inverter, wherein a basic voltage vector includes 6 large vectors, 4 medium vectors, 6 small vectors, and 2 zero vectors, and specifically, the large vectors include: the vectors [ PNN ], [ PPN ], [ NPN ], [ NPP ], [ NNP ], [ PNP ], comprise: [ PON ], [ NPO ], [ NOP ], [ PNO ], and the small vector comprises: [ POO ], [ PPO ], [ NON ], [ NOO ], [ NNO ], [ POP ], wherein the zero vector comprises: [ PPP ], [ NNN ].
The control block diagram of the method is shown in fig. 3, and in order to obtain three-phase symmetrical output current and achieve the goals of neutral-point voltage balance control, boosting and the like, the space vector modulation method of the asymmetric quasi-Z-source three-level inverter is designed, and comprises the following steps:
step S1: judging the sector of the reference voltage vector in the space vector diagram according to the amplitude and the phase angle of the reference voltage vector;
step S2: selecting corresponding basic voltage vectors by combining the voltage deviation of the two capacitors in the sector where the reference voltage vector is located and the quasi-Z source network, and generating a switch sequence flag bit;
capacitance C in sampling quasi Z source network 2 And C 3 The voltage at two ends is used for calculating the voltage deviation delta V of two capacitors in the quasi-Z source network np 。
Setting a midpoint voltage balance control threshold value (delta V) according to the midpoint voltage balance control requirement of the system np_th ) Combining the Sector (Sector) in which the reference voltage vector is located and the capacitor C 2 、C 3 Voltage deviation (Δ V) of np ) Selecting corresponding basic voltage vectors to synthesize a reference voltage vector and generating a switch sequence Flag bit (Flag), wherein the specific rule is as follows:
when Sector =1 and Δ V np ≤ΔV np_th Then, select the large vector [ PNN]Middle vector [ PON ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =1 of a switching sequence;
when Sector =1 and Δ V np >ΔV np_th Then, select the large vector [ PNN]Middle vector [ PON ]]Small vector [ POO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =2 in a switching sequence;
when Sector =2 and Δ V np ≤ΔV np_th Then, select the large vector [ PPN]Middle vector [ PON ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =3 of a switching sequence;
when Sector =2 and Δ V np >ΔV np_th Then, select the large vector [ PPN]Middle vector [ PON ]]Small vector [ PPO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =4 of a switching sequence;
when a Sector =3 or 4, selecting a large vector [ PPN ], a large vector [ NPN ], a small vector [ PPO ] and a small vector [ NON ] to synthesize a reference voltage vector, simultaneously injecting a lower through state into the small vector [ PPO ], and injecting an upper through state into the small vector [ NON ] to realize a boosting function, wherein a switch sequence Flag =5;
when S isector =5 and Δ V np ≥-ΔV np_th Then, select the large vector (NPN)]Middle vector [ NPO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected, a boosting function is realized, and a Flag bit of a switching sequence is =6;
when Sector =5 and Δ V np <-ΔV np_th Then, select the large vector (NPN)]Middle vector [ NPO ]]Small vector of [ NON ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected to realize a boosting function, and the Flag bit Flag =7 of a switch sequence;
when Sector =6 and Δ V np ≥-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NPO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =8 of a switching sequence;
when Sector =6 and Δ V np <-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NPO ]]Small vector of [ NOO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =9 of a switching sequence;
when Sector =7 and Δ V np ≥-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NOP ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected, a boosting function is realized, and a Flag bit of a switching sequence is =10;
when Sector =7 and Δ V np <-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NOP ]]Small vector of [ NOO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected, a boosting function is realized, and a Flag bit of a switching sequence is =11;
when Sector =8 and Δ V np ≥-ΔV np_th Then, select the large vector [ NNP ]]Middle vector [ NOP ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =12 in a switching sequence;
when Sect isor =8, and Δ V np <-ΔV np_th Then, select the large vector [ NNP ]]Middle vector [ NOP ]]Small vector of [ NNO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected to realize a boosting function, and the Flag bit Flag =13 of a switch sequence;
when the Sector =9 or 10, selecting a large vector [ NNP ], a large vector [ PNP ], a small vector [ POP ] and a small vector [ NNO ] to synthesize a reference voltage vector, simultaneously injecting a lower through state into the small vector [ POP ], and injecting an upper through state into the small vector [ NNO ], so that a boosting function is realized, and the Flag bit Flag =14 of the switching sequence;
when Sector =11 and Δ V np ≤ΔV np_th Then, choose the large vector [ PNP ]]Middle vector [ PNO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =15 of a switching sequence;
when Sector =11 and Δ V np >ΔV np_th Then, choose the large vector [ PNP ]]Middle vector [ PNO ]]Small vector [ POP]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =16 of a switching sequence;
when Sector =12 and Δ V np ≤ΔV np_th Then, select the large vector [ PNN]Middle vector [ PNO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =17 of a switching sequence;
when Sector =12 and Δ V np >ΔV np_th Then, select the large vector [ PNN]Middle vector [ PNO ]]Small vector [ POO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]And a full-through state is injected, a boosting function is realized, and a Flag =18 of a switching sequence is set.
And step S3: adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller;
deviation Delta V of voltage of two capacitors in quasi-Z source network np And sent to PI regulator for further absolute measurementValue operation to obtain the output quantity of the DC side capacitor voltage balance controller, i.e.
Figure BDA0003871398070000101
Wherein, V C2 And V C3 Are respectively a capacitor C 2 And C 3 Voltage across, k p,np And k i,np Is a parameter of the PI regulator.
The resulting DC-side capacitor-voltage-balancing controller output (i.e., y) np ) And the method is used for carrying out amplitude limiting processing on the output quantity of the DC side capacitor voltage balance controller in the next step, and ensuring that the duty ratio of each basic voltage vector is greater than 0 and less than 1, thereby realizing midpoint voltage balance control.
And step S4: based on the switch sequence zone bit, selecting and injecting different types of through states, calculating the duty ratio of a basic voltage vector, and limiting the output quantity of the direct current side capacitor voltage balance controller according to the calculated duty ratio;
determining a basic voltage vector duty ratio calculation mode according to the value condition of the switch sequence zone bit; the method comprises the following steps of solving the duty ratio of a basic voltage vector by using a volt-second balance principle column writing equation set, wherein the specific steps are as follows:
(1) When the Flag bit Flag of the switching sequence is =1,3,6,8,10,12,15,17, the duty ratio of the large vector, the medium vector and the zero vector is solved by adopting a direct calculation mode.
Without loss of generality, taking the switch sequence Flag =1,3 as an example, detailed solving steps are given as follows.
When the Flag bit Flag =1, the basic voltage vector includes a large vector [ PNN ], a medium vector [ PON ], and a zero vector [ PPP ], and the equation set is written by using the volt-second balance principle:
Figure BDA0003871398070000111
wherein, V 1 、V 7 And V 0 Individual watchBig vector [ PNN ]]Middle vector [ PON ]]And zero vector PPP]Expression of (a), d 1 、d 7 And d 0 Respectively representing large vectors [ PNN]Middle vector [ PON ]]And zero vector PPP]Duty cycle of (d), V ref Is the magnitude of the reference voltage vector.
Solving the equation set, and simultaneously considering the injection of a through state in a zero vector [ PPP ], the duty ratio of each basic voltage vector is obtained as follows:
Figure BDA0003871398070000112
where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively, d st Is the through duty cycle. The modulation m is defined as
Figure BDA0003871398070000113
Wherein, V ref Is the magnitude of the reference voltage vector, V dc And outputting the voltage amplitude for the quasi Z source network.
When the Flag bit Flag =3 of the switching sequence, the basic voltage vector includes a large vector [ PPN ], a medium vector [ PON ], a zero vector [ PPP ], and a system of equations is written by using the volt-second balance principle:
Figure BDA0003871398070000114
wherein, V 2 、V 7 And V 0 Respectively representing large vectors [ PPN]Middle vector [ PON ]]And zero vector PPP]，d 2 、d 7 And d 0 Respectively represent large vectors [ PPN]Middle vector [ PON ]]And zero vector PPP]Duty cycle of (d), V ref Is a reference voltage vector.
Solving the equation set, simultaneously considering injecting the through state in the zero vector [ PPP ], directly subtracting the through duty ratio from the duty ratio of the zero vector to express the injection of the through state, and obtaining the duty ratio of each basic voltage vector as follows:
Figure BDA0003871398070000121
where m and θ are the modulation and phase angle of the reference voltage vector, respectively, d st Is the through duty cycle.
When the Flag of the switch sequence takes other values, a similar method can be adopted and the symmetry of the space vector diagram is combined to complete the solving process.
(2) When the Flag bits Flag of the switching sequence is =2,4,7,9,11,13,16,18, the output quantity of the dc-side capacitance voltage balance controller is used as the duty ratio of a small vector, an indirect calculation mode is further designed, the duty ratios of a large vector, a medium vector and a zero vector are solved, and meanwhile, the output quantity of the dc-side capacitance voltage balance controller needs to be subjected to amplitude limiting processing so as to ensure that the duty ratios of all basic voltage vectors are greater than 0 and less than 1.
Without loss of generality, taking the switch sequence Flag =2,4 as an example, detailed solving steps are given as follows.
When the Flag of the switching sequence is =2, the basic voltage vector includes a large vector [ PNN ], a medium vector [ PON ], a small vector [ POO ], and a zero vector [ PPP ], and the equation set is written by using the volt-second balance principle:
Figure BDA0003871398070000122
wherein, V 1 、V 7 、V 11 And V 0 Respectively representing large vectors [ PNN]Middle vector [ PON ]]Small vector [ POO ]]And zero vector PPP]，d 1 、d 7 、d 11 And d 0 Respectively representing large vectors [ PNN]Middle vector [ PON ]]Small vector [ POO ]]And zero vector PPP]Duty ratio of V ref Is a vector of reference voltages.
The output quantity of the direct current side capacitor voltage balance controller is taken as the duty ratio of a small vector, and the direct-through state is injected into a zero vector [ PPP ] in consideration, so that the duty ratio of each basic voltage vector is further obtained as follows:
Figure BDA0003871398070000131
where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively, y np Output quantity of the DC side capacitor voltage balance controller, d st Is the through duty cycle.
In order to ensure that the duty ratio of each basic voltage vector is more than 0 and less than 1, the output quantity y of the DC side capacitor voltage balance controller np Performing amplitude limiting processing, namely:
Figure BDA0003871398070000132
when the Flag bit Flag =4, the basic voltage vector includes a large vector [ PPN ], a medium vector [ PON ], a small vector [ PPO ], and a zero vector [ PPP ], and the equation set is written by using the volt-second balance principle:
Figure BDA0003871398070000133
wherein, V 2 、V 7 、V 12 And V 0 Respectively representing large vectors [ PPN]Middle vector [ PON ]]Small vector of PPO]And zero vector PPP]，d 2 、d 7 、d 12 And d 0 Respectively representing large vectors [ PPN]Middle vector [ PON ]]Small vector [ PPO ]]And zero vector PPP]Duty ratio of V ref Is a reference voltage vector.
The output quantity of the direct current side capacitor voltage balance controller is taken as the duty ratio of a small vector, and the direct-through state is injected into a zero vector [ PPP ] in consideration, so that the duty ratio of each basic voltage vector is further obtained as follows:
Figure BDA0003871398070000134
where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively, y np Output quantity of the DC side capacitor voltage balance controller, d st Is the through duty cycle.
In order to ensure that the duty ratio of each basic voltage vector is more than 0 and less than 1, the output quantity y of the DC side capacitor voltage balance controller np By amplitude limiting, i.e.
Figure BDA0003871398070000141
When the Flag of the switch sequence takes other values, a similar method can be adopted and the symmetry of the space vector diagram is combined to complete the solving process.
(3) When the Flag bit Flag of the switching sequence is =5,14, the output quantity of the direct-current side capacitor voltage balance controller is used as the variable quantity of the duty ratio distribution factor of the small vector, an indirect calculation mode is further designed, the duty ratios of the two large vectors and the two small vectors are solved, and meanwhile, the output quantity of the direct-current side capacitor voltage balance controller needs to be subjected to amplitude limiting processing, so that the duty ratios of all basic voltage vectors are ensured to be larger than 0 and smaller than 1.
Without loss of generality, taking the switch sequence Flag =5 as an example, detailed solving steps are given as follows.
When the switch sequence Flag =5, the basic voltage vector includes a large vector [ PPN ], a large vector [ NPN ], a small vector [ PPO ], and a small vector [ NON ], and the equation set is written by using the volt-second balance principle:
Figure BDA0003871398070000142
wherein, V 2 、V 3 、V 12 And V 13 Respectively represent large vectors [ PPN]Large vector of NPN]Small vector [ PPO ]]And small vector [ NON ]]，d 2 、d 3 、d 12 And d 13 Respectively representing large vectors [ PPN]Large vector of NPN]Small vector [ PPO ]]Sum small vector [ NON]Duty ratio of V ref Is a vector of reference voltages.
The expression of each basic voltage vector is substitutedFormula (12) in combination with the definition of modulation degree (formula (4)), and duty ratio d can be simplified 12 And d 13 Satisfies the following conditions:
d 12 +d 13 ＝2-2·m·sinθ (14)
introducing a small vector duty cycle division factor lambda (0)<λ<1) For representing duty cycle d 12 、d 13 I.e. by
Figure BDA0003871398070000143
The duty cycle of each fundamental voltage vector may be further expressed as:
Figure BDA0003871398070000151
obviously, the duty ratio of each basic voltage vector should be greater than 0 and less than 1, and meanwhile, the duty ratio of the small vector should be greater than the through duty ratio so as to accurately inject the through state to realize the boosting function. Therefore, the small vector duty cycle allocation factor λ satisfies the following constraint:
Figure BDA0003871398070000152
by comprehensively considering all constraint conditions which should be met by the small vector duty ratio distribution factor lambda, the following conditions can be obtained:
λ min <λ<λ max (18)
wherein λ is max And λ min As shown in formulas (18) and (19), respectively:
Figure BDA0003871398070000153
Figure BDA0003871398070000154
taking small vector duty cyclesWith a factor of lambda initial value λ 0 Is λ max And λ min Is an arithmetic mean of
Figure BDA0003871398070000161
Considering capacitance C in quasi-Z source network 2 And C 3 And taking the output quantity of the direct-current side capacitor voltage balance controller as the variable quantity of the small-vector duty ratio distribution factor to obtain a small-vector duty ratio distribution factor correction value as follows:
Figure BDA0003871398070000162
and (3) carrying out amplitude limiting processing on the correction value of the small vector duty ratio distribution factor by using the constraint conditions given by the formula (17) to the formula (19), and then substituting the correction value into the formula (15), so that the duty ratio of each basic voltage vector can be updated, and further the midpoint voltage balance control is realized.
In order to realize the boosting function, a lower through state and an upper through state are respectively injected into small vectors [ PPO ] and [ NON ], and the duty ratio of each basic voltage vector is further updated as follows:
Figure BDA0003871398070000163
when the Flag of the switch sequence takes other values, a similar method can be adopted and the symmetry of the space vector diagram is combined to complete the solving process.
Step S5: according to the duty ratio of a switch sequence zone bit and a basic voltage vector, considering factors such as low output harmonic content, as little as possible switching loss and the like, designing a switch sequence, converting the switch sequence into a PWM (pulse-width modulation) driving signal of a power switch tube, and controlling an asymmetric quasi-Z-source three-level inverter to work.
Designing a switch sequence, wherein the specific rule is as follows:
when the switch sequence Flag is =1, the switch sequence is designed to:
PPP-FFF-PON-PNN-PON-FFF-PPP；
when the switch sequence Flag is =2, the switch sequence is designed to:
PPP-FFF-POO-PON-PNN-PON-POO-FFF-PPP；
when the switch sequence Flag is =3, the switch sequence is designed to:
PPP-FFF-PON-PPN-PON-FFF-PPP；
when the switch sequence Flag =4, the switch sequence is designed to:
PPP-FFF-PPO-PON-PPN-PON-PPO-FFF-PPP；
when the switch sequence Flag =5, the switch sequence is designed to:
PPO-PPD-PPN-NPN-NUN-NON-NUN-NPN-PPN-PPD-PPO；
when the switch sequence Flag is =6, the switch sequence is designed to:
NNN-FFF-NPO-NPN-NPO-FFF-NNN；
when the Flag of the switching sequence is =7, the switching sequence is designed as follows:
NNN-FFF-NON-NPO-NPN-NPO-NON-FFF-NNN；
when the Flag of the switching sequence is =8, the switching sequence is designed as follows:
NNN-FFF-NPO-NPP-NPO-FFF-NNN；
when the switch sequence Flag is =9, the switch sequence is designed to:
NNN-FFF-NOO-NPO-NPP-NPO-NOO-FFF-NNN；
when the switch sequence Flag is =10, the switch sequence is designed to:
NNN-FFF-NOP-NPP-NOP-FFF-NNN；
when the switch sequence Flag is =11, the switch sequence is designed to:
NNN-FFF-NOO-NOP-NPP-NOP-NOO-FFF-NNN；
when the switch sequence Flag is =12, the switch sequence is designed to:
NNN-FFF-NOP-NNP-NOP-FFF-NNN；
when the switch sequence Flag is =13, the switch sequence is designed to:
NNN-FFF-NNO-NOP-NNP-NOP-NNO-FFF-NNN；
when the switch sequence Flag is =14, the switch sequence is designed to:
NNO-NNU-NNP-PNP-PDP-POP-PDP-PNP-NNP-NNU-NNO；
when the switch sequence Flag is =15, the switch sequence is designed to:
PPP-FFF-PNO-PNP-PNO-FFF-PPP；
when the Flag of the switching sequence is =16, the switching sequence is designed as follows:
PPP-FFF-POP-PNO-PNP-PNO-POP-FFF-PPP；
when the switch sequence Flag is =17, the switch sequence is designed to:
PPP-FFF-PNO-PNN-PNO-FFF-PPP；
when the Flag of the switching sequence is =18, the switching sequence is designed as follows:
PPP-FFF-POO-PNO-PNN-PNO-POO-FFF-PPP。
and finally, converting the switching sequence into a PWM (pulse-width modulation) driving signal of a power switching tube, and controlling an asymmetric quasi-Z-source three-level inverter to work.
FIGS. 4 (a) and 4 (b) are waveforms illustrating the operation of the method of the present invention in a non-boost operating mode, including the DC input voltage (V) in ) quasi-Z source network output voltage (V) dc ) Line voltage (v) ab 、v bc 、v ca ) Three-phase output current (i) a 、i b 、i c ) DC side capacitor voltage (V) C1 、V C2 、V C3 、V C4 ). At this time, the dc input voltage is set to 400V, and the modulation degree and the through duty are set to 0.8 and 0, respectively.
The working waveform diagram shows that: the output voltage of the quasi-Z source network is basically equal to the direct current input voltage; line voltage v ab And v ca In an asymmetrical five-level waveform, line voltage v bc Is a symmetrical five-level waveform; the output current is a three-phase symmetrical sine waveform; DC side capacitor C 2 And C 3 The voltages at the two ends are equal, are both 200V, and have small fluctuation, and the method can effectively control the midpoint voltage balance.
FIGS. 5 (a) and 5 (b) are waveforms illustrating the operation of the method of the present invention in boost mode, including the DC input voltage (V) in ) quasi-Z source network output voltage (V) dc ) Line voltage (v) ab 、v bc 、v ca ) Three-phase output current (i) a 、i b 、i c ) DC side capacitor voltage (V) C1 、V C2 、V C3 、V C4 ). At this time, the dc input voltage was set to 300V, and the modulation degree and the through duty were set to 0.8 and 0.125, respectively.
From the working waveform diagram, it can be seen that: the amplitude of the output voltage of the quasi-Z source network is 400V, which is higher than the direct current input voltage, and the method provided by the invention can realize the normal boosting function of the system; when the full-through state is injected in the zero vector, the output voltage of the quasi-Z source network is changed within the range of 0 to 400V; when the upper direct connection state and the lower direct connection state are injected into a small vector, the output voltage of the quasi-Z source network is changed within the range of 200V to 400V; capacitor C 2 And C 3 The voltages at the two ends are equal and the fluctuation is very small, which shows that the method can effectively control the midpoint voltage balance.
FIG. 6 (a) is a waveform diagram of the operation of the method of the present invention in the non-boost operation mode, when the modulation degree changes from 0.6 step to 0.8, including the DC input voltage (V) in ) quasi-Z source network output voltage (V) dc ) Line voltage (v) ab ) Three-phase output current (i) a 、i b 、i c ) Dc side capacitor voltage (V) C1 、V C2 、V C3 、V C4 ). FIG. 6 (b) is a waveform diagram of the operation of the method of the present invention in the boost operation mode when the modulation degree changes from 0.6 to 0.8 in steps, including the DC input voltage (V) in ) quasi-Z source network output voltage (V) dc ) Line voltage (v) ab ) Three-phase output current (i) a 、i b 、i c ) DC side capacitor voltage (V) C1 、V C2 、V C3 、V C4 )。
From the working waveform diagram, it can be seen that: when the modulation degree is increased in a step mode, the amplitude of the three-phase output current is correspondingly increased; meanwhile, the boosting function of the system and the neutral point voltage balance control are not influenced, and the effectiveness of the method is verified.
FIG. 7 (a) is a waveform diagram illustrating the operation of the method of the present invention from the enabled to the disabled of the midpoint voltage balance control in the non-boost operating mode, including the DC input voltage (V) in ) quasi-Z source network output voltage (V) dc ) Line voltage (v) ab ) Three-phase output current (i) a 、i b 、i c ) Dc side capacitor voltage (V) C2 、V C3 ). FIG. 7 (b) is a waveform diagram illustrating the operation of the method of the present invention from the enabled to the disabled of the midpoint voltage balance control in the boost mode of operation, including the DC input voltage (V) in ) quasi-Z source network output voltage (V) dc ) Line voltage (v) ab ) Three-phase output current (i) a 、i b 、i c ) DC side capacitor voltage (V) C2 、V C3 )。
To verify the midpoint voltage balance control function of the method of the present invention, at capacitor C 2 、C 3 The two ends are respectively connected with resistors with the resistance values of 1k omega and 10k omega in parallel. Before the simulation time is 0.6s, the midpoint balance control function is enabled, at the moment, the voltages at two ends of the two capacitors can be kept equal, and the method can effectively control midpoint voltage balance. After the simulation time is 0.6s, the midpoint balance control function is cancelled, the voltages at two ends of the two capacitors are obviously deviated, and the midpoint voltage balance state cannot be kept, so that the method has the midpoint voltage balance active control capability.
Example two
The embodiment discloses a space vector modulation system of an asymmetric quasi-Z source three-level inverter;
the space vector modulation system of the asymmetric quasi-Z source three-level inverter comprises a sector judgment module, a zone bit calculation module, a direct-current side capacitance voltage balance control module, a duty ratio calculation module and a switch design module;
a sector determination module configured to: judging the sector of the reference voltage vector in the space vector diagram according to the amplitude and the phase angle of the reference voltage vector;
a flag bit calculation module configured to: selecting corresponding basic voltage vectors by combining the voltage deviation of the two capacitors in the sector where the reference voltage vector is located and the quasi-Z source network, and calculating a switch sequence zone bit;
a DC side capacitance voltage balance control module configured to: adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller;
a duty cycle calculation module configured to: based on the switch sequence zone bit, selecting and injecting different types of direct-connection states, calculating the duty ratio of a basic voltage vector, and limiting the output quantity of the direct-current side capacitor voltage balance controller according to the calculated duty ratio;
a switch design module configured to: and designing a switching sequence according to the duty ratio of the switch sequence zone bit and the basic voltage vector, and controlling the work of the asymmetric quasi-Z source three-level inverter.
EXAMPLE III
An object of the present embodiment is to provide a computer-readable storage medium.
A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, implements the steps in the space vector modulation method of an asymmetric quasi-Z-source three-level inverter according to embodiment 1 of the present disclosure.
Example four
An object of the present embodiment is to provide an electronic apparatus.
Electronic equipment, including memory, a processor and a program stored on the memory and executable on the processor, the processor when executing the program realizes the steps in the space vector modulation method of the asymmetric quasi-Z source three-level inverter according to embodiment 1 of the present disclosure.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The space vector modulation method of the asymmetric quasi-Z source three-level inverter is characterized by comprising the following steps:
judging the sector of the reference voltage vector in the space vector diagram according to the amplitude and the phase angle of the reference voltage vector;
selecting corresponding basic voltage vectors by combining the voltage deviation of the two capacitors in the sector where the reference voltage vector is located and the quasi-Z source network, and generating a switch sequence flag bit;
adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller;
based on the switch sequence zone bit, selecting and injecting different types of through states, calculating the duty ratio of a basic voltage vector, and limiting the output quantity of the direct current side capacitor voltage balance controller according to the calculated duty ratio;
and designing a switching sequence according to the duty ratio of the switch sequence zone bit and the basic voltage vector, converting the switching sequence into a PWM (pulse-width modulation) driving signal of a power switch tube, and controlling the work of the asymmetric quasi-Z-source three-level inverter.
2. The space vector modulation method of the asymmetric quasi-Z-source three-level inverter as claimed in claim 1, wherein the midpoint voltage balance control threshold Δ V is set according to the midpoint voltage balance control requirement of the system np_th Combining the Sector in which the reference voltage vector is located with the capacitor C 2 、C 3 Voltage deviation Δ V of np Selecting corresponding basic voltage vectors according to a rule to synthesize a reference voltage vector and generating a Flag bit Flag of a switch sequence, wherein the specific rule is as follows:
when Sector =1 and Δ V np ≤ΔV np_th Then, choose the large vector [ PNN]Middle vector [ PON ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =1 of a switching sequence;
when Sector =1 and Δ V np >ΔV np_th Then, choose the large vector [ PNN]Middle vector [ PON ]]Small vector [ POO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =2 in a switching sequence;
when Sector =2 and Δ V np ≤ΔV np_th Then, select the large vector [ PPN]Middle vector [ PON ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =3 of a switching sequence;
when Sector =2 and Δ V np >ΔV np_th Then, select the large vector [ PPN]Middle vector [ PON ]]Small vector of PPO]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =4 of a switching sequence;
when a Sector =3 or 4, selecting a large vector [ PPN ], a large vector [ NPN ], a small vector [ PPO ] and a small vector [ NON ] to synthesize a reference voltage vector, simultaneously injecting a lower through state into the small vector [ PPO ], and injecting an upper through state into the small vector [ NON ] to realize a boosting function, wherein a switch sequence Flag =5;
when Sector =5 and Δ V np ≥-ΔV np_th Then, select the large vector (NPN)]Middle vector [ NPO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected, a boosting function is realized, and a Flag bit of a switching sequence is =6;
when Sector =5 and Δ V np <-ΔV np_th Then, select the large vector (NPN)]Middle vector [ NPO ]]Small vector of [ NON ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =7 of a switching sequence;
when Sector =6 and Δ V np ≥-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NPO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected to realize a boosting function, and the Flag bit Flag =8 of a switch sequence;
when Sector =6 and Δ V np <-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NPO ]]Small vector of [ NOO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected to realize a boosting function, and the Flag bit Flag =9 of a switch sequence;
when Sector =7 and Δ V np ≥-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NOP ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected, a boosting function is realized, and a Flag bit of a switching sequence is =10;
when Sector =7 and Δ V np <-ΔV np_th Then, choose the large vector [ NPP]Middle vector [ NOP]Small vector of [ NOO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected to realize a boosting function, and the Flag bit Flag =11 of a switching sequence;
when Sector =8 and Δ V np ≥-ΔV np_th Then, select the large vector [ NNP ]]Middle vector [ NOP]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector NNN]A full-through state is injected to realize a boosting function, and the Flag bit Flag =12 of a switching sequence;
when Sector =8 and Δ V np <-ΔV np_th Then, select the large vector [ NNP ]]Middle vector [ NOP]Small vector of [ NNO ]]Zero vector [ NNN ]]Synthesizing reference voltage vectors while in the zero vector [ NNN ]]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =13 of a switching sequence;
when the Sector =9 or 10, selecting a large vector [ NNP ], a large vector [ PNP ], a small vector [ POP ] and a small vector [ NNO ] to synthesize a reference voltage vector, simultaneously injecting a lower through state into the small vector [ POP ], and injecting an upper through state into the small vector [ NNO ], so that a boosting function is realized, and the Flag bit Flag =14 of the switching sequence;
when Sector =11 and Δ V np ≤ΔV np_th Then, choose the large vector [ PNP ]]Middle vector [ PNO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =15 of a switching sequence;
when the Sector =11,And Δ V np >ΔV np_th Then, choose the large vector [ PNP ]]Middle vector [ PNO ]]Small vector [ POP]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected to realize a boosting function, and the Flag bit Flag =16 of a switching sequence;
when Sector =12 and Δ V np ≤ΔV np_th Then, choose the large vector [ PNN]Middle vector [ PNO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]A full-through state is injected, a boosting function is realized, and a Flag bit Flag =17 of a switching sequence;
when Sector =12 and Δ V np >ΔV np_th Then, choose the large vector [ PNN]Middle vector [ PNO ]]Small vector [ POO ]]Zero vector [ PPP ]]Synthesizing reference voltage vectors while in the zero vector PPP]And a full-through state is injected, a boosting function is realized, and the Flag bit Flag =18 of the switching sequence.
3. The space vector modulation method of the asymmetric quasi-Z source three-level inverter as claimed in claim 1, characterized in that the voltage deviation Δ V of two capacitors in the quasi-Z source network np And sending the output value to a PI regulator, and further taking an absolute value for operation to obtain the output quantity of the direct current side capacitor voltage balance controller.
4. The space vector modulation method of the asymmetric quasi-Z-source three-level inverter as claimed in claim 1, wherein a basic voltage vector duty cycle calculation mode is determined according to the value of a switch sequence flag bit; writing an equation set by using a volt-second balance principle, and solving the duty ratio of a basic voltage vector;
when the Flag bit Flag of the switching sequence is =1,3,6,8,10,12,15 and 17, the duty ratio of a large vector, a medium vector and a zero vector is solved by adopting a direct calculation mode; when the Flag bits Flag of the switching sequence is =2,4,7,9,11,13,16 and 18, the output quantity of the direct-current side capacitance voltage balance controller is used as the duty ratio of a small vector, an indirect calculation mode is further designed, the duty ratios of a large vector, a middle vector and a zero vector are solved, and meanwhile, the output quantity of the direct-current side capacitance voltage balance controller needs to be subjected to amplitude limiting processing so as to ensure that the duty ratios of all basic voltage vectors are greater than 0 and less than 1; when the Flag bit Flag of the switching sequence is =5,14, the output quantity of the direct-current side capacitor voltage balance controller is used as the variable quantity of the distribution factor of the duty ratio of the small vector, an indirect calculation mode is further designed, the duty ratios of the two large vectors and the two small vectors are solved, and meanwhile, the output quantity of the direct-current side capacitor voltage balance controller needs to be subjected to amplitude limiting processing, so that the duty ratios of all basic voltage vectors are guaranteed to be larger than 0 and smaller than 1.
5. The space vector modulation method of the asymmetric quasi-Z source three-level inverter as claimed in claim 1, wherein when the switch sequence Flag =1, the duty ratios of the large vector [ PNN ], the medium vector [ PON ], and the zero vector [ PPP ] are respectively the duty ratios
Figure FDA0003871398060000041
Where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively, d st Is the through duty cycle;
when the switch sequence Flag is =3, the duty ratios of the large vector [ PPN ], the medium vector [ PON ], and the zero vector [ PPP ] are respectively
Figure FDA0003871398060000051
Where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively, d st Is the through duty cycle;
when the Flag of the switching sequence is =2, the duty ratios of the large vector [ PNN ], the medium vector [ PON ], the small vector [ POO ] and the zero vector [ PPP ] are respectively equal to
Figure FDA0003871398060000052
Wherein m and theta are the modulation degree and the phase angle of the reference voltage vector, respectively,y np output quantity of the DC side capacitor voltage balance controller, d st Is the through duty cycle; output y to DC side capacitor voltage balance controller np As a clipping process, i.e.
Figure FDA0003871398060000053
When the switch sequence Flag =4, the duty ratios of the large vector [ PPN ], the medium vector [ PON ], the small vector [ PPO ], and the zero vector [ PPP ] are respectively equal to
Figure FDA0003871398060000054
Where m and θ are the modulation degree and the phase angle of the reference voltage vector, respectively, y np Output quantity of the DC side capacitor voltage balance controller, d st Is the through duty cycle; output y to DC side capacitor voltage balance controller np As a clipping process, i.e.
Figure FDA0003871398060000061
When the switch sequence Flag =5, the duty ratios of the large vector [ PPN ], the large vector [ NPN ], the small vector [ PPO ], and the small vector [ NON ] are respectively equal to
Figure FDA0003871398060000062
Wherein the content of the first and second substances,
Figure FDA0003871398060000063
Figure FDA0003871398060000064
Figure FDA0003871398060000065
Figure FDA0003871398060000066
y np the output quantity of the DC side capacitor voltage balance controller;
when the Flag of the switch sequence takes other values, a similar method can be adopted and the symmetry of the space vector diagram is combined to complete the solving process.
6. The space vector modulation method of the asymmetric quasi-Z-source three-level inverter according to claim 1, wherein the selective injection of the different types of shoot-through states is performed by: when the Flag bit Flag of the switching sequence is =5 or 14, a lower through state is injected into the P-type small vector, and an upper through state is injected into the N-type small vector, so that the boosting function is realized, and the normal output alternating voltage of the system is not influenced; when the Flag bit Flag of the switching sequence takes other values, a full-through state is injected into the zero vector [ PPP ] or [ NNN ], so that the boosting function is realized, and the normal output alternating voltage of the system is not influenced.
7. The space vector modulation method of the asymmetric quasi-Z-source three-level inverter according to claim 1, wherein the switching sequence is designed according to a value of a flag bit of the switching sequence, and specifically, the method comprises the following steps:
when the switch sequence Flag is =1, the switch sequence is designed to:
PPP-FFF-PON-PNN-PON-FFF-PPP；
when the switch sequence Flag is =2, the switch sequence is designed to:
PPP-FFF-POO-PON-PNN-PON-POO-FFF-PPP；
when the switch sequence Flag is =3, the switch sequence is designed to:
PPP-FFF-PON-PPN-PON-FFF-PPP；
when the Flag of the switching sequence is =4, the switching sequence is designed as follows:
PPP-FFF-PPO-PON-PPN-PON-PPO-FFF-PPP；
when the switch sequence Flag =5, the switch sequence is designed to:
PPO-PPD-PPN-NPN-NUN-NON-NUN-NPN-PPN-PPD-PPO；
when the switch sequence Flag is =6, the switch sequence is designed to:
NNN-FFF-NPO-NPN-NPO-FFF-NNN；
when the Flag of the switching sequence is =7, the switching sequence is designed as follows:
NNN-FFF-NON-NPO-NPN-NPO-NON-FFF-NNN；
when the switch sequence Flag is =8, the switch sequence is designed as follows:
NNN-FFF-NPO-NPP-NPO-FFF-NNN；
when the switch sequence Flag is =9, the switch sequence is designed to:
NNN-FFF-NOO-NPO-NPP-NPO-NOO-FFF-NNN；
when the switch sequence Flag is =10, the switch sequence is designed to:
NNN-FFF-NOP-NPP-NOP-FFF-NNN；
when the switch sequence Flag is =11, the switch sequence is designed to:
NNN-FFF-NOO-NOP-NPP-NOP-NOO-FFF-NNN；
when the switch sequence Flag is =12, the switch sequence is designed to:
NNN-FFF-NOP-NNP-NOP-FFF-NNN；
when the switch sequence Flag is =13, the switch sequence is designed to:
NNN-FFF-NNO-NOP-NNP-NOP-NNO-FFF-NNN；
when the Flag of the switching sequence is =14, the switching sequence is designed as follows:
NNO-NNU-NNP-PNP-PDP-POP-PDP-PNP-NNP-NNU-NNO；
when the Flag of the switching sequence is =15, the switching sequence is designed as follows:
PPP-FFF-PNO-PNP-PNO-FFF-PPP；
when the switch sequence Flag is =16, the switch sequence is designed to:
PPP-FFF-POP-PNO-PNP-PNO-POP-FFF-PPP；
when the Flag of the switching sequence is =17, the switching sequence is designed as follows:
PPP-FFF-PNO-PNN-PNO-FFF-PPP；
when the switch sequence Flag is =18, the switch sequence is designed to:
PPP-FFF-POO-PNO-PNN-PNO-POO-FFF-PPP。
8. the space vector modulation system of the asymmetric quasi-Z-source three-level inverter is characterized by comprising a sector judgment module, a zone bit calculation module, a direct-current side capacitance voltage balance control module, a duty ratio calculation module and a switch design module;
a sector determination module configured to: judging the sector of the reference voltage vector in the space vector diagram according to the amplitude and the phase angle of the reference voltage vector;
a flag bit calculation module configured to: selecting corresponding basic voltage vectors by combining the sector where the reference voltage vector is located and the voltage deviation of two capacitors in the quasi-Z source network, and calculating a switch sequence zone bit;
a DC side capacitance voltage equalization control module configured to: adjusting voltage deviation of two capacitors in the Z source network to obtain output quantity of the direct current side capacitor voltage balance controller;
a duty cycle calculation module configured to: based on the switch sequence zone bit, selecting and injecting different types of direct-connection states, calculating the duty ratio of a basic voltage vector, and limiting the output quantity of the direct-current side capacitor voltage balance controller according to the calculated duty ratio;
a switch design module configured to: and designing a switching sequence according to the duty ratio of the switch sequence zone bit and the basic voltage vector, converting the switching sequence into a PWM (pulse-width modulation) driving signal of a power switch tube, and controlling the work of the asymmetric quasi-Z-source three-level inverter.
9. Computer readable storage medium, on which a program is stored which, when being executed by a processor, carries out the steps of the method for space vector modulation of an asymmetric quasi-Z-source three-level inverter according to any one of claims 1 to 7.
10. Electronic device comprising a memory, a processor and a program stored on the memory and executable on the processor, characterized in that the processor when executing the program implements the steps in the method for space vector modulation of an asymmetric quasi-Z source three-level inverter as claimed in any of the claims 1 to 7.
CN202211198260.5A 2022-09-29 2022-09-29 Space vector modulation method and system of asymmetric quasi-Z-source three-level inverter Pending CN115459621A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117424474A (en) * 2023-11-02 2024-01-19 西安航空学院 Modulation method for reducing inductance current pulsation of quasi-Z source inverter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117424474A (en) * 2023-11-02 2024-01-19 西安航空学院 Modulation method for reducing inductance current pulsation of quasi-Z source inverter
CN117424474B (en) * 2023-11-02 2024-05-24 西安航空学院 Modulation method for reducing inductance current pulsation of quasi-Z source inverter

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