CN115458514A - Half-bridge module - Google Patents

Half-bridge module Download PDF

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Publication number
CN115458514A
CN115458514A CN202211256626.XA CN202211256626A CN115458514A CN 115458514 A CN115458514 A CN 115458514A CN 202211256626 A CN202211256626 A CN 202211256626A CN 115458514 A CN115458514 A CN 115458514A
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CN
China
Prior art keywords
substrate
bridge module
chip
port
chip set
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CN202211256626.XA
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Chinese (zh)
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张学伦
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Jiguang Semiconductor Shaoxing Co ltd
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Jiguang Semiconductor Shaoxing Co ltd
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Priority to CN202211256626.XA priority Critical patent/CN115458514A/en
Publication of CN115458514A publication Critical patent/CN115458514A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a half-bridge module. The first substrate provided with the first chip set and the second substrate provided with the second chip set are stacked, so that the whole size of the half-bridge module is reduced. The layout adjustment of the DC + port, the DC-port and the AC port is combined to correspondingly change a current main loop of the half-bridge circuit, so that the current main loop can generate a larger mutual inductance effect, and the inductance of the main loop is reduced. In addition, the half-bridge module can also utilize the first substrate and the second substrate to dissipate heat simultaneously, so that the heat dissipation effect of the half-bridge module is effectively improved.

Description

Half-bridge module
Technical Field
The invention relates to the technical field of semiconductors, in particular to a half-bridge module.
Background
In recent years, with the progress of semiconductor technology, the third generation wide bandgap power semiconductor is rapidly developed, and the SiC device has the characteristics of small on-resistance, high breakdown field strength, high switching speed, high temperature resistance and the like, so that the SiC device is widely applied to application scenes of high frequency, high voltage, high temperature and the like, and is beneficial to improving the efficiency and the power density of a power electronic system. In a half-bridge module based on a silicon carbide chip, the problem of parasitic inductance generally exists, and the problem of serious voltage overshoot and the like easily caused by the large parasitic inductance in the process of high-speed switching of a SiC device is solved.
In the existing half-bridge module, an upper bridge chip and a lower bridge chip are respectively and independently packaged in two modules, and the two modules are connected in series to form a half-bridge circuit, so that the half-bridge module is large in size. And the current main loop of the half-bridge module transversely flows to the DC-port from the DC + port, and the whole main loop has no mutual inductance, so that larger stray inductance exists. An improvement mode is that a large busbar is arranged above a half-bridge module, and a DC-port is led out from the large busbar, so that mutual inductance of a current main loop is realized by the large busbar, and the aim of reducing stray inductance is fulfilled. Although the inductance of the main circuit can be reduced through the large busbar, a large optimization space still exists; in addition, the additionally arranged large busbar brings extra loss on one hand, and on the other hand, the large busbar is also easily oxidized, so that the performance of the bridge module is influenced.
Disclosure of Invention
The invention aims to provide a half-bridge module, which is used for reducing the inductance of the half-bridge module, reducing the size of the half-bridge module and improving the heat dissipation performance of the half-bridge module.
To this end, the invention provides a half-bridge module comprising: the chip module comprises a first substrate, a second substrate and a third substrate, wherein a first chip group is arranged on the first substrate; the second substrate is provided with a second chip set, the second substrate and the first substrate are oppositely arranged, and the first chip set and the second chip set are positioned between the first substrate and the second substrate; and the DC + port is electrically connected with the first chip set and extends out of the first end of the half-bridge module, the DC-port is electrically connected with the second chip set and extends out of the first end of the half-bridge module, and the AC port is electrically connected between the first chip set and the second chip set and extends out of the second end of the half-bridge module.
Optionally, the first substrate has a first metal region, and the first chip group is disposed on the first metal region; the second substrate is provided with a second metal area, and the second chip set is arranged on the second metal area.
Optionally, the DC + port is attached to the first metal region to connect to a chip drain in the first chip group; the AC port is attached to the second metal area so as to be connected with a chip drain electrode in the second chip set; and the DC-port is electrically connected with the chip source electrode in the second chip group.
Optionally, a connecting member is disposed between the first substrate and the second substrate, and the connecting member is electrically connected to each chip in the first chip set and the second substrate, so that the chip source electrode of the first chip set is electrically connected to the chip drain electrode in the second chip set.
Optionally, a support is disposed between the first substrate and the second substrate, and the support is disposed between each chip in the second chip group and the first substrate.
Optionally, the DC-port has at least one contact pad, each contact pad contacting each chip in the second chipset in a one-to-one correspondence, and the contact pad is sandwiched between the support and the corresponding chip.
Optionally, the first chip set is disposed in a region of the first substrate near the second end, and the second chip set is disposed in a region of the second substrate near the first end.
Optionally, the first chip set is disposed in a region of the first substrate near the first end, and the second chip set is disposed in a region of the second substrate near the second end.
Optionally, the DC-port has a contact pad, a connection arm and an extension port, the contact pad contacts a chip in the second chipset, the connection arm connects the contact pad and extends toward the first end to connect with the extension port, and the extension port extends from the first end of the half-bridge module.
Optionally, the stacked first substrate and second substrate are packaged to form a sub-module, and the half-bridge module has one sub-module or several sub-modules connected in parallel.
Optionally, the chips in the first chip set and the second chip set are silicon carbide chips.
In the half-bridge module provided by the invention, the first substrate provided with the first chip set and the second substrate provided with the second chip set are stacked, so that the whole size of the half-bridge module can be effectively reduced. And the layout adjustment of the DC + port, the DC-port and the AC port is combined to correspondingly change a current main loop of the half-bridge circuit, so that the current main loop can generate a larger mutual inductance effect, and the inductance of the main loop is reduced. The method specifically comprises the following steps: the DC + port and the DC-port extend out of the first end of the half-bridge module, the AC port extends out of the second end of the half-bridge module, so that current flowing from the first end to the second end and current flowing from the second end to the first end exist in a current main loop of the half-bridge circuit, and the mutual inductance effect can be realized by the currents flowing in opposite directions.
In addition, the first substrate and the second substrate of the half-bridge module are arranged face to face, so that the first substrate and the second substrate can be used for radiating heat simultaneously, and the radiating effect of the half-bridge module is effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a half-bridge module according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of a half-bridge module according to a first embodiment of the invention.
Fig. 3 is a schematic diagram of a first substrate and a second substrate of a half-bridge module according to a first embodiment of the invention.
Fig. 4 is a simplified equivalent circuit diagram of a half-bridge module according to a first embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a split half-bridge module according to a second embodiment of the invention.
Fig. 6 is a schematic diagram of a first substrate and a second substrate of a half-bridge module according to a second embodiment of the invention.
Fig. 7 is a schematic diagram of a half-bridge module provided by the present invention having a sub-module.
Fig. 8 is a schematic diagram of a half-bridge module provided by the present invention having a plurality of sub-modules.
Wherein the reference numbers are as follows:
100-a first substrate;
110-a first metal region;
200-a second substrate;
210-a second metal region;
300H-a first chipset;
300L-a second chipset;
410-a connector;
420-a support;
510-a contact pad;
520-a linker arm;
530-an epitaxial port;
700-lead wire.
Detailed Description
The half-bridge module according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It will be understood that relative terms, such as "above," "below," "top," "bottom," "above," and "below," may be used in relation to various elements shown in the figures. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures. For example, if the device were inverted relative to the view in the drawings, an element described as "above" another element, for example, would now be below that element.
< first embodiment >
Fig. 1 is a schematic structural diagram of a half-bridge module according to a first embodiment of the present invention, fig. 2 is a schematic exploded view of the half-bridge module according to the first embodiment of the present invention, fig. 3 is a schematic diagram of a first substrate and a second substrate of the half-bridge module according to the first embodiment of the present invention, and fig. 4 is a simplified equivalent circuit diagram of the half-bridge module according to the first embodiment of the present invention.
Referring first to fig. 1 and 2, the half bridge module in the present embodiment includes a first substrate 100 and a second substrate 200 stacked, and the first substrate 100 and the second substrate 200 are disposed opposite to each other. The first substrate 100 is provided with a first chip set 300H, the second substrate 200 is provided with a second chip set 300L, and the first chip set 300H and the second chip set 300L are located between the first substrate 100 and the second substrate 200. In a specific example, the first chip set 300H forms an upper bridge chip of a half-bridge module, for example, and the second chip set 300L forms a lower bridge chip of the half-bridge module, for example.
Further, the chips in the first chip set 300H and the second chip set 300L are, for example, silicon carbide chips. And, the current capacity of a single chip is limited, so that the current can be spread in a manner that a plurality of chips are connected in parallel in a high-power situation, and thus the first chip set 300H and the second chip set 300L may each include at least two chips connected in parallel, for example, two chips, four chips, or six chips, and the like. In this embodiment, the first chipset 300H and the second chipset 300L are each described as including two chips.
With continued reference to fig. 1 and 2, the half-bridge module further includes: a DC + port, a DC-port, and an AC port. The DC + port is electrically connected to the first chipset 300H and extends from a first end of the half-bridge module; the DC-port is electrically connected to the second chip set 300L and extends from a first end of the half bridge module; the AC port is electrically connected between the first chipset 300H and the second chipset 300L and extends from a second end of the half-bridge module, where the first end and the second end are opposite ends of the half-bridge module.
Referring next to fig. 1 and 4, in the present embodiment, the current paths in the half-bridge module are, for example: the current entering the DC + port flows through the first chipset 300H on the first substrate 100 in the direction from the first end to the second end of the half-bridge module, then flows to the second substrate 200, and further flows from the second end to the first end of the half-bridge module, to pass through the second chipset 300L on the second substrate 200, and further flows to the DC-port. That is, the current on the first substrate 100 flows along the direction from the first end to the second end (i.e., the direction from the right to the left in fig. 1), the current on the second substrate 200 flows along the direction from the second end to the first end (i.e., the direction from the left to the right in fig. 1), and the flowing directions of the upper and lower currents are opposite, so that the mutual inductance effect can be realized, and the main loop inductance can be effectively reduced.
In addition, in this embodiment, the first chip set 300H and the second chip set 300L are respectively disposed on the first substrate 100 and the second substrate 200, and the first substrate 100 and the second substrate 200 are stacked, so that the size of the half-bridge module can be effectively reduced, and the first substrate 100 and the second substrate 200 can be used to dissipate heat from the upper side and the lower side of the half-bridge module, thereby effectively improving the heat dissipation effect of the half-bridge module.
Referring to fig. 3, the first substrate 100 has a first metal region 110 thereon, and the first chip group 300H is disposed on the first metal region 110. And, the second substrate 200 has a second metal region 210 thereon, and the second chipset 300L is disposed on the second metal region 210. In this embodiment, the chips in the first chip group 300H are disposed in the region of the first substrate 100 near the second end, and the chips in the first chip group 300H can be arranged along the direction perpendicular to the first end to the second end; the second chipset 300L is disposed in a region of the second substrate 200 near the first end, and the chips in the second chipset 300L may be arranged along a direction perpendicular to the first end to the second end.
Further, the DC + port is attached to the first metal region 110 to connect to the chip drain of the first chip set 300H; the AC port is attached to the second metal region 210 to connect to the drain of the chip of the second chipset 300L; and the DC-port is electrically connected to the chip sources of the second chipset 300L, thereby forming a half-bridge circuit as shown in fig. 4, for example.
In this embodiment, the DC + port is specifically attached to the first metal region 110 of the first substrate at a position close to the first end, and extends from the first end of the half-bridge module; the AC port is specifically attached to the second metal region 210 of the second substrate at a position near the second end and extends from the second end of the half-bridge module; the DC-port is mounted on the surface of the second chipset 300L and extends from the first end of the half-bridge module. In a specific example, the DC-port has at least one contact pad 510, and each contact pad 510 is electrically connected to each chip in a one-to-one correspondence; the DC-port in this embodiment has two contact pads 510 for connecting two chips in a one-to-one correspondence.
With continued reference to fig. 1 and fig. 2, at least one connecting member 410 is further disposed between the first substrate 100 and the second substrate 200, and the connecting member 410 is electrically connected to the first chip set 300H and the second metal region 210, so that the chip source of the first chip set 300H is electrically connected to the chip drain of the second chip set 300L. The connecting member 410 is, for example, a cylindrical structure, and two opposite ends of the connecting member respectively abut against the chip in the first chip group 300H and the second metal region 210.
In this embodiment, the first chip set 300H is disposed in a region of the first substrate 200 near the second end, and the connection member 410 is correspondingly disposed in a region near the second end, and the first substrate 100 and the second substrate 200 can be supported by the connection member 410 at a position near the second end. Based on this, a support 420 may be further disposed between the first substrate 100 and the second substrate 200, and the support 420 is particularly disposed in a region near the first end for supporting the first substrate 100 and the second substrate 200 at a position near the first end to improve stability of the entire module. In a specific example, the contact pads 510 of the DC-port are clamped between the support 420 and the chips of the second chipset 300L, ensuring a secure connection of the DC-port to the second chipset 300L.
Further, the support member 420 may be formed of an insulating material to be insulated from the first metal region 110. Alternatively, the supporting member 420 and the connecting member 410 may be both made of conductive materials, and at this time, an opening may be formed in the first metal region 110 at a position corresponding to the supporting member 420, and the supporting member 420 abuts against the substrate in the opening, so as to prevent the supporting member 420 and the first metal region 110 from being electrically connected. Alternatively, an island 130 is disposed at a position of the first substrate 100 corresponding to the support member 420, a trench exists between the island 130 and the first metal region 110 to isolate the two from each other, and one end of the support member 420 abuts against the island 130.
In this embodiment, the connecting member and the supporting member are not only used for electrically connecting and supporting the first substrate and the second substrate, but also used for providing a heat dissipation path for the chipset. Specifically, the heat generated by the first chip set 300H can be dissipated through the first substrate 100, and can be conducted to the second substrate 200 through the connecting member 410, and dissipated through the second substrate 200; similarly, the heat generated by the second chipset 300L can be dissipated through the second substrate 200, and can be conducted to the first substrate 100 through the supporting member 420, and can be dissipated through the first substrate 100. Therefore, the heat dissipation performance of the half-bridge module is further improved.
Continuing with reference to fig. 2, the half-bridge module further includes a first source port S H First gate terminal G H A second source terminal S L And a second gate port G L . The first source port S H Electrically connected to the source of the chip in the first chip set 300H, in this embodiment, the first source port S H Is connected to the AC port and extends from the second end of the half bridge module in common with the AC port. The first gate port G H Electrically connected to the chip gates of the first chip set 300H, in this embodiment, the first gate port G H Can be electrically connected to the first metal region 110 through a wire 700 (the first gate port G) H Specifically, it may be disposed at the second end of the half-bridge module), and further electrically connected to the die gate of the first die group 300H. The second source port S L Electrically connected to the source of the second chip set 300L, in this embodiment, the second source port S L Is connected to the DC-port and extends from the first end of the half-bridge module together with the DC-port. The first gate port G H Electrically connected to the chip gates of the first chip set 300H, in this embodiment, the second gate port G L Can be electrically connected to the second metal region 210 (the second gate port G) by a wire 700 L Particularly at the first end of the half-bridge module) and is electrically connected to the chip gate of the second chipset 300L.
It should be noted that the chip and the metal region, and the metal region and the port may be connected to each other through the lead 700.
< example two >
The difference from the first embodiment is that the first chip set in this embodiment is disposed in a region of the first substrate near the second end, and the second chip set is disposed in a region of the second substrate near the first end.
Fig. 5 is a schematic exploded view of a half-bridge module according to a second embodiment of the present invention, and fig. 6 is a schematic view of a first substrate and a second substrate of the half-bridge module according to the second embodiment of the present invention.
With reference to fig. 5 and fig. 6, in the embodiment, the first chip set 300H is disposed in a region of the first substrate 100 near the first end, and the second chip set 300L is disposed in a region of the second substrate 200 near the second end. That is, the arrangement positions of the first chipset and the second chipset in the second embodiment and the first embodiment are interchanged. Accordingly, the connecting member 410 is disposed adjacent to the first end, and the supporting member 420 is disposed adjacent to the second end.
Wherein, for the DC-port, its contact pad 510 will also be correspondingly disposed in the area near the second end to electrically connect with the second chip set 300L. Specifically, the DC-port has a contact pad 510, a connection arm 520 and an extension port 530, the contact pad 510 contacts the chip in the second chipset 300L, the connection arm 520 connects the contact pad 510 and extends toward the first end to connect with the extension port 530, and the extension port 530 extends from the first end of the half-bridge module.
Further, the second substrate 200 is further provided with a gate line 220, the chip gate of the second chipset 300L may be electrically connected to the gate line 220 through a lead 700, an end of the gate line 220 extends to a position of the second substrate 200 near the first end, and a second gate port G is formed at the end of the gate line 220 L May be electrically connected to the gate line 220 by a wire 700.
In the half-bridge module provided in the above-described embodiment, the first chip set 300H and the second chip set 300L are respectively disposed on the first substrate 100 and the second substrate 200, and the first substrate 100 and the second substrate 200 are oppositely stacked, so that the overall size of the half-bridge module can be effectively reduced. And the DC + port and the DC-port are arranged to extend out from the first end of the half-bridge module, and the AC port is arranged to extend out from the second end of the half-bridge module, so that current flowing from the first end to the second end and current flowing from the second end to the first end exist in a current main loop of the half-bridge circuit, the current flowing in opposite directions can realize a mutual inductance effect, and the inductance of the main loop is effectively reduced. And, the half-bridge module can also utilize the first substrate 100 and the second substrate 200 to dissipate heat at the upper and lower sides of the half-bridge module, which effectively improves the heat dissipation effect of the half-bridge module.
It should be noted that the first substrate and the second substrate are disposed in an opposite manner, so that the first substrate and the second substrate disposed in a stacked manner can be packaged in the same module to form a sub-module. In a specific example, the half-bridge module may include one or several sub-modules connected in parallel, each sub-module including a first substrate and a second substrate stacked in a stack. For example, fig. 7 illustrates a half-bridge module having one sub-module; fig. 8 illustrates a half-bridge module having a plurality of sub-modules connected in parallel.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Although the present invention has been described in connection with the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention will still fall within the protection scope of the technical solution of the present invention.
It should also be understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and not for describing a sequential or logical relationship between various components, elements, steps, or the like, unless otherwise specified or indicated. It should also be understood that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims (11)

1. A half-bridge module, comprising:
the chip module comprises a first substrate, a second substrate and a third substrate, wherein a first chip group is arranged on the first substrate;
the second substrate is provided with a second chip set, the second substrate and the first substrate are oppositely arranged, and the first chip set and the second chip set are positioned between the first substrate and the second substrate; and the number of the first and second groups,
the DC + port is electrically connected with the first chip set and extends out of the first end of the half-bridge module, the DC-port is electrically connected with the second chip set and extends out of the first end of the half-bridge module, and the AC port is electrically connected between the first chip set and the second chip set and extends out of the second end of the half-bridge module.
2. The half-bridge module of claim 1, wherein the first substrate has a first metal region thereon, the first chip group being disposed on the first metal region; the second substrate is provided with a second metal area, and the second chip set is arranged on the second metal area.
3. The half-bridge module of claim 2, wherein the DC + port is mounted on the first metal region to connect to a chip drain within the first chip set; the AC port is attached to the second metal area so as to be connected with a chip drain electrode in the second chip set; and the DC-port is electrically connected with the chip source electrode in the second chip group.
4. The half-bridge module of claim 1, wherein a connection is disposed between the first substrate and the second substrate, the connection electrically connecting each die within the first die set and the second substrate such that a die source of the first die set electrically connects a die drain within the second die set.
5. The half-bridge module of claim 1, wherein a support is disposed between the first substrate and the second substrate, the support disposed between each chip within the second chipset and the first substrate.
6. The half-bridge module of claim 5, wherein the DC-port has at least one contact pad, each contact pad contacting each chip within the second chipset in a one-to-one correspondence, the contact pad being sandwiched between the support and the corresponding chip.
7. The half-bridge module of claim 1, wherein the first chip set is disposed in a region of the first substrate proximate the second end and the second chip set is disposed in a region of the second substrate proximate the first end.
8. The half-bridge module of claim 1, wherein the first chipset is disposed in a region of the first substrate proximate the first end and the second chipset is disposed in a region of the second substrate proximate the second end.
9. The half-bridge module of claim 8, wherein the DC-port has a contact pad that contacts a chip within the second chipset, a connecting arm that connects the contact pad and extends in a direction toward the first end to connect with the epitaxial port, and an epitaxial port that extends from the first end of the half-bridge module.
10. The half-bridge module of claim 1, wherein the first and second substrates in a stacked arrangement are packaged to form a sub-module, the half-bridge module having one sub-module or a plurality of sub-modules in parallel.
11. The half-bridge module of any one of claims 1-10, wherein the chips in the first chipset and the second chipset are silicon carbide chips.
CN202211256626.XA 2022-10-14 2022-10-14 Half-bridge module Pending CN115458514A (en)

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CN202211256626.XA CN115458514A (en) 2022-10-14 2022-10-14 Half-bridge module

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Application Number Priority Date Filing Date Title
CN202211256626.XA CN115458514A (en) 2022-10-14 2022-10-14 Half-bridge module

Publications (1)

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CN115458514A true CN115458514A (en) 2022-12-09

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