CN115458029A - Method and device for verifying memory repair and memory repair equipment - Google Patents
Method and device for verifying memory repair and memory repair equipment Download PDFInfo
- Publication number
- CN115458029A CN115458029A CN202211026752.6A CN202211026752A CN115458029A CN 115458029 A CN115458029 A CN 115458029A CN 202211026752 A CN202211026752 A CN 202211026752A CN 115458029 A CN115458029 A CN 115458029A
- Authority
- CN
- China
- Prior art keywords
- repair
- memory
- controller
- time programmable
- control parameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
Landscapes
- Programmable Controllers (AREA)
Abstract
The invention provides a method and a device for verifying memory repair and a memory repair device, wherein the method comprises the following steps: reading a control parameter from the one-time programmable device as a repair actual value and outputting the repair actual value; the control parameters are generated by a repair controller and stored in the one-time programmable device, and when the repair controller repairs the to-be-repaired fault memory, the control parameters are read out of the one-time programmable device by the repair controller and input into the to-be-repaired fault memory; and receiving the control parameter generated by the repair controller from the repair controller as a repair expected value, and outputting the repair expected value. The invention further locates the reason of the fault of the memory to be repaired by comparing the expected value input into the memory to be repaired with the actual value read out by the one-time programmable device.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a method and an apparatus for verifying memory repair, and a memory repair device.
Background
In the manufacturing process of the semiconductor memory, due to process defects and the like, the memory cells with physical defects exist in the manufactured memory array of the chip memory. The existence of the defective memory unit causes the produced chip to have abnormal functions under the condition of accessing certain specific addresses of the memory, and data cannot be safely and effectively accessed, so that the memory of the chip fails. The redundancy repair technology is characterized in that redundant rows and redundant columns are introduced into the design of a memory array of a chip, and the redundant rows and the redundant columns are combined with a memory test technology and a redundancy analysis means to replace a fault unit in the memory array, so that the purpose of repairing the functional failure problem of the memory caused by the fault of the memory unit is achieved. The occurrence of the redundancy repair technology effectively improves the yield of the memory chip manufacture, and has important significance for reducing the unit manufacturing cost of the memory chip.
However, after performing the chip memory repair, if the failed memory to be repaired still has a failure, the reason for the failure of memory repair needs to be further located.
Disclosure of Invention
The invention aims to provide a method and a device for verifying memory repair, which are used for solving the technical problem that the reason of the fault of a memory after repair is still not determined.
In a first aspect of the invention, a method is provided for verifying memory repair. The method comprises the following steps: reading a control parameter from the one-time programmable device as a repair actual value and outputting the repair actual value; the control parameters are generated by a repair controller and stored in the one-time programmable device, and when the repair controller repairs the to-be-repaired fault memory, the control parameters are read out of the one-time programmable device by the repair controller and input into the to-be-repaired fault memory; and receiving the control parameter generated by the repair controller from the repair controller as a repair expected value, and outputting the repair expected value.
In an embodiment of the present invention, the method further includes: and comparing the repair expected value with the repair actual value to confirm the control parameters stored in the one-time programmable device and to be input into the memory to be repaired.
In an embodiment of the present invention, the method further includes: receiving the control parameter generated by the repair controller from the repair controller through a first gate, and outputting the repair expected value through the first gate.
In an embodiment of the present invention, the method further includes: and inputting the read control parameter as the repair actual value to a second gate, and outputting the repair actual value through the second gate.
In an embodiment of the present invention, the method further includes: and respectively receiving the control parameter input into the one-time programmable device and the control parameter read from the one-time programmable device from the repair controller through a data comparator, and comparing the repair expected value with the repair actual value.
In an embodiment of the present invention, the method further includes: and reading the control parameters stored in the one-time programmable device through a one-time programmable device controller.
In a second aspect of the invention, an apparatus for verifying memory repairs is provided. The device includes: a reading device electrically coupled with the one-time programmable device and configured to read the control parameter from the one-time programmable device as a repair real value and output the repair real value; the control parameters are generated by a repair controller and stored in the one-time programmable device, and when the repair controller repairs the to-be-repaired fault memory, the control parameters are read out of the one-time programmable device by the repair controller and input into the to-be-repaired fault memory; and a receiving device electrically coupled with the repair controller and configured to receive the control parameter generated by the repair controller from the repair controller as a repair expected value and output the repair expected value.
In an embodiment of the present invention, the receiving device includes a data comparator; the data comparator is also coupled with the reading device and configured to compare the repair expected value and the repair actual value to confirm the control parameter stored in the one-time programmable device to be input into the fault memory to be repaired.
In an embodiment of the invention, the receiving device includes a first gate: the first gate is electrically coupled to the repair controller, the first gate is configured to output the repair expected value in response to a test mode being active, and the second gate is configured to output the repair actual value in response to a test mode being active.
In an embodiment of the present invention, the method further includes: a second gate electrically coupled to the read device and the one-time programmable device, respectively, configured to receive the read control parameter from the read device as a repair actual value in response to a test mode being active, and configured to output the repair actual value.
In a third aspect of the present invention, there is provided a memory repair device including: the apparatus as described above; a one-time programmable device; and the repair controller is configured to generate and store control parameters into the one-time programmable device, and read out the control parameters from the one-time programmable device and input the control parameters into the to-be-repaired fault memory when the to-be-repaired fault memory is repaired.
According to the method and the device for verifying the memory repair and the memory repair equipment, the reason that the to-be-repaired fault memory still fails is further located by comparing the expected value input into the to-be-repaired fault memory with the actual value read by the one-time programmable device. In addition, the invention reads the control parameters in the one-time programmable device through the one-time programmable device controller to form an actual value, and compares and analyzes the actual value and an expected value to determine the repair parameters of the memory to be repaired by the memory repair controller.
Drawings
FIG. 1 is a flow diagram illustrating a method for chip memory repair verification according to an embodiment of the invention.
FIG. 2 is a schematic diagram showing an architecture of an apparatus for chip memory repair verification according to an embodiment of the present invention.
Fig. 3 is a schematic diagram showing another structure of an apparatus for chip memory repair verification according to an embodiment of the present invention.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
A solution for repairing a memory failure is proposed in the prior art, wherein the failed memory is modified by a memory modification controller. However, in this repair method, after the memory repair information is written into the failed memory, if the failed memory to be repaired still has a failure, the cause of the memory repair failure cannot be further located.
It is an aim of embodiments of the present invention to provide a scheme for verifying memory repair. According to an embodiment of the invention, a one-time programmable device receives a repair value to be input into a failed memory to be repaired, and outputs an expected value scheduled to be input into the failed memory to be repaired and an actual value read out from the one-time programmable device for comparison. In this way, the reason that the memory to be repaired fails still can be located, so that the technical problem that the failure reason of the repaired memory cannot be determined in the prior art is solved.
Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a flow diagram illustrating a method for verifying memory repair according to an embodiment of the present invention. As shown in fig. 1, the method includes the following steps S1 to S2.
In step S1, a control parameter is read from a one-time programmable device as a repair actual value, and the repair actual value is output, wherein the control parameter is generated by a repair controller and stored in the one-time programmable device, and the control parameter is read out from the one-time programmable device by the repair controller and input into a to-be-repaired failure memory when the repair controller repairs the to-be-repaired failure memory.
In this embodiment, the control parameter stored in the otp device is read from the otp device by a reading device to be used as a repair actual value. Specifically, in this embodiment, the reading device includes a one-time programmable device controller. In other words, in this embodiment, the otp device controller reads the control parameters in the otp device to form an actual value, and the actual value is compared with an expected value for subsequent analysis, so as to determine the repair parameters of the memory to be repaired by the memory repair controller.
In this embodiment, when the repair controller repairs the to-be-repaired failure memory, the control parameter in the otp device is generated by the repair controller, and when the to-be-repaired failure memory is repaired, the repair controller reads out the control parameter from the otp device and inputs the control parameter into the to-be-repaired failure memory. The one-time programmable device is respectively connected with a repair controller and a to-be-repaired fault memory, and when the repair controller repairs the to-be-repaired fault memory, the one-time programmable device simultaneously receives control parameters input into the to-be-repaired fault memory from the repair controller.
In this way, the otp device stores therein a control parameter for repairing the to-be-repaired failure memory, i.e., a repair actual value. In this embodiment, when the to-be-repaired fault memory is powered on again, the repair controller reads out the control parameters from the otp device and inputs the control parameters into the to-be-repaired fault memory, and the to-be-repaired fault memory recovers to work normally according to the control parameters received from the otp device.
In step S2, the control parameter generated by the repair controller is received from the repair controller as a repair expected value, and the repair expected value is output.
In this embodiment, when the repair controller inputs the control parameter into the otp device for storage, the otp device may have a risk of changing the control parameter during storage, which causes a deviation between the control parameter stored in the otp device and the control parameter to be input into the to-be-repaired fault storage by the repair controller.
In some embodiments, the method may further comprise: and comparing the repair expected value with the repair actual value to confirm the control parameters stored in the one-time programmable device and to be input into the to-be-repaired fault memory.
In this embodiment, the method may further include: and inputting the read control parameter as the repair actual value to a second gate, and outputting the repair actual value through the second gate. The reading device is connected between the one-time programmable device and the second gate, reads the control parameter in the one-time programmable device, and outputs the control parameter through the second gate.
In this embodiment, the second gate is in a test mode when receiving the test instruction, and receives the control parameter from the otp device controller in the test mode.
Specifically, in this embodiment, the second gate obtains the control parameter output by the otp device, and uses the received control parameter as a repair actual value, so as to compare and analyze the repair expected value and the repair actual value, and determine the repair parameter input by the repair controller to the to-be-repaired fault memory.
When the to-be-repaired fault memory is powered on again, the repair controller reads the control parameters from the one-time programmable device and inputs the control parameters into the to-be-repaired fault memory, if the control parameters stored in the one-time programmable device are different from the control parameters expected to be input into the to-be-repaired fault memory by the repair controller, the to-be-repaired fault memory is not the control parameters when the repair controller repairs the fault according to the control parameters received from the one-time programmable device, and at this time, the to-be-repaired fault memory has a risk of being difficult to recover to normal operation, and it cannot be accurately known what the control parameters input into the to-be-repaired fault memory by the one-time programmable device are, whether the control parameters are changed, and what the control parameters are changed.
Therefore, in this embodiment, the expected value directly output by the repair controller is compared with the control parameter (actual value) stored in the otp device, and the repair parameter input by the repair controller to the to-be-repaired fault memory is determined, so as to know what the control parameter input to the to-be-repaired fault memory is, whether the control parameter is changed, and what the control parameter is changed.
Specifically, in the present embodiment, the control parameters input into the otp device are received from the repair controller by, but not limited to, the following two ways. Fig. 2 and 3 are block diagrams illustrating an apparatus 100 for verifying memory repair according to an embodiment of the present invention.
As shown in fig. 2, the control parameter generated by the repair controller is received from the repair controller through a first gate, and the repair expected value is output through the first gate.
In this embodiment, the first gate is in a test mode when receiving the test command, and simultaneously receives the control parameters input to the otp device from the repair controller in the test mode.
That is, in this embodiment, the repair controller outputs a control parameter to be used when repairing the to-be-repaired fault memory, simultaneously inputs the control parameter input into the otp device into the first gate, and takes the control parameter output by the first gate as an expected value.
Although the repair controller simultaneously inputs the control parameter input into the memory to be repaired into the first gate and the otp device, the first gate directly outputs the control parameter, which corresponds to an original value output by the repair controller as the expected value for repair. That is, the expected value output from the first gate corresponds to a value directly output by the repair controller.
As shown in fig. 3, the control parameters input into the otp device and the control parameters read from the otp device from the repair controller are received by a data comparator, respectively, and the repair expected value and the repair actual value are compared.
And after the data comparator compares the repair expected value with the repair actual value, outputting a comparison result, and confirming the control parameters stored in the one-time programmable device and to be input into the to-be-repaired fault memory according to the comparison result.
Therefore, according to the method for verifying memory repair of the embodiment, the reason why the to-be-repaired fault memory still fails is further located by comparing the expected value input into the to-be-repaired fault memory with the actual value read by the otp device.
Referring to fig. 2 and 3, the apparatus 100 includes a reading device 110 and a receiving device.
In this embodiment, the reading device 110 is electrically coupled to the otp device 400, and is configured to read the control parameter from the otp device 400 as the repair real value, and output the repair real value. The control parameters in the otp device 400 are generated by the repair controller 300, and the repair controller 300 reads the control parameters from the otp device 400 and inputs the control parameters into the to-be-repaired failure memory 200 when repairing the to-be-repaired failure memory 200.
Specifically, in the present embodiment, the reading device 110 includes a one-time programmable device controller.
That is, in this embodiment, the otp controller is configured to read the control parameter from the otp 400 to form an actual value, and then compare and analyze the actual value with the expected value to determine the repair parameter of the to-be-repaired failure memory 200 by the memory repair controller 300.
In this embodiment, when repairing the to-be-repaired failure memory 200, the repair controller 300 simultaneously inputs the control parameters input into the to-be-repaired failure memory 200 into the otp device 400. The otp device 400 is respectively connected to a repair controller 300 and the to-be-repaired fault memory 200, and when the repair controller 300 repairs the to-be-repaired fault memory 200, the repair controller 300 simultaneously receives control parameters input into the to-be-repaired fault memory 200.
In this way, the otp device 400 stores therein a control parameter for repairing the to-be-repaired failure memory 200, i.e., a repair actual value. In this embodiment, when the to-be-repaired fault memory 200 is powered on again, the repair controller 300 reads out the control parameters from the otp device 400 and inputs the control parameters into the to-be-repaired fault memory 200, and the to-be-repaired fault memory 200 recovers normal operation according to the control parameters received from the otp device 400.
In this embodiment, the apparatus 100 further includes a second gate 130. The second gate 130 is electrically coupled to the reading device 110 and the one-time programmable device 400, respectively, is configured to receive the read control parameter from the reading device 110 as a repair real value in response to the test mode being active, and is configured to output the repair real value.
In this embodiment, the second gate 130 is configured to be in a test mode when receiving the test command, and to receive the control parameters from the otp device 400 controller in the test mode.
Specifically, in this embodiment, the second gate 130 is configured to obtain the control parameter output by the otp device 400, and use the received control parameter as a repair actual value, so as to compare and analyze the repair expected value and the modification actual value, and determine the repair parameter input by the repair controller 300 to the to-be-repaired fault memory 200.
In the present embodiment, the receiving device is electrically coupled to the repair controller 300, configured to receive the control parameter input into the one-time programmable device 400 from the repair controller 300 as a repair expected value, and output the repair expected value.
In this embodiment, when the repair controller 300 inputs the control parameter into the otp device 400 for storage, there is a risk that the otp device 400 may change the control parameter during storage, so that the control parameter stored in the otp device 400 is different from the control parameter that the repair controller 300 will input into the to-be-repaired fault memory 200. In this embodiment, the expected repair value and the actual repair value are compared to confirm the control parameters stored in the otp device 400 to be input into the to-be-repaired fault memory 200.
In the present embodiment, as shown in fig. 2, the receiving device includes a first gate 120. The first gate 120 is electrically coupled to the repair controller 300, the first gate 120 is configured to output the repair expected value in response to the test mode being valid, and the second gate 130 is configured to output the repair actual value in response to the test mode being valid.
In this embodiment, the first gate 120 is in a test mode when receiving a test command, and simultaneously receives control parameters input to the otp device 400 from the repair controller 300 in the test mode. The second gate 130 is configured to be in a test mode upon receiving the test instruction and to receive control parameters from the otp device 400 controller in the test mode.
That is, in this embodiment, the repair controller 300 outputs a control parameter to be used when repairing the to-be-repaired defective memory 200, simultaneously inputs the control parameter input into the otp device 400 into the first gate 120, and takes the control parameter output by the first gate 120 as an expected value.
Although the repair controller 300 inputs the control parameter inputted into the to-be-repaired fault memory 200 to the first gate 120 and the otp device 400 at the same time, the first gate 120 directly outputs the control parameter, which corresponds to outputting the original value outputted by the repair controller 300 as the repair expected value. That is, the expected value output from the first gate 120 corresponds to a value directly output from the repair controller 300.
In the present embodiment, as shown in fig. 3, the receiving device includes a data comparator 140. The data comparator 140 is further coupled to the reading device 110 and configured to compare the repair expected value and the repair actual value to confirm the control parameter stored in the otp device 400 to be input into the to-be-repaired fault memory 200.
After the data comparator 140 compares the repair expected value with the repair actual value, a comparison result is output, and the control parameters stored in the otp device 400 and to be input into the to-be-repaired fault memory 200 are confirmed through the comparison result.
The apparatus 100 for verifying memory repair according to the present embodiment further locates the reason why the defective memory 200 to be repaired still fails by comparing the expected value inputted into the defective memory 200 to be repaired with the actual value read out by the otp device 400.
In addition, the embodiment also provides a memory repair device. The memory repair apparatus includes: the apparatus 100 for verifying memory repair, the one-time programmable device 400, and the repair controller 300 as described above. The repair controller 300 is configured to generate and store control parameters into the otp device 400, and to read out the control parameters from the otp device 400 and input the control parameters into the to-be-repaired fault memory 200 when repairing the to-be-repaired fault memory 200. The apparatus 100 for verifying memory repair has been described in detail above, and will not be described herein again.
In summary, the invention further locates the reason of the failure of the memory to be repaired by comparing the expected value input into the memory to be repaired with the actual value read out by the one-time programmable device; the method comprises the steps of reading control parameters in the one-time programmable device through the one-time programmable device controller to form an actual value, and comparing and analyzing the actual value with an expected value to determine the repair parameters of the memory to be repaired by the memory repair controller. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A method for verifying memory repair, comprising:
reading a control parameter from a one-time programmable device as a repair actual value, and outputting the repair actual value, wherein the control parameter is generated by a repair controller and stored in the one-time programmable device, and the control parameter is read out from the one-time programmable device by the repair controller and input into a to-be-repaired fault memory when the repair controller repairs the to-be-repaired fault memory; and
receiving the control parameter generated by the repair controller from the repair controller as a repair expected value, and outputting the repair expected value.
2. The method for verifying memory repair as recited in claim 1, further comprising: and comparing the repair expected value with the repair actual value to confirm the control parameters stored in the one-time programmable device and to be input into the to-be-repaired fault memory.
3. The method for verifying memory repair as claimed in claim 1 or 2, further comprising: receiving the control parameter generated by the repair controller from the repair controller through a first gate, and outputting the repair expected value through the first gate.
4. The method for verifying memory repair as claimed in claim 1 or 2, further comprising:
and inputting the read control parameter as the repair actual value to a second gate, and outputting the repair actual value through the second gate.
5. The method for verifying memory repair as recited in claim 2, further comprising:
and respectively receiving the control parameter input into the one-time programmable device and the control parameter read from the one-time programmable device from the repair controller through a data comparator, and comparing the repair expected value with the repair actual value.
6. The method for verifying memory repair as recited in claim 1, further comprising:
and reading the control parameters stored in the one-time programmable device through a one-time programmable device controller.
7. An apparatus for verifying memory repair, comprising:
a reading device electrically coupled with the one-time programmable device and configured to read a control parameter from the one-time programmable device as a repair actual value and output the repair actual value, wherein the control parameter is generated by a repair controller and stored in the one-time programmable device, and the control parameter is read out from the one-time programmable device by the repair controller and input into a to-be-repaired failure memory when the repair controller repairs the to-be-repaired failure memory; and
a receiving device electrically coupled with the repair controller and configured to receive the control parameter generated by the repair controller from the repair controller as a repair expected value and output the repair expected value.
8. The apparatus for verifying memory repair of claim 7, wherein the receiving device comprises a data comparator;
the data comparator is also coupled with the reading device and configured to compare the repair expected value and the repair actual value to confirm the control parameter stored in the one-time programmable device to be input into the fault memory to be repaired.
9. The apparatus for verifying memory repair of claim 7 or 8, wherein the receiving device comprises a first gate:
the first gate is electrically coupled to the repair controller, the first gate is configured to output the repair expected value in response to a test mode being active, and the second gate is configured to output the repair actual value in response to a test mode being active.
10. The apparatus for verifying memory repair of claim 9, further comprising:
a second gate electrically coupled to the read device and the one-time programmable device, respectively, configured to receive the read control parameter from the read device as a repair actual value in response to a test mode being active, and configured to output the repair actual value.
11. A memory repair device, comprising:
the apparatus of any one of claims 7 to 10;
a one-time programmable device; and
and the repair controller is configured to generate and store control parameters into the one-time programmable device, and read the control parameters out of the one-time programmable device and input the control parameters into the to-be-repaired fault memory when the to-be-repaired fault memory is repaired.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211026752.6A CN115458029A (en) | 2022-08-25 | 2022-08-25 | Method and device for verifying memory repair and memory repair equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211026752.6A CN115458029A (en) | 2022-08-25 | 2022-08-25 | Method and device for verifying memory repair and memory repair equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115458029A true CN115458029A (en) | 2022-12-09 |
Family
ID=84298961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202211026752.6A Pending CN115458029A (en) | 2022-08-25 | 2022-08-25 | Method and device for verifying memory repair and memory repair equipment |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN115458029A (en) |
-
2022
- 2022-08-25 CN CN202211026752.6A patent/CN115458029A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111312321A (en) | Memory device and fault repairing method thereof | |
US8509014B2 (en) | Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs | |
US6067262A (en) | Redundancy analysis for embedded memories with built-in self test and built-in self repair | |
US7721163B2 (en) | JTAG controlled self-repair after packaging | |
US8037376B2 (en) | On-chip failure analysis circuit and on-chip failure analysis method | |
US6922649B2 (en) | Multiple on-chip test runs and repairs for memories | |
CN102237146A (en) | Repair circuit and repair method of semiconductor memory apparatus | |
US20160093401A1 (en) | Integrated circuits with built-in self test mechanism | |
US20210166777A1 (en) | Memory repair circuit, memory repair method, and memory module using memory repair circuit | |
CN101303897A (en) | Memory structure, repair system and method for testing the same | |
US7890820B2 (en) | Semiconductor test system with self-inspection of memory repair analysis | |
CN110322921A (en) | A kind of terminal and electronic equipment | |
JP2005332436A (en) | Semiconductor device and its testing method | |
KR100825068B1 (en) | Built in self test and built in self repair system | |
CN116540059A (en) | Semiconductor chip testing method, device, equipment and storage medium | |
KR100944325B1 (en) | Repair fuse device | |
CN115458029A (en) | Method and device for verifying memory repair and memory repair equipment | |
CN109215724B (en) | Method and device for automatically detecting and repairing memory | |
CN109390028B (en) | Method and device for automatically repairing NOR type memory array bit line fault | |
JP2003100094A (en) | Semiconductor memory | |
US20060168488A1 (en) | Method and system for testing RAM redundant integrated circuits | |
KR20160138767A (en) | Semiconductor memory device and operating method thereof | |
US7536611B2 (en) | Hard BISR scheme allowing field repair and usage of reliability controller | |
KR100555574B1 (en) | Semiconductor memory device having fail address programming circuit and fail address programming circuit thereof | |
JP2012099603A (en) | Wafer test equipment, wafer test method and program |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |