CN115455903A - System for verifying operational characters - Google Patents
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- CN115455903A CN115455903A CN202211408446.9A CN202211408446A CN115455903A CN 115455903 A CN115455903 A CN 115455903A CN 202211408446 A CN202211408446 A CN 202211408446A CN 115455903 A CN115455903 A CN 115455903A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F30/00—Computer-aided design [CAD]
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Abstract
The invention relates to the technical field of electronic design automation, in particular to a system for verifying an operator, which comprises: a database including an operator set OP and a predetermined operand set OD, the OP including all operators in a hardware description language, a processor and a memory storing a computer program, which when executed by the processor implements the steps of: randomly selecting an operational character and combining the operational character combination to generate a random expression, respectively inserting the random expression into a circuit to be tested of a standard simulator and a simulator to be verified, comparing whether the numerical values of output results are equal or not, and if not, failing to verify; the accuracy and the completeness of the simulator to be verified are tested by randomly selecting the operational characters to generate the random expression, the defect of incomplete test such as missing test and the like caused by artificially and subjectively compiling the test case can be eliminated, and meanwhile, the test efficiency is improved.
Description
Technical Field
The invention relates to the technical field of electronic design automation, in particular to a system for verifying an operator.
Background
In the electronic design automation software product test, a tester needs to verify the support correctness and completeness of an electronic design automation software waveform window for expression operators of a hardware description language.
The expression operation characters of the hardware description language are of multiple types, the combination mode of the operation characters and the operation numbers is complex, the priority of the operation characters is complex, and the combination number of the operation characters is large.
In the prior art, the result after operation is checked through the limited test case created manually, the result is a manual incomplete result, and the efficiency and completeness of the test cannot be guaranteed by development and test personnel.
Disclosure of Invention
Aiming at the technical problem, the technical scheme adopted by the invention is as follows:
a system to validate operators, the system comprising: a database including an operator set OP and a predetermined operand set OD, wherein the OP includes all operators in a hardware description language and the OD includes different operands, and a memory storing a computer program which, when executed by the processor, implements the steps of:
s100, classifying the OP to obtain N operator categories OR = { OR = { (OR) } 1 ,OR 2 ,…,OR i ,…,OR N }，OR i ={or i,1 ,or i,2 ,…,or i,j ,…,or i,M In which OR is i Is the ith operator category, the value range of i is 1 to N, N is the number of the operator categories, or i,j Is the jth operator in the ith operator category, j has a value ranging from 1 to M, and M is OR i Number of operators in.
S200, randomly generating Q random expressions F = { F according to OR 1 ,F 2 ,…, F q ,…,F Q In which F q The expression is a qth random expression, the value range of Q is 1 to Q, and Q is the number of the random expressions; wherein, F q The generating step of (a) comprises:
s210, randomly selecting K times of operator categories from the OR to obtain K target categories OR = { OR = } 1 ´,OR 2 ´,…,OR k ´,…,OR K ´}，OR k For production of F q The operator category obtained by the kth random selectionThe value range of K is 1 to K, and K is the random selection frequency.
And S220, randomly selecting an operator from each object type of OR' to obtain K object operators.
S230, selecting the operand from the OD, combining the operand with K target operators to generate F q 。
S300, inserting each random expression in the F into a circuit to be tested of a standard simulator and a circuit to be tested of a simulator to be verified respectively, verifying Q random expressions in the F through the standard simulator and the simulator to be verified respectively, and if all random expressions pass verification, passing verification of the simulator to be verified, otherwise, not passing verification.
Compared with the prior art, the invention has obvious beneficial effects, and by means of the technical scheme, the system for verifying the operational characters can achieve considerable technical progress and practicability, has wide industrial utilization value, and at least has the following beneficial effects:
the invention provides a system for verifying operational characters, which generates a random expression by randomly selecting the operational characters and combining operand combination, inserts the random expression into a circuit to be tested of a standard simulator and a simulator to be verified respectively, compares whether the numerical values of output results are equal or not, if not, verifies not to pass, and indicates that an error exists in the simulation result of the simulator to be verified. The accuracy and the completeness of the simulator to be verified are tested by randomly selecting the operational characters to generate the random expression, the defect of incomplete test such as missing test and the like caused by artificially and subjectively compiling the test case can be eliminated, and meanwhile, the test efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for validating an operator according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
An embodiment of the present invention provides a system for verifying an operator, where the system includes: the system comprises a database, a processor and a memory for storing a computer program, wherein the database comprises an operator set OP and a preset operand set OD, the OP comprises all operators in a hardware description language, and the OD comprises different operands.
Wherein the operator set OP comprises H operators OP = { or = } 1 ,or 2 ,…,or h ,…or H H ranges from 1 to H, H is the number of operators, and H is a positive integer.
Wherein the predetermined operand set OD includes T predetermined operands OD = { OD = 1 ,od 2 ,…,od t ,…,od T And f, wherein the value range of T is 1 to T, T is the number of preset operands, and T is a positive integer.
Further, referring to FIG. 1, there is shown a flow chart of a method of validating an operator, which when executed by a processor, performs the steps of:
s100, classifying the OP to obtain N operator categories OR = { OR = { (OR) } 1 ,OR 2 ,…,OR i ,…,OR N }，OR i ={or i,1 ,or i,2 ,…,or i,j ,…,or i,M In which OR is i For the ith operator type, the value range of i is 1 to N, N is the number of the operator types, or i,j Is the jth operator in the ith operator category, j has a value ranging from 1 to M, and M is OR i Number of operators in.
It should be noted that all operators in the hardware description language include assignment operators, condition operators, monocular operators, binocular operators, plus-1 or minus-1 operators, stream operators, and so on.
Alternatively, the preset operator set OR includes a conditional operator, a monocular operator, and a binocular operator, and the operators "+", "- >" and "< - >" are not included in the binocular operator.
Optionally, before S100, the step of obtaining the preset operator set OR further includes: and eliminating the assignment operator, the plus 1 OR minus 1 operator and the stream operator in all operators in the hardware description language, and eliminating the 'star', 'and' < - > in the binocular operator to obtain a preset operator set OR.
Specifically, conditional operators include "
: ". A monocular operator includes a "+" - "! "-") "&”“~&"|" - | "" or ^ a "- [ circumflex ]". The binocular operator includes "+" "-" "" "" + "" "" "%" = "" | ". = "! = = =' "=
”“&&”“||”“<”“<=”“>”“>=”“&”“|”“^”“^~”“~^”“>>”“<<”“>>>”“<<<”。
Optionally, the operator set OR is divided into N operator categories according to the number of operands required by the operator, and the operator categories include a monocular operator, a binocular operator, and a trinocular operator.
Alternatively, the operator set OR is divided into N operator categories according to the functions of the operators. Operator categories include arithmetic operators, relational operators, equation operators, logical operators, bit operators, reduction operators, shift operators, and conditional operators.
Optionally, the classification is performed according to the classification method in the IEEE _1800 standard. May be the IEEE _1800 _2017standard. The operator categories include conditional operators, monocular operators, and binocular operators.
Preferably, the classification is performed according to the classification method in the IEEE _1800 standard.
S200, randomly generating Q random expressions F = { F) according to OR 1 ,F 2 ,…, F q ,…,F Q In which F q The Q-th random expression is obtained, the value range of Q is from 1 to Q, and Q is the number of the random expressions; wherein, F q The generating step comprises:
s210, randomly selecting K times of operator categories from the OR to obtain K target categories OR = { OR = } 1 ´,OR 2 ´,…,OR k ´,…,OR K ´}，OR k For generation of F q And randomly selecting the obtained operational character category at the kth time, wherein the value range of K is from 1 to K, and K is the number of times of random selection.
Optionally, the randomly selected K target categories may be the same operator category or different. That is, OR' includes ORs having the same operator class k And OR r Wherein r ranges from 1 to N, and k ≠ r.
Optionally, the step of randomly selecting the operator category K times from the OR is to randomly select the operator category K times through a random number generator, where the random number generator is implemented by calling a function, such as a random () function. It should be noted that an operator category may be randomly selected from all operator categories of OR through a random (OR) function, and K target categories are obtained by randomly selecting K times.
And S220, randomly selecting an operator from each object type of OR' to obtain K object operators.
Wherein the number of randomly selected target classes is equal to the number of target operators, and K also represents the combined depth of the target operators. Preferably, K has a value of 10.
It should be noted that, no matter whether the K target categories are the same or not, an operator needs to be randomly selected from each category.
Illustratively, an operator is randomly selected from the binocular operator category, resulting in an operator "+", which is a target operator.
Optionally, the operator is randomly selected by a random number generator.
S230, selecting the operand from the OD, combining the operand with K target operators to generate F q 。
Further, combining the operands with K target operators generates F q Comprises the following steps:
s231, determining the number Q of required operands of the k-th target operator in the expression k 。
It should be noted that the operand of the monocular operator is one, the operand of the binocular operator is two, and the operand of the trinocular operator is three. Since the preceding k-1 target operators are already combined into an expression when the kth target operator is combined, and the expression occupies an operand position in the target operator, in the expression, the operands required by the monocular operator are 0, the operands required by the binocular operator are 1, and the operands required by the trinocular operator are two.
S232, selecting Q from OD k And combining the operands with expressions generated by the first (k-1) target operators to obtain expressions of the first k target operator combinations.
It should be noted that the operand is a component of the expression, for example, for "a", "b" and "c" in "a + b-c", the operand is used, and the "+" - "is used as the binocular operator. "a + b" is the expression of the first operator combination, and "a + b + c" is the expression from the first two operator combinations.
Optionally, Q is selected from OD k The steps of the method include: selecting Q from OD k An operand, wherein the first k-1 operators generate the operands in the expression and the selected Q k The individual operands are different.
As an example, the 3 operators selected randomly are: binocular operator "+", binocular operator "-", and monocular operator "&"; sequentially selecting from ODSelecting operands, two operands being required for the first binocular operator "+", in order from OD = { OD = 1 ,od 2 ,…,od t ,…,od T Get out { od } 1 ,od 2 The expression obtained by combining the first operator and operand is od 1 +od 2 "; for the second operator "-", in order from OD = { OD = 1 ,od 2 ,…,od t ,…,od T Get the third operand od 3 ", the expression resulting from combining the second operator with the previous expression is" od 1 +od 2 -od 3 "; for the third operator "&", in order from OD = { OD = 1 ,od 2 ,…,od t ,…,od T Get the fourth operand od 4 ", the expression resulting from combining the third operator with the previous expression is" od 1 +od 2 -od 3 &od 4 ”。
Optionally, Q is selected from OD k The step of counting the operands comprises: randomly selecting Q from OD k Multiple operands, wherein the first k-1 operators generate operands in the expression with the selected Q k The individual operands are different.
S233, repeating S231-233 to obtain a random expression F of K target operator combinations q In which F is q All operands in (a) are different from each other.
S300, respectively inserting each random expression in the F into a circuit to be tested of the standard simulator and a circuit to be tested of the simulator to be verified, respectively verifying Q random expressions in the F through the standard simulator and the simulator to be verified, if all the random expressions pass through the verification, the verification of the simulator to be verified passes, otherwise, the random expressions do not pass through.
The circuit to be tested of the standard simulator is the same as that of the simulator to be verified, and the structures, the number and the sequence of the expressions in the standard simulator and the circuit to be tested of the simulator to be verified are completely the same.
It should be noted that the circuit to be tested is implemented by a hardware description language, and each expression in the circuit to be tested represents a hardware circuit module. The circuit to be tested of the standard simulator is the same as that of the simulator to be verified, which shows that the circuit structures of the standard simulator and the simulator to be verified are the same.
And sequentially and respectively inserting the expressions generated each time into the circuit to be tested of the standard simulator and the circuit to be tested of the simulator to be verified according to the sequence.
The circuit to be tested comprises a plurality of expressions.
Optionally, the file of the circuit to be tested is a header file, and the expression in the circuit to be tested is an expression in the header file called by the execution program.
Alternatively, the standard simulator is a mature EDA simulation tool.
Wherein S300 comprises F q The verification step of (2):
s310, the standard simulator generates F according to the circuit to be tested q The simulator to be verified generates F according to the circuit to be tested q The standard waveform and the input waveform of the operand in the waveform to be verified are the same.
The fact that the waveforms of the operands are the same means that the values of the operands in the standard waveforms change with the period is the same as the values of the operands in the waveforms to be verified change with the period.
S320, comparing the standard waveform with the F in the waveform to be verified q If the calculated results are consistent, F is determined q And (5) passing the verification.
It should be noted that the calculation results of the expressions in the standard waveform and the waveform to be verified are stored according to values, and whether the calculation results are consistent or not is compared, that is, whether the values in the calculation results are the same or not is compared.
In summary, the embodiments of the present invention provide a system for verifying an operator, where the operator is randomly selected and combined with an operand combination to generate a random expression, the random expression is respectively inserted into to-be-tested circuits of a standard simulator and a to-be-verified simulator, and the same input number is given to the operands, and whether the numerical values of the output results are equal or not is compared, and if not, it is determined that an error exists in the simulation result of the to-be-verified simulator. The random test case is generated by randomly selecting the operational characters, the accuracy and the completeness of the simulator to be verified are tested according to the random test case, the defects of incomplete tests such as missing test and the like caused by artificially and subjectively compiling the test case can be eliminated, and meanwhile, the test efficiency is improved.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. A system for validating operators, the system comprising: a database including an operator set OP and a predetermined operand set OD, wherein the OP includes all operators in a hardware description language and the OD includes different operands, and a memory storing a computer program which, when executed by the processor, implements the steps of:
s100, classifying the OP to obtain N operator categories OR = { OR = { (OR) } 1 ,OR 2 ,…,OR i ,…,OR N }，OR i ={or i,1 ,or i,2 ,…,or i,j ,…,or i,M In which OR is i For the ith operator type, the value range of i is 1 to N, N is the number of the operator types, or i,j Is the jth operator in the ith operator category, j has a value ranging from 1 to M, and M is OR i The number of medium operators;
s200, randomly generating Q random expressions F = { F) according to OR 1 ,F 2 ,…, F q ,…,F Q In which F q The expression is a qth random expression, the value range of Q is 1 to Q, and Q is the number of the random expressions; wherein, F q The generating step of (a) comprises:
s210, randomly selecting K times of operator categories from the OR to obtain K target categories OR = { OR = } 1 ´,OR 2 ´,…,OR k ´,…,OR K ´}，OR k Is' aGeneration of F q Randomly selecting the obtained operator category at the kth time, wherein the value range of K is from 1 to K, and K is the number of times of random selection;
s220, randomly selecting an operational character from each target category of OR' to obtain K target operational characters;
s230, selecting the operand from the OD, combining the operand with K target operators to generate F q ；
S300, inserting each random expression in the F into a circuit to be tested of a standard simulator and a circuit to be tested of a simulator to be verified respectively, verifying Q random expressions in the F through the standard simulator and the simulator to be verified respectively, and if all random expressions pass verification, passing verification of the simulator to be verified, otherwise, not passing verification.
2. The system of claim 1, wherein the operator set OP comprises a conditional operator, a monocular operator, and a binocular operator, and wherein the binocular operator does not comprise the operators "_," - > "and" < - > ".
3. The system of claim 1, wherein S100 further comprises:
s110, dividing the operator set OR into N operator categories according to the number of the operands required by the operators.
4. The system of claim 1, wherein S230 further comprises:
s231, determining the number Q of required operands of the k-th target operator in the expression k ；
S232, selecting Q from OD k Combining the operands with expressions generated by the first (k-1) target operational characters to obtain expressions of the first k target operational character combinations;
s233, repeating S231-S232 to obtain a random expression F of K target operator combinations q In which F q All operands in (a) are different from each other.
5. According to claimThe system of claim 1, wherein OR 'includes OR's having the same operator class k And OR r Wherein r ranges from 1 to N, and k ≠ r.
6. The system of claim 4, wherein Q is selected from OD k The plurality of operands includes: sequential selection of Q from OD k An operand, wherein the operand in the expression generated by the first k-1 target operators and the selected Q k The individual operands are different.
7. The system of claim 4, wherein Q is selected from OD k The plurality of operands includes: randomly selecting Q from OD k An operand, wherein the operand in the expression generated by the first k-1 target operators and the selected Q k The individual operands are different.
8. The system of claim 1, wherein the circuit under test of the standard simulator is the same as the circuit under test of the simulator to be verified.
9. The system according to claim 1, wherein the step of randomly choosing K times of operator categories from the OR in S210 is randomly choosing K times of operator categories by a random number generator.
10. The system of claim 1, wherein S300 comprises F q The verification step of (2):
s310, the standard simulator generates F according to the circuit to be tested q The simulator to be verified generates F according to the circuit to be tested q The standard waveform is the same as the input waveform of the operand in the waveform to be verified;
s320, comparing the standard waveform with F in the waveform to be verified q If the calculated results are consistent, F is determined q And (5) passing the verification.
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| CN104731556A (en) * | 2013-12-23 | 2015-06-24 | 国际商业机器公司 | Method and system for generating SIMD code from code statements |
| CN112905446A (en) * | 2020-12-29 | 2021-06-04 | 深圳前海微众银行股份有限公司 | Test case generation method, device, equipment and storage medium |
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| CN1696893A (en) * | 2004-05-13 | 2005-11-16 | 华为技术有限公司 | System and method for random number generatin apparatus and software testing |
| US20150067690A1 (en) * | 2013-09-05 | 2015-03-05 | Tata Consultancy Services Limited | System and method for generating a plan to complete a task in computing environment |
| CN104731556A (en) * | 2013-12-23 | 2015-06-24 | 国际商业机器公司 | Method and system for generating SIMD code from code statements |
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