CN115440672A

CN115440672A - Three-dimensional memory, manufacturing method thereof and storage system

Info

Publication number: CN115440672A
Application number: CN202210993856.8A
Authority: CN
Inventors: 何亚东
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-08-18
Filing date: 2022-08-18
Publication date: 2022-12-06

Abstract

The embodiment of the disclosure discloses a three-dimensional memory, a manufacturing method thereof and a storage system, wherein the method comprises the following steps: forming a stacked structure on the first semiconductor layer; forming a channel structure penetrating through the stacked structure; the channel structure includes a core, a first channel layer surrounding the core, and a functional layer; etching one end of the core part far away from the first semiconductor layer to form a first opening; filling the first opening to form a sacrificial part; forming an insulating layer and a selection gate covering the stacked structure and the sacrificial portion; forming a second opening penetrating through the selection gate and the insulating layer; the bottom of the second opening hole exposes the sacrificial part; forming a first dielectric layer covering the side wall of the second opening; removing the sacrificial portion through a second opening including the first dielectric layer to form a third opening; the third opening comprises a second opening; filling the third opening to form a conductive plug; the conductive plug includes a second channel layer penetrating the select gate and the insulating layer, the second channel layer being coupled with the first channel layer.

Description

Three-dimensional memory, manufacturing method thereof and storage system

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a three-dimensional memory, a manufacturing method thereof and a storage system.

Background

In order to meet the demand for higher memory density, a memory having a three-dimensional structure is developed. The 3D NAND memory has been widely used due to its advantages of fast writing speed, simple erasing operation, high storage density, etc.

In a conventional 3D NAND memory, a stacked structure and a channel structure penetrating through the stacked structure are usually disposed on a first semiconductor layer, and the stacked structure includes a gate layer and an interlayer dielectric layer stacked on each other. The gate layers can be used as word lines of the memory, each gate layer can correspond to one memory unit, and the higher the number of stacked gate layers is, the higher the storage density is. However, some gate layers in the stacked structure may be configured as top select gates, and the arrangement of the top select gates may occupy a portion of the stacked layers in the stacked structure, thereby reducing the number of word line layers, and thus reducing the storage density. How to better arrange the top selection gate becomes an urgent problem to be solved on the premise of not occupying the stacking layer number of the stacking structure.

Disclosure of Invention

According to a first aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a three-dimensional memory, including:

forming a stacked structure on the first semiconductor layer; wherein the stacked structure comprises gate layers and interlayer dielectric layers which are alternately stacked;

forming a channel structure through the stacked structure; along a radial direction of the channel structure, the channel structure includes: a core, a first channel layer surrounding the core, and a functional layer, the first channel layer being between the core and the functional layer;

etching one end of the core part far away from the first semiconductor layer to form a first opening;

filling the first opening to form a sacrificial part;

forming an insulating layer and a selection gate covering the stacked structure and the sacrificial part; wherein the insulating layer is located between the stack structure and the select gate;

forming a second opening penetrating through the selection gate and the insulating layer; wherein the sacrificial part is exposed from the bottom of the second opening;

forming a first dielectric layer covering the side wall of the second opening;

removing the sacrificial portion through the second opening including the first dielectric layer to form a third opening; wherein the third opening comprises a second opening;

filling the third opening to form a conductive plug; wherein the conductive plug includes a second channel layer extending through the select gate and the insulating layer, the second channel layer being coupled to the first channel layer.

According to a second aspect of embodiments of the present disclosure, there is provided a three-dimensional memory including:

a first semiconductor layer;

a stacked structure on the first semiconductor layer; the stacked structure comprises gate layers and interlayer dielectric layers which are alternately stacked;

a channel structure extending through the stacked structure; wherein, along a radial direction of the channel structure, the channel structure includes: a core, a first channel layer surrounding the core, and a functional layer, the first channel layer being between the core and the functional layer; the distance from the upper surface of the core part to the first semiconductor layer is smaller than the distance from the upper surface of the functional layer to the first semiconductor layer;

the selection gate is positioned at one end of the stacked structure far away from the first semiconductor layer;

an insulating layer between the select gate and the stack structure;

a conductive plug penetrating the select gate and the insulating layer; the conductive plug extends into the channel structure in contact with the core; wherein the conductive plug includes a second channel layer that extends through the select gate and into the channel structure, the second channel layer coupled with the first channel layer;

a first dielectric layer penetrating the select gate and surrounding the second channel layer.

According to a third aspect of embodiments of the present disclosure, there is provided a storage system including:

a memory including the three-dimensional memory in the above embodiments;

a memory controller coupled to the memory and configured to control the memory.

According to the embodiment of the disclosure, one end of the core part of the channel structure, which is far away from the first semiconductor layer, is etched to form a first opening, a sacrificial part is formed in the first opening, an insulating layer and a selection gate are formed to cover the stacked structure and the sacrificial part, a second channel layer penetrating through the selection gate and the insulating layer is formed after the sacrificial part is removed, and the second channel layer is coupled with the first channel layer in the channel structure. Compared with the scheme that the selection gate is arranged in the stack structure, the selection gate does not occupy a gate layer of the stack structure, and the storage density of the memory is improved. In addition, compared with the scheme of forming the opening penetrating through the select gate and the insulating layer, removing part of the core based on the opening etching, and then forming the second channel layer, the formation of the sacrificial part in the embodiment can reduce the over-etching of the core and the insulating layer, reduce the contact leakage phenomenon between the second channel layer and the select gate, improve the manufacturing yield of the memory, and maintain the good stability of the memory.

Drawings

FIGS. 1 a-1 h are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to an exemplary embodiment;

FIGS. 2a and 2b are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to another exemplary embodiment;

FIGS. 3a and 3b are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to yet another exemplary embodiment;

FIG. 4 is a flow chart illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;

fig. 5a to 5j are schematic diagrams illustrating a method for fabricating a three-dimensional memory according to an embodiment of the disclosure;

fig. 6a to 6e are schematic diagrams illustrating another method for fabricating a three-dimensional memory according to an embodiment of the disclosure;

FIG. 7 is a block diagram illustrating a system including a memory in accordance with an embodiment of the present disclosure;

FIG. 8a is a schematic diagram illustrating a memory card including a memory in accordance with an embodiment of the present disclosure;

FIG. 8b is a schematic diagram illustrating a Solid State Drive (SSD) including a memory in accordance with an embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating a memory including peripheral circuitry in accordance with an embodiment of the present disclosure;

FIG. 10 is a block diagram illustrating a memory including peripheral circuitry in accordance with an embodiment of the present disclosure.

Detailed Description

The technical solution of the present disclosure is further described in detail below with reference to the drawings and specific embodiments of the specification.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not used for describing a particular order or sequence.

In the disclosed embodiments, the term "a and B in contact" encompasses the situation where a and B are in direct contact, or A, B with other components interposed between them, with a in contact with B indirectly.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sublayers.

It is to be understood that the meaning of "on … …", "above … …" and "above … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something "with intervening features or layers therebetween.

It should be noted that although the present description is described in terms of embodiments, not every embodiment includes only a single technical solution, and such description of the embodiments is merely for clarity, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that can be understood by those skilled in the art.

FIG. 1 is a schematic diagram illustrating a method of fabricating a three-dimensional memory, according to an example embodiment.

With reference to fig. 1a to 1h, the manufacturing method includes the following steps:

the method comprises the following steps: referring to fig. 1a, a stack structure 110 is formed on a first semiconductor layer, and a channel structure 120 penetrating the stack structure 110 is formed, where the stack structure 110 includes a gate layer 111 and an interlayer dielectric layer 112 stacked in a z-direction; in a radial direction of the channel structure 120, the channel structure 120 includes a core portion 121, a first channel layer 122 surrounding the core portion 121, and a functional layer 123, the first channel layer 122 being located between the core portion 121 and the functional layer 123;

step two: referring to fig. 1a, forming an insulating layer 131 covering the stack structure 110 and the channel structure 120, forming a select gate 132 covering the insulating layer 131, and etching the select gate 132 to form an opening 140 penetrating the select gate 132 by using the mask layer 133 as an etching mask; wherein, the insulating layer 131 is exposed at the bottom of the opening 140;

step three: referring to fig. 1b, a dielectric layer 141 is formed to cover the sidewalls of the opening 140;

step four: referring to fig. 1c, a sacrificial layer 142 is formed to cover the dielectric layer 141 and the bottom of the opening 140; referring to fig. 1d, the bottom of the sacrificial layer 142 is etched to expose the insulating layer 131;

step five: referring to fig. 1e, the core 121 is etched through the opening 140 including the dielectric layer 141 and the sacrificial layer 142, removing a portion of the core 121, and forming a cavity 150 on top of the channel structure 120 away from the first semiconductor layer; the cavity 150 and the opening 140 are communicated in the z direction;

step six: referring to fig. 1f, the sacrificial layer 142 on the sidewall of the opening 140 and the first channel layer 122 on the sidewall of the cavity 150 are removed;

step seven: referring to fig. 1g, forming a second channel layer 161 covering sidewalls of the opening 140, covering sidewalls and/or a bottom of the cavity 150, the second channel layer 161 being coupled with the first channel layer 122;

step eight: referring to fig. 1h, after the second channel layer 161 is formed, the opening 140 and the remaining region of the cavity 150 are filled with an insulating material to form a filling portion 162, and a conductive portion 163 may be formed on the filling portion 162, and an upper surface of the conductive portion 163 may be flush with an upper surface of the second channel layer 161.

In this embodiment, with continued reference to fig. 1h, the select gate 132 may include a top select gate, and the top of the stacked structure 110 away from the first semiconductor layer (the first semiconductor layer is not shown in the drawing of this embodiment) may be turned on and off by applying different operating voltages to the select gate 132 to implement selection and non-selection of the channel structure 120. The gate layer 111 is not configured as a top select gate, and the gate layer 111 may be configured as a word line or a bottom select gate, and the word line may be configured to control a read, write, or erase operation of the memory cell. The bottom select gate may be configured to form a gate induced drain leakage current with the first semiconductor layer to perform an erase operation of the channel structure 120, in addition to being configured as a select-and-not-select for the channel structure 120. Conductive portions 163 may be used to couple with bit lines of a memory.

It can be understood that compared to the scheme of configuring a part of the gate layer 111 on the top of the stacked structure 110 as the top select gate, the top select gate of this embodiment does not occupy the gate layer 111 of the stacked structure 110, and on the premise that the stacked structures 110 have the same number of stacked layers, this embodiment is beneficial to increasing the number of layers of word lines, the number of layers of memory cells, and the storage density of the memory.

In the actual manufacturing process, over-etching occurs in the fifth step, which causes a low yield problem, and further reduces the stability of the memory. The etching process may include: dry etching, wet etching, or any combination thereof.

In some embodiments, the core portion 121 is wet etched through the openings 140 in fig. 1d, and due to the flow guiding effect of the openings 140, the core portion 121 directly under the openings 140 is etched by the etchant, so that the etching rate of the core portion 121 area directly under the openings 140 is higher than that of other areas, and the wet etching also has a higher etching rate than the dry etching, further deepening the difference of the etching rates of different areas of the core portion 121, and causing over-etching of the core portion 121, so as to form the cavity 150 with the tip protruding away from the select gate 132 as shown in fig. 2 a. And performing the sixth step and the seventh step, and removing the sacrificial layer 142 to form the second channel layer 161, thereby obtaining the structure shown in fig. 2 b.

Referring to fig. 2b, the second channel layer 161 also has a tip protruding away from the select gate 132. On one hand, the tip may cause a tip discharge phenomenon, increasing the risk of the tip discharge breaking down the first channel layer 122, and reducing the memory stability. On the other hand, the tip of the second channel layer 161 protrudes away from the select gate 132, so that the channel layer 122 corresponding to the several gate layers 111 close to the select gate 132 is formed by the protrusion and the first channel layer 122, so that the resistance of the part of the channel layer 122 is increased, which causes the operating voltage of the several gate layers 111 close to the select gate 132 to be shifted, and the stability of the memory is reduced.

In other embodiments, the core 121 is dry gas etched through the opening 140 in fig. 1d, the etch rate of the dry gas etch being smaller compared to the etch rate of the wet etch for the same material. When the etching time is increased to obtain the target etching amount, the etching gas diffuses and contacts the insulating layer 131, causing over-etching of the insulating layer 131, so that the formed cavity 150 exposes a portion of the select gate 132, resulting in the structure shown in fig. 3 a. And performing the sixth step and the seventh step, and removing the sacrificial layer 142 to form a second channel layer 161, thereby obtaining the structure shown in fig. 3 b.

Referring to fig. 3b, the second channel layer 161 and the select gate 132 are formed to contact each other to drain, so that the select gate 132 fails to work, and the control function of turning on and off the second channel layer 161 cannot be realized.

In view of this, a method for fabricating a three-dimensional memory is provided to increase the storage density of the memory without occupying the number of stacked layers of the stacked structure 110, and to improve the yield of fabricating the select gate 132 and maintain the stability of the memory.

Fig. 4 is a flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the disclosure. As shown in fig. 4, the manufacturing method includes the following steps:

s100: forming a stack structure 210 on the first semiconductor layer; the stack structure 210 includes gate layers 211 and interlayer dielectric layers 212 stacked alternately;

s200: referring to fig. 5a, a channel structure 220 is formed through the stacked structure 210; along a radial direction of the channel structure 220, the channel structure 220 includes: a core 221, a first channel layer 222 surrounding the core 221, and a functional layer 223, the first channel layer 222 being located between the core 221 and the functional layer 223;

s300: referring to fig. 5b, an end of the core portion 221 away from the first semiconductor layer is etched to form a first opening 230;

s400: referring to fig. 5c, the first opening 230 is filled to form a sacrificial portion 231;

s500: referring to fig. 5d, an insulating layer 241 and a select gate 242 are formed covering the stack structure 210 and the sacrificial portion 231; wherein the insulating layer 241 is located between the stacked structure 210 and the select gate 242;

s600: referring to fig. 5e, a second opening 250 is formed through the select gate 242 and the insulating layer 241; wherein, the bottom of the second opening 250 exposes the sacrificial portion 231;

s700: referring to fig. 5f, a first dielectric layer 251 is formed covering the sidewalls of the second opening 250;

s800: referring to fig. 5g and 5h, the sacrificial portion 231 is removed through the second opening 250 including the first dielectric layer 251 to form a third opening 270; wherein the third opening 270 includes the second opening 250;

s900: referring to fig. 5i and 5j, the third opening 270 is filled to form a conductive plug 271; the conductive plug 271 includes a second channel layer 272 penetrating the select gate 242 and the insulating layer 241, and the second channel layer 272 is coupled to the first channel layer 222.

Specifically, the stack structure 210 may include gate layers 211 and interlayer dielectric layers 212 alternately stacked on the first semiconductor layer. The method of forming the channel structure 220 may include: a trench hole penetrating the stack structure 210 is formed, the trench hole is filled to form the functional layer 223 covering sidewalls of the trench hole, the first channel layer 222 covering the functional layer 223 is formed, and the core portion 221 is formed. Referring to fig. 5a, the stacked structure 210 is covered by a filling material for forming the functional layer 223 and the first channel layer 222, and a portion of the filling material covering the stacked structure 210 may be removed by using a mechanochemical polishing. In order to reduce the damage of the etching process to the stack structure 210, the embodiments of the present disclosure need to etch the top of the core 221, and integrate the mechanical and chemical polishing process step into fig. 5c after the sacrificial part 231 is formed, so that the upper surface of the sacrificial part 231, the first channel layer 222, the functional layer 223, and the upper surface of the stack structure 210 are flush. The top or upper portion of the core 221 is the end of the core 221 away from the first semiconductor layer.

It should be emphasized that the first semiconductor layer in the embodiments of the present disclosure is a film structure with a certain thickness, and may include a bare wafer or an epitaxial layer. For example, the first semiconductor layer is a bare wafer (e.g., a bare silicon wafer) on which a plating process, an etching process, etc. is not performed. Or, the first semiconductor layer is an epitaxial layer epitaxially grown on the surface of the bare wafer, the material of the epitaxial layer may be the same as or different from that of the bare wafer, and the bare wafer may be removed in a certain manufacturing process, leaving the epitaxial layer as the first semiconductor layer.

The one channel structure 220 shown in the embodiment of the present disclosure is merely an example, and a plurality of channel structures 220 may be included to constitute a memory array. The channel structure 220 may extend through the stack structure 210 into the first semiconductor layer, to which the first channel layer 222 of the channel structure 220 is coupled, and which serves as a common source (alternatively referred to as an array common source ACS) to power the channel structure 220.

In some other embodiments, the stacked structure 210 may be formed on a bare wafer, and after forming the channel structure 220 penetrating the stacked structure 210, the bare wafer is removed to expose the bottom of the channel structure 220. The functional layer 223 at the bottom of the channel structure 220 is etched away to expose the first channel layer 222, and the exposed first channel layer 222 is covered with a semiconductor material to form a first semiconductor layer, which serves as a common source to supply power to the channel structure 220.

In some embodiments, along a radial direction of the channel structure 220, the functional layer 223 includes a barrier sublayer, a storage sublayer and a tunneling sublayer, the storage sublayer is located between the barrier sublayer and the tunneling sublayer, and the tunneling sublayer is located between the storage sublayer and the first channel layer 222. Wherein the barrier sublayer may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The storage sub-layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling sublayer may include silicon oxide, silicon oxynitride, or any combination thereof. In the disclosed embodiment, the combination of the functional layer 223 is a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO), and the channel layer is a polysilicon layer.

Illustratively, the constituent materials of the interlayer dielectric layer 212, the insulating layer 241, and the core portion 221 may include: an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

Illustratively, the material of the gate layer 211 and the select gate 242 may include: tungsten, platinum, gold, silver, copper, nickel, titanium, single crystal silicon, polycrystalline silicon, or the like.

Illustratively, the process of forming the stack structure 210, the first channel layer 222, the functional layer 223, and the select gate 242 includes: low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, atomic layer deposition, or plasma enhanced chemical vapor deposition.

Referring to fig. 5d, one select gate 242 is shown as an example, and the number of select gates 242 is not limited. For example, two, three, or more select gates 242 are provided, and adjacent select gates 242 are electrically isolated from each other by a dielectric layer, so that the situation that the channel structure 220 cannot be selected due to failure of one select gate 242 can be prevented, and the stability of the memory can be improved.

In some embodiments, as shown in fig. 5d and 5e, a mask layer 243, such as silicon nitride, silicon oxynitride or aluminum oxide, may be further formed on the select gate 242. The mask layer 243 is used as an etching mask to etch the select gate 242 and the insulating layer 241, so as to form a second opening 250 penetrating through the select gate 242 and the insulating layer 241, wherein the sacrificial portion 231 is exposed from the second opening 250. The etching process may also partially etch the sacrificial portion 231, i.e., the second opening 250 may also extend into the sacrificial portion 231. The mask layer 243 covers the surface of the select gate 242, and may also reduce oxidation of the select gate 242.

Referring to fig. 5f, the sidewalls of the second opening 250 are filled with an insulating material, and a first dielectric layer 251 is formed to cover at least the sidewalls of the select gate 242 exposed from the second opening 250 as a gate dielectric layer between the select gate 242 and the second channel layer 272. In some embodiments, the first dielectric layer 251 may also cover the side of the insulating layer 241 exposed from the second opening 250.

Illustratively, the constituent material of the sacrificial portion 231 may include: monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

As shown in fig. 5f and fig. 5g, the materials of the sacrificial portion 231 and the core portion 221 may be different, which is beneficial to increase the etching rate of the sacrificial portion 231 and the core portion 221 in the etching process, increase the etching selectivity, facilitate the removal of the sacrificial portion 231 in S800, reduce the over-etching phenomenon of the core portion 221, and improve the manufacturing yield. For example, the core 221 and insulating layer 241 may be a common silicon oxide, the sacrificial portion 231 is polysilicon, and the etchant may be chlorine, carbon tetrachloride, or any combination of other gaseous and liquid etchants. The etching rate of the sacrificial part 231 in the etchant is greater than that of the core part 221, and the etching rate of the sacrificial part 231 in the etchant is also greater than that of the insulating layer 241 in the etchant, so that the removal of the sacrificial part 231 is facilitated, the overetching of the core part 221 and the insulating layer 241 is reduced, the phenomena shown in fig. 2a and fig. 3a are reduced, and the manufacturing yield is improved.

Referring to fig. 5g, after the sacrificial portion 231 is removed, a cavity 260 is formed at the top of the channel structure 220, and the cavity 260 is communicated with the second opening 250 to form a third opening 270. In some embodiments, as illustrated with reference to fig. 5h, a portion of the first channel layer 222 in contact with the sacrificial portion 231 may also be removed when the sacrificial portion 231 is removed.

Referring to fig. 5i, a second channel layer 272 covering sidewalls and/or a bottom of the third opening 270 is formed, the second channel layer 272 extending into the channel structure 220 and being coupled with the first channel layer 222. Different voltages are applied to the select gate 242 to control the on and off of the second channel layer 272, so as to select and deselect the channel structure 220, and after the channel structure 220 is selected, an operation voltage is applied to the gate layer 211 to perform operations such as reading, writing or erasing on the memory cell. The material of the second channel layer 272 may be the same as the material of the first channel layer 222, for example, polysilicon.

Referring to fig. 5j, the conductive plug 271 may include a second channel layer 272, a filling portion 273 and a conductive portion 274. The method of forming the conductive plug 271 includes: the third opening 270 including the second channel layer 272 in fig. 5h is filled to form a filling portion 273, and a conductive portion 274 coupled to the second channel layer 272 is formed on the filling portion 273, wherein the conductive portion 274 may be used as a contact point for coupling to a memory bit line. The filling portion 273 may provide support for the second channel layer 272, and the constituent material of the filling portion 273 may include: an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

In the embodiment of the present disclosure, a first opening 230 is formed by etching an end of the core 221 of the channel structure 220 away from the first semiconductor layer, a sacrificial portion 231 is formed in the first opening, an insulating layer 241 and a select gate 242 covering the stacked structure 210 and the sacrificial portion 231 are formed, a second channel layer 272 penetrating the select gate 242 and the insulating layer 241 is formed after removing the sacrificial portion 231, and the second channel layer 272 is coupled to the first channel layer 222 in the channel structure 220. Compared with the scheme that the select gate 242 is disposed in the stack structure 210, the select gate 242 of the embodiment of the disclosure does not occupy the gate layer 211 of the stack structure 210, which is beneficial to improving the storage density of the memory. In addition, compared to the scheme of forming the opening penetrating through the select gate 242 and the insulating layer 241, etching and removing part of the core 221 based on the opening, and then forming the second channel layer 272, the formation of the sacrificial portion 231 according to this embodiment can reduce over-etching to the core 221 and the insulating layer 241, reduce the contact leakage phenomenon between the second channel layer 272 and the select gate 242, improve the manufacturing yield of the memory, and maintain the good stability of the memory.

In some embodiments, referring to fig. 5b, the stacked structure 210 includes a gate layer 211 and an interlayer dielectric layer 212 stacked on each other, and a layer of the stacked structure 210 farthest from the first semiconductor layer is a top interlayer dielectric layer 213;

the depth of the first opening 230 is less than the thickness of the top interlevel dielectric layer 213 in a direction perpendicular to the first semiconductor layer.

In this embodiment, referring to fig. 5d, the topmost layer of the stacked structure 210 is a top interlayer dielectric layer 213, the thickness of the top interlayer dielectric layer 213 in the z-direction may be greater than the thickness of the gate layer 211 and the other interlayer dielectric layers 212, and the top interlayer dielectric layer 213 is located between the topmost gate layer 211 and the insulating layer 241. In fig. 5b, the depth of the first opening 230 in the z-direction is less than the thickness of the top interlevel dielectric layer 213.

In some embodiments, referring to fig. 5h, the method further comprises: a portion of the first channel layer 222 contacting the sacrificial portion 231 is removed through the second opening 250.

As shown in fig. 5g, in the process of removing the sacrificial portion 231 by etching, the etchant may damage or oxidize a portion of the first channel layer 222 in contact with the sacrificial portion 231, and when the sacrificial portion 231 is removed, a portion of the first channel layer 222 in contact with the sacrificial portion 231 may also be removed, and then the second channel layer 272 shown in fig. 5i is formed. Compared with the damaged part of the first channel layer 222, the reformed second channel layer 272 has better film forming quality, which is beneficial to improving the stability of the memory.

It is understood that, referring to fig. 5b, when the first opening 230 is formed in the step S300, the depth of the first opening 230 is positively correlated to the depth of the second channel layer 272 extending into the channel structure 220. The greater the depth of the first opening 230 in fig. 5b, the more the first channel layer 222 in fig. 5h needs to be removed, and the greater the depth that the second channel layer 272 extends into the channel structure 220 in fig. 5 i. The second channel layer 272 and the first channel layer 222 are manufactured through two processes, the crystal form and the thickness of the second channel layer 272 are difficult to be consistent with those of the first channel layer 222, and electrical properties such as resistance are different. For example, the depth of the third opening 270 is smaller than that of the trench hole, which is beneficial for filling the filling material, and the thickness of the second channel layer 272 formed under the same process conditions is thicker than that of the first channel layer 222, the resistance is smaller, and the operating voltage such as the on-state voltage is reduced.

If the depth of the first opening 230 is too large to be larger than the thickness of the top interlayer dielectric layer 213, a portion of the gate layer 211 close to the select gate 242 corresponds to the second channel layer 272, and the rest of the gate layer 211 corresponds to the first channel layer 222, so that the operating voltage of the portion of the gate layer 211 close to the select gate 242 is shifted, the operating voltage between the two portions of the gate layer 211 is greatly different, and the stability of reading, writing or erasing of the memory is reduced.

In the embodiment of the present disclosure, the depth of the first opening 230 is smaller than the thickness of the top interlayer dielectric layer 213, and the second channel layer 272 only extends in the region of the top interlayer dielectric layer 213, so that on one hand, all channel layers corresponding to the gate layer 211 are the first channel layer 222, thereby reducing the offset of the operating voltage of the gate layer 211, improving the stability of the memory, and on the other hand, the formation amount of the second channel layer 272 can be reduced, and the manufacturing cost can be reduced.

In some embodiments, forming the second opening 250 through the select gate 242 and the insulating layer 241 includes:

referring to fig. 6a, a first sub-hole 252 is formed through the select gate 242 and extending into the insulating layer 241; wherein the bottom of the first sub-hole 252 is located in the insulating layer 241;

referring to fig. 6b, a second dielectric layer 253 is formed covering the sidewalls and/or bottom of the first sub-hole 252;

referring to fig. 6c, a sacrificial layer 254 is formed overlying the second dielectric layer 253;

referring to fig. 6d and 6e, the sacrificial layer 254 and/or the second dielectric layer 253 at the bottom of the first sub-hole 252 are removed until the sacrificial portion 231 is exposed to form a second opening 250 including the first dielectric layer 251 and the sacrificial layer 254.

In this embodiment, the second opening 250 may be formed by etching the select gate 242 a plurality of times to form a first sub-opening 252, and etching through the insulating layer 241 based on the first sub-opening 252 to form a second sub-opening exposing the sacrificial portion 231. In some examples, referring to fig. 6a, during the etching of the select gate 242, a portion of the bottom-thick insulating layer 142 may be etched such that the first sub-hole 252 extends into the insulating layer 241, and then a second dielectric layer 253 is formed as shown in fig. 6b, the second dielectric layer 253 at least covering the exposed select gate 242 sidewalls in the first sub-hole 252. In other examples, the first sub-hole 252 may only penetrate the select gate 242, and the first sub-hole 252 exposes the upper surface of the insulating layer 241.

Referring to fig. 6d, the sacrificial layer 254 and the second dielectric layer 253 at the bottom of the first sub-hole 252 are removed to expose the insulating layer 241, and etching is continued through the insulating layer 241 until the sacrificial portion 231 is exposed, and the second dielectric layer 253 covering the select gate 242 forms the first dielectric layer 251 shown in fig. 6 e. The sacrificial layer 254 is made of a different material than the second dielectric layer 253, and during the etching process for forming the second opening 250 in fig. 6d and 6e, the sacrificial layer 254 is used to protect the second dielectric layer 253 from the etchant, and to maintain the thickness and the shape of the first dielectric layer 251. Illustratively, the constituent materials of the sacrificial layer 254 may include: single crystal silicon, polycrystalline silicon, or amorphous silicon. The second dielectric layer 253 may include: an insulating material such as silicon oxide, silicon oxynitride, or aluminum oxide.

In some embodiments, as shown in conjunction with fig. 6e and 5h, removing the sacrificial portion 231 through the second opening 250 to form the third opening 270 further comprises: the sacrificial layer 254 is removed.

The sacrificial layer 254 in fig. 6e is removed to expose the first dielectric layer 251, and the third opening 270 in fig. 5h is formed, so as to form a second channel layer 272 covering the first dielectric layer 251. The sacrificial layer 254 may be removed after the sacrificial portion 231 is removed, and the sacrificial layer 254 may also be removed at the same time as the sacrificial portion 231 is removed. The sacrificial layer 254 and the sacrificial portion 231 may be made of the same material, so that the sacrificial layer 254 and the sacrificial portion 231 can be removed in the same etching process, the process can be completed conveniently, and the manufacturing cost can be reduced.

In some embodiments, as shown with reference to fig. 5i, filling the third opening 270 to form the conductive plug 271 includes:

forming a second channel layer 272 covering sidewalls and/or a bottom of the third opening 270; wherein the second channel layer 272 is coupled with the first channel layer 222.

The process of forming the second channel layer 272 may be the same as the first channel layer 222, and the material of the second channel layer 272 may be the same as the material of the first channel layer 222, for example, a semiconductor material such as polysilicon.

The second channel layer 272 extends into the channel structure 220 and is coupled to the first channel layer 222, and the on and off of the second channel layer 272 are controlled by applying different voltages to the select gate 242, so as to select or deselect the entire channel structure 220, and after the channel structure 220 is selected, different operating voltages are applied to the gate layer 211 to perform operations such as reading, writing or erasing on the memory cell.

In some embodiments, the third opening 270 is filled with polysilicon, and after forming a polysilicon layer covering the third opening 270 and/or the bottom, the filling is continued, and the second channel layer 272 is formed to fill the cavity 260 and/or the second opening 250 at the top of the channel structure 220. The second channel layer 272 of this embodiment may not only couple to the first channel layer 222, but may also provide mechanical support to the conductive plug 271.

In some embodiments, referring to fig. 5j, the conductive plug 271 further comprises a filling portion 273, and filling the third aperture 270 to form the conductive plug 271 further comprises:

the third opening 270 including the second channel layer 272 is filled with an insulating material, forming a filling portion 273.

After forming the second channel layer 272 covering the third opening 270 as shown in fig. 5i, the fabrication process of the second channel layer 272 is stopped, and the filling with the insulating material is continued, so as to form a filling portion 273 as shown in fig. 5j, wherein the filling portion 273 provides support for the second channel layer 272.

Referring to fig. 5j, an insulating fill portion 273 may extend from the top of the channel structure 220 toward the select gate 242, and an upper surface of the fill portion 273 may be flush with an upper surface of the select gate 242. Compared with the filling part 273 formed of a semiconductor material or a conductive material, the insulating filling part 273 does not increase the actual thickness of the second conductive layer, thereby being beneficial to reducing the thickness difference and the resistance difference between the second channel layer 272 and the first channel layer 222, being beneficial to reducing the difference between the turn-on voltage of the first channel layer 222 and the turn-on voltage of the second channel layer 272, and improving the stability of the memory.

In some embodiments, with continued reference to fig. 5j, filling the third opening 270 to form the conductive plug 271 further comprises:

forming a conductive portion 274 on the filling portion 273, the conductive portion 274 being coupled with the second channel layer 272; wherein the upper surface of the conductive portion 274 is flush with the upper surface of the second channel layer 272.

In this embodiment, the conductive portion 274 is surrounded by the second channel layer 272, a side surface of the conductive portion 274 is coupled with a side surface of the second channel layer 272, and the conductive portion 274 may serve as a contact site with a memory bit line. The conductive portions 274 may comprise a doped semiconductor material. The conductive portion 274 may be made of the same material as the second channel layer 272 in the embodiment of the disclosure, for example, polysilicon, which may be n-doped to improve conductivity. The doping process may include: ion implantation, diffusion, or any combination thereof. The n-type doped element includes a pentavalent element such as nitrogen, phosphorus, or arsenic.

FIG. 5j is a schematic diagram illustrating a three-dimensional memory according to an embodiment of the present disclosure. Referring to fig. 5j, the three-dimensional memory includes:

a first semiconductor layer;

a stack structure 210 on the first semiconductor layer; the stack structure 210 includes gate layers 211 and interlayer dielectric layers 212 stacked alternately;

a channel structure 220 penetrating the stacked structure 210; wherein, along a radial direction of the channel structure 220, the channel structure 220 includes: a core 221, a first channel layer 222 surrounding the core 221, and a functional layer 223, the first channel layer 222 being located between the core 221 and the functional layer 223; the distance from the upper surface of the core portion 221 to the first semiconductor layer is smaller than the distance from the upper surface of the functional layer 223 to the first semiconductor layer;

a select gate 242 at an end of the stacked structure 210 away from the first semiconductor layer;

an insulating layer 241 between the select gate 242 and the stack structure 210;

a conductive plug 271 penetrating the select gate 242 and the insulating layer 241; a conductive plug 271 extends into the channel structure 220 in contact with the core 221; the conductive plug 271 includes a second channel layer 272, the second channel layer 272 penetrates through the select gate 242 and extends into the channel structure 220, and the second channel layer 272 is coupled to the first channel layer 222;

the first dielectric layer 251 penetrates the select gate 242 and surrounds the second channel layer 272.

For example, the composition material of the first semiconductor layer may include: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. The first semiconductor layer may be used to support the stacked structure 210 and the channel structure 220, is located at a lower portion of the stacked structure 210, and may also be used as a common source to supply power to the channel structure 220, which is not shown in the drawing of the present embodiment.

In fig. 5j, the stacked structure 210 includes a gate layer 211 and an interlayer dielectric layer 212 stacked on each other, the gate layer 211 is used as a word line of the memory, and different operating voltages are applied through the gate layer 211 to perform read, write or erase operations. The gate layer 211 shown in this embodiment is only an example, and there may be a stack of more gate layers 211, for example, 32 layers, 64 layers, 96 layers, 128 layers, or more.

In a radial direction of the channel structure 220, the channel structure 220 includes a core 221, a first channel layer 222 surrounding the core 221, and a functional layer 223 surrounding the first channel layer 222. The functional layer 223 includes a barrier sublayer, a storage sublayer and a tunneling sublayer, the storage sublayer is located between the barrier sublayer and the tunneling sublayer, and the tunneling sublayer is located between the storage sublayer and the first channel layer 222. Wherein the barrier sublayer may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The storage sub-layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling sublayer may include silicon oxide, silicon oxynitride, or any combination thereof. In the disclosed embodiment, the combination of the functional layer 223 is a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO), and the channel layer is a polysilicon layer.

The insulating layer 241 is used for electrically isolating the stacked structure 210, the channel structure 220, the second channel layer 272 and the select gate 242, so as to reduce the phenomenon of mutual contact and leakage between the select gate 242 and the second channel layer 272, and maintain good stability of the memory.

In the channel structure 220, the upper surface of the core portion 221 is a surface of the core portion 221 on a side away from the first semiconductor layer, that is, a surface of the core portion 221 on a side close to the select gate 242. In the z direction, the upper surface of the core 221 is below the upper surface of the functional layer 223, and after the conductive plug 271 penetrates through the selection gate 242 and the insulating layer 241, the conductive plug 271 extends into the channel structure 220 to contact the upper surface of the core 221, and the portion of the conductive plug 271 extending into the channel structure 220 is surrounded by the functional layer 223. The second channel layer 272 is coupled to the first channel layer 222 together with the conductive plug 271 extending through the channel structure 220, and a portion of the second channel layer 272 extending into the channel structure 220 is surrounded by the functional layer 223. The second channel layer 272 is coupled to the first channel layer 222, and the on/off of the second channel layer 272 is controlled by applying different voltages to the select gate 242, so as to select or deselect the entire channel structure 220, and after the channel structure 220 is selected, an operation voltage is applied to the gate layer 211 to perform operations such as reading, writing, or erasing on the memory cell.

The first dielectric layer 251, located between the select gate 242 and the second channel layer 272, extends through at least the select gate 242, the first dielectric layer 251 electrically isolating the select gate 242 from the second channel layer 272 as a gate first dielectric layer between the select gate 242 and the second channel layer 272. In some embodiments, the first dielectric layer 251 extends through the select gate 242 and may extend into the insulating layer 241.

With continued reference to fig. 5j, the second channel layer 272 in the disclosed embodiments extends through the select gate 242 and into the channel structure 220 to couple with the first channel layer 222. Compared with the solution of disposing a conductive block surrounded by a functional layer on top of the channel structure 220 and using the conductive block to couple the second channel layer 272 and the first channel layer 222, the second channel layer 272 and the first channel layer 222 of the present embodiment may both have a film structure, which may reduce the thickness difference between the first channel layer 222 and the second channel layer 272 and avoid the situation that the introduction of the conductive block makes the channel layer thicker and thus reduces the stability of the memory. In some embodiments, an upper surface of the first channel layer 222 is flush with an upper surface of the core 221.

Referring to fig. 5j, the second channel layer 272 extends into the channel structure 220, and a lower surface of the second channel layer 272 is contact-coupled with an upper surface of the first channel layer 222. In the x direction, the second channel layer 272 and the first channel layer 222 do not overlap, that is, in the z direction, the second channel layer 272 covers a part of the functional layer 223, and the remaining functional layer 223 is covered by the first channel layer 222. Compared with the way that the first channel layer 222 and the second channel layer 272 are stacked and intersected to form coupling, the thickness difference between the first channel layer 222 and the second channel layer 272 can be reduced, and the situation that the channel layers are thickened due to the stacking and intersecting to reduce the stability of the memory is avoided.

In some embodiments, referring to fig. 5j, the stacked structure 210 includes a gate layer 211 and an interlayer dielectric layer 212 stacked on each other, and a layer of the stacked structure 210 farthest from the first semiconductor layer is a top interlayer dielectric layer 213;

the second channel layer 272 extends into the channel structure 220 to a depth less than the thickness of the top interlayer dielectric layer 213.

The depth of the second channel layer 272 extending into the channel structure 220 is too large, and exceeds the thickness of the top interlayer dielectric layer 213, so that a part of the gate layer 211 near the select gate 242 corresponds to the second channel layer 272, and the rest of the gate layer 211 corresponds to the first channel layer 222, so that the operating voltage of a part of the gate layer 211 near the select gate 242 is shifted, a large difference is generated between the operating voltages of two parts of the gate layer 211, and the stability of reading, writing or erasing of the memory is reduced.

The second channel layer 272 in the embodiment of the present disclosure only extends in the region of the top interlayer dielectric layer 213, so that on one hand, all channel layers corresponding to the gate layer 211 are the first channel layer 222, which reduces the offset of the operating voltage of the gate layer 211, and improves the stability of the memory, and on the other hand, the amount of the second channel layer 272 formed can also be reduced, and the manufacturing cost can be reduced.

In some embodiments, as shown with reference to fig. 5j, the conductive patch 271 further includes a filler portion 273; the filling portion 273 is surrounded at the side and/or bottom by the second channel layer 272.

The filling portion 273 provides support for the second channel layer 272, reducing deformation of the conductive plug 271. The filling portion 273 may include an insulating material, and compared to forming the filling portion 273 with a semiconductor material or a conductive material, the insulating filling portion 273 may not increase the actual thickness of the second conductive layer, thereby facilitating to reduce the thickness difference and the resistance difference between the second channel layer 272 and the first channel layer 222, facilitating to reduce the difference between the turn-on voltage of the first channel layer 222 and the turn-on voltage of the second channel layer 272, and improving the stability of the memory. A filling portion 273 may extend from the top of the channel structure 220 toward the select gate 242, and an upper surface of the filling portion 273 may be flush with an upper surface of the select gate 242.

In some embodiments, referring to fig. 5j, the conductive plug 271 further includes a conductive portion 274, the conductive portion 274 being coupled with the second channel layer 272; the conductive portions 274 are located above the filling portions 273, and the upper surfaces of the conductive portions 274 are flush with the upper surface of the second channel layer 272.

In this embodiment, the conductive portion 274 is surrounded by the second channel layer 272, a side surface of the conductive portion 274 is coupled with a side surface of the second channel layer 272, and the conductive portion 274 may serve as a contact site with a memory bit line. The conductive portions 274 may comprise a doped semiconductor material. The conductive portion 274 may be made of the same material as the second channel layer 272 in the embodiment of the present disclosure, for example, polysilicon, which may be n-doped to improve conductivity.

In some other embodiments, an upper surface of the filling portion 273 is flush with an upper surface of the second channel layer 272, the conductive portion 274 is located on the filling portion 273 to be above the second channel layer 272, and a lower surface of the conductive portion 274 is coupled with the upper surface of the channel layer.

FIG. 7 is a block diagram illustrating a system 700 including a storage system according to an embodiment of the disclosure.

Referring to FIG. 7, a storage system 702 includes:

a memory 704 comprising the three-dimensional memory shown in FIGS. 1h and 5j of the disclosed embodiments;

a memory controller 706 coupled to the memory 704 and configured to control the memory.

In particular, system 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein.

As shown in fig. 7, the system 700 may include a host 708 and a storage system 702, the storage system 702 having one or more memories 704 and a memory controller 706. The host 708 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of the electronic device. Host 708 may be configured to send data to memory 704 or receive data from memory 704.

Memory 704 may include a three-dimensional memory in embodiments of the present disclosure, such as the three-dimensional memory shown in fig. 5j that includes channel structure 220 and select gate 242. As explained in detail below, the memory 704 (e.g., a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory)) may have reduced leakage current from the drive transistors (e.g., string drivers) coupled to unselected word lines during an erase operation, which allows for further scaling of the drive transistors.

In some embodiments, memory controller 706 is coupled to memory 704 and host 708 and is configured to control memory 704. The memory controller 706 may manage data stored in the memory 704 and communicate with the host 708.

In some embodiments, the memory controller 706 is designed for operation in low duty cycle environments, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth.

In some embodiments, the memory controller 706 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data store for mobile devices such as smart phones, tablets, laptops, etc., as well as enterprise memory arrays. The memory controller 706 may be configured to control operations of the memory 704, such as read, erase, and program operations. The memory controller 706 may also be configured to manage various functions with respect to data stored or to be stored in the memory 704, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

In some embodiments, the memory controller 706 is also configured to process Error Correction Codes (ECC) with respect to data read from the memory 704 or written to the memory 704. The memory controller 706 may also perform any other suitable functions, such as formatting the memory 704. The memory controller 706 may communicate with external devices (e.g., the host 708) according to a particular communication protocol. For example, the memory controller 706 may communicate with external devices via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 706 and the one or more memories 704 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 702 may be implemented and packaged into different types of end electronic products.

Referring to FIG. 8a, in some embodiments, the memory controller 706 and the single memory 704 may be integrated into the memory card 802. The memory card 802 may include a PC card (PCMCIA, personal computer memory card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, minisD, microsD, SDHC), UFS, and the like. The memory card 802 may also include a memory card connector 804 that couples the memory card 802 with a host (e.g., host 708 in FIG. 5).

Referring to fig. 8b, in some embodiments, memory controller 706 and plurality of memories 704 may be integrated into SSD 806. SSD 806 may also include an SSD connector 808 that couples SSD 806 with a host (e.g., host 708 in fig. 5).

In some embodiments, the storage capacity and/or operating speed of SSD 806 may be greater than the storage capacity and/or operating speed of memory card 802.

Fig. 9 is a schematic circuit diagram illustrating a memory 900 including peripheral circuits according to an embodiment of the present disclosure. Memory 900 may be an example of memory 704 in fig. 7. Referring to fig. 9, a memory 900 may include a memory array 901 and peripheral circuitry 902 coupled to the memory array 901. The memory array 901 may be a NAND flash memory array in which the memory cells 906 are provided in an array of NAND memory strings 908, each NAND memory string 908 extending vertically above a first semiconductor layer (not shown). The memory array 901 shown in fig. 9 may be a circuit diagram of the memory array (including the plurality of channel structures 220) shown in fig. 5 j.

In some embodiments, each NAND memory string 908 comprises a plurality of memory cells 906 coupled in series and stacked vertically. Each memory cell 906 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 906. Each memory cell 906 may be a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

Memory string 908 in fig. 9 may include any of the channel structures 220 in fig. 5 j. One memory cell 906 may include, in the x-direction, one gate layer 211 corresponding to a portion of the first channel layer 222 and a portion of the functional layer 223 of the channel structure 220. The number of layers of the gate layer 211 (i.e., the word line 918 in fig. 9) may determine the number of memory cells 906.

In some embodiments, each memory cell 906 is a Single Level Cell (SLC) that has two possible memory states and therefore can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

In some embodiments, each memory cell 906 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, MLCs may store two bits per cell, three bits per cell (also known as Triple Level Cells (TLC)), or four bits per cell (also known as Quadruple Level Cells (QLC)). Each MLC may be programmed to assume a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values to the cell. The fourth nominal storage value may be used for the erased state.

Referring to fig. 9, each NAND memory string 908 can include a Source Select Gate (SSG) 910 at its source end and a Drain Select Gate (DSG) 912 at its drain end. The SSGs 910 and DSGs 912 may be configured to activate selected NAND memory strings 908 (columns of the memory array) during read and program operations. The gate of Drain Select Gate (DSG) 912 may comprise select gate 242 in fig. 5 j.

In some embodiments, the sources of NAND memory strings 908 in the same block 904 are coupled by the same Source Line (SL) 914 (e.g., a common SL). All of the NAND memory strings 908 in the same block 904 may have an Array Common Source (ACS).

In some embodiments, the DSG912 of each NAND memory string 908 is coupled to a respective bit line 916, and data can be read from or written to the bit line 916 via an output bus (not shown).

In some embodiments, each NAND memory string 908 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the DSG 912) or a deselect voltage (e.g., 0V) to the corresponding DSG912 via one or more DSG lines 913 and/or by applying a select voltage (e.g., above the threshold voltage of the transistor having the SSG 910) or a deselect voltage (e.g., 0V) to the corresponding SSG 910 via one or more SSG lines 915.

Referring to fig. 9, NAND memory strings 908 may be organized into a plurality of blocks 904, each of the plurality of blocks 904 may have a common source line 914 (e.g., coupled to ground).

In some embodiments, each block 904 may be the basic unit of data for an erase operation, i.e., all storage cells 906 on the same block 904 may be erased at the same time. To erase memory cells 906 in selected blocks 904a, the source lines 914 coupled to the selected blocks 904a and the unselected blocks 904b in the same plane as the selected blocks 904a may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

It will be appreciated that the erase operation may be performed at a half block level, at a quarter block level, or at any suitable level with any suitable number of blocks or fractions of blocks. The memory cells 906 of adjacent NAND memory strings 908 can be coupled by a word line 918, with the word line 918 selecting which row of memory cells 906 is affected by the read and program operations.

In some embodiments, each word line 918 is coupled to a page 920 of memory cells 906, the page 920 may be the basic unit of data for a programming operation. The size of a page 920 in bits may be related to the number of NAND memory strings 908 coupled by a word line 918 in one block 904. Each word line 918 may include a plurality of control gates (gate electrodes) at each memory cell 906 in a respective page 920 and a gate line coupling the control gates.

With continued reference to FIG. 9, the peripheral circuitry 902 may be coupled to the memory array 901 through bit lines 916, word lines 918, source lines 914, SSG lines 915, and DSG lines 913. The peripheral circuitry 902 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory array 901 by applying and sensing voltage and/or current signals to and from each target memory cell 906 via the bit line 916, the word line 918, the source line 914, the SSG line 915, and the DSG line 913. The peripheral circuitry 902 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

For example, fig. 10 shows some exemplary peripheral circuits, and peripheral circuit 902 may include page buffers/sense amplifiers 1004, column decoders/bit line drivers 1006, row decoders/word line drivers 1008, voltage generators 1010, control logic units 1012, registers 1014, interfaces 1016, and a data bus 1018. It will be appreciated that in some embodiments, additional peripheral circuitry not shown in fig. 10 may also be included.

As shown in connection with fig. 9 and 10, the page buffer/sense amplifier 1004 may be configured to read data from the memory array 901 and program (write) data to the memory array 901 in accordance with a control signal from the control logic unit 1012.

In some embodiments, the page buffer/sense amplifier 1004 may store a page of program data (write data) to be programmed into one page 920 of the memory array 901. In some other embodiments, the page buffer/sense amplifiers 1004 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 906 coupled to the selected word line 918. In still other embodiments, the page buffer/sense amplifier 1004 may also sense low power signals from the bit lines 916 representing data bits stored in the memory cells 906 and amplify the small voltage swing to recognizable logic levels in read operations. The column decoder/bit line driver 1006 may be configured to be controlled by the control logic unit 1012 and select one or more NAND memory strings 908 by applying a bit line voltage generated from the voltage generator 1010.

The row decoder/word line drivers 1008 may be configured to be controlled by the control logic unit 1012 and to select/deselect the blocks 904 of the memory array 901 and to select/deselect the word lines 918 of the blocks 904. The row decoder/word line driver 1008 may also be configured to drive the word line 918 using the word line voltage generated from the voltage generator 1010.

In some embodiments, the row decoder/word line driver 1008 may also select/deselect and drive the SSG lines 915 and DSG lines 913. As described in detail below, the row decoder/word line driver 1008 is configured to perform an erase operation on memory cells 906 coupled to the selected word line(s) 918. The voltage generator 1010 may be configured to be controlled by the control logic unit 1012 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 901.

The control logic unit 1012 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 1014 may be coupled to the control logic unit 1012 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. Interface 1016 may be coupled to control logic 1012 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 1012 and to buffer and relay status information received from control logic 1012 to the host. The interface 1016 may also be coupled to the column decoder/bit line drivers 1006 via a data bus 1018, and acts as a data I/O interface and data buffer to buffer data and relay it to or from the memory array 901.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:

filling the first opening to form a sacrificial part;

forming a first dielectric layer covering the side wall of the second opening;

removing the sacrificial portion through the second opening including the first dielectric layer to form a third opening; wherein the third opening comprises the second opening;

2. The method of claim 1, wherein a layer of the stacked structure farthest from the first semiconductor layer is a top interlayer dielectric layer;

in the direction perpendicular to the first semiconductor layer, the depth of the first opening is smaller than the thickness of the top interlayer dielectric layer.

3. The method of manufacturing of claim 1, further comprising:

removing a portion of the first channel layer in contact with the sacrificial portion through the second opening.

4. The method of claim 1, wherein forming a second opening through the select gate and the insulating layer comprises:

forming a first sub-hole penetrating through the selection gate and extending into the insulating layer; wherein a bottom of the first sub-hole is located in the insulating layer;

forming a second dielectric layer covering the side wall and the bottom of the first sub-hole;

forming a sacrificial layer overlying the second dielectric layer;

and removing the sacrificial layer and the second dielectric layer at the bottom of the first sub-hole until the sacrificial part is exposed to form a second opening comprising the first dielectric layer and the sacrificial layer.

5. The method of claim 4, wherein the removing the sacrificial portion through the second opening to form a third opening further comprises:

and removing the sacrificial layer.

6. The method of claim 1, wherein the filling the third opening to form a conductive plug comprises:

forming a second channel layer covering the third opening sidewall and/or bottom; wherein the second channel layer is coupled with the first channel layer.

7. The method of claim 6, wherein filling the third opening to form a conductive plug further comprises:

and filling the third opening including the second channel layer with an insulating material to form a filling portion.

8. The method of claim 7, wherein filling the third opening to form a conductive plug further comprises:

forming a conductive portion on the filling portion, the conductive portion being coupled with a second channel layer; wherein an upper surface of the conductive portion is flush with an upper surface of the second channel layer.

9. A three-dimensional memory, comprising:

a first semiconductor layer;

an insulating layer between the select gate and the stack structure;

a conductive plug penetrating the selection gate and the insulating layer; the conductive plug extending into the channel structure in contact with the core; wherein the conductive plug includes a second channel layer that extends through the select gate and into the channel structure, the second channel layer coupled with the first channel layer;

10. The three-dimensional memory according to claim 9, wherein an upper surface of the first channel layer is flush with an upper surface of the core.

11. The three-dimensional memory according to claim 9, wherein a layer of the stacked structure furthest from the first semiconductor layer is a top interlevel dielectric layer;

the depth of the second channel layer extending into the channel structure is smaller than the thickness of the top interlayer dielectric layer.

12. The three-dimensional memory according to claim 11, wherein the conductive plug further comprises a filling portion; the filling portion is surrounded at a side and/or a bottom by the second channel layer.

13. The three-dimensional memory according to claim 12, wherein the conductive plug further comprises a conductive portion coupled with the second channel layer; the conductive part is located above the filling part, and the upper surface of the conductive part is flush with the upper surface of the second channel layer.

14. A storage system, comprising:

a memory comprising the three-dimensional memory of any one of claims 9 to 13;

a memory controller coupled to the memory and configured to control the memory.