CN115437846A - Firmware maintenance method and electronic equipment - Google Patents
Firmware maintenance method and electronic equipment Download PDFInfo
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- CN115437846A CN115437846A CN202211071746.2A CN202211071746A CN115437846A CN 115437846 A CN115437846 A CN 115437846A CN 202211071746 A CN202211071746 A CN 202211071746A CN 115437846 A CN115437846 A CN 115437846A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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Abstract
The application discloses a firmware maintenance method and electronic equipment. The firmware maintenance method is applied to an electronic device which is connected with a host and comprises a processor, a memory and a logic device, wherein the logic device comprises a selector, a memory control module and an interface controller. The firmware maintenance method comprises the following steps: the interface controller judges that the interface data sent by the host is the same as the default characteristic value, and connects the host with the memory control module; the selector connects the memory to the memory control module based on a switching command sent by the host to the memory control module; the memory control module acquires an operation command and firmware data sent by the host through the interface controller, writes the firmware data into the memory based on the operation command, and returns status data to the host through the interface controller after the writing is finished; and after the interface controller receives a restart command sent by the host based on the state data, restarting the logic device and the processor, enabling the selector to connect the memory to the processor, and loading the firmware data by the processor.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a firmware maintenance method and an electronic device.
Background
Firmware is widely used in electronic devices, and functions to be designed are achieved through cooperation between firmware creation software and hardware designed by developers of the electronic devices. Electronic devices typically contain a processor whose startup relies on its firmware, which is typically stored in an external memory.
Sometimes, the firmware needs to be maintained for repairing defects, increasing functional characteristics, and the like, and the processor needs to obtain a new version of boot firmware through an external interface and then maintain the firmware through an interface bus with the flash memory. In the process, the processor cannot work in case of maintenance failure caused by power failure, system abnormality, software defect and the like. Therefore, manufacturers propose a scheme of applying two flash memories and a flash memory chip selection switch based on consideration of backup of the boot firmware, so that when the boot firmware stored in a certain flash memory fails to be maintained, a user can select to load and execute the boot firmware from another flash memory by setting the switch, and then perform firmware maintenance on the flash memory which fails to be upgraded again.
However, in the firmware maintenance process, if an abnormal condition occurs and the firmware is interrupted, failed to be maintained or damaged, the processor cannot work due to incomplete firmware, so that an engineer must open the shell of the electronic device and manually intervene in the setting switch to perform firmware maintenance again, or an auxiliary tool is used to write the complete firmware into the memory, and thus, the existing firmware maintenance method has the problems of poor maintainability, high maintenance cost and increased downtime of the electronic device.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the application provides a firmware maintenance method and electronic equipment, which can solve the problems of poor maintainability, high maintenance cost and increased downtime of the electronic equipment in the conventional firmware maintenance method.
In order to solve the technical problem, the present application is implemented as follows:
the application provides a firmware maintenance method which is applied to electronic equipment connected with a host, wherein the electronic equipment comprises a processor, a memory and a logic device, and the logic device comprises a selector, a memory control module and an interface controller. The firmware maintenance method comprises the following steps: the interface controller receives and judges that the interface data sent by the host is the same as the default characteristic value, and connects the host with the memory control module; the selector connects the memory with the memory control module based on a switching command sent by the host to the memory control module; the memory control module acquires an operation command and firmware data sent by the host through the interface controller, writes the firmware data into the memory based on the operation command, and returns status data to the host through the interface controller after the writing of the firmware data is completed; and after the interface controller receives a restart command sent by the host based on the state data, restarting the logic device and the processor, enabling the selector to connect the memory with the processor, and enabling the processor to load the firmware data in the memory.
The application provides an electronic equipment, connect the host computer and include: the memory device comprises a processor, a memory and a logic device, wherein the logic device comprises a selector, a memory control module and an interface controller, the selector is configured to connect the memory with the processor or the memory control module, and the interface controller is configured to connect the processor or the memory control module. The interface controller receives and judges that the interface data sent by the host is the same as the default characteristic value, and connects the host with the memory control module; the selector connects the memory to the memory control module based on a switching command sent by the host to the memory control module; the memory control module acquires an operation command and firmware data sent by the host through the interface controller, writes the firmware data into the memory based on the operation command, and returns status data to the host through the interface controller after the writing of the firmware data is completed; and after the interface controller receives a restart command sent by the host based on the state data, restarting the logic device and the processor, enabling the selector to connect the memory with the processor, and loading the firmware data in the memory by the processor.
In the embodiment of the application, when the host computer wants to maintain the firmware of the electronic equipment, the default characteristic value is sent to the interface controller; after monitoring the default characteristic value, the interface controller connects the host with the memory control module (namely, the interface data sent by the host is not sent to the processor); the selector connects the memory to the memory control module based on a switching command sent by the host to the memory control module; and then, the host writes the firmware data into the memory through the memory control module, and sends a restart command to the interface controller after the writing is finished so as to restart the logic device and the processor, so that the processor loads and executes the firmware data in the memory, and the firmware maintenance of the electronic equipment is finished. Therefore, in the firmware maintenance method and the electronic device of the embodiment of the application, extra memory (i.e. two memories are not needed) and maintenance cost are not needed, so that the cost can be saved; firmware maintenance of the electronic equipment can be realized only by connecting the host computer with the interface controller and corresponding software on the application host computer, so that the method has the advantage of convenience and rapidness in operation; when the firmware maintenance fails, an operator can operate the firmware remotely without manual intervention or tools, so that time, labor and material resources are saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of an embodiment of a host-connected electronic device in a normal mode according to the present application;
FIG. 2 is a schematic diagram of an embodiment of a host-connected electronic device in a maintenance mode according to the present application;
FIG. 3 is a schematic view of another embodiment of a host-connected electronic device in a maintenance mode according to the present application; and
FIG. 4 is a flowchart illustrating a firmware maintenance method according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, are taken to specify the presence of stated features, values, method steps, operations, and/or components, but do not preclude the presence or addition of further features, values, method steps, operations, components, and/or groups thereof.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Referring to fig. 1 and 2, fig. 1 is a diagram illustrating an embodiment of a host-connected electronic device in a normal mode according to the present application, and fig. 2 is a diagram illustrating an embodiment of the host-connected electronic device in a maintenance mode according to the present application. As shown in fig. 1 and 2, the electronic apparatus 100 includes: the memory device comprises a processor 110, a memory 120 and a logic device 130, wherein the logic device 130 comprises a selector 132, a memory control module 134 and an interface controller 136, the selector 132 is configured to connect the memory 120 to the processor 110 or the memory control module 134, and the interface controller 136 is configured to connect the host 40 to the processor 110 or the memory control module 134. In some embodiments, logic device 130 may be, but is not limited to, a programmable logic device; the Programmable Logic Device may be, but is not limited to, a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA).
Specifically, when the electronic device 100 is in the normal mode, the selector 132 connects the memory 120 to the processor 110, and the interface controller 136 connects the host 40 to the processor 110; after the electronic device 100 is powered on and restarted, the processor 110 may be booted by loading and executing the firmware data in the memory 120, and may receive and process the interface data from the host 40 through the interface controller 136 after booting. When the electronic device 100 is in the maintenance mode, the selector 132 connects the memory 120 to the memory control module 134, and the interface controller 136 connects the host 40 to the memory control module 134; host 40 may perform firmware maintenance on electronic device 100 via memory control module 134 in logic device 130, as described in more detail below. Note that, in fig. 1 and 2, a solid line indicates that a signal or data is transmitted thereon, and a dashed line indicates that no signal or data is transmitted thereon; that is, the connection between the devices described herein means that there is a signal or data transmitted between the devices.
Wherein the normal mode is a default mode; host 40 may be, but is not limited to, an upgrade device, such as: a computer device connected locally or remotely to the electronic apparatus 100; the electronic device 100 may be, but is not limited to, a server, a switch, or an embedded system; the processor 110 may be, but is not limited to, a central processing unit or an embedded processor; the memory 120 may be, but is not limited to, a Serial Peripheral Interface (SPI) flash memory or a parallel Interface flash memory.
In this embodiment, when the interface controller 136 receives and determines that the interface data sent by the host 40 is the same as the default characteristic value, the interface controller 136 connects the host 40 to the memory control module 134; the selector 132 connects the memory 120 to the memory control module 134 (i.e., the electronic apparatus 100 switches from the normal mode to the maintenance mode) based on a switch command sent by the host 40 to the memory control module 134. The interface controller 136 monitors the interface data sent from the host 40 and compares the interface data to default characteristic values; in some embodiments, interface controller 136 is a device that continuously monitors interface data sent from host 40. When the host 40 wants to perform firmware maintenance on the electronic device 100, the default feature value is sent to the interface controller 136, so that after the interface controller 136 monitors the default feature value, the interface controller 136 connects the host 40 to the memory control module 134 (i.e., the interface data sent by the host 40 is not sent to the processor 110); the host 40 sends a switch command to the memory control module 134 through the interface controller 136, so that the selector 132 connects the memory 120 to the memory control module 134 based on the switch command. The default characteristic value is specified when the logic device 130 encodes, and may be set to 0xdeadbeef, but this embodiment is not intended to limit the present application. In one embodiment, interface controller 136 may include a read only register 1362, read only register 1362 for storing the default feature values.
In this embodiment, when the electronic device 100 is in the maintenance mode, the memory control module 134 obtains the operation command and the firmware data sent by the host 40 through the interface controller 136, writes the firmware data into the memory 120 based on the operation command, and returns the status data to the host 40 through the interface controller 136 after the writing of the firmware data is completed. In other words, the host 40 writes the firmware data it sends to the memory 120 through the memory control module 134, and acquires the status data after the writing of the firmware data is completed. The operation command may include, but is not limited to, a read command, a write command, and an erase command, among others.
In this embodiment, after the interface controller 136 receives the reboot command sent by the host 40 based on the status data, the logic device 130 and the processor 110 are rebooted, the selector 132 connects the memory 120 to the processor 110, and the interface controller 136 connects the host 40 to the processor 110, so that the processor 110 loads and executes the firmware data in the memory 120 (i.e., the electronic device 100 is switched from the maintenance mode to the normal mode). In other words, after the host 40 obtains the status data, it sends a restart command to the interface controller 136, so that the logic device 130 can restart the processor 110 in addition to the logic device 130 itself.
Please refer to fig. 3, which is a diagram illustrating another embodiment of a host-connected electronic device in a maintenance mode according to the present application. As shown in FIG. 3, memory control module 134 may also include a memory controller 50, a command register 60, and a data register 70; command register 60 may be configured to store operational commands sent by host 40; data register 70 may be configured to store firmware data sent by host 40; memory controller 50 may be configured to access memory 120 based on the operating commands stored by command register 60 and to write the firmware data stored by data register 70 into memory 120. Additionally, command register 60 may also be configured to store a toggle command sent by host 40 such that selector 132 connects memory 120 to memory control module 134 based on the toggle command.
In one embodiment, the interface controller 136 is configured to determine that the interface data belongs to the operation command or the firmware data according to an identification code included in the interface data of the host 40 via the serial port 42; recombining two successive interface data belonging to an operation command to obtain the operation command and writing it into the command register 60; two successive interface data belonging to the firmware data are recombined to obtain the firmware data and written to the data register 70. Serial port 42 may be, but is not limited to, an external interface that may be originally connected directly to processor 110.
That is, the interface data sent by the host 40 through the serial port 42 is in a Universal Asynchronous Receiver Transmitter (UART) format, and is transmitted in units of bytes, which interface data belongs to the operation command and which interface data belongs to the firmware data cannot be distinguished, so when the host 40 transmits an operation command, for example, 0x89, it is disassembled into 2 bytes, the first half of each byte is an identification code, and since the identification code of the operation command is 0x10, 0x89 becomes 0x18 and 0x19; when the host 40 transmits a piece of firmware data, for example, 0x87, it is split into 2 bytes, and since the identification code of the firmware data is 0x20, 0x87 becomes 0x28 and 0x27; in this way, the interface controller 136 can distinguish whether the received interface data belongs to the operation command or the firmware data.
For example, when the memory 120 is a serial peripheral interface flash memory, since all commands (e.g., a command to erase a sector, a command to read a status, etc.) and data (e.g., a start address, an offset address, contents, etc.) sent by the memory are one byte long, in order to facilitate the interface controller 136 to determine whether a byte (i.e., interface data) transmitted by the host 40 belongs to an operation command or firmware data, it is designed to determine the type of the byte by an identification code (e.g., when the identification code included in the byte is 0x10, the byte belongs to the operation command, and when the identification code included in the byte is 0x20, the byte belongs to the firmware data); therefore, the host 40 will split the interface data to be sent into two bytes, the first half of each byte is the identifier of the type of the interface data, and the second half of each byte is the real content, so that after receiving the two split bytes of the interface data, the interface controller 136 will recombine the two bytes and write them into the command register 60 or the data register 70 according to the type of the bytes (i.e. the byte belongs to the operation command and writes it into the command register 60, and the byte belongs to the firmware data and writes it into the data register 70).
In an embodiment, memory control module 134 may also include status register 80; the memory controller 50 may be further configured to read status bits in the memory 120 based on the operation command stored in the command register 60 and write to the status register 80 after the writing of the firmware data is completed; and send status data to the host 40 via the interface controller 136 based on the data stored by the status register 80. Thus, the host 40, upon receiving the status data, may recognize that the firmware data write is complete, and send a reboot command to the interface controller 136.
In one embodiment, the memory control module 134 may further include a reset register 90, the reset register 90 being coupled to the processor 110; interface controller 136 is configured to set restart register 90 upon receiving the restart command, thereby restarting logic device 130 and processor 110. Specifically, when the identification code included in the interface data transmitted by the host 40 belongs to a restart command (e.g., 0x 30), the interface controller 136 may determine that the received interface data is a restart command, and then set the restart register 90 to enable the logic device 130 to restart the processor 110 through the restart register 90, and then the logic device 130 restarts itself.
In one embodiment, the memory controller 50 is a serial peripheral interface controller when the memory 120 is a serial peripheral interface flash memory. In another embodiment, memory controller 50 is a parallel interface controller when memory 120 is a parallel interface flash memory.
Referring to fig. 1, fig. 2 and fig. 4, fig. 4 is a flowchart illustrating an embodiment of a firmware maintenance method according to the present application. The firmware maintenance method is applicable to the electronic device 100 and includes: when the interface controller 136 receives and determines that the interface data sent by the host 40 is the same as the default eigenvalue, the interface controller 136 connects the host 40 to the memory control module 134 (step 210); the selector 132 connects the memory 120 to the memory control module 134 based on the switch command sent by the host 40 to the memory control module 134 (step 220); the memory control module 134 acquires the operation command and the firmware data sent by the host 40 through the interface controller 136 to write the firmware data to the memory 120 based on the operation command, and returns status data to the host 40 through the interface controller 136 after the writing of the firmware data is completed (step 230); and after the interface controller 136 receives the reboot command sent by the host 40 based on the status data, the logic device 130 and the processor 110 are rebooted, so that the selector 132 connects the memory 120 to the processor 110, and the processor 110 loads the firmware data in the memory 120 (step 240).
Therefore, the firmware maintenance of the electronic device 100 can be realized through the steps 210 to 240, and the electronic device has the advantage of convenient operation; and when the firmware maintenance fails, the operator can operate remotely without tools, so that time, labor and material resources are saved. For detailed description, reference may be made to the related description of the above embodiments, which are not repeated herein.
In an embodiment, the firmware maintenance method may further include: the interface controller 136 monitors the interface data sent from the host 40 and compares the interface data to default characteristic values stored by the read only register 1362 it includes. For a detailed description, reference may be made to the related description of the above embodiments, which is not repeated herein.
Referring to fig. 3 and 4, the step 230 of the memory control module 134 obtaining the operation command and the firmware data sent by the host 40 through the interface controller 136 to write the firmware data to the memory 120 based on the operation command may include: the command register 60 receives and stores an operation command sent by the host 40; the data register 70 receives and stores firmware data transmitted by the host 40; the memory controller 50 accesses the memory 120 based on the operation command stored in the command register 60 and writes the firmware data stored in the data register 70 into the memory 120. For a detailed description, reference may be made to the related description of the above embodiments, which is not repeated herein.
Referring to fig. 3 and 4, the step 230 of the memory control module 134 obtaining the operation command and the firmware data sent by the host 40 through the interface controller 136 may include: the interface controller 136 determines that the interface data belongs to the operation command or the firmware data according to the identification code included in the interface data sent by the host 40 through the serial port 42; the interface controller 136 recombines two consecutive interface data belonging to the operation command to obtain the operation command, and writes into the command register 60; and the interface controller 136 reassembles two successive interface data belonging to the firmware data to obtain the firmware data and write to the data register 70. For detailed description, reference may be made to the related description of the above embodiments, which are not repeated herein.
Referring to fig. 3 and 4, the step 230 of returning the status data to the host 40 through the interface controller 136 by the memory control module 134 after the writing of the firmware data is completed may include: after the writing of the firmware data is completed, the memory control module 134 reads the status bit in the memory 120 based on the operation command and writes to the status register 80 included in the memory control module 134; and memory control module 134 sends status data to host 40 through interface controller 136 based on the data stored by status register 80. For a detailed description, reference may be made to the related description of the above embodiments, which is not repeated herein.
Referring to fig. 3 and 4, after the interface controller 136 receives the reboot command sent by the host 40 based on the status data in step 240, rebooting the logic device 130 and the processor 110 may include: upon receiving the restart command, the interface controller 136 sets the restart register 90 included in the logic device 130, thereby restarting the logic device 130 and the processor 110. For a detailed description, reference may be made to the related description of the above embodiments, which is not repeated herein.
To sum up, the firmware maintenance method and the electronic device of the present application can monitor whether the host wants to perform firmware maintenance on the electronic device (i.e. whether to send the default feature value) through the setting of the interface controller; when the interface controller receives the default characteristic value, the interface controller connects the host computer with the memory control module; the selector connects the memory to the memory control module (i.e. the electronic device enters a maintenance mode) based on a switching command sent by the host to the memory control module; then, the host writes the firmware data into the memory through the memory control module, and sends a restart command to the interface controller after the writing is completed, so as to restart the programmable logic device and the processor, and the processor loads and executes the firmware data in the memory (i.e. the electronic device returns to the normal mode). Therefore, in the firmware maintenance method and the electronic device of the embodiment of the application, the cost can be saved because extra memory (namely two memories are not needed) and maintenance cost are not needed; the firmware maintenance of the electronic equipment can be realized only by connecting the host computer, the interface controller and corresponding software on the application host computer, so that the method has the advantage of convenience and rapidness in operation; when the firmware maintenance fails, an operator can operate the firmware remotely without tools, so that time, labor and material resources are saved.
While the invention is illustrated using the above embodiments, it should be noted that the description is not intended to limit the invention. Rather, this invention encompasses modifications and similar arrangements as would be apparent to one skilled in the art. The scope of the claims is, therefore, to be construed in the broadest possible manner to cover all such modifications and similar arrangements.
Claims (15)
1. A firmware maintenance method is applied to an electronic device connected with a host, the electronic device comprises a processor, a memory and a logic device, the logic device comprises a selector, a memory control module and an interface controller, and the firmware maintenance method comprises the following steps:
the interface controller receives and judges that the interface data sent by the host is the same as the default characteristic value, and the interface controller connects the host with the memory control module;
the selector connects the memory to the memory control module based on a switch command sent by the host to the memory control module;
the memory control module acquires an operation command and firmware data sent by the host through the interface controller, writes the firmware data into the memory based on the operation command, and returns status data to the host through the interface controller after the firmware data is written; and
and after the interface controller receives a restart command sent by the host based on the state data, restarting the logic device and the processor, and enabling the selector to connect the memory with the processor, so that the processor loads the firmware data in the memory.
2. The firmware maintenance method of claim 1, wherein the interface controller further comprises a read-only register, the firmware maintenance method further comprising:
the interface controller monitors the interface data sent from the host and compares the interface data with the default characteristic value stored by the read-only register.
3. The firmware maintenance method according to claim 1, wherein the step of the memory control module acquiring the operation command and the firmware data sent by the host through the interface controller comprises:
the interface controller judges whether the interface data belongs to the operation command or the firmware data according to an identification code included in the interface data sent by the host through a serial port;
the interface controller recombines two continuous interface data belonging to the operation command to obtain the operation command, and writes the operation command into a command register included in the memory control module; and
the interface controller recombines two successive interface data belonging to the firmware data to obtain the firmware data, and writes to a data register included in the memory control module.
4. The firmware maintenance method of claim 1, wherein the memory control module comprises a memory controller, a command register, and a data register; the step that the memory control module acquires the operation command and the firmware data sent by the host through the interface controller so as to write the firmware data into the memory based on the operation command comprises the following steps:
the command register receives and stores the operation command;
the data register receives and stores the firmware data; and
the memory controller accesses the memory based on the operation command and writes the firmware data into the memory.
5. The firmware maintenance method of claim 1, wherein the step of the memory control module returning status data to the host through the interface controller after the writing of the firmware data is completed, comprises:
after the firmware data is written, the memory control module reads the status bit in the memory based on the operation command and writes the status bit into a status register included in the memory control module; and
the memory control module sends the status data to the host through the interface controller based on the data stored by the status register.
6. The firmware maintenance method of claim 1, wherein the step of restarting the logic device and the processor after the interface controller receives a restart command sent by the host based on the status data comprises:
and after receiving the restart command, the interface controller sets a restart register included by the logic device so as to restart the logic device and the processor.
7. An electronic device, connected to a host, the electronic device comprising:
a processor;
a memory; and
a logic device, comprising: a selector configured to connect the memory to the processor or the memory control module, a memory control module, and an interface controller configured to connect the host to the processor or the memory control module;
the interface controller receives and judges that the interface data sent by the host computer is the same as the default characteristic value, and the interface controller connects the host computer with the memory control module; the selector connects the memory to the memory control module based on a switch command sent by the host to the memory control module; the memory control module acquires an operation command and firmware data sent by the host through the interface controller, writes the firmware data into the memory based on the operation command, and returns status data to the host through the interface controller after the firmware data is written; and after the interface controller receives a restart command sent by the host based on the state data, restarting the logic device and the processor, and enabling the selector to connect the memory to the processor so that the processor loads the firmware data in the memory.
8. The electronic device of claim 7, wherein the interface controller includes a read-only register that stores the default feature value.
9. The electronic device of claim 7, wherein the memory control module includes a command register and a data register; the interface controller is configured to judge whether the interface data belongs to the operation command or the firmware data according to an identification code included in the interface data sent by the host through a serial port; recombining two successive interface data belonging to the operation command to obtain the operation command, and writing the operation command into the command register; and recombining two continuous interface data belonging to the firmware data to obtain the firmware data, and writing the firmware data into the data register.
10. The electronic device of claim 7, wherein the memory control module includes a reboot register coupled to the processor; the interface controller is configured to set the reboot register after receiving the reboot command, thereby rebooting the logic device and the processor.
11. The electronic device of claim 7, wherein the memory control module comprises a memory controller, a command register, and a data register; the command register is configured to store the operation command; the data register is configured to store the firmware data; the memory controller is configured to access the memory based on the operation command and write the firmware data into the memory.
12. The electronic device of claim 7, wherein the memory control module comprises a memory controller and a status register; the memory controller is configured to read a status bit in the memory based on the operation command and write to the status register after the writing of the firmware data is completed; and transmitting the status data to the host through the interface controller based on the data stored by the status register.
13. The electronic device of claim 11 or 12, wherein the memory is a serial peripheral interface flash memory and the memory controller is a serial peripheral interface controller.
14. The electronic device of claim 11 or 12, wherein the memory is a parallel interface flash memory and the memory controller is a parallel interface controller.
15. The electronic device of claim 7, wherein the logic device is a complex programmable logic device or a field programmable gate array.
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| CN202211071746.2A CN115437846A (en) | 2022-09-02 | 2022-09-02 | Firmware maintenance method and electronic equipment |
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| CN202211071746.2A CN115437846A (en) | 2022-09-02 | 2022-09-02 | Firmware maintenance method and electronic equipment |
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