CN115433901A - Antistatic coating - Google Patents

Abstract

The present invention discloses a substrate coated with a coating layer in a multi-layer form and a method for preparing the same, the substrate coated with the coating layer in the multi-layer form sequentially comprising: i. a substrate; ii, a seed layer; a ta-C containing layer, and iv a DLC containing layer. Wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

Description

Antistatic coating

Technical Field

The present invention relates to improved coatings to reduce electrostatic charging and discharging and methods of producing such coatings.

Background

A variety of deposition techniques are used to coat the substrate. Vapor deposition techniques are commonly used to form thin film deposited layers in various types of applications, including microelectronics applications and heavy duty applications. Such deposition techniques can be divided into two broad categories. A first class of such deposition techniques is known as Chemical Vapor Deposition (CVD). CVD generally refers to a deposition process that occurs as a result of a chemical reaction. Common examples of CVD processes include semiconductor silicon layer deposition, epitaxy, and thermal oxidation.

The second type of deposition is commonly referred to as Physical Vapor Deposition (PVD). PVD generally refers to the deposition of solid matter that occurs as a result of physical processes. The main concept of PVD processes is the physical transfer of the deposited material to the substrate surface by direct mass transfer. Generally, no chemical reaction occurs during the process and the thickness of the deposited layer is independent of the kinetics of the chemical reaction, which is contrary to CVD processes.

Sputtering is a known physical vapor deposition technique for depositing compounds on a substrate, wherein atoms, ions or molecules are ejected from a target (also referred to as a sputtering target) by particle bombardment, such that the ejected atoms or molecules accumulate as a thin film on the substrate surface.

Another known physical vapor deposition technique is the Cathodic Vapor Arc (CVA) deposition method. In this method, an electric arc is used to evaporate material from the cathode target. Thus, the resulting vaporized material condenses on the substrate to form a coating film.

Amorphous carbon is a free, activated form of carbon that does not have a crystalline form. There are various forms of amorphous carbon films, typically in terms of the hydrogen content of the film and the sp of the carbon atoms in the film ² ：sp ³ The ratio is classified.

In the literature examples in the field, amorphous carbon films are classified into 7 classes (see the following table, abstracted from Fraunhofer institute Schich-und)

"Carbon coating Name Index (Name Index of Carbon Coatings)"):

the tetrahedral non-hydrogen containing amorphous carbon (ta-C) is characterized in that it contains little or no hydrogen (less than 5% and usually less than 2% by mol) and a high sp content ³ Hybridized carbon atoms (typically more than 80% of the carbon atoms are in sp ³ Status).

Although the term "diamond-like carbon" (DLC) is sometimes used to refer to all forms of amorphous carbon material, the term as used herein refers to amorphous carbon materials other than ta-C. A common method of DLC manufacture uses a hydrocarbon (e.g., acetylene) and thus incorporates hydrogen into the film (in contrast to ta-C films, which are typically hydrogen-free high purity graphite as a starting material).

In other words, DLC typically has an sp greater than 50% ² Carbon content and/or 20% by mol or more of hydrogen content. The DLC may be undoped or doped with metals or non-metals (see table above).

In recent years, the manufacture of electrical components has become automated to reduce labor costs and to reduce the presence of personnel in clean rooms and the risk of contamination from manual operations. In particular, there has been a trend toward increasingly automated semiconductor manufacturing.

Automated robotic equipment now performs many of the process steps required to produce finished semiconductor wafers. This means that there are now more "pick and place" operations that move wafers from a Front Opening Unified Pod (FOUP) into a processing system or analysis tool. The scale of repeated mechanical operations and movements throughout the manufacturing process is an important factor in potential device damage in semiconductor manufacturing due to electrostatic charging and subsequent electrical discharge (ESD) or electrostatic attraction of particles.

Semiconductor chips and wafer products are susceptible to static electricity, especially during handling and transportation. Electrostatic discharge can alter the electrical characteristics of the semiconductor device in a degrading manner and even destroy it. The accumulation of static charge and subsequent electrostatic discharge is a major cause of failure in the semiconductor industry.

Currently, most of the electrostatic dissipation methods in the market are based on a "wet process" process, and an anti-static coating is sprayed on integrated circuits and wafer products. However, it is well known that these products have low surface abrasion resistance, which shortens the service life of these products.

Current static dissipation methods involve coating the manufactured product itself. This can affect the characteristics of the resulting products, thereby reducing the quality and/or useful life of these products.

Therefore, there is a need for such coatings: electrostatic charging and discharging can be reduced, but the manufactured product does not have the above-mentioned low surface wear resistance problem or other disadvantages.

Disclosure of Invention

It is an object of the present invention to provide such a coating which can be employed to address one or more problems present in the art, and preferably to provide improvements in reducing static charge build-up and hence electrostatic discharge (ESD).

The inventors of the present application have found that a carbon coating having one or more layers ta-C and one or more layers DLC has suitable static dissipative properties that can reduce static buildup and subsequent static discharge.

Accordingly, the present invention provides a substrate having a coating in the form of a plurality of layers, comprising in order:

i. a substrate, a first electrode and a second electrode,

ii, a seed layer,

a ta-C containing layer, and

a layer comprising a DLC layer, wherein the DLC layer comprises a first polymer,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

Similarly provided is a coating for a substrate comprising, in order:

i. a seed layer,

a ta-C containing layer, and

a DLC-containing layer, iii,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

Suitably, as illustrated in the examples, the present invention provides a coated substrate comprising, in order:

i. a metal substrate, a metal base and a metal base,

a conductive metal seed layer (e.g. titanium or chromium),

a ta-C containing layer, and

a layer comprising a DLC layer, wherein the DLC layer comprises a first polymer,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

The present invention also provides a coated substrate comprising, in order:

i. a substrate comprising silicon or glass,

a seed layer comprising silicon,

a ta-C containing layer, and

a layer comprising a DLC layer, wherein the DLC layer comprises a first polymer,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

Also provided is a method of preparing a coated substrate comprising providing a substrate and coating on the substrate in the following order:

i. a seed layer,

a ta-C containing layer, and

DLC-containing layer

Wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

The sheet resistance can be varied by varying the thickness of the DLC-containing layer in the coating. The sheet resistance may also be varied by varying one or more of the CVD source design, coating temperature, gas flow, bias voltage, and duty cycle. Accordingly, the present invention provides a static dissipative coating with a tunable surface resistance. These coatings reduce static buildup and subsequent static discharge as shown by tests of the embodiments of the invention described in more detail below.

As mentioned above, the term "tetrahedral amorphous carbon" (ta-C or TAC) as used herein refers to carbon with low hydrogen content and low sp ² Amorphous carbon of carbon content.

Ta-C is a dense amorphous material described by disordered sp ³ Compositions, interconnected by strong bonds, similar to those present in disordered diamond (see Neuville S, "New application look-ahead of tetrahedral amorphous carbon coating", QSscience Connect 2014 8, http:// dx.doi.org/10.5339/connect.2014.8). Due to its structural similarity to diamond, ta-C is also a very hard material, typically with hardness values greater than 30GPa.

For example, the hydrogen content of ta-C may be less than 10%, typically 5% or less, preferably 2% or less (e.g., 1% or less). The percent hydrogen content provided herein is in mole percent(rather than the mass percent of hydrogen). Sp of ta-C ² The carbon content may be less than 30%, typically 20% or less, preferably 15% or less. Preferably, ta-C may have a hydrogen content of 2% or less and an sp of 15% or less ² Carbon content. the ta-C is preferably undoped with other materials (whether metallic or non-metallic).

In contrast, the term "diamond-like carbon" (DLC) as used herein refers to amorphous carbon other than ta-C. DLC therefore has a higher hydrogen content and a higher sp than ta-C ² The carbon content. For example, DLC may have a hydrogen content of 20% or more, typically 25% or more, for example 30% or more. The percentage amounts of hydrogen provided herein again refer to mole percent (rather than mass percent of hydrogen). DLC may have an sp of 50% or more ² The carbon content is usually 60% or more. In general, DLC may have a hydrogen content of greater than 20% and sp of greater than 50% ² Carbon content. The DLC may be undoped and/or doped with metals and/or non-metals.

The present invention advantageously provides a static dissipative coating that results in reduced build-up of static charge and thus reduced static discharge.

Accordingly, the present invention provides a substrate having a coating in the form of a plurality of layers, comprising in order:

i. a substrate, a first electrode and a second electrode,

ii, a seed layer,

a ta-C containing layer, and

a DLC-containing layer, the DLC-containing layer,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

DLC-containing layer

The DLC-containing layer allows the coating of the invention to be electrically conductive. This is desirable to allow the coating to function as a static dissipative coating by preventing static buildup and subsequent static discharge.

The uppermost layer of the coating (i.e. the layer exposed to the environment) is the DLC containing layer. In a preferred embodiment, the DLC containing layer is adjacent to the ta-C containing layer. This layer may contain more than 70%, for example more than 80%, preferably more than 90% by weight of DLC, or it may consist of DLC. In a preferred embodiment, the DLC containing layer is comprised of DLC.

DLC may have a hydrogen content of 20% or more, typically 25% or more, for example 30% or more. The percentage amounts of hydrogen provided herein again refer to mole percent (rather than mass percent of hydrogen).

DLC may have an sp of 60% or greater, typically 70% or greater, preferably 80% or greater or 90% or greater ² The carbon content.

DLC may have an sp of 40% or less, typically 30% or less, preferably 20% or less or 10% or less ³ Carbon content.

In general, DLC may have a hydrogen content of greater than 20% and sp of greater than 50% ² Carbon content.

In a particularly preferred embodiment, the DLC-containing layer is composed of DLC, wherein DLC has a hydrogen content of greater than 20% and sp of greater than 50% ² Carbon content.

The DLC may be undoped and/or doped with metals and/or non-metals.

DLC is typically deposited by a CVD process (preferably PACVD), as described in further detail below. DLC-containing layers are typically deposited by methods other than FCVA.

The DLC-containing layer has a thickness of usually 0.5 μm or more, for example, 1.0 μm or more, preferably 1.5 μm or more. The DLC coating also typically has a thickness of 4.5 μm or less, for example 4.0 μm or less, preferably 3.5 μm or less. Thus, the DLC coating may have a thickness of 0.5 μm to 4.5 μm, such as 1.0 μm to 4.0 μm, preferably 1.5 μm to 3.5 μm.

Ta-C containing layer

The ta-C containing layer increases the hardness and thus the wear resistance of the coated substrate of the invention. This in turn increases the lifetime of the coated substrate of the present invention. The ta-C containing layer also increases the adhesion of the DLC layer to the seed layer, reducing delamination and thus increasing the lifetime of the inventive coated substrate.

Typically, the ta-C containing layer is adjacent to the DLC containing layer. Typically, the ta-C containing layer is adjacent to the seed layer. In a preferred embodiment, the ta-C containing layer is adjacent to the DLC containing layer and the seed layer.

The ta-C containing layer may comprise more than 70%, such as more than 80%, preferably more than 90% by weight of ta-C, or the layer may consist of ta-C. In a preferred embodiment, the ta-C containing layer is composed of ta-C.

the hydrogen content of ta-C is usually 5% or less, preferably 2% or less, most preferably 1% or less.

ta-C generally has an sp of 20% or less, preferably 15% or less ² Carbon content.

ta-C generally has an sp of 80% or more, preferably 85% or more ³ Carbon content.

Generally, ta-C may have a hydrogen content of 5% or less and an sp of 20% or less ² The carbon content, preferably, ta-C may have a hydrogen content of 2% or less and an sp of 15% or less ² And (4) content.

In a particularly preferred embodiment, the ta-C containing layer is composed of ta-C, wherein ta-C has a hydrogen content of 5% or less and an sp of 20% or less ² The carbon content.

The thickness of the ta-C containing layer is usually 0.01 μm or more, for example 0.05 μm or more, preferably 0.1 μm or more. The thickness of the ta-C containing layer is also typically 2.0 μm or less, e.g. 1.5 μm or less, preferably 1.0 μm or less. Thus, the thickness of the ta-C containing layer may be 0.01 μm to 2.0 μm, e.g. 0.05 μm to 1.5 μm, preferably 0.1 μm to 1.0 μm.

ta-C is preferably deposited by a PVD process, such as the CVA process (preferably FCVA).

Seed layer

The seed layer is included to improve adhesion of the ta-C containing layer to the underlying substrate. The seed layer increases the adhesion between the substrate and the ta-C containing layer. This reduces the likelihood of delamination of the coating from the substrate.

Typically, the seed layer is adjacent to the ta-C containing layer. Typically, the seed layer is adjacent to the substrate. In a preferred embodiment, the seed layer is adjacent to the ta-C containing layer and the substrate.

The seed layer is also typically conductive to provide a conductive surface on which the carbon-containing ta-C and DLC layers can be deposited.

Thus, the properties of the seed layer will depend on the properties of the substrate. The thickness of the seed layer is usually 0.05 μm or more, for example 0.1 μm or more, preferably 0.3 μm or more. The thickness of the seed layer is also usually 2 μm or less, for example 1 μm or less, preferably 0.8 μm or less. Thus, the thickness of the seed layer may be 0.05 μm to 2 μm, for example 0.1 μm to 1 μm, preferably 0.3 μm to 0.8 μm.

Typically, the seed layer is a conductive metal. Typically, when the substrate is a metal, the seed layer is a conductive metal. When the substrate is a metal, the seed layer preferably comprises Ti or Cr. In the most preferred embodiment, when the substrate is a metal, the seed layer is Ti. When the substrate is silicon or glass, the seed layer typically comprises silicon.

The seed layer is typically deposited by a PVD method and preferably the seed layer is deposited by sputtering.

Substrate

The choice of substrate material is wide and many substrates made of a variety of materials can be coated. The substrate is typically metallic and is typically or comprises a metal, an alloy, silicon or glass.

In one embodiment, suitable substrates include various steels (e.g., steel, stainless steel, HSS, tool steel, and alloy steel), copper or alloys thereof, and aluminum or alloys thereof. The article is typically made of a substrate and the coating of the present invention is then applied/deposited.

In another embodiment, suitable substrates include silicon and glass.

The substrate may be any device where electrostatic discharge may cause problems, such as a device in contact with a semiconductor.

It should be noted that the coating may be applied to the equipment rather than the product within the manufacturing apparatus. Thus, there is no need to apply an antistatic coating to the article of manufacture. This advantageously prevents any disadvantages associated with the coated product itself. In particular, the quality and/or the lifetime of these products are not reduced. In fact, the coating on the device helps to prolong the service life of the manufactured product.

Monolithic coated substrate

The total thickness of the coating layers (including the seed layer, the DLC containing layer and the ta-C containing layer) is typically 0.7 μm or more, suitably 1.0 μm or more, for example 2.0 μm or more, preferably 3.0 μm or more. The total thickness of the coating is also typically 9.0 μm or less, suitably 7.0 μm or less, for example 5.0 μm or less, preferably 4.0 μm or less. Thus, the total thickness of the coating may be from 0.7 μm to 9.0 μm, suitably from 1.0 μm to 7.0 μm, for example from 2.0 μm to 5.0 μm, preferably from 3.0 μm to 4.0 μm.

The coated substrate has an adjustable resistance depending on the thickness of the DLC-containing layer. The temperature and speed of application of the DLC-containing layer also affects the surface resistance of the coated substrate. Typically, the surface resistance of the coating is 10 ⁴ Omega/sq to 10 ¹² Omega/sq, suitably 10 ⁵ Omega/sq to 10 ¹⁰ Omega/sq, preferably 10 ⁵ Omega/sq to 10 ⁹ Omega/sq, and most preferably 10 ⁶ Omega/sq to 10 ⁷ Ω/sq。

The coating typically has a hardness of 500HV or greater, preferably 1000HV or greater, most preferably 1500HV or greater. The coating also typically has a hardness of 3500HV or less, preferably 3000HV or less, most preferably 2000HV or less. Thus, the coating may have a hardness of from 500HV to 3500HV, preferably from 1000HV to 3000HV, most preferably from 1500HV to 2000 HV.

Hardness, as measured by the Vickers hardness test (Vickers hardness test) (developed by Robert L.Smith and George E.Sandland in 1921 by Vickers Ltd.; standard test see ASTM E384-17), is used for all metals and has the broadest range of applications in various hardness tests. The hardness units given by the test are called Vickers Pyramid Hardness Values (HV), which can be converted to pascal units (GPa). The hardness value is determined by the load on the surface area of the indentation used in the test. By way of example, martensite, which is a hard steel, has an HV of about 1000, while diamond has an HV of about 10,000HV (about 98 GPa). The hardness of diamond varies with the particular crystal structure and orientation, but common hardnesses range from about 90 to over 100 GPa.

Typically, the ta-C containing layer and the DLC containing layer are adjacent, i.e., no other layer is present between the ta-C containing layer and the DLC containing layer. Furthermore, the seed layer and the ta-C containing layer are preferably adjacent to each other, i.e. no further layers are present between the seed layer and the ta-C containing layer. The substrate and seed layer are preferably also adjacent, i.e. no further layers are present between the substrate and seed layer.

In a preferred embodiment, the seed layer and the ta-C containing layer are adjacent, and the ta-C containing layer and the DLC containing layer are adjacent. In other embodiments, the substrate and seed layer are adjacent, and the ta-C containing layer and the DLC containing layer are adjacent. In other embodiments, the substrate and seed layer are adjacent and the seed layer and ta-C containing layer are adjacent. In a particularly preferred embodiment, the substrate and the seed layer are adjacent, and the seed layer and the ta-C containing layer are adjacent, and the ta-C containing layer and the DLC containing layer are adjacent.

In one embodiment of the present invention, there is provided a coated substrate comprising, in order:

i. a substrate, wherein the substrate is provided with a plurality of grooves,

ii, a seed layer,

a ta-C containing layer, and

a DLC containing layer.

Wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

The substrate, seed layer, ta-C containing layer, and DLC containing layer may have the characteristics described above.

In a further embodiment, the present invention provides a coated substrate comprising, in order:

i. a metal substrate, a metal base,

a conductive metal seed layer (e.g. titanium or chromium),

a ta-C containing layer, and

a DLC containing layer.

In another embodiment, the present invention provides a coated substrate comprising, in order:

i. a substrate comprising silicon or glass,

a seed layer comprising silicon,

a ta-C containing layer, and

a DLC containing layer.

Method

The present invention also provides a method of preparing a coated substrate according to the above disclosure, comprising providing a substrate and sequentially coating the substrate with:

i. a seed layer,

a ta-C containing layer, and

DLC containing layer

Wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Omega/sq (e.g. 10) ⁶ Omega/sq to 10 ⁷ Ω/sq).

Conventional CVD and PVD methods, in particular CVA and FCVA processes, are known and used for a wide range of substrates, and the method of the invention is equally applicable to coating a wide range of substrates. Solids, whether conductive or non-conductive, are generally suitable, and seed and adhesion layers may be used to improve coating adhesion and strength and to facilitate coating of the surface. Substrates made of metals, alloys, ceramics and mixtures thereof may be coated. In general, substrates tend to accumulate static charges and thus to generate electrostatic discharges.

The coating processes described herein may all be performed at low temperatures, for example at a temperature of 100 ℃ or less, for example at a temperature of 70 ℃. In addition, the coating process described herein can be carried out at a temperature of from 80 ℃ to 220 ℃, optionally from 100 ℃ to 200 ℃, typically from 100 ℃ to 150 ℃, preferably from 110 ℃ to 130 ℃, more preferably from 115 ℃ to 125 ℃ (e.g., 120 ℃). This is an advantage, since the method of coating a substrate can thus be performed at relatively low temperatures, avoiding the energy costs associated with the coating process.

The coatings of the present invention may be multilayered and the individual layers may be independently deposited using a range of known and conventional deposition techniques, including CVD, PVD, magnetron sputtering and multi-arc ion plating. Sputtering is a suitable method, particularly for seed layers. PVD is suitable for ta-C containing layers, such as CVA. The CVA process is typically a Filtered Cathode Vacuum Arc (FCVA) process, for example, as described below. Apparatus and methods for FCVA coating are known and may be used as part of the process of the present invention. FCVA coating apparatus generally comprise a vacuum chamber, an anode, a cathode assembly for generating a plasma from a target, and a power supply for biasing a substrate to a given voltage. The characteristics of FCVA are conventional and not part of the present invention.

CVD processes may deposit materials using ion sources including end-hall ion sources, kaufman ion sources, anode layer sources, hot wire ion sources, and hollow cathode ion sources. The CVD process may preferably be a plasma activated CVD process (PACVD, also known as plasma enhanced CVD, PECVD). PACVD processes have lower deposition temperatures, higher purity, and easier control of reaction parameters than conventional (i.e., thermally activated) CVD processes. The PACVD process also has higher coating energy compared to conventional CVD processes, resulting in better coating adhesion and higher coating hardness and density. The PACVD process may also result in better coating coverage and uniformity compared to conventional CVD processes. Alternatively, the coating material may be provided as a gas, which is then charged/ionized using a power source (e.g., a dc power source, a pulsed dc power source, or a radio frequency power source).

In a preferred embodiment, the seed layer is deposited by sputtering. In other preferred embodiments, the ta-C containing layer is deposited by FCVA. In a further preferred embodiment the DLC-containing layer is deposited by CVD, most preferably PACVD.

The surface resistance (also referred to as surface resistance or sheet resistance) of the coating layer is determined by controlling the thickness of the DLC-containing layer during application of the DLC-containing layer, controlling the application speed and temperature of the layer, and controlling the gas flow, bias voltage and duty cycle. Thus, the methods disclosed herein may include varying the thickness of the DLC layer to obtain a coated substrate with a desired resistance. The method may further comprise independently varying one or more of the temperature, gas flow, bias voltage, and duty cycle of the application of the DLC-containing layer to obtain a coated substrate having a desired resistance.

Increasing the thickness of the DLC-containing layer will decrease the electrical conductivity of the coating and will therefore increase the surface resistance of the coating. Without wishing to be bound by theory, this is because increasing the thickness of the DLC-containing layer increases the thickness of the conductive layer, and the sheet resistance is inversely proportional to the thickness.

The method may further comprise independently varying the speed and/or temperature of DLC and/or ta-C application to obtain a coated substrate with the desired electrical resistance. Suitable temperature ranges for depositing DLC-containing layers are discussed above, as the same (or similar) temperature may be used for the entire coating process.

During CVD deposition of DLC containing layers, a controlled gas flow is passed through the deposition chamber. The gas flow can be from 50sccm to 200sccm, typically from 75sccm to 150sccm, preferably from 80sccm to 120sccm, and most preferably from 90sccm to 110sccm. The gas used may be selected from CH ₄ 、C ₂ H ₆ Or C ₂ H ₂ The preferred gas is C ₂ H ₂ . In a preferred embodiment of CVD deposition of a DLC-containing layer as described herein, the gas is C ₂ H ₂ And the gas flow is from 90sccm to 110sccm (e.g., 100 sccm).

The deposition of the DLC containing layer described herein may be carried out at a negative bias of-50V to-1200V, optionally-200V to-1200V, typically-500V to-1200V, preferably-800V to-1200V, most preferably-1000V to-1200V. A duty cycle of 3.2% to 100% may be used to deposit the DLC containing layer. Alternatively, the duty cycle is 3.2% to 75%, typically 3.2% to 50%, preferably 3.2% to 20%, and most preferably 3.2% to 10%. In a preferred embodiment of the CVD deposition of DLC containing layers described herein, the bias voltage is from-1000V to-1200V (e.g., -1200V) and the duty cycle is from 3.2% to 10% (e.g., 3.2%).

Drawings

FIG. 1 shows a coating apparatus for producing a coated substrate of the present invention.

Detailed Description

EXAMPLE 1 coating method (1)

As shown in fig. 1, the coated substrates were produced using a coating apparatus having a Ti sputtering source, two FCVA sources, a CVD source and an ion beam source disposed around a central coating chamber.

The coating device 1 has a central coating chamber 6. Around the coating chamber there is an ion beam source 2, two FCVA sources 3 and a sputter source 4. In use, a substrate (not shown) is mounted on a coating fixture (not shown) which is then loaded into the coating chamber and centrally positioned on the platform 5. The coating chamber 6 can then be sealed and evacuated to the desired vacuum before the substrate is coated.

Coating a substrate by performing the following steps in order:

1. a pre-cleaned steel substrate is mounted on a coating fixture (also referred to as a substrate holder).

2. The coating jig with the substrate mounted thereon was loaded into the coating chamber and evacuated to the desired vacuum level (see below, for understanding the pressure required for each step). The heater temperature was set at 100 ℃ and maintained throughout the coating process.

3. The substrate is etched using an ion beam source.

4. The Ti layer is applied by sputtering with a Ti target until the desired thickness is reached. During sputtering, the chamber pressure was about 2.0x10 ^-3 And (5) Torr. During the sputtering step, the substrate holder was biased at-300V at a 50% duty cycle.

5. The ta-C layer is applied through FCVA using a graphite source until the desired thickness is reached. During FCVA, the FCVA coating pressure is lower than 2.0x10 ^-5 And (5) Torr. During the FCVA step, the substrate holder was biased at-1200V at a 3.2% duty cycle.

6. Use of C ₂ H ₂ The CVD source applies the DLC layer by CVD until the desired thickness is reached. CVD pressure was about 2.0x10 ^-3 And (5) Torr. During the CVD step, the substrate holder was biased at-1200V at a 3.2% duty cycle.

7. The vacuum is released and the mounted coated substrate is removed from the coating chamber.

8. The coated substrate is removed from the coating fixture.

The resulting coated substrate had the following properties:

the Young's modulus of the DLC layer is 90GPa, and the density is 2.410kg/m ³ . Some further tests were performed on the coated substrates, and detailed information is provided below.

Example 2 testing of sheet resistance

Using PRS-801 resistorsThe system measures surface resistance, and the measured surface resistance is 5.7x10 ⁷ Ω/sq。

EXAMPLE 3 test of hardness

The hardness of the inventive coating described in example 1 was determined using a NMT3 nanoindenter tester with a maximum load of 500 mN. However, only 4mN was used for the hardness measurement. A loading/unloading rate of 16mN/min and a pause of 30 seconds were used. From the load/unload curve showing force versus indentation, the vickers hardness number (HV) of the coating was determined to be 3000HV.

EXAMPLE 4 testing of abrasion resistance

A friction test (Tribo test) was performed using the Bruker TriboLab system to determine the wear resistance of the coating under repeated vigorous oscillatory movements. The friction test is a reciprocating "pin-on-disk" type of sliding test and simulates oscillatory wear that may occur during use. The coating passed 1500 cycles at 400N. The coating also passed 10000 cycles under load of 750g and CS-17tip (CS-17 tip).

Example 5 coating method (2)

As shown in fig. 1, the coated substrates were produced using a coating apparatus having a Ti sputtering source, two FCVA sources, a CVD source and an ion beam source disposed around a central coating chamber. The CVD source is a PACVD source.

Coating a substrate by performing the following steps in order:

1. a pre-cleaned steel substrate is mounted on a coating fixture (also referred to as a substrate holder).

2. The coating jig with the substrate mounted thereon was loaded into the coating chamber and evacuated to a desired degree of vacuum (see below, for understanding the pressure required for each step). The heater temperature was set at 120 ℃ and maintained throughout the coating process.

3. The substrate is etched using an ion beam source.

4. The Ti layer is applied by sputtering with a Ti target until the desired thickness is reached. During sputtering, the chamber pressure was about 2.0x10 ^-3 And (5) Torr. During the sputtering step, the substrate holder was biased at-300V at a 50% duty cycle.

5. Applying a ta-C layer through FCVA with a graphite source untilTo achieve the desired thickness. During FCVA, the FCVA coating pressure is lower than 2.0x10 ^-5 And (5) Torr. During the FCVA step, the substrate holder was biased at-1200V at a duty cycle of 3.2%.

6. By C ₂ H ₂ The PACVD source applies the DLC layer by PACVD until the desired thickness is reached. PACVD pressure is about 2.0x10 ^-3 And (5) Torr. During the PACVD step, the substrate holder was biased at-1200V at a 3.2% duty cycle. During the PACVD step, C ₂ H ₂ The gas flow entered the coating chamber at 100 sccm.

7. The vacuum is released and the mounted coated substrate is removed from the coating chamber.

8. The coated substrate is removed from the coating fixture.

The coated substrate was determined to have a 10 ⁷ Surface resistance of Ω/sq. The coating also has desirable film hardness, density and uniformity.

Claims (20)

1. A substrate coated with a coating in the form of a plurality of layers comprising, in order:

i. a substrate, a first electrode and a second electrode,

a conductive metal seed layer (e.g. titanium or chromium),

a ta-C containing layer, and

a layer comprising a DLC layer, wherein the DLC layer comprises a first polymer,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

2. The substrate according to claim 1, wherein the ta-C containing layer has a thickness of 0.1 to 1.0 μ ι η.

3. Substrate according to claim 1 or 2, wherein the DLC-containing layer has a thickness of 1.5 to 3.5 μ η ι.

4. The substrate according to any one of the preceding claims, wherein the ta-C containing layer consists of ta-C and/or the DLC containing layer consists of DLC.

5. According to any one of the preceding claimsThe substrate of (1), wherein the coating has a thickness of 10 ⁶ Omega/sq to 10 ⁷ Surface resistance of Ω/sq.

6. The substrate according to any one of the preceding claims, wherein the ta-C containing layer and the DLC containing layer are adjacent.

7. The substrate of any one of the preceding claims, wherein the seed layer is adjacent to the ta-C containing layer.

8. The substrate of any one of the preceding claims, wherein the DLC comprising layer has a hydrogen content of 20% or more.

9. The substrate according to any one of the preceding claims, wherein the ta-C has a hydrogen content of 5% or less and an sp of 20% or less ² And (4) content.

10. Substrate according to any one of the preceding claims, wherein the DLC has a hydrogen content of 20% or more and a sp of 50% or more ² And (4) content.

11. The substrate according to any of the preceding claims, wherein the substrate is made of metal (e.g. copper, aluminum, steel), silicon or glass.

12. The substrate according to any one of the preceding claims, wherein the DLC containing layer is deposited by a CVD method.

13. Substrate according to any one of the preceding claims, wherein the ta-C containing layer is deposited by a PVD process, such as CVA process (preferably FCVA).

14. The substrate according to any one of the preceding claims, wherein the DLC containing layer is deposited by a PACVD process having the following deposition parameters:

i.100 ℃ to 200 ℃,

ii, a gas flow of 50sccm to 200sccm, wherein the gas is selected from CH ₄ 、C ₂ H ₆ Or C ₂ H ₂ ，

A bias voltage of-50V to-1200V, and

a duty cycle of 3.2% to 75%.

15. The substrate according to any one of the preceding claims, wherein the DLC containing layer is deposited by a PACVD process having the following deposition parameters:

coating temperatures of from 110 ℃ to 120 ℃,

ii.80sccm to 120sccm of a gas flow, wherein the gas is C ₂ H ₂ ，

A bias voltage of-800V to-1200V, and

a duty cycle of 3.2% to 20%.

16. A substrate coated with a coating in multilayer form according to any one of the preceding claims, comprising in sequence:

i. a substrate, a first electrode and a second electrode,

ii, a seed layer,

a ta-C containing layer, and

a layer comprising a DLC layer, wherein the DLC layer comprises a first polymer,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

17. The substrate according to any one of the preceding claims, comprising in sequence:

i. a metal substrate, a metal base and a metal base,

a conductive metal seed layer (e.g. titanium or chromium),

a ta-C containing layer having a thickness of 0.1 μm to 1.0 μm, and

a DLC containing layer having a thickness of 1.5 μm to 3.5 μm.

18. A method of making a substrate according to any preceding claim, comprising providing the substrate and applying to the substrate in sequence:

i. a seed layer,

a ta-C containing layer, and

DLC-containing layer

Wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

19. The method according to claim 18, wherein said ta-C is deposited by FCVA.

20. A method according to claim 16 or 17, comprising providing a substrate and applying to the substrate in sequence:

i. a seed layer,

a ta-C containing layer deposited by FCVA, and

DLC layer deposited by a PACVD process with the following deposition parameters:

a coating temperature of 100 ℃ to 200 ℃,

b, a gas flow of 50sccm to 200sccm, wherein the gas is selected from CH ₄ 、C ₂ H ₆ Or C ₂ H ₂ ，

c. A bias voltage of-50V to-1200V, an

d.3.2% to 75% duty cycle,

wherein the coating has a thickness of 10 ⁵ Omega/sq to 10 ⁹ Surface resistance of Ω/sq.

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