CN115428164A

CN115428164A - Display panel, preparation method and display device

Info

Publication number: CN115428164A
Application number: CN202180000579.XA
Authority: CN
Inventors: 李永谦; 冯雪欢
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-03-24
Filing date: 2021-03-24
Publication date: 2022-12-02
Also published as: WO2022198496A1; WO2022198496A8

Abstract

A display panel, a preparation method and a display device are provided. The display area of the display panel comprises a plurality of pixel areas and a plurality of grid driving circuit areas, wherein the grid driving circuit areas are positioned between two adjacent pixel areas, and the display panel comprises: a substrate; the back plate circuit layer is positioned on the substrate, is arranged in the grid electrode driving circuit area and is provided with a plurality of thin film transistors; the display panel is provided with a shading hole, a metal layer is filled in the shading hole, and the shading hole and the orthographic projection position of the metal layer on the substrate are configured to shield active layer light irradiating the thin film transistor.

Description

Display panel, preparation method and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel, a preparation method and a display device.

Background

In the display field, especially in Organic Light Emitting Diode (OLED) based display devices, the gate driving circuit is an important component in the display device. The gate driving circuit may include a plurality of cascaded shift registers, and the shift registers generate scanning signals to scan each row of sub-pixels in the display device, so as to display the image. With the prevalence of large-sized and narrow-bezel display devices, more and more display devices adopt a strategy of disposing a gate driving circuit on a display panel to narrow the bezel of the display device.

Therefore, the current display panel, the preparation method and the display device still need to be improved.

Disclosure of Invention

The present application aims to mitigate or solve at least to some extent at least one of the above mentioned problems.

The inventor finds that in some display devices, especially in large-size OLED display, the gate driving circuit is usually disposed on both sides of the display panel, which makes it difficult to achieve ultra-narrow frames even without frames, and many display panels are designed in non-rectangular shapes at present, which makes it difficult to achieve narrow frames in the conventional design. Particularly, when a Thin Film Transistor (TFT) in a gate driver circuit is designed in a display area (AA area), the TFT is negatively floated due to light interference emitted from a light emitting area of an adjacent pixel, which affects the panel life.

In view of the above, in one aspect of the present application, a display panel is provided. This display panel's display area includes a plurality of pixel areas and a plurality of grid drive circuit region, grid drive circuit region is located adjacent two between the pixel area, display panel includes: a substrate; the back plate circuit layer is positioned on the substrate, is arranged in the grid electrode driving circuit area and is provided with a plurality of thin film transistors; the display panel is provided with a shading hole, a metal layer is filled in the shading hole, and the shading hole and the orthographic projection position of the metal layer on the substrate are configured to shield light irradiating an active layer of the thin film transistor. Therefore, the influence of the light emission of the light-emitting element on the TFT in the grid driving circuit region can be relieved or even avoided by the light-shielding hole and the metal layer of the display panel, and the service life of the display panel can be further prolonged on the premise of realizing a narrow frame.

In some examples of the present application, the light shielding holes and the metal layer are located on a side of the backplane circuit layer away from the substrate. Therefore, the active layer of the thin film transistor can be better protected, and the negative drift can be prevented.

In some examples of the present application, the pixel region and the gate driving circuit region are adjacently disposed, the light emitting elements are located in the pixel region, and a pixel defining structure is provided between the adjacent light emitting elements, and the light shielding hole is formed on the pixel defining structure. Thus, the light shielding hole and the metal layer can be easily provided.

In some examples of the present application, the metal layer includes a cathode metal. Thus, the light shielding hole and the metal layer can be easily provided.

In some examples of the present application, a plurality of the light shielding holes are included, and the light shielding holes are provided between each of the pixel regions and the thin film transistors in the gate driving circuit region. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved.

In some examples of the present application, the thin film transistor within the gate driving circuit region includes: an active layer; the grid electrode and the grid insulating layer are positioned on one side, far away from the substrate, of the active layer; the source and drain electrodes are positioned on one side, far away from the substrate, of the active layer, interlayer dielectric layers are arranged between the source and drain electrodes and the grid electrode at intervals, the source and drain electrodes are connected with the active layer through holes penetrating through the interlayer dielectric layers, and no overlapping region exists between the orthographic projection of the shading holes on the substrate and the orthographic projection of the through holes of the interlayer dielectric layers on the substrate. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved.

In some examples of the present application, the pixel region further includes a pixel light emitting sub-region and a pixel circuit sub-region, the light emitting element is located in the pixel light emitting region, the pixel light emitting sub-region and the pixel circuit sub-region are arranged along a first direction, and the light shielding hole extends along the first direction. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved.

In some examples of the present application, two of the light shielding holes are provided between two adjacent pixel regions, a length of the light shielding hole in the first direction is identical to a length of the transistor group, and a plurality of thin film transistors in the transistor group are arranged between the two light shielding holes in the first direction. The protection of the light shielding hole on the active layer of the thin film transistor can be further improved.

In some examples of the present application, the pixel regions are arranged in an array on the substrate, each pixel region includes at least two sub-pixels, each row of the pixel regions corresponds to at least two gate driving circuit regions, each gate driving circuit region is located between two adjacent pixel regions, the gate driving circuit includes a plurality of cascaded shift registers, and each shift register is electrically connected to one row of the sub-pixels; each of the shift registers includes a plurality of transistor groups, each of the transistor groups including at least one of the thin film transistors.

In some examples of the present application, the light shielding holes have a depth of 1 to 3 micrometers and a width of 3 to 10 micrometers. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved.

In another aspect of the present application, a method of manufacturing the aforementioned display panel is provided, the method comprising: forming a backboard circuit layer on a substrate, and forming a plurality of thin film transistors in the grid driving circuit area in the display panel; forming a plurality of light-emitting elements on one side of the backboard circuit layer, which is far away from the substrate, and enabling the light-emitting elements to be located in the pixel area; and the method comprises the operation of forming a light shielding hole and a metal layer, and filling the metal layer into the light shielding hole, wherein the light shielding hole and the orthographic projection position of the metal layer on the substrate are configured to shield the light of the light-emitting element from irradiating an active layer of the thin film transistor. Thus, the display panel can be obtained easily.

In some examples of the present application, forming the light shielding hole and the metal layer includes: forming a pixel defining structure between a plurality of the light emitting elements in advance before forming the light emitting elements, and forming the light shielding hole on the pixel defining structure; the metal layer is formed using a cathode metal when the light emitting element is formed. Thus, the light shielding hole and the metal layer can be formed easily.

In yet another aspect of the present application, a display device is presented. The display device comprises the display panel. Therefore, the display device has at least one of the advantages of narrow frame, long service life and the like.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 shows a schematic structural diagram of a display panel according to an example of the present application;

FIG. 2 isbase:Sub>A schematic cross-sectional view of the display panel along the line A-A' in FIG. 1;

FIG. 3 shows a schematic structural diagram of a display panel according to an example of the present application;

FIG. 4 shows a circuit schematic of a pixel circuit according to an example of the present application;

FIG. 5 shows a circuit schematic of a gate driver circuit according to an example of the present application;

FIG. 6 shows a circuit schematic of a gate driver circuit according to another example of the present application;

FIG. 7 shows a circuit schematic of a gate driver circuit according to yet another example of the present application;

FIG. 8 shows a circuit schematic of a gate driver circuit according to yet another example of the present application;

fig. 9 shows a flow chart of a method of manufacturing a display panel according to an example of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In one aspect of the present application, a display panel is presented. Referring to fig. 1 and fig. 2, the display area of the display surface 1000 includes a plurality of pixel areas 1100 and a plurality of gate driving circuit areas 1200, and the gate driving circuit areas 1200 are located between two adjacent pixel areas 1100. The substrate 100 has a backplane circuit layer thereon, and the backplane circuit layer has a plurality of thin film transistors in the gate driving circuit region. A plurality of light emitting elements (only one is shown in fig. 2) 800 are located on a side of the backplane circuit layer away from the substrate 100 and within the area of the pixel area. The light blocking hole (see 1220 in fig. 1) is filled with a metal layer 50, and the light blocking hole and the position of the orthographic projection of the metal layer on the substrate are configured to block light irradiated to the active layer of the thin film transistor. Therefore, the shading holes and the metal layer of the display panel can relieve or even avoid the influence of the light emission of the light-emitting elements and the like on the TFT in the grid drive circuit area, and further can further prolong the service life of the display panel on the premise of realizing narrow frames.

For easy understanding, the following first briefly explains the principle of the display panel that can achieve the above beneficial effects:

according to some examples of the present application, in order to narrow a bezel of the display panel, a gate driving circuit may be disposed between two adjacent pixel regions in a display region. However, since the gate driving circuit has a complicated structure, in order to reduce an occupied area thereof, a plurality of thin film transistors in the gate driving circuit are collectively arranged and set as a transistor group 1210 adjacent to the pixel region. The design can achieve the effect of narrowing the frame well, but at the same time, if the light shielding hole and the metal layer are not arranged, the light emitted by the pixel light-emitting sub-area 1110 in the pixel area can easily irradiate the active layer of the transistor group, which causes the negative drift of the thin film transistor. With the setting of crossing shading hole and metal level, can shelter from the light that the luminous subregion of pixel sent better, prevent to shine to active layer, and then can alleviate or even avoid because the illumination and the burden that takes place floats to realize prolonging this display panel's life's effect.

In some examples of the present application, specific positions of the light-shielding hole and the metal layer in a cross-sectional direction (i.e., a direction perpendicular to a plane in which the substrate 100 is located) in the display panel are not particularly limited as long as light shielding can be achieved. For example, referring to fig. 2, the light shielding holes and the metal layer 50 may be located on a side of the backplane circuit layer away from the substrate, i.e., on a side of the thin film transistor away from the substrate 100. Therefore, the active layer of the thin film transistor can be better protected, and negative drift can be prevented.

Specifically, as shown in fig. 2, adjacent light emitting elements 800 have a pixel defining structure 600 therebetween, and a light blocking hole may be formed on the pixel defining structure. The metal layer 50 includes a cathode metal. Thus, the light shielding hole and the metal layer can be easily provided: on one hand, the light shielding holes and the metal layer 50 are arranged without affecting the change of the etching patterns of the metal and the various laminated structures in the backplane circuit layer. On the other hand, the pixel defining structure has a relatively large thickness due to the need of structures such as light emitting layers for separating two adjacent light emitting elements, and the like, thereby facilitating the preparation of light shielding holes. Also, the pixel defining structure 600 itself has an opening for receiving the light emitting element 800, and thus the light shielding hole may be formed in synchronization with the opening. The metal layer 50 filled in the light blocking holes can be formed by using the cathode metal of the light emitting device 800.

In some examples of the present application, the display panel may include a plurality of the light shielding holes. Referring to fig. 1, each pixel region and the tft in the gate driving circuit region may have the light shielding hole therebetween. For example, when the gate driving circuit includes the transistor group 1210, each gate driving circuit region may have two light shielding holes 1220 to isolate light emission of two pixel regions 1100 adjacent thereto. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved.

In some examples of the present application, the specific number and structure of the thin film transistors in the gate driving circuit region are not particularly limited, and those skilled in the art can design the thin film transistors according to actual needs. For example, in some examples of the present application, a thin film transistor may include an active layer 10, a gate electrode 21, and a gate insulating layer 700, the gate electrode and the gate insulating layer being located on a side of the active layer 10 away from the substrate 100; the source and drain electrodes (source 31 and drain 32) may be located on a side of the active layer 10 away from the substrate 100, an interlayer dielectric layer 300 is spaced between the source and drain electrodes and the gate, and the source and drain electrodes are connected to the active layer 10 through a through hole penetrating through the interlayer dielectric layer 300.

It should be particularly noted that the foregoing thin film transistor is only an example of the present invention, and is not to be construed as limiting the specific structure of the thin film transistor. For example, the backplane circuit layer may include the buffer layer 200, the aforementioned various levels of the thin film transistor, and the passivation layer 400, the planarization layer 500, and the like, on the substrate 100.

According to some examples of the present application, there may be no overlapping area between an orthographic projection of the light blocking hole on the substrate and an orthographic projection of the via hole penetrating the interlayer dielectric layer 300 on the substrate. That is, the position of the light shielding hole may be disposed as close to the pixel region as possible. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved: at this time, the light blocking hole and the metal layer 50 filled therein may better protect the channel region between the source and drain electrodes. Light emitted from the light emitting element 800 or the like can be better shielded by the metal layer 50 (refer to the direction shown by the arrow in fig. 2).

In some examples of the present application, referring to fig. 1 and 3, the pixel region further includes a pixel light emitting sub-region 1110 and a pixel circuit sub-region 1120, the light emitting element is located in the pixel light emitting region, the pixel light emitting sub-region and the pixel circuit sub-region are arranged in a first direction, and the light blocking hole 1220 extends in the first direction. Therefore, the protection of the light shielding hole on the active layer of the thin film transistor can be further improved: as mentioned above, in order to save the occupied area of the gate driving circuit, the plurality of thin film transistors in the transistor group 1210 are mostly arranged in sequence, for example, arranged along the first direction. At this time, the light shielding holes 1220 are arranged along the first direction, so that the occupied area can be saved, and the transistor group can be better shielded. The pixel circuit in the sub-light emitting area of the pixel may also have a plurality of thin film transistors and capacitor structures, and the active layer 10 of the plurality of thin film transistors may be formed of an entire layer of semiconductor material through a patterning process. Similarly, the gate layer 20 may be formed by a whole layer of metal material through a patterning process to form a plurality of metal blocks and metal traces, which serve as gates of the tfts, traces such as gate lines, and form a capacitor structure with other metal layers. The source drain layer 30 may also be used to form source drain electrodes and data traces. The plurality of signal lines 40 may be formed by gate metal or source-drain metal through a patterning process, metal traces to be electrically connected need to be formed, and the source-drain of the thin film transistor and the active layer may be connected through a via hole.

In some examples of the present application, two light shielding holes are provided between two adjacent pixel regions 1100. The length of the light shielding hole in the first direction corresponds to the length of the transistor group 1210. That is, the protection of the active layer of the thin film transistor by the light shielding hole can be further improved. According to some examples of the present application, the depth and width of the light shielding holes are not particularly limited, for example, in some examples, the depth of the light shielding holes may be 1 to 3 micrometers and the width of the light shielding holes may be 3 to 10 micrometers. The depth of the light shielding hole is the extension depth along the direction perpendicular to the plane of the substrate 100, and the width is the dimension perpendicular to the first direction of the light shielding hole on the plane of the substrate 100.

In the present application, the specific shape and size of the light-shielding holes are not particularly limited, and may be selected by those skilled in the art according to the actual circumstances. For example, the light shielding hole may be a through hole penetrating the pixel defining structure, or may be a blind hole not completely penetrating the pixel defining structure. The orthographic projection of the light shielding holes on the substrate 100 may be in the shape of a bar, a circular hole, or other shapes, as long as the metal layer filled in the light shielding holes can shield light irradiated to the active layer.

Similarly, the specific structure of the metal layer 50 is also not particularly limited. For example, when the metal layer 50 is formed of a cathode metal, the metal layer 50 may be connected to the cathode 830 of the light emitting element 80 (such a structure is not shown in the drawing), or may have a structure as shown in fig. 2, that is, the metal layer 50 is not connected to the cathode 830. It will be understood by those skilled in the art that the light emitting element 800 is shown here only in one case, i.e., the light emitting element 800 includes an anode 810, a cathode 830, and a light emitting layer 820 sandwiched therebetween. In other examples of the present application, the structure of the light emitting element 800 is not limited thereto, and may have a structure including, but not limited to, an electron transport layer, an electron blocking layer, a hole transport layer, a hole blocking layer, and the like.

It should be noted that the length of the light shielding hole along the first direction is equal to the length of the transistor group 1210, which means that the lengths are substantially equal, not exactly equal. That is, the length of the light shielding hole can be approximately the same as the extended length of the transistor group, so that a better shielding effect is realized. The length of the light shielding hole can be slightly shorter than that of the transistor group or longer than that of the transistor group. The skilled person can adjust the position and length of the light shielding holes according to the specific positions of the plurality of active layers in the transistor group.

In some examples of the present application, pixel regions are arranged in an array on the substrate, each of the pixel regions includes at least two sub-pixels, each row of the pixel regions corresponds to at least two gate driving circuit regions, each gate driving circuit region is located between two adjacent pixel regions, the gate driving circuit includes a plurality of cascaded shift registers, and each shift register is electrically connected to one row of the sub-pixels; each of the shift registers includes a plurality of transistor groups, each of the transistor groups including at least one of the thin film transistors.

The following briefly describes the specific structure and operation principle of the gate driving circuit with reference to some examples of the present application:

referring to fig. 1, 3 and 4, the pixel circuit sub-area 1100 may have a pixel circuit therein. Each sub-pixel corresponds to a pixel circuit, and the structure of the pixel circuit is not particularly limited, and the pixel circuit is used for controlling the light emission of the light emitting element in the light emitting sub-area of the pixel, for example, controlling the on and off thereof, and adjusting the light emission luminance. The specific pixel circuit structure can be set according to actual needs. For example, the structure of the pixel circuit may include a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C", where "T" is a thin film transistor, the number located in front of "T" indicates the number of thin film transistors, "C" is a storage capacitor, and the number located in front of "C" indicates the number of storage capacitors. The pixel circuit may typically comprise a switching transistor and a driving transistor. In one example of the present application, the pixel circuit may have a structure as illustrated in fig. 4.

During the use of the display panel, the stability of the thin film transistor and the light emitting device (OLED) in the pixel circuit may be reduced (e.g., the threshold voltage of the driving transistor is shifted), which affects the display effect of the display panel, and therefore, the pixel circuit of the sub-pixel needs to be compensated. The compensation mode can comprise various modes, and the setting can be selected according to actual needs. For example, a pixel compensation circuit may be provided in the sub-pixel to internally compensate the sub-pixel using the pixel compensation circuit. For another example, the driving transistor or the light emitting device may be measured by a thin film transistor inside the sub-pixel, and the measured data may be transmitted to an external sensing circuit, so that the external sensing circuit may be used to calculate a driving voltage value to be compensated and perform external compensation.

Taking the external compensation mode as an example, and the pixel circuit adopts a structure of 3T1C (including the switching transistor T1, the driving transistor T2, the sensing transistor T3, and the storage capacitor Cst), in some examples, the control electrode (gate) of the switching transistor T1 is electrically connected to the first gate signal terminal G1, the first electrode (one of the source and drain electrodes) of the switching transistor T1 is electrically connected to the Data signal terminal Data, and the second electrode (the other of the source and drain electrodes) of the switching transistor T1 is electrically connected to the first node G. At this time, the switching transistor T1 may respond to the first gate signal received at the first gate signal terminal G1, that is, the switching transistor T1 is turned on to transmit the Data signal received at the Data signal terminal Data to the first node G. The data signal may specifically include a detection data signal and a display data signal. A control electrode of the driving transistor T2 is electrically connected to the first node G, a first electrode of the driving transistor T2 is electrically connected to the fourth voltage signal terminal ELVDD, and a second electrode of the driving transistor T2 is electrically connected to the second node S. And the driving transistor T2 is turned on under the control of the voltage of the node G, the fourth voltage signal received at the fourth voltage signal terminal ELVDD may be transmitted to the second node S. The storage capacitor Cst has a first terminal electrically connected to the first node G and a second terminal electrically connected to the second node S. Thus, the switching transistor T1 can simultaneously charge the storage capacitor Cst while charging the first node G. An anode of the light emitting device (OLED) is electrically connected to the second node S, and a cathode is electrically connected to the fifth voltage signal terminal ELVSS, so that light can be emitted in cooperation with the fourth voltage signal from the second node S and the fifth voltage signal transmitted from the fifth voltage signal terminal ELVSS.

The control electrode of the sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first electrode is electrically connected to the second node S, and the second electrode is electrically connected to the sensing signal terminal Sense. The sensing transistor T3 may detect an electrical characteristic of the driving transistor T2 in response to the second gate signal received at the second gate signal terminal G2 to implement external compensation. According to some examples of the present application, the electrical characteristic may include one or both of a threshold voltage and a carrier mobility of the driving transistor T2. The sensing signal terminal Sense may provide a reset signal for resetting the second node S or a sensing signal for acquiring a threshold voltage of the driving transistor T2.

In some examples, the first gate signal received at the first gate signal terminal G1 and the second gate signal received at the second gate signal terminal G2 of each sub-pixel may be the same. Specifically, the plurality of pixel circuits in the same row of sub-pixels may be electrically connected to two gate lines (formed as the gate layer 20 shown in fig. 3) that transmit the same electrical signal. Alternatively, a plurality of pixel circuits in the same row of sub-pixels may be electrically connected to one gate line.

In some examples of the present application, the display phase of one frame may include a display period and a blanking period that are sequentially performed. Specifically, in the display period in the one-frame display phase, the operation process of the sub-pixels may include, for example, a reset phase, a data write phase, and a light emission phase. In the following, the thin film transistors are all N-type transistors as an example:

in the reset phase, referring to fig. 4, the level of the second gate signal provided by the second gate signal terminal G2 is high level, and the sensing signal terminal Sense provides a reset signal (the level of the reset signal is, for example, low level). The sensing transistor T3 is turned on under the control of the second gate signal, receives a reset signal, transmits the reset signal to the second node S, and resets the second node S. In the Data writing phase, the level of the first gate signal provided by the first gate signal terminal G1 is at a high level, and the level of the display Data signal provided by the Data signal terminal Data is at a high level. The switching transistor T1 is turned on under the control of the first gate signal, receives a display data signal, and transmits the display data signal to the first node G while charging the storage capacitor Cst. In the light emitting phase, the level of the first gate signal provided by the first gate signal terminal G1 is at a low level, the level of the second gate signal provided by the second gate signal terminal G2 is at a low level, and the level of the fourth voltage signal provided by the fourth voltage signal terminal ELVDD is at a high level. The switching transistor T1 is turned off under the control of the first gate signal, and the sensing transistor T3 is turned off under the control of the second gate signal. The storage capacitor Cst starts discharging so that the voltage of the first node G is maintained at a high level. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal, and transmits the fourth voltage signal to the second node S, so that the light emitting device emits light under the cooperation of the fourth voltage signal and the fifth voltage signal transmitted from the fifth voltage signal terminal ELVSS.

The operation of the blanking period sub-pixels in the display phase of one frame may include: a first stage and a second stage. In the first phase, the level of the first gate signal provided by the first gate signal terminal G1 and the level of the second gate signal provided by the second gate signal terminal G2 are both high levels, and the level of the detection Data signal provided by the Data signal terminal Data is high level. The switching transistor T1 is turned on under the control of the first gate signal, receives the detection data signal, transmits the detection data signal to the first node G, and charges the first node G. The sensing transistor T3 is turned on under the control of the second gate signal, the sensing signal receiving terminal Sense provides a reset signal, and the reset signal is transmitted to the second node S. In the second phase, the Sense signal terminal Sense is in a floating state. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal provided by the fourth voltage signal terminal ELVDD, and transmits the fourth voltage signal to the second node S, which is charged such that the voltage of the second node S increases until the driving transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2. Since the sensing transistor T3 is in the on state and the sensing signal terminal Sense is in the floating state, the sensing signal terminal Sense is also charged during the process of charging the second node S by the driving transistor T2. By sampling the voltage of the sensing signal terminal Sense (i.e., acquiring the sensing signal), the threshold voltage Vth of the driving transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal. After the threshold voltage Vth of the driving transistor T2 is calculated, the threshold voltage Vth can be compensated into the display data signal of the display period in the next frame display phase, completing the external compensation for the sub-pixels.

In some examples, referring to fig. 5 and 6, the gate driving circuit may include a plurality of cascaded stages of shift registers 1230, and one stage of the shift register may be electrically connected to a plurality of pixel circuits in one row of sub-pixels. In the display stage of one frame, the first gate signal transmitted by the first gate signal terminal G1 and the second gate signal transmitted by the second gate signal terminal G2 may be both provided by the gate driving circuit, and each stage of the shift register 1230 in the gate driving circuit may be electrically connected to the first gate signal terminal G1 through a first gate line, transmit the first gate signal to the first gate signal terminal G1 through the first gate line, and be electrically connected to the second gate signal terminal G2 through a second gate line, and transmit the second gate signal to the second gate signal terminal G2 through the second gate line.

The structure of the shift register 1230 is not particularly limited, and may be selected according to actual needs. The following schematically illustrates the structure of the shift register in two configurations, but is not to be construed as limiting the shift register 1230:

in some examples, as shown in fig. 5 and 6, shift register 1230 may include: a first input circuit 3101, an electric leak preventing circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108, and a fifth reset circuit 3109.

Illustratively, as shown in fig. 5 and 6, the first input circuit 3101 is electrically connected to an input signal terminal (abbreviated as Iput in the drawings and below), a pull-up node Q < N >, and an anti-leakage node OFF < N >. The first input circuit 3101 may transmit an input signal to the pull-up node Q < N > based on the input signal received at the input signal terminal Iput during a display period in one frame display phase. Where N is a positive integer expressed as the number of rows of subpixels. More specifically, in the case where the level of the input signal is a high level, the first input circuit 3101 may be turned on by the input signal and transmit the input signal to the pull-up node Q < N >, charging the pull-up node Q < N >, so that the voltage of the pull-up node Q < N > is raised. The first input circuit 3101 may specifically include a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, the first electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the second transistor M2 and the first anti-leakage node OFF 1. A control electrode of the second transistor M2 is electrically connected to the input signal terminal Iput, and a second electrode of the second transistor M2 is electrically connected to the first pull-up node Q1.

Accordingly, when the level of the input signal transmitted through the input signal terminal Iput is high, the first transistor M1 and the second transistor M2 can be simultaneously turned on by the input signal. The first transistor M1 may receive an input signal transmitted from the input signal terminal Iput, and transmit the received input signal to the first electrode of the second transistor M2 and the anti-leakage node OFF < N >. The second transistor M2 may transmit the received input signal to the pull-up node Q < N >, charging the pull-up node Q < N >, so that the voltage of the pull-up node Q < N > is raised.

According to some examples of the present application, the leakage prevention circuit 3102 may be electrically connected to the pull-up node Q < N >, the first voltage signal terminal VDD, and the leakage prevention node OFF < N >. The leakage prevention circuit 3102 may transmit the first voltage signal transmitted from the first voltage signal terminal VDD to the leakage prevention node OFF < N > under the control of the voltage of the pull-up node Q < N > to prevent leakage at the pull-up node Q < N >: specifically, the leakage of the pull-up node Q < N > through the first input circuit 3101 can be avoided, so that the pull-up node Q < N > can maintain a higher and more stable voltage. The first voltage signal may be a constant high voltage signal.

For example, when the voltage of the pull-up node Q < N > is high, the anti-leakage circuit 3102 may be turned on under the control of the voltage of the pull-up node Q < N >, receive and transmit the first voltage signal to the anti-leakage node OFF < N >, so as to raise the voltage of the anti-leakage node OFF < N >. The anti-leakage circuit 3102 may specifically include a third transistor M3, wherein a control electrode of the third transistor M3 is electrically connected to the pull-up node Q < N >, a first electrode of the third transistor M3 is electrically connected to the first voltage signal terminal VDD, and a second electrode of the third transistor M3 is electrically connected to the anti-leakage node OFF < N >. Therefore, when the voltage of the pull-up node Q < N > is at a high level, the third transistor M3 may be turned on under the control of the voltage of the pull-up node Q < N >, transmit the first voltage signal to the anti-leakage node OFF < N >, raise the voltage of the anti-leakage node OFF < N >, and make the voltage difference between the control electrode and the first electrode of the second transistor M2 less than zero, thereby ensuring that the second transistor M2 is completely or relatively completely turned OFF.

Illustratively, as shown in fig. 5 and 6, the Output circuit 3103 is electrically connected to the pull-up node Q < N >, the first clock signal terminal CLKE _1, and a first Output signal terminal Output1< N > (abbreviated as Oput1< N > in the drawings and hereinafter). Among them, the output circuit 3103 may transfer the first clock signal received at the first clock signal terminal CLKE _1 to the first output signal terminal Oput1< N > under the control of the voltage of the pull-up node Q < N > for a display period in one frame display phase.

Of course, as shown in fig. 5, the output circuit 3103 may also be electrically connected to the third clock signal terminal CLKD _1 and the shift signal terminal CR < N >, for example. Among them, the output circuit 3103 may also transmit the third clock signal received at the third clock signal terminal CLKD _1 to the shift signal terminal CR < N > under the control of the voltage of the pull-up node Q < N > in the display period in one frame display phase.

Of course, the exemplary Output circuit 3103 may also be electrically connected to the fourth clock signal terminal CLKF _1 and the second Output signal terminal Output2< N > (abbreviated as Oput2< N > in the drawings and below). During a blanking period in the one-frame display period, the output circuit 3103 may transfer the fourth clock signal received at the fourth clock signal terminal CLKF _1 to the second output signal terminal Oput2< N > under the control of the voltage of the pull-up node Q < N >. Specifically, in the case where the voltage of the pull-up node Q < N > rises, the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q < N >, outputting the third clock signal received at the third clock signal terminal CLKD _1 as a shift signal from the shift signal terminal CR < N >; the first clock signal received at the first clock signal terminal CLKE _1 is output from the first output signal terminal Oput1< N > as a first output signal. In the blanking period in the one-frame display stage, in the case where the voltage of the pull-up node Q < N > is raised, the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q < N >, outputting the fourth clock signal received at the fourth clock signal terminal CLKF _1 as the second output signal from the second output signal terminal Oput2< N >. More specifically, the first output signal terminal Oput1< N > may be electrically connected to the first gate line, and a first output signal output from the first output signal terminal Oput1< N > may be transmitted as a first gate signal to the pixel circuit 12 through the first gate line and the first gate signal terminal G1 in sequence. The second output signal terminal Oput2< N > may be electrically connected to the second gate line, and a second output signal output from the second output signal terminal Oput2< N > may be transmitted to the pixel circuit as a second gate signal sequentially through the second gate line and the second gate signal terminal G2.

According to some examples of the present application, referring to fig. 6, the output circuit 3103 may include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2. A control electrode of the fourth transistor M4 is electrically connected to the pull-up node Q < N >, a first electrode of the fourth transistor M4 is electrically connected to the third clock signal terminal CLKD _1, and a second electrode of the fourth transistor M4 is electrically connected to the shift signal terminal CR < N >.

In the display period in the one-frame display phase, in the case where the first input circuit 3101 is turned on so that the voltage of the pull-up node Q < N > is raised, the fourth transistor M4 may be turned on under the control of the high voltage of the pull-up node Q < N >, transmit the third clock signal to the shift signal terminal CR < N >, and output the third clock signal as the shift signal from the shift signal terminal CR < N >. A control electrode of the fifth transistor M5 is electrically connected to the pull-up node Q < N >, a first electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE _1, and a second electrode of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1< N >. A first terminal of the first capacitor C1 is electrically connected to the pull-up node Q < N >, and a second terminal of the first capacitor C1 is electrically connected to the first output signal terminal Oput1< N >.

In a display period in the one-frame display phase, the first capacitor C1 is charged while the first input circuit 3101 is turned on, so that the voltage of the pull-up node Q < N > is raised. With the first input circuit 3101 turned off, the first capacitor C1 may be discharged such that the pull-up node Q < N > is maintained at a high level, and thus the fifth transistor M5 may be maintained in an on state, transmit the first clock signal to the first output signal terminal Oput1< N >, and output the first clock signal as the first output signal from the first output signal terminal Oput1< N >.

Illustratively, a control electrode of the sixth transistor M6 is electrically connected to the pull-up node Q < N >, a first electrode of the sixth transistor M6 is electrically connected to the fourth clock signal terminal CLKF _1, and a second electrode of the sixth transistor M6 is electrically connected to the second output signal terminal Oput2< N >. A first terminal of the second capacitor C2 is electrically connected to the pull-up node Q < N >, and a second terminal of the second capacitor C2 is electrically connected to the second output signal terminal Oput2< N >. In a blanking period in a display period of one frame, the second capacitor C2 is charged while the voltage of the pull-up node Q < N > is raised. In a corresponding stage, the second capacitor C2 may be discharged so that the pull-up node Q < N > is maintained at a high level, and thus the sixth transistor M6 may be maintained in a turn-on state, transmit the fourth clock signal to the second output signal terminal Oput2< N >, and output the fourth clock signal as the second output signal from the second output signal terminal Oput2< N >.

According to some examples of the present application, after the plurality of stages of shift registers 1230 are cascaded to form the gate driving circuit, the shift signal terminal CR < N > of the nth stage shift register may be electrically connected to the input signal terminal Iput of the (N + 1) th stage shift register, for example, so as to use the shift signal output from the shift signal terminal CR < N > of the nth stage shift register as the input signal of the (N + 1) th stage shift register 21. Of course, the cascade connection relationship of the shift registers is not limited to this, and those skilled in the art can design the cascade connection relationship according to practical situations.

According to other examples of the present application, the input signal terminal Iput of a part of the shift register 1230 may be electrically connected to the start signal terminal STU, i.e., receive a start signal transmitted by the start signal terminal STU as an input signal. Specifically, the partial shift register may be a first stage shift register in the gate driver circuit, or may be a first stage shift register and a second stage shift register, or the like. The number of shift registers electrically connected to the start signal terminal STU is not limited, and those skilled in the art can select the arrangement according to actual needs.

Illustratively, as shown in fig. 5 and 6, the control circuit 3104 is electrically connected to the pull-up node Q < N >, the sixth voltage signal terminal VDD _ a, the pull-down node QB _ a, and the second voltage signal terminal VGL 1. The control circuit 3104 is configured to control the voltage of the pull-down node QB _ a under the control of the voltage of the pull-up node Q < N > and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD _ a. The level of the sixth voltage signal may be, for example, constant during the display phase of one frame. The second voltage signal terminal VGL1 may be configured to transmit a direct current low level signal (e.g., lower than or equal to a low level portion of the clock signal). The second voltage signal terminal VGL1 may be grounded, for example.

Specifically, in the case where the voltage of the pull-up node Q < N > is raised, the control circuit 3104 may transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB _ a, and pull down the voltage of the pull-down node QB _ a to a low voltage. In a case where the voltage of the pull-up node Q < N > is a low voltage, the control circuit 3104 may transmit the sixth voltage signal transmitted by the sixth voltage signal terminal VDD _ a to the pull-down node QB _ a, and pull up the voltage of the pull-down node QB _ a to a high level. The control circuit 3104 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. A control electrode of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD _ a, a first electrode of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD _ a, and a second electrode of the seventh transistor M7 is electrically connected to a control electrode of the eighth transistor M8 and a first electrode of the ninth transistor M9. A first pole of the eighth transistor M8 is electrically connected to the sixth voltage signal terminal VDD _ a, and a second pole of the eighth transistor M8 is electrically connected to the pull-down node QB _ a and the first pole of the tenth transistor M10. A control electrode of the ninth transistor M9 is electrically connected to the pull-up node Q < N >, and a second electrode of the ninth transistor M9 is electrically connected to the second voltage signal terminal VGL 1. A control electrode of the tenth transistor M10 is electrically connected to the pull-up node Q < N >, and a second electrode of the tenth transistor M10 is electrically connected to the second voltage signal terminal VGL 1.

Accordingly, when the level of the sixth voltage signal transmitted from the sixth voltage signal terminal VDD _ a is at a high level, the seventh transistor M7 is turned on by the sixth voltage signal, and receives and transmits the sixth voltage signal to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The eighth transistor M8 is turned on by the sixth voltage signal, and receives and transmits the sixth voltage signal to the pull-down node QB _ a and the first pole of the tenth transistor M10.

In a case where the voltage of the pull-up node Q < N > is at a high level, the ninth transistor M9 and the tenth transistor M10 may be turned on under the control of the voltage of the pull-up node Q < N >, the ninth transistor M9 may transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the control electrode of the eighth transistor M8, such that the eighth transistor M8 is turned off, and the tenth transistor M10 may transmit the second voltage signal to the pull-down node QB _ a, pulling the voltage of the pull-down node QB _ a low.

In a case where the voltage of the pull-up node Q < N > is low, the ninth transistor M9 and the tenth transistor M10 may be turned off under the control of the voltage of the pull-up node Q < N >, and the eighth transistor M8 may transmit the received sixth voltage signal to the pull-down node QB _ a, pulling the voltage of the pull-down node QB _ a high.

According to some examples of the present application, the first reset circuit 3105 is electrically connected to the pull-down node QB _ a, the pull-up node Q < N >, the second voltage signal terminal VGL1, and the leakage preventing node OFF < N >. The first reset circuit 3105 may reset the pull-up node Q < N > under the control of the voltage of the pull-down node QB _ a:

when the voltage of the pull-down node QB _ a is at a high level, the first reset circuit 3105 may be turned on by the voltage of the pull-down node QB _ a, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q < N >, and perform pull-down reset on the pull-up node Q < N >. Specifically, the first reset circuit 3105 may include: an eleventh transistor M11 and a twelfth transistor M12. A control electrode of the eleventh transistor M11 is electrically connected to the pull-down node QB _ a, a first electrode of the eleventh transistor M11 is electrically connected to the pull-up node Q < N >, and a second electrode of the eleventh transistor M11 is electrically connected to a first electrode of the twelfth transistor M12 and the anti-leakage node OFF < N >. A control electrode of the twelfth transistor M12 is electrically connected to the pull-down node QB _ a, and a second electrode of the twelfth transistor M12 is electrically connected to the second voltage signal terminal VGL 1.

When the voltage of the pull-down node QB _ a is at a high level, the eleventh transistor M11 and the twelfth transistor M12 may be simultaneously turned on by the voltage of the pull-down node QB _ a, the twelfth transistor M12 may transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the anti-leakage node OFF < N >, and the eleventh transistor M11 may transmit the second voltage signal from the anti-leakage node OFF < N > to the pull-up node Q < N > to reset the pull-up node Q < N >.

When the potential of the pull-up node Q < N > is high and the first reset circuit 3105 is in a non-operating state, the third transistor M3 may be turned on under the control of the voltage of the pull-up node Q < N >, and transmit the first voltage signal to the anti-leakage node OFF < N >, so that the voltage of the anti-leakage node OFF < N > is raised, and further, the voltage difference between the control electrode and the second electrode of the eleventh transistor M11 is smaller than zero, thereby ensuring that the eleventh transistor M11 is completely or relatively completely turned OFF. Thus, the pull-up node Q < N > is prevented from leaking through the first reset circuit 3105, so that the pull-up node Q < N > can maintain a high and stable voltage.

As shown in fig. 5 and 6, the second reset circuit 3106 may be electrically connected to the display reset signal terminal STD, the pull-up node Q < N >, the second voltage signal terminal VGL1, and the leakage preventing node OFF < N >. Thus, the second reset circuit 3106 can reset the pull-up node Q < N > under the control of the display reset signal transmitted from the display reset signal terminal STD:

when the display reset signal is at a high level, the second reset circuit 3106 may be turned on by the display reset signal, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q < N >, and perform a pull-down reset on the pull-up node Q < N >. The second reset circuit 3106 may include a thirteenth transistor M13 and a fourteenth transistor M14. A control electrode of the thirteenth transistor M13 is electrically connected to the display reset signal terminal STD, a first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node Q < N >, and a second electrode of the thirteenth transistor M13 is electrically connected to a first electrode of the fourteenth transistor M14 and the anti-leakage node OFF < N >. A control electrode of the fourteenth transistor M14 is electrically connected to the display reset signal terminal STD, and a second electrode of the fourteenth transistor M14 is electrically connected to the second voltage signal terminal VGL 1.

When the display reset signal is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 may be turned on simultaneously by the display reset signal, the fourteenth transistor M14 may transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the anti-leakage node OFF < N >, and the thirteenth transistor M13 may transmit the second voltage signal from the anti-leakage node OFF < N > to the pull-up node Q < N > to reset the pull-up node Q < N >.

Specifically, when the potential of the pull-up node Q < N > is high and the second reset circuit 3106 is in a non-operating state, the third transistor M3 may be turned on under the control of the voltage of the pull-up node Q < N >, and transmit the first voltage signal to the anti-leakage node OFF < N >, so that the voltage of the anti-leakage node OFF < N > is increased, and further, the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 is smaller than zero, thereby ensuring that the thirteenth transistor M13 is completely or relatively completely turned OFF. This prevents the pull-up node Q < N > from leaking through the second reset circuit 3106, so that the pull-up node Q < N > can maintain a high and stable voltage.

Similarly, after the plurality of shift registers are cascade-connected to form the gate driving circuit, the display reset signal terminal STD of the nth shift register stage 1230 may be electrically connected to the shift signal terminal CR < N > of the (N + 4) th shift register stage, for example, and the shift signal output from the shift signal terminal CR < N > of the (N + 4) th shift register stage may be used as the display reset signal of the nth shift register stage.

Illustratively, as shown in fig. 5 and 6, the third reset circuit 3107 may be electrically connected to the global reset signal terminal TRST, the pull-up node Q < N >, the second voltage signal terminal VGL1, and the leakage prevention node OFF < N >. The third reset circuit 3107 can thus reset the pull-up node Q < N > under the control of the global reset signal transmitted from the global reset signal terminal TRST:

for example, when the global reset signal is at a high level, the third reset circuit 3107 may be turned on by the global reset signal, transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the pull-up node Q < N >, and perform pull-down reset on the pull-up node Q < N >. Specifically, the third reset circuit 3107 may include: a fifteenth transistor M15 and a sixteenth transistor M16. A control electrode of the fifteenth transistor M15 is electrically connected to the global reset signal terminal TRST, a first electrode of the fifteenth transistor M15 is electrically connected to the pull-up node Q < N >, and a second electrode of the fifteenth transistor M15 is electrically connected to a first electrode of the sixteenth transistor M16 and the anti-leakage node OFF < N >. A control electrode of the sixteenth transistor M16 is electrically connected to the global reset signal terminal TRST, and a second electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal VGL 1.

When the voltage of the global reset signal is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 may be turned on simultaneously by the global reset signal, the sixteenth transistor M16 may transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF < N >, and the fifteenth transistor M15 may transmit the fifth voltage signal from the anti-leakage node OFF < N > to the pull-up node Q < N > to reset the pull-up node Q < N >.

Here, when the potential of the pull-up node Q < N > is high and the third reset circuit 3107 is in a non-operating state, the third transistor M3 may be turned on under the control of the voltage of the pull-up node Q < N >, transmit the first voltage signal to the anti-leakage node OFF < N >, raise the voltage of the anti-leakage node OFF < N >, further make the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 less than zero, and ensure that the fifteenth transistor M15 is completely or relatively completely turned OFF. Thus, the leakage of the pull-up node Q < N > through the third reset circuit 3107 can be avoided, so that the pull-up node Q < N > can maintain a higher and more stable voltage.

For example, as shown in fig. 6, the fourth reset circuit 3108 may be electrically connected to the pull-down node QB _ a, the shift signal terminal CR < N >, the first output signal terminal Oput1< N >, the second output signal terminal Oput2< N >, the second voltage signal terminal VGL1, and the third voltage signal terminal VGL 2. The fourth reset circuit 3108 may reset the shift signal terminal CR < N >, the first output signal terminal Oput1< N >, and the second output signal terminal Oput2< N > under the control of the voltage of the pull-down node QB _ a.

In some examples of the present application, the third voltage signal terminal VGL2 is configured to transmit a dc low level signal (e.g., lower than or equal to a low level portion of the clock signal). The third voltage signal terminal VGL2 may be grounded, for example. The low level signals transmitted by the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 may be equal or unequal.

Specifically, when the voltage of the pull-down node QB _ a is at a high level, the fourth reset circuit 3108 may be turned on by the voltage of the pull-down node QB _ a, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, pull-down reset the shift signal terminal CR < N >, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1< N >, pull-down reset the first output signal terminal Oput1< N >, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second output signal terminal Oput2< N >, and pull-down reset the second output signal terminal Oput2< N >.

More specifically, the fourth reset circuit 3108 may include: a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19. A control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB _ a, a first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR < N >, and a second electrode of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal VGL 1.

When the voltage of the pull-down node QB _ a is at a high level, the seventeenth transistor M17 may be turned on by the voltage of the pull-down node QB _ a, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, and pull-down reset the shift signal terminal CR < N >. A control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB _ a, a first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1< N >, and a second electrode of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the pull-down node QB _ a is at a high level, the eighteenth transistor M18 may be turned on by the voltage of the pull-down node QB _ a, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the first output signal terminal Oput1< N >, and pull-down reset the first output signal terminal Oput1< N >. A control electrode of the nineteenth transistor M19 is electrically connected to the pull-down node QB _ a, a first electrode of the nineteenth transistor M19 is electrically connected to the second output signal terminal Oput2< N >, and a second electrode of the nineteenth transistor M19 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the pull-down node QB _ a is at a high level, the nineteenth transistor M19 may be turned on by the voltage of the pull-down node QB _ a, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the second output signal terminal Oput2< N >, and pull-down reset the second output signal terminal Oput2< N >.

Illustratively, as shown in fig. 5 and 6, the fifth reset circuit 3109 is electrically connected to the input signal terminal Iput, the pull-down node QB _ a, and the second voltage signal terminal VGL 1. The fifth reset circuit 3109 may reset the pull-down node QB _ a under control of the input signal transmitted by the input signal terminal Iput:

for example, when the level of the input signal is high, the fifth reset circuit 3109 may be turned on by the input signal, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB _ a, and perform pull-down reset on the pull-down node QB _ a. Specifically, the fifth reset circuit 3109 may include: a twentieth transistor M20.

A control electrode of the twentieth transistor M20 is electrically connected to the input signal terminal Iput, a first electrode of the twentieth transistor M20 is electrically connected to the pull-down node QB _ a, and a second electrode of the twentieth transistor M20 is electrically connected to the second voltage signal terminal VGL 1. When the level of the input signal is high, the twentieth transistor M20 may be turned on by the input signal, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB _ a, and perform pull-down reset on the pull-down node QB _ a.

In some examples of the present application, referring to fig. 6, the gate driving circuit may further include a plurality of blanking input circuits 3200. One blanking input circuit may be electrically connected to at least two adjacent stages of shift registers. In other words, at least two stages of shift registers may share one blanking input circuit. The blanking input circuit may control the corresponding shift register to input a blanking control signal to the pixel circuits of the corresponding row in a blanking period of the one frame display period, so that the pixel circuits acquire the sensing signal:

specifically, as shown in fig. 6, the blanking input circuit 3200 may include, for example, a selection control circuit 3201, a second input circuit 3202, and at least two transmission circuits 3203. The selection control circuit 3201 is electrically connected to the selection control signal terminal OE, the shift signal terminal CR < N >, the second voltage signal terminal VGL1, and the first blanking node H, and transmits the shift signal received at the shift signal terminal CR < N > to the first blanking node H under the control of the selection control signal transmitted by the selection control signal terminal OE.

Specifically, in the case where the level of the selection control signal is a high level, the selection control circuit 3201 may be turned on under the control of the selection control signal and transmit the received shift signal to the first blanking node H, charging the first blanking node H, so that the voltage of the first blanking node H is raised. In the blanking period of one frame display period, in the case where the sensing signal needs to be acquired, the waveform timing of the selection control signal and the waveform timing of the input signal can be made the same, thereby turning on the selection control circuit 3201. Specifically, the selection control circuit 3201 may include: a twenty-first transistor M21, a twenty-second transistor M22, and a third capacitor C3. A control electrode of the twenty-first transistor M21 is electrically connected to the selection control signal terminal OE, a first electrode of the twenty-first transistor M21 is electrically connected to the shift signal terminal CR < N >, and a second electrode of the twenty-first transistor M21 is electrically connected to a first electrode of the twenty-second transistor M22. A control electrode of the twentieth transistor M22 is electrically connected to the selection control signal terminal OE, and a second electrode of the twentieth transistor M22 is electrically connected to the first blanking node H.

When the level of the selection control signal transmitted by the selection control signal terminal OE is high level, the twenty-first transistor M21 and the twenty-second transistor M22 may be turned on simultaneously under the action of the selection control signal, the twenty-first transistor M21 may transmit the shift signal transmitted by the shift signal terminal CR < N > to the first pole of the twenty-second transistor M22, and the twenty-second transistor M22 may receive and transmit the shift signal to the first blanking node H to charge the first blanking node H. A first terminal of the third capacitor C3 is electrically connected to the first blanking node H, and a second terminal of the third capacitor C3 is electrically connected to the second voltage signal terminal VGL 1. The third capacitor C3 is also charged during the charging of the first blanking node H by the selection control circuit 3201. This makes it possible to discharge with the third capacitor C3 with the selection control circuit 3201 turned off, so that the first blanking node H maintains a high level.

Specifically, the selection control circuit 3201 may further include, for example: a twenty-third transistor M23. A control electrode of the twenty-third transistor M23 is electrically connected to the first blanking node H, a first electrode of the twenty-third transistor M23 is electrically connected to the first voltage signal terminal VDD, and a second electrode of the twenty-third transistor M23 is electrically connected to the first electrode of the twenty-second transistor M22. Therefore, under the condition that the voltage of the first blanking node H is at a high level and the twenty-first transistor M21 and the twenty-second transistor M22 are not operating, the twenty-third transistor M23 may be turned on under the control of the voltage of the first blanking node H, and transmit the first voltage signal transmitted by the first voltage signal terminal VDD to the first pole of the twenty-second transistor M22, so that the voltage of the first pole of the twenty-second transistor M22 is raised, and further, the voltage difference between the control pole and the first pole of the twenty-second transistor M22 is smaller than zero, thereby ensuring that the twenty-second transistor M22 is completely or relatively completely turned off. This prevents the first blanking node H from leaking through the twenty-second transistor M22, so that the first blanking node H can maintain a high and stable voltage.

According to some examples of the present invention, the second input circuit 3202 is electrically connected with the first blanking node H, the second blanking node N, and the second clock signal terminal CLKA or the first voltage signal terminal VDD to transmit the second clock signal received at the second clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N under the control of the voltage of the first blanking node H.

For example, in a case where the selection control circuit 3201 is turned on such that the voltage of the first blanking node H is raised, the second input circuit 3202 may be turned on under the control of the voltage of the first blanking node H, receive the second clock signal transmitted by the second clock signal terminal CLKA, and transmit the second clock signal to the second blanking node N. Specifically, the second input circuit 3202 may include: a twenty-fourth transistor M24. A control electrode of the twenty-fourth transistor M24 is electrically connected to the first blanking node H, a first electrode of the twenty-fourth transistor M24 is electrically connected to the second clock signal terminal CLKA or the first voltage signal terminal VDD, and a second electrode of the twenty-fourth transistor M24 is electrically connected to the second blanking node N.

In case that the voltage of the first blanking node H is a high level, the twenty-fourth transistor M24 may be turned on under the control of the voltage of the first blanking node H, transmitting the fourth clock signal received at the fourth clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N.

For example, the at least two transmission circuits 3203 may be electrically connected to at least two shift registers in a one-to-one correspondence. A transmission circuit 3203 is electrically connected to the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q < N > of the first stage of shift register. Wherein the transmission circuit 3202 is configured to transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q < N > under control of the second clock signal transmitted by the second clock signal terminal CLKA.

For example, in a case where the level of the second clock signal transmitted by the second clock signal terminal CLKA is a high level, the transmission circuit 3202 may be turned on under the control of the second clock signal, and receive the second clock signal or the first voltage signal from the second blanking node N, transmit the received second clock signal or the first voltage signal to the pull-up node Q < N >, so that the voltage of the pull-up node Q < N > is raised, and may further turn on the output circuit 3103, so that the second output signal terminal Oput2< N > of the output circuit 3103 outputs the second output signal. Specifically, the transmission circuit 3203 may include: a twenty-fifth transistor M25 and a twenty-sixth transistor M26. A control electrode of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, a first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and a second electrode of the twenty-fifth transistor M25 is electrically connected to a first electrode of the twenty-sixth transistor M26. A control electrode of the twenty-sixth transistor M26 is electrically connected to the second clock signal terminal CLKA, and a second electrode of the twenty-sixth transistor M26 is electrically connected to the pull-up node Q < N >.

Therefore, when the level of the second clock signal transmitted by the second clock signal terminal CLKA is at a high level, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 may be turned on simultaneously under the action of the second clock signal, the twenty-fifth transistor M25 may transmit the second clock signal or the first voltage signal from the second blanking node N to the first pole of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 may receive and transmit the second clock signal or the first voltage signal to the pull-up node Q < N >, so as to charge the pull-up node Q < N >. The sixth transistor M6 in the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q < N >, receive the fourth clock signal, and output the fourth clock signal as the second output signal from the second output signal terminal Oput2< N >.

When the transmission circuit 3203 is further electrically connected to the anti-leakage node OFF < N >, the first pole of the twenty-sixth transistor M26 may be electrically connected to the anti-leakage node OFF < N > and the second pole of the twenty-fifth transistor M25, and at this time, when the potential of the pull-up node Q < N > is high and the transmission circuit 3203 is in an inactive state, the third transistor M3 may be turned on under the control of the voltage of the pull-up node Q < N >, transmit the first voltage signal to the anti-leakage node OFF < N >, raise the voltage of the anti-leakage node OFF < N >, further make the voltage difference between the control pole and the first pole of the twenty-sixth transistor M26 less than zero, and ensure that the twenty-sixth transistor M26 is completely or relatively completely turned OFF. Therefore, the pull-up node Q < N > can be prevented from generating electric leakage through the transmission circuit 3203, and the pull-up node Q < N > can keep a higher and more stable voltage.

According to some examples of the present application, in a case where the gate driving circuit further includes a blanking input circuit, the shift register may further include a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB _ a, and the second voltage signal terminal VGL1, so that the pull-down node QB _ a can be reset under the common control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H in the blanking period of one frame display period.

For example, in the blanking period of the one-frame display period, when the level of the second clock signal is at a high level and the voltage of the first blanking node H is at a high level, the sixth reset circuit 3110 may be turned on under the common control of the second clock signal and the voltage of the first blanking node H, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB _ a, and perform pull-down reset on the pull-down node QB _ a. Specifically, the sixth reset circuit 3110 may include: a thirtieth transistor M32 and a thirtieth transistor M33. A control electrode of the thirty-second transistor M32 is electrically connected to the second clock signal terminal CLKA, a first electrode of the thirty-second transistor M32 is electrically connected to the pull-down node QB _ a, and a second electrode of the thirty-second transistor M32 is electrically connected to a first electrode of the thirty-third transistor M33. A control electrode of the thirty-third transistor M33 is electrically connected to the first blanking node H, and a second electrode of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL 1.

When the level of the second clock signal is at a high level and the voltage of the first blanking node H is at a high level, the thirty-third transistor M33 may be turned on under the control of the voltage of the first blanking node H to transmit the second voltage signal to the first pole of the thirty-third transistor M33, and the thirty-second transistor M32 may be turned on under the control of the second clock signal to transmit the second voltage signal from the first pole of the thirty-third transistor M33 to the pull-down node QB _ a, thereby performing pull-down reset on the pull-down node QB _ a.

In the following, the structure of the gate driving circuit is schematically described by taking an example in which two adjacent stages of shift registers share one blanking input circuit 3200: in the following description, N is represented as a positive odd number.

As shown in fig. 6, in the adjacent two stages of shift registers, the fourth transistor M4 may not be provided in the output circuit 3103 in the next stage of shift register, and is not electrically connected to the third clock signal terminal CLKD _1. At this time, the shift signal terminal CR < N > of the nth stage shift register may be electrically connected to the input signal terminal Iput of the (N + 2) th and (N + 3) th stage shift registers, and the shift signal output from the shift signal terminal CR < N > of the nth stage shift register may be used as the input signal of the (N + 2) th and (N + 3) th stage shift registers. The display reset signal terminal STD of the nth stage and the (N + 1) th stage shift register may be electrically connected to the shift signal terminal CR < N +4> of the (N + 4) th stage shift register, for example, and the shift signal output from the shift signal terminal CR < N +4> of the (N + 4) th stage shift register may be used as the display reset signal of the nth stage and the (N + 1) th stage shift register.

For example, the shift signal terminal CR < N > in the first stage shift register may be electrically connected to the input signal terminal Iput in the third and fourth stage shift registers. The shift signal terminal CR < N > in the fifth stage shift register may be electrically connected to the display reset signal terminal STD in the first and second stage shift registers. Therefore, the structure of the gate driving circuit can be simplified, and the space occupation ratio of the gate driving circuit in the display panel can be reduced. Of course, the cascade relationship of the multi-stage shift register may not be limited to the foregoing description, and may be modified by those skilled in the art according to the circumstances.

In some examples of the present application, referring to fig. 6, a shift register 1230a of a previous stage (i.e., nth stage) of adjacent two stages of shift registers may be referred to as a first scan unit, and a shift register 1230b of a next stage (i.e., N +1 th stage) may be referred to as a second scan unit 21b. The pull-up node Q < N > in the first scan unit 21a may be referred to as a first pull-up node Q < N >, and the pull-up node Q < N > in the second scan unit 21b may be referred to as a second pull-up node Q < N +1>. Similarly, the pull-down node QB _ a in the first scan cell 21a is referred to as a first pull-down node QB _ a, and the pull-down node QB _ a in the second scan cell 21B is referred to as a second pull-down node QB _ B; the leakage-preventing node OFF < N > in the first scanning unit 21a is referred to as a first leakage-preventing node OFF < N >, and the leakage-preventing node OFF < N > in the second scanning unit 21b is referred to as a second leakage-preventing node OFF < N +1>; the first clock signal CLKE _1 in the second scanning unit 21b is called a fifth clock signal CLKE _2, and the fourth clock signal CLKF _1 in the second scanning unit 21b is called a sixth clock signal CLKF _2; the first output signal terminal Oput1< N > in the first scanning unit 21a is referred to as a first sub-output signal terminal Oput1< N >, the second output signal terminal Oput2< N > in the first scanning unit 21a is referred to as a second sub-output signal terminal Oput2< N >, the first output signal terminal Oput1< N > in the second scanning unit 21b is referred to as a third sub-output signal terminal Oput1< N +1>, and the second output signal terminal Oput2< N > in the second scanning unit 21b is referred to as a fourth sub-output signal terminal Oput2< N +1>.

Referring to fig. 6, the control circuit 3104 in the second scan unit 21B may be electrically connected to the seventh voltage signal terminal VDD _ B, replacing the sixth voltage signal terminal VDD _ a with the seventh voltage signal terminal VDD _ B. In the display phase of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD _ a and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD _ B are inverse signals.

According to some examples of the present application, referring to fig. 6, the first reset circuit 3105 in the first scan cell 21a may also be electrically connected with the second pull-down node QB _ B. The first reset circuit 3105 may reset the first pull-up node Q < N > under control of the voltage of the second pull-down node QB _ B:

specifically, when the voltage of the second pull-down node QB _ B is at a high level, the first reset circuit 3105 may be turned on by the voltage of the second pull-down node QB _ B, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the first pull-up node Q < N >, and perform pull-down reset on the first pull-up node Q < N >. The first reset circuit 3105 in the first scan cell 21a may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

More specifically, in the first scan cell 21a, the control electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-down node QB _ B, the first electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-up node Q < N >, and the second electrode of the twenty-seventh transistor M27 is electrically connected to the first electrode of the twenty-eighth transistor M28 and the first anti-leakage node OFF < N >. A control electrode of the twenty-eighth transistor M28 is electrically connected to the second pull-down node QB _ B, and a second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL 1.

When the voltage of the second pull-down node QB _ B is at a high level, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 may be simultaneously turned on by the voltage of the second pull-down node QB _ B, the twenty-eighth transistor M28 may transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the first anti-leakage node OFF < N >, and the twenty-seventh transistor M27 may transmit the second voltage signal from the first anti-leakage node OFF < N > to the first pull-up node Q < N >, and reset the first pull-up node Q < N >.

In some examples of the present application, referring to fig. 6, the first reset circuit 3105 in the second scan cell 21b may also be electrically connected with the first pull-down node QB _ a. Wherein the first reset circuit 3105 is further configured to reset the second pull-up node Q < N +1> under the control of the voltage of the first pull-down node QB _ a. Specifically, when the voltage of the first pull-down node QB _ a is at a high level, the first reset circuit 3105 may be turned on by the voltage of the first pull-down node QB _ a, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the second pull-up node Q < N +1>, and perform pull-down reset on the second pull-up node Q < N +1>. More specifically, the first reset circuit 3105 in the second scan unit 21b may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

That is, in the second scan cell 21b, the control electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB _ a, the first electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-up node Q < N +1>, and the second electrode of the twenty-seventh transistor M27 is electrically connected to the first electrode of the twenty-eighth transistor M28 and the second anti-leakage node OFF < N +1>. A control electrode of the twenty-eighth transistor M28 is electrically connected to the first pull-down node QB _ a, and a second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL 1.

When the voltage of the first pull-down node QB _ a is at a high level, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 may be turned on at the same time by the voltage of the first pull-down node QB _ a, the twenty-eighth transistor M28 may transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the second leakage prevention node OFF < N +1>, and the twenty-seventh transistor M27 may transmit the second voltage signal from the second leakage prevention node OFF < N +1> to the second pull-up node Q < N +1>, and reset the second pull-up node Q < N +1>.

In other examples of the present application, the fourth reset circuit 3108 in the first scan cell 21a may also be electrically connected to the second pull-down node QB _ B. Accordingly, the fourth reset circuit 3108 can reset the shift signal terminal CR < N >, the first sub output signal terminal Oput1< N >, and the second sub output signal terminal Oput2< N > under the control of the voltage of the second pull-down node QB _ B: in a case where the voltage of the second pull-down node QB _ B is at a high level, the fourth reset circuit 3108 may be turned on by the voltage of the second pull-down node QB _ B, transfer the second voltage signal transferred from the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, pull-down reset the shift signal terminal CR < N >, and transfer the third voltage signal transferred from the third voltage signal terminal VGL2 to the first sub output signal terminal Oput1< N > and the second sub output signal terminal Oput2< N >, pull-down reset the first sub output signal terminal Oput1< N > and the second sub output signal terminal Oput2< N >.

Specifically, the fourth reset circuit 3108 in the first scan unit 21a may further include: a twenty-ninth transistor M29, a thirtieth transistor M30, and a thirty-first transistor M31. A control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB _ B, a first electrode of the twenty-ninth transistor M29 is electrically connected to the shift signal terminal CR < N >, and a second electrode of the twenty-ninth transistor M29 is electrically connected to the second voltage signal terminal VGL 1. Therefore, when the voltage of the second pull-down node QB _ B is at a high level, the twenty-ninth transistor M29 may be turned on by the voltage of the second pull-down node QB _ B, transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, and pull-down reset the shift signal terminal CR < N >.

A control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB _ B, a first electrode of the thirtieth transistor M30 is electrically connected to the first sub output signal terminal Oput1< N >, and a second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the second pull-down node QB _ B is at a high level, the thirtieth transistor M30 may be turned on by the voltage of the second pull-down node QB _ B, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub output signal terminal Oput1< N >, and perform pull-down reset on the first sub output signal terminal Oput1< N >.

A control electrode of the thirty-first transistor M31 is electrically connected to the second pull-down node QB _ B, a first electrode of the thirty-first transistor M31 is electrically connected to the second sub output signal terminal Oput2< N >, and a second electrode of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the second pull-down node QB _ B is at a high level, the thirty-first transistor M31 may be turned on by the voltage of the second pull-down node QB _ B, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput2< N >, and perform pull-down reset on the second sub-output signal terminal Oput2< N >.

According to some examples of the present application, the fourth reset circuit 3108 in the second scan cell 21b may also be electrically connected with the first pull-down node QB _ a. That is, the fourth reset circuit 3108 may reset the third and fourth sub output signal terminals Oput1< N +1> and Oput2< N +1> under the control of the voltage of the first pull-down node QB _ a:

when the voltage of the first pull-down node QB _ a is at a high level, the fourth reset circuit 3108 may be turned on by the voltage of the first pull-down node QB _ a, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1< N +1>, perform pull-down reset on the third sub-output signal terminal Oput1< N +1>, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2< N +1>, and perform pull-down reset on the fourth sub-output signal terminal Oput2< N +1>. Specifically, the fourth reset circuit 3108 may further include: a thirtieth transistor M30 and a thirty-first transistor M31.

At this time, the control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB _ a, the first electrode of the thirtieth transistor M30 is electrically connected to the third sub output signal terminal Oput1< N +1>, and the second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the first pull-down node QB _ a is at a high level, the thirtieth transistor M30 may be turned on by the voltage of the first pull-down node QB _ a, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1< N +1>, and pull-down reset the third sub-output signal terminal Oput1< N +1>.

A control electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB _ a, a first electrode of the thirty-first transistor M31 is electrically connected to the fourth sub output signal terminal Oput2< N +1>, and a second electrode of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL 2. When the voltage of the first pull-down node QB _ a is at a high level, the thirty-first transistor M31 may be turned on by the voltage of the first pull-down node QB _ a, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2< N +1>, and pull-down reset the fourth sub-output signal terminal Oput2< N +1>.

In other examples, as shown in fig. 5 and 8, shift register 1230 may include: a first input circuit 3101, a leakage prevention circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108, and a fifth reset circuit 3109. Specifically, the structures of the first input circuit 3101, the anti-leakage circuit 3102, the output circuit 3103, the control circuit 3104, the first reset circuit 3105, the second reset circuit 3106, the third reset circuit 3107, the fourth reset circuit 3108 and the fifth reset circuit 3109 shown in fig. 8 may be the same as the corresponding circuit structures shown in fig. 6, and the structures and functions of the same circuits are not described herein again.

Unlike the foregoing example, the output circuit 3103 as shown in fig. 8 is electrically connected to the pull-up node Q < N >, the first clock signal terminal CLKE _1, and the first output signal terminal Oput1< N >, and the first clock signal received at the first clock signal terminal CLKE _1 is transmitted to the first output signal terminal Oput1< N > under the control of the voltage of the pull-up node Q < N > during the display period in one frame display phase; the first clock signal received at the first clock signal terminal CLKE _1 is transmitted to the first output signal terminal Oput1< N > under the control of the voltage of the pull-up node Q < N > during a blank period in one frame display period.

Alternatively, the output circuit 3103 may be electrically connected to, for example, the third clock signal terminal CLKD _1 and the shift signal terminal CR < N >. Thus, the third clock signal received at the third clock signal terminal CLKD _1 can be transmitted to the shift signal terminal CR < N > under the control of the voltage of the pull-up node Q < N > in the display period in one frame display stage. Specifically, in the case where the voltage of the pull-up node Q < N > rises in the display period in the one-frame display phase, the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q < N >, outputting the third clock signal received at the third clock signal terminal CLKD _1 as a shift signal from the shift signal terminal CR < N >; the first clock signal received at the first clock signal terminal CLKE _1 is outputted from the first output signal terminal Oput1< N > as an output signal (i.e., a first gate signal received by the pixel circuit). In the blanking period in the one frame display phase, in the case where the voltage of the pull-up node Q < N > is raised, the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q < N >, outputting the first clock signal received at the first clock signal terminal CLKE _1 as an output signal (i.e., the second gate signal received by the pixel circuit) from the first output signal terminal Oput1< N >.

In this example, the first output signal terminal Oput1< N > of the shift register 1230 may be electrically connected to both the first gate line and the second gate line, so that the first output signal terminal Oput1< N > of the shift register may transmit the first gate signal to the pixel circuit through the first gate line and the first gate signal terminal G1 in sequence during the display period in the one frame display phase, and the first output signal terminal Oput1< N > of the shift register may transmit the second gate signal to the pixel circuit through the second gate line and the second gate signal terminal G2 in sequence during the blank period in the one frame display phase. In still other examples, the first output signal terminal Oput1< N > of the shift register may be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 through a gate line, respectively, so that the first output signal terminal Oput1< N > of the shift register may transmit the first gate signal to the pixel circuit 12 through the gate line and the first gate signal terminal G1 in sequence during a display period in one frame display period, and the first output signal terminal Oput1< N > of the shift register may transmit the second gate signal to the pixel circuit through the gate line and the second gate signal terminal G2 in sequence during a blank period in one frame display period.

Specifically, the output circuit 3103 may include a fourth transistor M4, a fifth transistor M5 and a first capacitor C1, a control electrode of the fourth transistor M4 being electrically connected to the pull-up node Q < N >, a first electrode of the fourth transistor M4 being electrically connected to the third clock signal terminal CLKD _1, and a second electrode of the fourth transistor M4 being electrically connected to the shift signal terminal CR < N >. Thus, in a display period in the one-frame display phase, in the case where the first input circuit 3101 is turned on so that the voltage of the pull-up node Q < N > is raised, the fourth transistor M4 may be turned on under the control of the high voltage of the pull-up node Q < N >, transmit the third clock signal to the shift signal terminal CR < N >, and output the third clock signal as the shift signal from the shift signal terminal CR < N >. A control electrode of the fifth transistor M5 is electrically connected to the pull-up node Q < N >, a first electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE _1, and a second electrode of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1< N >. A first terminal of the first capacitor C1 is electrically connected to the pull-up node Q < N >, and a second terminal of the first capacitor C1 is electrically connected to the first output signal terminal Oput1< N >.

In a display period in one frame display phase, the first capacitor C1 is charged while the first input circuit 3101 is turned on, so that the voltage of the pull-up node Q < N > is raised. In the case where the first input circuit 3101 is turned off, the first capacitor C1 may be discharged such that the pull-up node Q < N > is maintained at a high level, and thus the fifth transistor M5 may be maintained in an on state, transmit the first clock signal to the first output signal terminal Oput1< N >, and output the first clock signal as an output signal (i.e., the first gate signal received by the pixel circuit) from the first output signal terminal Oput1< N >.

In a blanking period in a display period of one frame, the first capacitor C1 is charged while the voltage of the pull-up node Q < N > is raised. At a corresponding stage, the first capacitor C1 may be discharged so that the pull-up node Q < N > is maintained at a high level, and thus the fifth transistor M6 may be maintained at a turn-on state, transmit the first clock signal to the first output signal terminal Oput1< N >, and output the first clock signal as an output signal (i.e., the second gate signal received by the pixel circuit) from the first output signal terminal Oput1< N >.

Referring to fig. 8, the fourth reset circuit 3108 is electrically connected to the pull-down node QB _ a, the shift signal terminal CR < N >, the first output signal terminal Oput1< N >, the second voltage signal terminal VGL1, and the third voltage signal terminal VGL 2. The fourth reset circuit 3108 is configured to reset the shift signal terminal CR < N > and the first output signal terminal Oput1< N > under the control of the voltage of the pull-down node QB _ a. Specifically, when the voltage of the pull-down node QB _ a is at a high level, the fourth reset circuit 3108 may be turned on by the voltage of the pull-down node QB _ a, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, pull-down reset the shift signal terminal CR < N >, transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1< N >, and pull-down reset the first output signal terminal Oput1< N >.

For example, the fourth reset circuit 3108 may include: a seventeenth transistor M17, and an eighteenth transistor M18. A control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB _ a, a first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR < N >, and a second electrode of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal VGL 1. When the voltage of the pull-down node QB _ a is at a high level, the seventeenth transistor M17 may be turned on by the voltage of the pull-down node QB _ a, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, and pull-down reset the shift signal terminal CR < N >. A control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB _ a, a first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1< N >, and a second electrode of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the pull-down node QB _ a is at a high level, the eighteenth transistor M18 may be turned on by the voltage of the pull-down node QB _ a, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the first output signal terminal Oput1< N >, and pull-down reset the first output signal terminal Oput1< N >.

Similarly, as shown in fig. 8, the gate driving circuit may further include a plurality of blanking input circuits 3200. Wherein one blanking input circuit may be electrically connected to at least two adjacent stages of shift registers. The blanking input circuit 3200 may control the corresponding shift register to input a blanking control signal to the pixel circuits of the corresponding row in a blanking period of the display period of one frame, so that the pixel circuits 12 acquire the sensing signal. Specifically, the blanking input circuit 3200 may include, for example: a selection control circuit 3201, a second input circuit 3202, and at least two transmission circuits 3203. Similarly, the selection control circuit 3201, the second input circuit 3202 and the at least two transmission circuits 3203 illustrated in fig. 8 may have structures and functions consistent with the corresponding structures illustrated in fig. 6, and are not described again.

Specifically, in the structure shown in fig. 8, the above-described at least two transmission circuits 3203 may be electrically connected with at least two shift registers in a one-to-one correspondence. A transmission circuit 3203 is electrically connected to the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q < N > of the first stage shift register, and transmits the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q < N > under the control of the second clock signal transmitted by the second clock signal terminal CLKA in a blanking period in a frame display stage.

For example, in a blanking period in one frame display phase, in the case where the level of the second clock signal transmitted by the second clock signal terminal CLKA is a high level, the transmission circuit 3202 may be turned on under the control of the second clock signal, and receive the second clock signal or the first voltage signal from the second blanking node N, transmit the received second clock signal or the first voltage signal to the pull-up node Q < N >, so that the voltage of the pull-up node Q < N > is raised, and may further turn on the output circuit 3103, so that the output signal terminal of the output circuit 3103 outputs an Oput < N > output signal. The transmission circuit 3203 may include: a control electrode of the twenty-fifth transistor M25, the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, a first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and a second electrode of the twenty-fifth transistor M25 is electrically connected to the pull-up node Q < N >. In the blanking period of one frame display phase, in the case that the level of the second clock signal transmitted by the second clock signal terminal CLKA is at a high level, the twenty-fifth transistor M25 may be turned on by the second clock signal, and the twenty-fifth transistor M25 may transmit the second clock signal or the first voltage signal from the second blanking node N to the pull-up node Q < N >, and charge the pull-up node Q < N >. The fifth transistor M5 in the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q < N >, receive the first clock signal, and output the first clock signal as an output signal from the first output signal terminal Oput1< N >.

Similarly, in the case where the gate driver circuit further includes a blanking input circuit, the shift register may further include a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB _ a, and the second voltage signal terminal VGL1, and resets the pull-down node QB _ a under the common control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H in the blanking period of one frame display period. Specifically, in the blanking period of the one-frame display period, when the level of the second clock signal is at a high level and the voltage of the first blanking node H is at a high level, the sixth reset circuit 3110 may be turned on under the common control of the second clock signal and the voltage of the first blanking node H, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB _ a, and perform pull-down reset on the pull-down node QB _ a. The sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33.

Specifically, a control electrode of the thirty-second transistor M32 is electrically connected to the first blanking node H, a first electrode of the thirty-second transistor M32 is electrically connected to the pull-down node QB _ a, and a second electrode of the thirty-third transistor M33 is electrically connected to a first electrode of the thirty-second transistor M32. A control electrode of the thirty-third transistor M33 is electrically connected to the second clock signal terminal CLKA, and a second electrode of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL 1. When the level of the second clock signal is at a high level and the voltage of the first blanking node H is at a high level, the thirty-third transistor M33 may be turned on under the control of the second clock signal to transmit the second voltage signal to the first pole of the thirty-third transistor M33, and the thirty-twelfth transistor M32 may be turned on under the control of the voltage of the first blanking node H to transmit the second voltage signal from the first pole of the thirty-third transistor M33 to the pull-down node QB _ a, thereby performing pull-down reset on the pull-down node QB _ a.

The following description will schematically describe the structure of the gate driver circuit, taking as an example that two adjacent stages of shift registers share one blanking input circuit. In the following description, N represents a positive odd number.

As shown in fig. 8, in the adjacent two stages of shift registers, the fourth transistor M4 may not be provided in the output circuit 3103 in the next stage of shift register, and the CLKD _1 is not electrically connected to the third clock signal terminal. At this time, the cascade relationship of the multi-stage shift register may be the same as the cascade relationship of the multi-stage shift register in some examples described above, and is not described herein again.

For example, a shift register of a previous stage (i.e., nth stage) among adjacent two stages of shift registers may be referred to as a first scan unit 21a, and a shift register of a next stage (i.e., N +1 th stage) may be referred to as a second scan unit 21b. Similarly, the pull-up node Q < N > in the first scan cell 21a may be referred to as a first pull-up node Q < N >, and the pull-up node Q < N > in the second scan cell 21b may be referred to as a second pull-up node Q < N +1>. The pull-down node QB _ a in the first scan cell 21a may be referred to as a first pull-down node QB _ a, and the pull-down node QB _ a in the second scan cell 21B may be referred to as a second pull-down node QB _ B. The leakage-preventing node OFF < N > in the first scanning unit 21a may be referred to as a first leakage-preventing node OFF < N >, and the leakage-preventing node OFF < N > in the second scanning unit 21b may be referred to as a second leakage-preventing node OFF < N +1>. The first clock signal CLKE _1 in the second scan cell 21b may be referred to as a fifth clock signal CLKE _2. The first output signal terminal Oput1< N > in the first scan unit 21a may be referred to as a first sub-output signal terminal Oput1< N >, and the first output signal terminal Oput1< N > in the second scan unit 21b may be referred to as a second sub-output signal terminal Oput1< N +1>.

Referring to fig. 8, the control circuit 3104 in the second scan unit 21B may be electrically connected to the seventh voltage signal terminal VDD _ B, replacing the sixth voltage signal terminal VDD _ a with the seventh voltage signal terminal VDD _ B. In the display phase of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD _ a and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD _ B are inverse signals. The structure and action of the first reset circuit 3105 in the first scan unit 21a in this example may be the same as those of the first reset circuit 3105 in the first scan unit 21a in some examples described above, and the structure and action of the first reset circuit 3105 in the second scan unit 21b in this example may be the same as those of the first reset circuit 3105 in the second scan unit 21b in some examples described above. The structure and function of the same circuit are not described in detail herein.

Specifically, the fourth reset circuit 3108 in the first scan cell 21a may also be electrically connected to the second pull-down node QB _ B. The fourth reset circuit 3108 is further configured to reset the shift signal terminal CR < N > and the first sub-output signal terminal Oput1< N > under the control of the voltage of the second pull-down node QB _ B. In a case where the voltage of the second pull-down node QB _ B is at a high level, the fourth reset circuit 3108 may be turned on by the voltage of the second pull-down node QB _ B, transfer the second voltage signal transferred from the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, pull-down reset the shift signal terminal CR < N >, transfer the third voltage signal transferred from the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1< N >, and pull-down reset the first sub-output signal terminal Oput1< N >. The fourth reset circuit 3108 in the first scan cell 21a may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30. A control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB _ B, a first electrode of the twenty-ninth transistor M29 is electrically connected to the shift signal terminal CR < N >, and a second electrode of the twenty-ninth transistor M29 is electrically connected to the second voltage signal terminal VGL 1. When the voltage of the second pull-down node QB _ B is at a high level, the twenty-ninth transistor M29 may be turned on by the voltage of the second pull-down node QB _ B, transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR < N >, and pull-down reset the shift signal terminal CR < N >. A control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB _ B, a first electrode of the thirtieth transistor M30 is electrically connected to the first sub output signal terminal Oput1< N >, and a second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL 2. In a case where the voltage of the second pull-down node QB _ B is at a high level, the thirtieth transistor M30 may be turned on by the voltage of the second pull-down node QB _ B, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1< N >, and pull-down reset the first sub-output signal terminal Oput1< N >.

For example, the fourth reset circuit 3108 in the second scan cell 21b may be further electrically connected to the first pull-down node QB _ a, and resets the second sub output signal terminal Oput1< N +1> under the control of the voltage of the first pull-down node QB _ a.

Specifically, in the case where the voltage of the first pull-down node QB _ a is at a high level, the fourth reset circuit 3108 may be turned on by the voltage of the first pull-down node QB _ a, transfer the third voltage signal transferred from the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1< N +1>, and perform pull-down reset on the second sub-output signal terminal Oput1< N +1>. The fourth reset circuit 3108 in the second scan unit 21b may further include: a thirtieth transistor M30. A control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB _ a, a first electrode of the thirtieth transistor M30 is electrically connected to the second sub output signal terminal Oput2< N +1>, and a second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL 2. When the voltage of the first pull-down node QB _ a is at a high level, the thirtieth transistor M30 may be turned on by the voltage of the first pull-down node QB _ a, transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1< N +1>, and perform pull-down reset on the second sub-output signal terminal Oput1< N +1>.

Next, the structure of the gate driver circuit will be further described by taking the structure of the shift register shown in the first example (as shown in fig. 6) as an example:

referring to fig. 7, the gate driving circuit may further include a plurality of control signal lines 33 extending in a second direction (perpendicular to the light shielding hole extending direction shown in fig. 1 and 3). The first-stage shift register is electrically connected to at least a part of the control signal lines 33, and supplies an output signal to the plurality of pixel circuits in a corresponding row under the control of at least a part of the control signal lines 33 connected thereto.

Specifically, referring to fig. 7, RS1, RS2, RS3 \8230: \8230, RS6 shown in the figure respectively represent a first-stage shift register, a second-stage shift register, a third-stage shift register \8230: \, a sixth-stage shift register, and are respectively and electrically connected with a pixel circuit of a first row of sub-pixels, a pixel circuit of a second row of sub-pixels, and a pixel circuit of a third row of sub-pixels \8230:, a pixel circuit of a sixth row of sub-pixels in the display panel.

The RS1, RS3, and RS5 may be electrically connected to the first gate signal terminal G1 in the corresponding row of pixel circuits through the first sub output signal terminal Oput1< N >, and electrically connected to the second gate signal terminal G2 in the corresponding row of pixel circuits through the second sub output signal terminal Oput2< N >, respectively. RS2, RS4, RS6 can be electrically connected to the first gate signal terminal G1 in the corresponding row of pixel circuits through the third sub output signal terminal Oput1< N +1>, and electrically connected to the second gate signal terminal G2 in the corresponding row of pixel circuits through the fourth sub output signal terminal Oput2< N +1>, respectively. In other words, RS1, RS3, and RS5 may be referred to as first scanning units 21a, and rs2, RS4, and RS6 may be referred to as second scanning units 21b, respectively.

In some examples, the plurality of control signal lines 33 may include a first clock signal line CLK _1, a second clock signal line CLK _2, and a third clock signal line CLK _3. The third clock signal terminal CLKD _1 of the first stage shift register is electrically connected to the first clock signal line CLK _1 for receiving the third clock signal. The third clock signal terminal CLKD _1 in the third stage of the shift register is electrically connected to the second clock signal line CLK _2 to receive the third clock signal. The third clock signal terminal CLKD _1 of the shift register of the fifth stage is electrically connected to the third clock signal line CLK _3 for receiving the third clock signal.

The plurality of control signal lines 33 may further include a fourth clock signal line CLK _4, a fifth clock signal line CLK _5, a sixth clock signal line CLK _6, a seventh clock signal line CLK _7, an eighth clock signal line CLK _8, a ninth clock signal line CLK _9, a tenth clock signal line CLK _10, an eleventh clock signal line CLK _11, a twelfth clock signal line CLK _12, a thirteenth clock signal line CLK _13, a fourteenth clock signal line CLK _14, and a fifteenth clock signal line CLK _15.

Specifically, the first clock signal terminal CLKE _1 of the first stage shift register is electrically connected to the fourth clock signal line CLK _4 for receiving the first clock signal, and the fourth clock signal terminal CLKF _1 is electrically connected to the fifth clock signal line CLK _5 for receiving the fourth clock signal. The fifth clock signal terminal CLKE _2 of the second stage shift register is electrically connected to the sixth clock signal line CLK _6 for receiving the fifth clock signal, and the sixth clock signal terminal CLKE _2 is electrically connected to the seventh clock signal line CLK _7 for receiving the sixth clock signal. The first clock signal terminal CLKE _1 of the third stage of the shift register is electrically connected to the eighth clock signal line CLK _8 for receiving the first clock signal, and the fourth clock signal terminal CLKF _1 is electrically connected to the ninth clock signal line CLK _9 for receiving the fourth clock signal. The fifth clock signal terminal CLKE _2 of the fourth stage shift register is electrically connected to the tenth clock signal line CLK _10 for receiving the fifth clock signal, and the sixth clock signal terminal CLKE _2 is electrically connected to the eleventh clock signal line CLK _11 for receiving the sixth clock signal. The first clock signal terminal CLKE _1 of the fifth stage shift register is electrically connected to the twelfth clock signal line CLK _12 for receiving the first clock signal, and the fourth clock signal terminal CLKF _1 is electrically connected to the thirteenth clock signal line CLK _13 for receiving the fourth clock signal. The fifth clock signal terminal CLKE _2 of the sixth stage shift register is electrically connected to the fourteenth clock signal line CLK _14 for receiving the fifth clock signal, and the sixth clock signal terminal CLKE _2 is electrically connected to the fifteenth clock signal line CLK _15 for receiving the sixth clock signal.

In other examples, the plurality of control signal lines 33 may further include a sixteenth clock signal line CLK _16. The global reset signal terminal TRST in each stage of the shift register is electrically connected to the sixteenth clock signal line CLK _16 to receive a global reset signal.

In other examples, the plurality of control signal lines 33 may further include a seventeenth clock signal line CLK _17 and an eighteenth clock signal line CLK _18. The selection control signal terminal OE of each blanking input circuit is electrically connected to the seventeenth clock signal line CLK _17 to receive the selection control signal. The second clock signal terminal CLKA of each blanking input unit is electrically connected to the eighteenth clock signal line CLK _18 to receive the second clock signal.

In some examples, the plurality of control signal lines 33 may further include a nineteenth clock signal line CLK _19 and a twentieth clock signal line CLK _20. The sixth voltage signal terminal VDD _ a in the first stage shift register, the sixth voltage signal terminal VDD _ a in the third stage shift register 21, and the sixth voltage signal terminal VDD _ a in the fifth stage shift register are electrically connected to the nineteenth clock signal line CLK _19 to receive the sixth voltage signal. The seventh voltage signal terminal VDD _ B in the second stage shift register, the seventh voltage signal terminal VDD _ B in the fourth stage shift register, and the seventh voltage signal terminal VDD _ B in the sixth stage shift register are electrically connected to the twentieth clock signal line CLK _20 to receive the seventh voltage signal.

In some examples, the plurality of control signal lines 33 may further include a twenty-first clock signal line CLK _21. The input signal terminal Iput of the first stage shift register and the input signal terminal Iput of the second stage shift register may be electrically connected to the twenty-first clock signal line CLK _21 to receive a start signal as an input signal.

The plurality of control signal lines 33 may further include a twenty-second clock signal line CLK _22. The display reset signal terminals STD of the last four stages of shift registers in the gate driving circuit may be all electrically connected to the twenty-second clock signal line CLK _22 to receive the display reset signal.

For example, in the gate driver circuit, in the shift registers of the other stages except the first and second stages, the shift signal terminal CR < N > of the nth stage shift register may be electrically connected to the input signal terminal Iput of the (N + 2) th and (N + 3) th shift registers, and the shift signal output from the shift signal terminal CR < N > of the nth stage shift register may be used as the input signal of the (N + 2) th and (N + 3) th shift registers. In the shift registers of the stages other than the last four stages, the display reset signal terminal STD of the shift register of the nth stage and the shift register of the (N + 1) th stage may be electrically connected to the shift signal terminal CR < N +4> of the shift register of the (N + 4) th stage 21, for example, and the shift signal output from the shift signal terminal CR < N +4> of the shift register of the (N + 4) th stage may be used as the display reset signal of the shift register of the nth stage and the shift register of the (N + 1) th stage.

It should be particularly noted that, in the present application, the terms "first pull-up node," second pull-up node, "first pull-down node," and "second pull-down node" do not mean actually existing components, but mean junctions of relevant electrical connections in the circuit diagram, that is, nodes equivalent to the junctions of relevant electrical connections in the circuit diagram. The term "pull-up" refers to charging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is raised, thereby enabling operation (e.g., conduction) of the corresponding transistor. The term "pull-down" means discharging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is lowered, thereby achieving operation (e.g., turning off) of the corresponding transistor.

In another aspect of the present application, a method of manufacturing the aforementioned display panel is provided. Referring to fig. 9, the method includes:

s100: forming a back panel circuit layer on a substrate, and forming a plurality of thin film transistors in the gate drive circuit region in the display panel

According to an example of the present application, an operation of forming a backplane circuit on a substrate may be performed in this step. The structures of the backplane circuit, the pixel circuit and the gate driving circuit have been described in detail above, and are not described herein again.

In general, this step may include a number of deposition materials and the operation of patterning processes to form structures that constitute transistors, capacitors, and signal lines.

S200: forming a plurality of light-emitting elements on one side of the backboard circuit layer far away from the substrate, and enabling the light-emitting elements to be positioned in the pixel area

According to an example of the present application, a plurality of light emitting elements are provided in this step. The plurality of light emitting elements may be OLEDs.

The method further comprises the operation of forming a light shielding hole and a metal layer, and filling the metal layer into the light shielding hole, wherein the light shielding hole and the orthographic projection position of the metal layer on the substrate are configured to shield the light of the light-emitting element from irradiating an active layer of the thin film transistor. Thus, the display panel can be obtained easily.

In some examples of the present application, taking the formation of the light shielding hole on the pixel defining structure as an example, the above-mentioned forming of the light shielding hole and the metal layer may include: forming a pixel defining structure between a plurality of the light emitting elements in advance before forming the light emitting elements, and forming the light blocking hole on the pixel defining structure; the metal layer is formed using a cathode metal when the light emitting element is formed. Thus, the light shielding hole and the metal layer can be formed easily.

Reference throughout this specification to the description of "one embodiment," "another embodiment," or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims

A display panel, a display region of the display panel including a plurality of pixel regions and a plurality of gate driving circuit regions, the gate driving circuit regions being located between two adjacent pixel regions, the display panel comprising:

a substrate;

the back plate circuit layer is positioned on the substrate, is arranged in the grid electrode driving circuit area and is provided with a plurality of thin film transistors;

a plurality of light-emitting elements, which are located on one side of the backplane circuit layer away from the substrate and in the area of the pixel region,

the display panel is provided with a light shielding hole, a metal layer is filled in the light shielding hole, and the position of the orthographic projection of the light shielding hole and the metal layer on the substrate is configured to shield light irradiating an active layer of the thin film transistor.
The display panel of claim 1, the light blocking holes and the metal layer being located on a side of the backplane circuit layer away from the substrate.
The display panel according to claim 2, the pixel region and the gate driver circuit region being adjacently disposed, the light emitting elements being located in the pixel region, and the adjacent light emitting elements having a pixel defining structure therebetween, the light shielding hole being formed on the pixel defining structure.
The display panel of claim 3, the metal layer comprising a cathodic metal.
The display panel according to claim 1, comprising a plurality of the light shielding holes, the light shielding holes being provided between each of the pixel regions and the thin film transistors in the gate driving circuit region.
The display panel defined in claim 1, the thin film transistors within the gate drive circuitry area comprising:

an active layer;

the grid electrode and the grid insulating layer are positioned on one side, far away from the substrate, of the active layer;

a source drain electrode, which is positioned on one side of the active layer far from the substrate, an interlayer dielectric layer is arranged between the source drain electrode and the grid electrode, and the source drain electrode is connected with the active layer through a through hole penetrating through the interlayer dielectric layer,

and no overlapping area exists between the orthographic projection of the shading hole on the substrate and the orthographic projection of the through hole of the interlayer dielectric layer on the substrate.
The display panel according to any one of claims 1 to 6, the pixel region further comprising a pixel light emitting sub-region and a pixel circuit sub-region, the light emitting element being located in the pixel light emitting region, the pixel light emitting sub-region and the pixel circuit sub-region being arranged in a first direction, and the light shielding hole extending in the first direction.
The display panel of claim 7, two of the light shielding holes being between two adjacent pixel regions, the gate driving circuit comprising a transistor group, a length of the light shielding hole along the first direction being equal to a length of the transistor group, and a plurality of thin film transistors in the transistor group being arranged between two of the light shielding holes along the first direction.
The display panel according to any one of claims 1 to 6, wherein the pixel regions are arranged in an array on the substrate, each pixel region includes at least two sub-pixels, each row of the pixel regions corresponds to at least two gate driving circuit regions, each gate driving circuit region is located between two adjacent pixel regions, the gate driving circuit includes a plurality of cascaded shift registers, and each shift register is electrically connected to one row of the sub-pixels; each of the shift registers includes a plurality of transistor groups, each of the transistor groups including at least one of the thin film transistors.
The display panel of any one of claims 1-6, the light-shielding holes having a depth of 1-3 microns and a width of 3-10 microns.
A method of making the display panel of any one of claims 1-10, comprising:

forming a back panel circuit layer on a substrate, and forming a plurality of thin film transistors in the gate driving circuit region in the display panel;

forming a plurality of light-emitting elements on one side of the backboard circuit layer far away from the substrate, and enabling the light-emitting elements to be located in the pixel area;

and the method comprises the operation of forming a light shielding hole and a metal layer, and filling the metal layer into the light shielding hole, wherein the light shielding hole and the orthographic projection position of the metal layer on the substrate are configured to shield the light of the light-emitting element from irradiating an active layer of the thin film transistor.
The method of claim 11, forming the light shielding holes and the metal layer comprising:

forming a pixel defining structure between a plurality of the light emitting elements in advance before forming the light emitting elements, and forming the light shielding hole on the pixel defining structure;

the metal layer is formed using a cathode metal when the light emitting element is formed.
A display device characterized by comprising the display panel according to any one of claims 1 to 10.