CN115424655A

CN115424655A - ZQ calibration method, memory and storage system

Info

Publication number: CN115424655A
Application number: CN202210975341.5A
Authority: CN
Inventors: 魏德波; 张黄鹏; 张思敏; 何旺
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-08-15
Filing date: 2022-08-15
Publication date: 2022-12-02

Abstract

The embodiment of the invention provides a ZQ calibration method, a memory and a storage system. Wherein the method comprises the following steps: obtaining a maximum cycle number configured for short ZQ calibration; the maximum number of cycles is used to indicate a calibration range for the short ZQ calibration; and after receiving a short ZQ calibration command, performing the short ZQ calibration on the interface impedance of the memory until the cycle number of the calibration is up to the maximum cycle number and/or the calibration result meets the requirement.

Description

ZQ calibration method, memory and storage system

Technical Field

The invention relates to the technical field of memories, in particular to a ZQ calibration method, a memory and a storage system.

Background

Semiconductor memories, which currently include integrated circuits such as microprocessors, memory circuits, and gate array circuits, are used in various electronic devices, such as personal computers, server computers, and workstations. As the operating speed of electronic devices increases, impedance mismatches at the interface end of memory in the electronic devices make it difficult for the electronic devices to transfer data at high speeds. Therefore, ZQ calibration is introduced in the memory to calibrate the impedance of the memory interface terminal, thereby ensuring high-speed transmission of data. However, the currently used ZQ calibration method cannot meet the calibration requirement.

Disclosure of Invention

In view of the above, the present invention provides a ZQ calibration method, a memory and a storage system. For short ZQ calibration, the impedance of the memory is calibrated within the maximum calibration cycle configured by a user until the cycle of executing calibration reaches the maximum cycle and/or the calibration result meets the requirement, so that the calibration range of the short ZQ calibration can be flexibly set, and errors in the long ZQ calibration can be corrected under the condition that the set maximum calibration cycle is proper.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a ZQ calibration method, where the method includes:

obtaining a maximum cycle number configured for short ZQ calibration; the maximum number of cycles is used to indicate a calibration range for the short ZQ calibration;

after receiving a short ZQ calibration command, performing the short ZQ calibration on the interface impedance of the memory until the cycle number of the calibration is up to the maximum cycle number and/or the calibration result meets the requirement.

In the above solution, when the memory supports an open NAND flash interface ONFI protocol, the maximum cycle number is Set in the memory by a memory controller coupled to the memory based on a Set Feature command in the ONFI protocol.

In the foregoing aspect, when the maximum cycle number includes a plurality of numbers, the obtaining the maximum cycle number configured for short ZQ calibration includes:

determining the degree of change of the current working environment;

acquiring the maximum cycle number configured for short ZQ calibration based on the current working environment change degree and the mapping relation;

wherein the degree of the change of the working environment is measured by the change of the environmental temperature and/or the change of the output voltage of the memory; and the mapping relation is used for reflecting the corresponding relation between the working environment change degree and the maximum cycle number.

In the above solution, the method further comprises:

when the number of cycles for performing calibration reaches the maximum number of cycles and the calibration result does not meet requirements, feeding back a first identifier indicating calibration failure to a memory controller coupled to the memory.

In the above aspect, the method further includes:

when the next calibration period is reached, receiving a long ZQ calibration command sent by the memory controller after the first identifier is received; performing a long ZQ calibration on an interface impedance of the memory upon receiving the long ZQ calibration command;

wherein the calibration period is a time interval between two adjacent memory controllers sending the short ZQ calibration command to the memory.

In the above aspect, the method further includes: after the calibration result meets the requirement, feeding back a second identifier for indicating successful calibration to a memory controller coupled with the memory; wherein the second identification is to cause the memory controller to increase a calibration period over which the short ZQ calibration command is to be sent.

In the above solution, after performing long ZQ calibration on the interface impedance of the memory, the method further includes: continuing to perform the short ZQ calibration of the interface impedance of the memory according to the calibration period.

In a second aspect, an embodiment of the present invention provides a memory, including: a storage array for storing data; and peripheral circuitry coupled to and for controlling the memory array; wherein,

the peripheral circuitry is configured to: obtaining a maximum cycle number configured for short ZQ calibration; the maximum number of cycles is used to indicate a calibration range for the short ZQ calibration; and after receiving a short ZQ calibration command, performing the short ZQ calibration on the interface impedance of the memory until the cycle number of the calibration is up to the maximum cycle number and/or the calibration result meets the requirement.

In the above aspect, the peripheral circuit includes: a control logic unit and a ZQ calibration unit, wherein;

the control logic unit configured to: obtaining a maximum cycle number configured for short ZQ calibration; after receiving a short ZQ calibration command, controlling the ZQ calibration unit to perform the short ZQ calibration on the interface impedance of the memory until the cycle number of the calibration is up to the maximum cycle number and/or the calibration result meets the requirement.

In the above aspect, the peripheral circuit further includes: a register configured to hold a first flag and/or a second flag, wherein the first flag is to feed back an flag indicating that calibration has failed to a memory controller coupled to the memory when the number of cycles for performing calibration reaches the maximum number of cycles and the calibration result does not meet a requirement; the second identifier is an identifier which is used for indicating that the calibration is successful and is fed back to a memory controller coupled with the memory after the calibration result meets the requirement.

In the scheme, the memory is a double data rate dynamic random access memory DDR DRAM.

In a third aspect, an embodiment of the present invention further provides a storage system, including: one or more of the above-described memories; and a memory controller coupled to the memory; the memory controller to: sending a short ZQ calibration command or a long ZQ calibration command to the memory.

In the above scheme, the storage system is a solid state disk or a memory card.

The embodiment of the invention provides a ZQ calibration method, a memory and a storage system. Wherein the method comprises the following steps: obtaining a maximum cycle number configured for short ZQ calibration; the maximum number of cycles is used to indicate a calibration range for the short ZQ calibration; and after receiving a short ZQ calibration command, performing the short ZQ calibration on the interface impedance of the memory until the cycle number of the calibration is up to the maximum cycle number and/or the calibration result meets the requirement. The ZQ calibration method provided by the embodiment of the invention has the advantages that the calibration cycle number configured by a user is utilized to flexibly set the calibration range of the short ZQ calibration so as to accurately calibrate the interface impedance of the memory, and the error of the interface impedance of the memory caused by the long ZQ calibration can be corrected under the condition that the set maximum calibration cycle number is proper, and the like.

Drawings

Aspects of the present invention are best understood from the following detailed description of the embodiments when read in connection with the accompanying drawings. Note that in accordance with standard practice in the industry various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a block diagram of an exemplary system having a memory in the related art;

FIG. 2 illustrates a schematic diagram of an exemplary memory card having a memory;

FIG. 3 shows a schematic diagram of an exemplary Solid State Disk (SSD) with memory;

FIG. 4 shows a schematic diagram of an exemplary memory containing peripheral circuitry;

FIG. 5 shows a side view in cross section of an exemplary memory array containing NAND memory strings;

FIG. 6 illustrates a block diagram of an exemplary memory including a memory array and peripheral circuitry;

FIG. 7 shows a block diagram of a ZQ calibration circuit in the related art;

FIG. 8 is a schematic diagram showing a structure of a pull-up resistor network in the related art;

fig. 9 shows a structural schematic of a pull-up resistor in the related art;

FIG. 10 is a schematic diagram showing a structure of a pull-down resistor net in the related art;

fig. 11 shows a structural schematic of a pull-down resistor in the related art;

FIG. 12 is a flow chart showing ZQ calibration in the related art;

fig. 13 is a schematic diagram illustrating a specific implementation flow of a long ZQ calibration or a short ZQ calibration in the related art;

FIG. 14 is a flow chart illustrating a ZQ calibration method according to an embodiment of the present invention;

FIG. 15 is a diagram illustrating a comparison of a prior ZQ calibration scheme provided by an embodiment of the present invention and a ZQ calibration scheme provided by an embodiment of the present invention

FIG. 16 is a flowchart illustrating the operation of ZQ calibration according to an embodiment of the present invention;

fig. 17 is a diagram illustrating an example of the maximum number of cycles of the configuration provided by the embodiment of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference data and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "under 8230%", "under 8230" "," under 8230 "," under "and" under "in 8230" "," over 8230 "", "upper" and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In Double Data Rate Dynamic Random Access Memory (DDR DRAM) technology, ZQ calibration commands are used to periodically calibrate DRAM input/output interface impedance. In particular, the memory controller may typically issue short ZQ calibration commands (corresponding to short ZQ calibration) or long ZQ calibration commands (corresponding to long ZQ calibration) to compensate for any system Voltage and Temperature (VT) variations in input/output (I/O) drivers associated with the DRAM, where long ZQ calibration commands are typically used during DRAM power-up initialization and during reset conditions; short ZQ calibration commands tend to be used to track small changes in voltage and temperature during normal operation, and periodically calibrate the DRAM at idle to maintain linear output driver and interface impedance over the entire voltage and temperature range. Typically, a short ZQ calibration command takes 128 DRAM clock cycles to complete, while a long ZQ calibration command takes longer to complete, e.g., 512 DRAM clock cycles, but it can compensate for larger voltage and temperature deviations relative to the ZQ calibration performed by a short ZQ calibration command. However, the currently used long ZQ calibration cannot acquire an accurate adjustment control signal, and cannot accurately calibrate the interface impedance of the DRAM; the short ZQ calibration sets a default adjustment range, and the calibration range is limited and cannot adapt to the calibration of the interface impedance of the DRAM under the severe environmental change.

In order to solve the foregoing technical problem, an embodiment of the present invention provides a ZQ calibration method, where for short ZQ calibration, the impedance of a memory is calibrated within a maximum calibration cycle configured by a user until the calibration cycle reaches the maximum cycle and/or a calibration result meets a requirement, so that not only a calibration range of the short ZQ calibration can be flexibly set, but also an error occurring in the long ZQ calibration can be corrected when the set maximum calibration cycle is appropriate.

The specific technical solution is described in detail below with reference to the accompanying drawings.

Fig. 1 shows a block diagram of an exemplary system having a memory in the related art. In fig. 1, the system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having memory therein. As shown in fig. 1, the system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a Processor of an electronic device, such as a Central Processing Unit (CPU) or a System on Chip (SoC), wherein the SoC may be an Application Processor (AP), for example. Host 108 may be configured to send data to memory 104 or receive data from memory 104. In particular, the memory 104 may be any of the memories disclosed in the present invention. Such as Phase Change Random Access Memory (PCRAM), three-dimensional NAND flash Memory, and the like.

According to some embodiments, memory controller 106 is coupled to memory 104 and host 108. And is configured to control the memory 104. Memory controller 106 may manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed for operation in low duty cycle environments, such as Secure Digital (SD) cards, compact Flash (CF) cards, universal Serial Bus (USB) Flash drives, or other media for use in electronic devices in low duty cycle environments, such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia Card (eMMC), where the SSD or eMMC serves as a data storage and enterprise storage array for mobile devices in a high duty cycle environment, such as smart phones, tablet computers, laptop computers, and the like. The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller 106 is also configured to process Error Correction Codes (ECCs) with respect to data read from the memory 104 or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device via at least one of various Interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (Integrated Drive Electronics) protocol, a Firewire protocol, and so forth.

The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 2, the memory controller 106 and the single memory 104 may be integrated into the memory card 202. The memory card may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card may also include a memory card connector 204 that couples the memory card with a host (e.g., host 108 in FIG. 1). In another example as shown in fig. 3, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 302. The SSD may also include SSD connector 304 that couples the SSD with a host (e.g., host 108 in fig. 1). In some embodiments, the storage capacity and/or operating speed of the SSD is greater than the storage capacity and/or operating speed of the memory card. In addition, the memory controller 106 may also be configured to control erase, read, and write operations of the memory 104.

Fig. 4 shows a schematic diagram of an exemplary memory containing peripheral circuitry. As shown in fig. 4, the memory 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401, wherein the memory array 401 may be a NAND flash memory array, wherein the memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes multiple memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the storage region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory Cell 406 is a Single Level Cell (SLC) having two possible memory states and therefore can store one bit of data, e.g., a first memory state "0" may correspond to a first voltage range and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory Cell 406 is a Multi-Level Cell (MLC) capable of storing data for a single bit in a plurality of four memory states, e.g., an MLC may store two bits per Cell, three bits per Cell (also referred to as a triple Level Cell), or four bits per Cell (also referred to as a quad Level Cell).

As shown in fig. 4, each NAND memory string 408 may include a Source Select Gate (SSG) 410 at its source end and a Drain Select Gate (DSG) 412 at its drain end. The

SSGs

410 and 412 may be configured to activate selected NAND memory strings 408 (columns of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same block 404 are coupled by the same Source Line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 408 in the same block 404 have an Array Common Source (ACS). According to some embodiments, the DSG412 of each NAND memory string 408 is coupled to a respective bit line 416, from which data can be read and written to via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the DSG 412) or a deselect voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and/or applying a select voltage (e.g., above the threshold voltage of the transistor having the SSG 410) or a deselect voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

As shown in FIG. 4, the NAND memory strings 408 may be organized into a plurality of blocks 404, each of the plurality of blocks 404 may have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is of the basic unit of data having an erase operation, i.e., all memory cells 406 on the same block 404 are erased at the same time. To erase memory cells 406 in a selected block 404, a source line 414 coupled to the selected block 404 and unselected blocks 404 in the same Plane (Plane) as the selected block 404 may be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or more). It should be appreciated that in some examples, erase operations may be performed at a half block level, at a quarter block level, or at any suitable fraction of any suitable number of blocks or blocks. The memory cells 406 of adjacent NAND memory strings 408 can be coupled by a wordline 418, the wordline 418 selecting which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same wordline 418 are referred to as a page 420. The page 420 is the basic unit of data for a program operation or a read operation, and the size of a page 420 in bits may be related to the number of NAND memory strings 408 coupled by a word line 418 in one block 404. Each wordline 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a respective page 420 and a gate line coupling the control gates.

FIG. 5 shows a side view of a cross section of an exemplary memory array containing NAND memory strings. As shown in fig. 5, NAND memory strings 408 may extend vertically through memory stack layer 504 above substrate 502. Substrate 502 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

Memory stack layer 504 may include alternating gate conductive layers 506 and gate-to-gate dielectric layers 508. The number of pairs of gate conductive layers 506 and gate-to-gate dielectric layers 508 in the memory stack layer 504 may determine the number of memory cells 406 in the memory array 401. The gate conductive layer 506 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 506 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 506 comprises a doped polysilicon layer. Each gate conductive layer 506 may include a control gate surrounding a memory cell 406 and may extend laterally at the top of the memory stack layer 504 as a DSG line 413, laterally at the bottom of the memory stack layer 504 as an SSG line 415, or laterally between the DSG line 413 and the SSG line 415 as a word line 418.

As shown in FIG. 5, the NAND memory string 408 includes a channel structure 512 that extends vertically through the memory stack layers 504. In some implementations, the channel structure 512 includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel 520) and dielectric material(s) (e.g., as a memory film 518). In some embodiments, the semiconductor channel 520 comprises silicon, e.g., polysilicon. In some embodiments, the memory film 518 is a composite dielectric layer that includes a tunneling layer 526, a storage layer 524 (also referred to as a "charge trapping/storage layer"), and a blocking layer 522. The channel structure 512 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 520, the tunneling layer 526, the storage layer 524, and the barrier layer 522 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 526 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 524 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 522 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, memory film 518 may comprise a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

According to some embodiments, as shown in fig. 5, a well 514 (e.g., a P-well and/or an N-well) is formed in the substrate 502 and the source terminal of the NAND memory string 408 is in contact with the well 514. For example, a source line 414 may be coupled to the well 514 to apply an erase voltage to the well 514 (i.e., the source of the NAND memory string 408) during an erase operation. In some implementations, the NAND memory string 408 also includes a channel plug 516 at the drain end of the NAND memory string 408. It should be understood that although not shown in fig. 5, additional features of the memory array 401 may be formed, including, but not limited to, gate line apertures/source contacts, local contacts, interconnect layers, and the like. It should be noted that fig. 5 is only an exemplary structure. The ZQ calibration method provided by the embodiment of the invention is suitable for memories with any structures.

Referring back to FIG. 4, the peripheral circuitry 402 may be coupled to the memory array 401 by bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuitry 402 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory array 401 by applying and sensing voltage and/or current signals to and from each target memory cell 406 via the bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. The peripheral circuitry 402 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 6 illustrates some exemplary peripheral circuits, with peripheral circuit 402 including page buffers/sense amplifiers 604, column decoders/bit line drivers 606, row decoders/word line drivers 608, voltage generators 610, control logic 612, registers 614, interfaces 616, and a data bus 618. It should be understood that in some examples, additional peripheral circuitry not shown in fig. 6 may also be included.

The page buffer/sense amplifier 604 may be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to control signals from the control logic unit 612. In one example, the page buffer/sense amplifier 604 may store a page of program data (write data) to be programmed into one page 420 of the memory array 401. In another example, the page buffer/sense amplifier 604 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 406 coupled to the selected word line 418. In yet another example, page buffer/sense amplifier 604 may also sense low power signals from bit line 416 that represent data bits stored in memory cells 406 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder/bit line driver 606 may be configured to be controlled by the control logic unit 612 and select one or more NAND memory strings 408 by applying the bit line voltages generated from the voltage generator 610.

The row decoder/word line drivers 608 may be configured to be controlled by the control logic unit 612 and to select/deselect the blocks 404 of the memory array 401 and to select/deselect the word lines 418 of the blocks 404. The row decoder/word line driver 608 may also be configured to drive the word line 418 using a word line voltage generated from a voltage generator 610. In some embodiments, the row decoder/word line driver 608 may also select/deselect and drive the SSG lines 415 and DSG lines 413. As described in detail below, the row decoder/wordline driver 608 is configured to perform an erase operation on the memory cells 406 coupled to the selected wordline(s) 418. The voltage generator 610 may be configured to be controlled by a control logic unit 612 and to generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 401.

The control logic unit 612 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The registers 614 may be coupled to the control logic unit 612 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 616 may be coupled to the control logic 612 and act as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic 612 and to buffer and relay status information received from the control logic 612 to the host. The interface 616 may also be coupled to a column decoder/bit line driver 606 via a data bus 618, and act as a data I/O interface and data buffer to buffer data and relay it to the memory array 401 or to relay or buffer data from the memory array 401.

With the aforementioned memory, as the operating speed of the electronic device in which the memory is located increases, the swing width (swing width) of the transmission signal between the memories in the electronic device decreases to minimize the delay time taken to transmit the signal. However, as the swing width decreases, signal transmission is affected by external noise to a greater extent, and signal reflection at the interface end increases due to impedance mismatch. This impedance mismatch is caused by variations in the manufacturing process, supply voltage, and operating temperature (PVT) of the memory. This impedance mismatch may distort a signal output from the memory, and may cause a set up/hold failure (false determination of a signal level) or the like in another memory of the interface distortion signal, thus making it difficult to transfer data at high speed. In general, a peripheral circuit of a memory may include an input circuit for receiving an external signal through an input PAD (PAD) and an output circuit for outputting an internal signal through the PAD, and particularly, a high-speed operation memory may include an impedance matching circuit for matching an interface impedance with another memory near the PAD in such a manner as to fail. However, these impedances vary with environmental changes, and therefore, in order to reduce the discontinuity of these impedances, it is necessary to introduce a calibration of the impedances, i.e., a ZQ calibration.

As shown in fig. 7, a schematic block diagram of a ZQ calibration circuit in the related art is shown. In fig. 7, the calibration circuit 70 includes: a ZQ calibration control unit 701, a pull-up resistor network 702, a pull-down resistor network 703, a reference voltage generator 704, a pull-up comparator 705, a pull-down comparator 706, a P-code counter 707 and an N-code counter 708, wherein the pull-up resistor network comprises a plurality of parallel pull-up resistors as shown in FIG. 8; each pull-up resistor, as shown in FIG. 9, includes a plurality of MOS transistors coupled in parallel. Similarly, the pull-down resistor network is shown in fig. 10 and includes a plurality of parallel pull-down resistors; each pull-down resistor, as shown in FIG. 11, includes a plurality of MOS transistors coupled in parallel. It should be noted that ZQ calibration includes calibrating a pull-up resistor in each pull-up resistor network and calibrating a pull-down resistor in each pull-down resistor network.

For calibration of a particular pull-up resistor, supply voltage VDDQ is divided by a pull-up resistor network and a reference resistor to provide a voltage to node ZQ. The reference resistor coupled to node ZQ typically has 240 ohms. The pull-up comparator table node compares the voltage at node ZQ with a reference voltage VREF output from a reference voltage generator, thereby generating a pull-up adjustment signal. The reference voltage VREF is typically set to one-half the supply voltage, i.e., VDDQ/2. The P-code comparator receives the pull-up adjustment signal, thereby generating a binary code PCODE <0 >. The binary code PCODE <0 > N > turns on/off MOS transistors coupled in parallel in a pull-up resistor network, so as to calibrate the pull-up resistor, and the calibrated pull-up resistor value has influence on the voltage at the node ZQ. The above operation is repeated so that the resistance value of the pull-up resistance is equal to the resistance value of the reference resistor 709. During this pull-up resistor calibration, the generated binary code PCODE <0 > is also input to and determines the resistance values of other pull-up resistors in the pull-up resistor network.

For pull-down calibration, similar to pull-up calibration, a binary code NCODE <0 is generated by a pull-down comparator and an N-code counter: n >, the voltage at node ZQ' becomes equal to the reference voltage VREF so that the pull-down resistor in the pull-down resistor grid is equal to the pull-up resistor in the pull-up resistor grid.

It should be noted that the ZQ calibration includes calibrating a pull-up resistor in each pull-up resistor network and/or calibrating a pull-down resistor in each pull-down resistor network. For example, the output driver included in the memory uses a pull-up resistor network and a pull-down resistor network, and the ZQ calibration includes calibration of a pull-up resistor in the pull-up resistor network and calibration of a pull-down resistor in the pull-down resistor network; for another example, the memory includes an input buffer that uses only a pull-up resistor network, and thus its ZQ calibration includes only calibration of the pull-up resistor in the pull-up resistor network.

A ZQ calibration control unit in a ZQ calibration circuit receives a short ZQ calibration command ZQCS, and generates a calibration start signal based on the ZQCS, thereby performing ZQ calibration.

Described above in fig. 7 to 11 are schematic diagrams of the ZQ calibration circuit. Based on the above-described ZQ calibration circuit, see fig. 12, which shows a schematic diagram of a ZQ calibration flow in the related art. In the related art, the ZQ calibration includes two parts: the method comprises the steps of long ZQ calibration and short ZQ calibration, wherein after the memory is initialized or reset, the long ZQ calibration is carried out, and an interface impedance with a fixed initial value is configured for the memory; then, on this basis, periodic short ZQ calibration is performed to calibrate for changes in interface impedance due to adaptation to environmental changes. In summary, the long ZQ calibration and the short ZQ calibration work together to obtain accurate calibration resistance values for the memory.

The foregoing fig. 7 to 11 describe the principle of the ZQ calibration circuit, and the specific implementation flow thereof is shown in fig. 13. The procedure may generally include three phases, whether long or short ZQ calibration.

A first phase, a preparation phase (or referred to as ZQ Dummy Cycle), in which a calibration algorithm is prepared for use, for example, when a long ZQ calibration is required, a calibration algorithm adapted to the long ZQ calibration must be prepared; for another example, in short ZQ calibration, a calibration algorithm adapted to the short ZQ calibration must be prepared.

In the second phase, the Calibration phase (or referred to as ZQ Calibration Cycle), i.e. the Calibration circuit depicted in fig. 7 to 11 is used to calibrate the interface impedance of the memory by using the aforementioned Calibration algorithm.

The third phase, the verification phase (alternatively referred to as Out of Boundary Check Cycle), is the phase in which, after the calibration phase is over, the obtained result needs to be verified to confirm whether the result exceeds the upper limit or the lower limit. If so, an indication of ZQ calibration failure may need to be fed back to the memory controller or host.

Based on the foregoing description of the ZQ calibration principle, since in the related art, the binary code PCODE <0 > or the binary code NCODE <0: and N > controls the on or off of a MOS transistor contained in the pull-up resistor or the pull-down resistor so as to calibrate the resistance value of the pull-up resistor or the pull-down resistor. It was found that for long ZQ calibration, for binary code PCODE <0 > or binary code NCODE <0: the adjustment of N > is performed from high order to low order, one order, and one order, in this case, once the high order has an error, the resistance value of the obtained pull-up resistor or pull-down resistor will be far away from the correct value, which finally results in the failure of the whole ZQ calibration, and the calibration needs to be performed again. For example, assuming that the binary code PCODE <0 > is 5 bits of PCODE <0 > which comprises 5 bits, one bit is calibrated for each comparison, and the calibration is performed from the most significant bit, if the most significant bit is wrong, the resistance value of the pull-up resistor or the pull-down resistor obtained by PCODE <0 >. For short ZQ calibration, after long ZQ calibration, small-amplitude calibration is performed on the basis of long ZQ calibration, a default adjustment range is set, the calibration range is limited, and the calibration cannot adapt to calibration of interface impedance of a DRAM under severe environmental change.

Based on this, an embodiment of the present invention provides a ZQ calibration method, and specifically, refer to fig. 14, which shows a schematic flow chart of the ZQ calibration method provided in the embodiment of the present invention. The method is applied to the memory and specifically comprises the following steps:

s1401: obtaining a maximum cycle number configured for short ZQ calibration; the maximum number of cycles is used to indicate a calibration range for the short ZQ calibration;

s1402: and after receiving a short ZQ calibration command, performing the short ZQ calibration on the interface impedance of the memory until the cycle number of the calibration is up to the maximum cycle number and/or the calibration result meets the requirement.

It should be noted that, since the long ZQ calibration takes a relatively long time, the long ZQ calibration is only used after the memory is initialized or reset, the short ZQ calibration is used most of the time, and the calibration range of the long ZQ calibration is relatively large, the maximum cycle number of the configuration provided by the embodiment of the present invention is calibrated for the short ZQ. This maximum number of cycles is used to indicate the calibration range for the short ZQ calibration. Here, the maximum number of cycles is the maximum number of times of calibration by the calibration circuit of fig. 7 to 11 in one short ZQ calibration command, which also reflects the calibration range of the interface impedance of the memory by the calibration circuit of fig. 7 to 11 in one short ZQ calibration command. The maximum number of cycles may be greater than a default number of cycles stored in the memory.

In some embodiments, when the memory supports an Open NAND Flash Interface (ONFI) protocol, the maximum number of cycles is Set in the memory by a memory controller coupled to the memory based on a Set Feature command in the ONFI protocol.

It should be noted that in the ONFI protocol, the Set Feature function is used to Set some special features of the memory, for example, the function may enable a power-on disabled function. In the memory, a setting space of the Set Feature function is specially opened, and parameters related to a certain function are Set and can be placed in the space for the memory to use. The maximum cycle number required by the embodiment of the invention, namely the maximum cycle number, is placed in the spaces for the memory to be used.

Specifically, one or more bits for indicating the maximum number of cycles are first defined in the memory for the free address specified for the Set Feature function; then, the memory controller writes the configured maximum number of cycles into the aforementioned one-bit or multi-bit free address in the memory by the Set Feature command. Then, when the short ZQ calibration is needed, the memory may obtain the stored maximum number of cycles to turn on the short ZQ calibration based on the short ZQ calibration command to obtain a calibration result that meets the requirements and/or until the number of cycles to perform the calibration reaches the maximum number of cycles.

In some embodiments, when the maximum number of cycles may include a plurality, the obtaining the maximum number of cycles configured for short ZQ calibration may include:

determining the degree of change of the current working environment;

It should be noted that, for flexibility of use, when the maximum number of cycles is set, a plurality of cycles may be set according to the degree of change of the operating environment. And then selecting a proper maximum cycle number according to the actually measured change degree of the working environment so as to obtain a more reasonable calibration range and obtain an accurate impedance calibration value. Here, the degree of change in the operating environment is positively correlated with a change in the ambient temperature and/or a change in the output voltage of the memory. That is, the greater the change in the ambient temperature and/or the change in the output voltage of the memory, the greater the degree of change in the operating environment. How to quantize specifically is set according to specific situations, and details are not described here.

In an optional embodiment, the mapping relationship may be a corresponding relationship between the change degree of the working environment and the maximum cycle count in a preset range, in other words, one change degree of the working environment corresponds to the maximum cycle count in a preset range, for example, assuming that the change degree of the working environment is 1, the corresponding range of the maximum cycle count is 1 to 3, and as for the attribute of the maximum cycle count, the value of the maximum cycle count may be any one of 1, 2, and 3. The specific final selection of which to use depends on the user's setting, for example, the user sets a plurality of maximum cycle times as follows: 2. 5, 8, 10, etc. After the preset range of the maximum cycle number is acquired to be 1-3, matching is performed with 2, 5, 8, 10 and the like Set by the user through the Set Feature function, and the maximum cycle number can be selected to be 2. And (5) obtaining the appropriate maximum cycle times by analogy with the change degrees of other working environments.

After the maximum cycle number is obtained, after a short ZQ calibration command is received, the interface impedance of the memory starts to be calibrated until the calibration cycle number reaches the maximum cycle number and/or a calibration result meets requirements.

Here, the requirement for the calibration result may mean that the impedance obtained after calibration meets the requirement, for example, the resistance value of the pull-up resistor is equal to the resistance value of the reference resistor; the resistance value of the pull-down resistor is equal to that of the pull-up resistor, which is a condition that the calibration result meets the requirement. The short ZQ calibration performed here is divided into three cases: one is that after the number of calibration cycles reaches the maximum number of calibration cycles, the calibration is stopped; one is that after the calibration result meets the requirement, the calibration is stopped; the other is that the calibration result meets the requirement just when the number of calibration cycles reaches the maximum number of cycles, and at this time, the calibration needs to be stopped again.

In some embodiments, the method may further comprise:

when the number of cycles of performing calibration reaches the maximum number of cycles and the calibration result does not meet requirements, feeding back a first identifier indicating calibration failure to a memory controller coupled to the memory.

It is described that a first flag indicating a failed calibration needs to be fed back to a memory controller coupled to the memory until the number of cycles for performing the calibration reaches the maximum number of cycles, and the calibration result does not satisfy the requirement.

In some embodiments, the method further comprises:

It should be noted that, as described above, the short ZQ calibration is performed periodically, where the calibration period is the time interval between two adjacent short ZQ calibrations. It is described that after the short ZQ calibration, when the next calibration period is reached, the memory controller receives the first flag, and it is obviously inappropriate to adopt the short ZQ calibration again, and at this time, the memory controller sends a long ZQ calibration command to make the memory long ZQ calibration command perform the long ZQ calibration to make a calibration of a larger range.

In some embodiments, the method further comprises: after the calibration result meets the requirement, feeding back a second identifier for indicating successful calibration to a memory controller coupled with the memory; wherein the second identification is to cause the memory controller to increase a calibration period over which the short ZQ calibration command is to be sent.

It should be noted that, when the calibration is successful, the memory feeds back the second identifier. This second flag may be used not only to indicate the success of this calibration, but also to trigger the memory control to adjust the time interval over which the short ZQ calibration command is sent, which will typically be increased. Since the short ZQ calibration is executed using the configured maximum cycle number, the calibration range is large, the difference between the interface impedance value obtained based on the calibration result and the target impedance value (the resistance value of the reference resistor) is small, and the time that can satisfy high-speed data transmission is long, so that the cycle of the short ZQ calibration can be increased, that is, the transmission time interval of two adjacent short ZQ calibration commands is increased.

Here, the first and second identifications are stored in registers. The registers may be general purpose registers.

In some embodiments, after performing a long ZQ calibration of an interface impedance of the memory, the method further comprises: continuing to perform the short ZQ calibration of the interface impedance of the memory according to the calibration period.

For an understanding of the present invention, referring to fig. 15 and 16, fig. 15 shows a comparison of a prior ZQ calibration scheme provided by an embodiment of the present invention with a ZQ calibration scheme provided by an embodiment of the present invention; fig. 16 is a schematic diagram illustrating an implementation flow of the ZQ calibration scheme provided in the embodiment of the present invention.

In fig. 15, in the prior art, the maximum number of cycles used for short ZQ calibration is the default, and the corresponding calibration range is usually smaller. In the scheme of the invention, the maximum cycle number adopted by the short ZQ calibration is user-configurable, and the maximum cycle number can be flexibly configured according to the design requirement.

In fig. 16, an implementation procedure of the ZQ calibration scheme provided in the embodiment of the present invention may include: configuring the maximum cycle number of short ZQ calibration through a Set Feature command of an ONFI protocol; the ZQ calibration control unit receives the short ZQ calibration command and obtains the configured maximum cycle number, then carries out short ZQ calibration based on the short ZQ calibration command and the maximum cycle number, and finally obtains a calibration result.

Compared with the prior art, the ZQ calibration method provided by the embodiment of the invention has the advantages that the maximum cycle number of the short ZQ calibration can be flexibly configured, a wider adjustment range can be obtained, and the calibration time can be saved, and particularly, referring to fig. 17, when the target calibration result falls between the calibration range of the long ZQ calibration and the calibration range of the short ZQ calibration, the time consumption is relatively long due to the adoption of the long ZQ calibration, but the calibration range is insufficient due to the adoption of the short ZQ calibration in the prior art, and the accurate calibration result cannot be obtained at one time. At this time, if the ZQ calibration method provided by the embodiment of the present invention is adopted, an accurate calibration result can be obtained at one time, so that the long ZQ calibration is not required, and time is saved. In addition, under the condition that the maximum calibration cycle number is set reasonably, the method not only can deal with severe working environment changes, but also can correct errors caused by long ZQ calibration.

Based on the same inventive concept, an embodiment of the present invention further provides a memory, including: a storage array for storing data; and peripheral circuitry coupled to and for controlling the memory array; wherein,

In some embodiments, the peripheral circuitry comprises: a control logic unit and a ZQ calibration unit, wherein;

In some embodiments, when the memory supports an open NAND flash interface ONFI protocol, the maximum number of cycles is Set in the memory by a user through a memory controller coupled to the memory based on a Set Feature command in the ONFI protocol.

In some embodiments, the peripheral circuitry further comprises: a register configured to hold a first flag and/or a second flag, wherein the first flag is to feed back an flag indicating that calibration has failed to a memory controller coupled to the memory when the number of cycles for performing calibration reaches the maximum number of cycles and the calibration result does not meet a requirement; the second identifier is an identifier which is used for indicating that the calibration is successful and is fed back to a memory controller coupled with the memory after the calibration result meets the requirement.

In some embodiments, the memory is a double data rate dynamic random access memory (DDR) DRAM.

It should be noted that the technical solution described in the memory and the technical solution of the ZQ calibration method belong to the same inventive concept, and both have the same technical features, and the foregoing has described the specific solution of the ZQ calibration method and the terms appearing in the technical solution of the present invention in detail, so that the terms appearing here can be understood according to the meaning of the foregoing description, and are not described again here.

The embodiment of the present invention further provides a storage system, which includes one or more of the foregoing memories; and a memory controller coupled to the memory; the memory controller to: sending the short ZQ calibration command or the long ZQ calibration command to the memory.

In some embodiments, the storage system is a solid state disk, SSD, or memory card.

It should be noted that the storage system herein includes the aforementioned memory, both have the same technical features, and the foregoing has described the structure of the memory and the terms appearing in the technical solutions of the present invention in detail, so that the terms appearing herein can be understood according to the meaning of the foregoing description, and are not described again here.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A ZQ calibration method applied to a memory, the method comprising:

2. The method of claim 1, wherein the maximum number of cycles is Set in the memory by a memory controller coupled to the memory based on a Set Feature command in an Open NAND Flash Interface (ONFI) protocol when the memory supports the ONFI protocol.

3. The method of claim 1, wherein obtaining the maximum number of cycles configured for short ZQ calibration when the maximum number of cycles comprises a plurality comprises:

determining the degree of change of the current working environment;

4. The method of claim 1, further comprising:

5. The method of claim 4, further comprising:

when the next calibration period is reached, receiving a long ZQ calibration command sent by the memory controller after the first identifier is received; performing long ZQ calibration on interface impedance of the memory when the long ZQ calibration command is received;

6. The method of claim 1, further comprising: after the calibration result meets the requirement, feeding back a second identifier for indicating successful calibration to a memory controller coupled with the memory; wherein the second identification is to cause the memory controller to increase a calibration period over which the short ZQ calibration command is to be sent.

7. The method of claim 5, wherein after performing the long ZQ calibration of the interface impedance of the memory, the method further comprises: continuing to perform the short ZQ calibration of the interface impedance of the memory per the calibration period.

8. A memory, comprising: a storage array for storing data; and peripheral circuitry coupled to and for controlling the memory array; wherein,

9. The memory of claim 8, wherein the peripheral circuitry comprises: a control logic unit and a ZQ calibration unit, wherein;

10. The memory of claim 9, wherein when the memory supports an Open NAND Flash Interface (ONFI) protocol, the maximum number of cycles is Set in the memory by a memory controller coupled to the memory based on a Set Feature command in the ONFI protocol.

11. The memory of claim 9, wherein the peripheral circuitry further comprises: a register configured to hold a first flag and/or a second flag, wherein the first flag is to feed back an indicator indicating that calibration failed to the memory controller coupled to the memory when the number of cycles for performing calibration reaches the maximum number of cycles and the calibration result does not meet a requirement; the second identifier is an identifier which is used for indicating that the calibration is successful and is fed back to a memory controller coupled with the memory after the calibration result meets the requirement.

12. The memory of claim 8, wherein the memory is a double data rate dynamic random access memory (DDR) DRAM.

13. A storage system, comprising: one or more memories as claimed in any one of claims 8 to 12;

and a memory controller coupled to the memory; the memory controller to: sending the short ZQ calibration command or the long ZQ calibration command to the memory.

14. The storage system according to claim 13, wherein the storage system is a Solid State Disk (SSD) or a memory card.