CN115424372B - Intelligent lock circuit, unlocking method and device and intelligent lock - Google Patents
Intelligent lock circuit, unlocking method and device and intelligent lock Download PDFInfo
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- CN115424372B CN115424372B CN202210898552.3A CN202210898552A CN115424372B CN 115424372 B CN115424372 B CN 115424372B CN 202210898552 A CN202210898552 A CN 202210898552A CN 115424372 B CN115424372 B CN 115424372B
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C9/00—Individual registration on entry or exit
- G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C9/00—Individual registration on entry or exit
- G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
- G07C9/00944—Details of construction or manufacture
-
- G—PHYSICS
- G07—CHECKING-DEVICES
- G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
- G07C9/00—Individual registration on entry or exit
- G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
- G07C2009/00968—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys shape of the data carrier
- G07C2009/00976—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys shape of the data carrier card
Abstract
The application discloses an intelligent lock circuit, an unlocking method, a device and an intelligent lock, wherein a signal transmission processing circuit and a detection circuit are used for detecting the feedback AD value of a card to update and judge whether a reference value of the card exists or not, and whether the card accords with the characteristics of card swiping approaching and slow approaching or not is used for judging that the card exists or not, so that the environment without the card can be updated at any time, the wrong reference value can be avoided being updated when the card does not leave a panel, the card approaching is fast responded, and the function of the low-power consumption detection card is stable and reliable.
Description
Technical Field
The application relates to the field of intelligent locks, in particular to an intelligent lock circuit, an unlocking method and device and an intelligent lock.
Background
An inductive card (ic card) is a verification door opening mode of an intelligent lock. When the intelligent lock system is dormant, whether the card is close to the card to be verified can be judged only by detecting whether the card is close to the card swiping panel of the intelligent lock, so that the response time is long, the response speed is low, and the user experience is reduced.
Accordingly, the above-mentioned technical problems of the related art are to be solved.
Disclosure of Invention
The present application is directed to solving one of the technical problems in the related art. Therefore, the embodiment of the application provides an intelligent lock circuit, an unlocking method and device and an intelligent lock, and can improve the unlocking efficiency of the intelligent lock.
According to an aspect of an embodiment of the present application, there is provided an intelligent lock circuit, the circuit including a signal transmission processing circuit, a detection circuit,
the detection circuit comprises a first capacitor, a first resistor and a second resistor, wherein the first capacitor is connected with the first resistor in parallel, the first end of the first capacitor is connected with a main control pin, the second end of the first capacitor is grounded, the first end of the second resistor is connected with the first end of the first capacitor, and the second end of the second resistor is connected with the signal transmission processing circuit.
The signal sending processing circuit comprises a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a diode;
the third capacitor, the fourth capacitor and the fifth capacitor are connected in parallel, the first end of the sixth capacitor is connected with the first end of the second capacitor, the second end of the sixth capacitor is connected with the first end of the third capacitor, the first end of the second capacitor is connected with the main control pin, the second ends of the second capacitor and the third capacitor are connected with the first end of the third resistor, and the second end of the third resistor is grounded; the fourth resistor is connected in parallel with the seventh capacitor, the first end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the first end of the eighth resistor and the first end of the ninth resistor, the second end of the ninth resistor is connected with the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor is connected with the first end of the eighth resistor and the second end of the tenth resistor, the first end of the tenth resistor is connected with the second end of the sixth resistor, the second ends of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the second end of the eighth resistor is connected with a power supply;
the first end of the seventh resistor is connected with the first radio frequency antenna connecting wire, and the second end of the seventh resistor is connected with the second radio frequency antenna connecting wire;
the second end of the sixth capacitor is connected with the positive electrode of the diode, and the negative electrode of the diode is connected with the first end of the fifth resistor. The second end of the second resistor is connected with the first end of the eighth capacitor.
The circuit also comprises a main control module, wherein the main control module transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna;
the main control module detects feedback analog signals through the detection circuit and the radio frequency antenna;
the main control module converts the feedback analog signal into a digital signal.
According to an aspect of the embodiments of the present application, an intelligent lock unlocking method is provided, which is applied to the intelligent lock circuit described in the previous embodiments, and the method includes:
acquiring a feedback AD value;
if the absolute value difference value between the feedback AD value and the reference value is smaller than a first preset difference value, updating the reference value according to the feedback AD value;
the reference value is a feedback AD value obtained by testing in a card-free approaching state.
Wherein, the obtaining the feedback AD value further includes:
detecting a feedback analog signal;
the feedback analog signal is converted into a feedback AD value.
Wherein the method further comprises:
obtaining the feedback AD value twice;
if the difference value between the feedback AD value obtained for the first time and the reference value is larger than or equal to a second preset difference value, and the difference value between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is larger than or equal to a third preset difference value, and the duration time is smaller than or equal to the first preset time, judging that the card is approaching slowly at present.
Wherein the method comprises the following steps:
if the difference value between the feedback AD value and the reference value is larger than or equal to a fourth preset difference value and the duration time is smaller than or equal to a second preset time, the current card is judged to be fast approaching, and the system is awakened to read the card.
According to an aspect of the embodiment of the present application, there is provided an intelligent lock unlocking device, including:
at least one processor;
at least one memory for storing at least one program;
the smart lock unlocking method as described in the previous embodiment is implemented when at least one of the programs is executed by at least one of the processors.
According to an aspect of embodiments of the present application, there is provided a smart lock comprising a smart lock circuit as described in the previous embodiments.
The intelligent lock circuit, the unlocking method and the device provided by the embodiment of the application have the beneficial effects that: the application detects the feedback AD value of the card through the radio frequency circuit, the detection circuit and the transmitting circuit to update and judge whether the reference value of the card exists or not, and judges whether the card exists or not according to the characteristics of card swiping approaching and slow approaching, so that the environment without the card can be updated at any time, the wrong reference value can be avoided being updated when the card does not leave the panel, the card exists to approach and responds fast, and the low-power consumption detection card function is stable and reliable.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of an intelligent lock circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an intelligent lock device according to an embodiment of the present application;
fig. 3 is a schematic diagram of another intelligent lock device according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
An inductive card (ic card) is a verification door opening mode of an intelligent lock. When the intelligent lock system is dormant, whether the card is close to the card to be verified can be judged only by detecting whether the card is close to the card swiping panel of the intelligent lock, so that the response time is long, the response speed is low, and the user experience is reduced.
In order to solve the problems, the application provides an intelligent lock circuit, an unlocking method, an unlocking device and an intelligent lock.
In the embodiment, when the intelligent lock system is dormant, whether the card approaches the card to be verified can be judged only by detecting whether the card approaches the card swiping panel of the intelligent lock, so that the function of detecting the card with low power consumption can be achieved; the low-power consumption card detection function is to detect the AD value of the feedback voltage of the antenna by sending an opening radio frequency (RFID enabling) method to the card swiping circuit and the antenna to judge whether the card is approaching or not, and the detected feedback voltage of the antenna has a fluctuation value, and a card approaching algorithm is made according to the characteristics of fast card approaching and slow card approaching without card approaching so as to achieve the purposes of card approaching and awakening system and preventing card swiping from being triggered by mistake.
FIG. 1 is a diagram: r47-first resistor, R48-second resistor, R55-third resistor, R51-fourth resistor, R49-fifth resistor, R52-sixth resistor, R53-seventh resistor, R56-eighth resistor, C11-first capacitor, C17-second capacitor, C18-third capacitor, C19-fourth capacitor, C20-fifth capacitor, C13-sixth capacitor, C21-seventh capacitor, C22-eighth capacitor, C14-ninth capacitor, C23-tenth capacitor.
Specifically, fig. 1 is a circuit diagram of an intelligent lock circuit provided by an embodiment of the present application, where, as shown in fig. 1, the intelligent lock circuit provided by the present application includes a radio frequency circuit, a detection circuit and a transmitting circuit, where the circuit includes a signal transmission processing circuit and a detection circuit, the detection circuit includes a first capacitor, a first resistor, and a second resistor, the first capacitor is connected in parallel with the first resistor, a first end of the first capacitor is connected to a main control pin, a second end of the first capacitor is grounded, a first end of the second resistor is connected to a first end of the first capacitor, and a second end of the second resistor is connected to the signal transmission processing circuit.
The signal sending processing circuit comprises a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a diode; the third capacitor, the fourth capacitor and the fifth capacitor are connected in parallel, the first end of the sixth capacitor is connected with the first end of the second capacitor, the second end of the sixth capacitor is connected with the first end of the third capacitor, the first end of the second capacitor is connected with the main control pin, the second ends of the second capacitor and the third capacitor are connected with the first end of the third resistor, and the second end of the third resistor is grounded; the fourth resistor is connected in parallel with the seventh capacitor, the first end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the first end of the eighth resistor and the first end of the ninth resistor, the second end of the ninth resistor is connected with the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor is connected with the first end of the eighth resistor and the second end of the tenth resistor, the first end of the tenth resistor is connected with the second end of the sixth resistor, the second ends of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the second end of the eighth resistor is connected with a power supply; the first end of the seventh resistor is connected with the first radio frequency antenna connecting wire, and the second end of the seventh resistor is connected with the second radio frequency antenna connecting wire; the second end of the sixth capacitor is connected with the positive electrode of the diode, and the negative electrode of the diode is connected with the first end of the fifth resistor. The second end of the second resistor is connected with the first end of the eighth capacitor.
The circuit also comprises a main control module, wherein the main control module transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna; the main control module detects feedback analog signals through the detection circuit and the radio frequency antenna; the main control module converts the feedback analog signal into a digital signal.
It should be noted that, the circuit diagram of the detection card and the feedback voltage AD value: transmitting a 13.6M radio frequency signal to the circuit through the RF_TXP, transmitting through an antenna connected with the CMP_INP and the CMP_INN, and detecting a feedback AD value of the antenna through the RF_ADC; typically, when no card approaches, the voltage AD value detected by the rf_adc is M units, if the card approaches quickly (approach time is less than 300 ms) is N units, if the card approaches slowly (approach time is more than twice 300 ms) is divided into P and Q units for two detections, respectively.
Based on the intelligent lock unlocking circuit provided by the above embodiment, this embodiment provides three unlocking conditions, including:
(1) Card-free approach detection algorithm:
the detection method for the card-free approach comprises the following steps: acquiring a feedback AD value detected by a detection circuit; if the absolute value difference value between the feedback AD value and the reference value is smaller than a first preset difference value, updating the reference value according to the feedback AD value; the reference value is a feedback AD value obtained by testing in a card-free approaching state. Specifically, when no card approaching is detected after the first power-on, M value of no card approaching is used as a reference value D, M is equal to D at the moment, and when no card approaching is performed next time, the difference between the absolute value of the detected M value of no card approaching and the reference value D is smaller than 60 units, and M is used for updating the reference value D of no card approaching; if the absolute value difference between the current detected value of M and the reference value D is larger than 60 units, the reference value D is kept unchanged (no update is needed), if the card is not separated from the panel all the time, the detected value belongs to more than plus or minus 60 units, and the reference value is not updated. The feedback AD value expression of this embodiment is:
if(M>D-60&&M<D+60)，D＝M
wherein M is the voltage AD value detected by the RF_ADC, and D is the reference value of no card approach.
(2) Detection algorithm for fast card approach
The detection method for the approach of the quick card comprises the following steps: if the difference value between the feedback AD value and the reference value is larger than or equal to a fourth preset difference value and the duration time is smaller than or equal to preset time, judging that the current card is fast approaching, and waking up the system to read the card. Specifically, if the card is not more than 300ms when approaching the card swiping panel, the value of the feedback AD value N is more than 800 units smaller than the reference value, and the card swiping approach is immediately judged, and the card is read after the system is awakened. The feedback AD value expression of this embodiment is:
if(N<D-800)
(3) Detection algorithm for approach of slow card
The detection method for the approach of the slow card comprises the following steps: obtaining the feedback AD value twice; if the difference value between the feedback AD value obtained for the first time and the reference value is larger than or equal to a second preset difference value, and the difference value between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is larger than or equal to a third preset difference value, judging that the card is approaching slowly. Specifically, if the card approaches the card swiping panel no more than 600ms, the detected AD value P and Q units are divided into two times, wherein the first time P is 100 or more unit values smaller than the reference value D and the second time Q is 100 or more unit values smaller than P. The feedback AD value expression of this embodiment is:
if(P<D-100&&Q<P-100)
wherein P is the first detected voltage AD value, and Q is the second detected voltage AD value.
According to an aspect of the embodiments of the present application, an intelligent lock unlocking method is provided, which is applied to the intelligent lock circuit described in the previous embodiments, and the method includes: acquiring a feedback AD value; if the absolute value difference value between the feedback AD value and the reference value is smaller than a first preset difference value, updating the reference value according to the feedback AD value; the reference value is a feedback AD value obtained by testing in a card-free approaching state. Wherein, the obtaining the feedback AD value further includes: detecting a feedback analog signal; the feedback analog signal is converted into a feedback AD value. Wherein the method further comprises: obtaining the feedback AD value twice; if the difference value between the feedback AD value obtained for the first time and the reference value is larger than or equal to a second preset difference value, and the difference value between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is larger than or equal to a third preset difference value, and the duration time is smaller than or equal to the first preset time, judging that the card is approaching slowly at present. Wherein the method comprises the following steps: if the difference value between the feedback AD value and the reference value is larger than or equal to a fourth preset difference value and the duration time is smaller than or equal to a second preset time, the current card is judged to be fast approaching, and the system is awakened to read the card.
The application detects the feedback AD value of the card by waking up once in 300ms of the low-power-consumption timer to update and judge whether the reference value of the card exists or not, and judges whether the card exists or not according to the characteristics of card swiping approaching and slow approaching, so that the environment without the card can be updated at any time, the error reference value can be prevented from being updated when the card does not leave the panel, the card exists to approach and respond quickly, and the low-power-consumption detection card function is stable and reliable.
Fig. 2 is a schematic diagram of an intelligent lock device provided by an embodiment of the present application, and as shown in fig. 2, the present application further provides an intelligent lock unlocking device, where the device includes:
the detection module is used for acquiring a feedback AD value;
the judging module is used for updating the reference value according to the feedback AD value if the difference value between the feedback AD value and the reference value is smaller than a first preset difference value;
the reference value is a feedback AD value obtained by testing in a card-free approaching state.
Fig. 2 is a schematic diagram of an intelligent lock device provided by an embodiment of the present application, and as shown in fig. 3, the present application further provides an intelligent lock unlocking device, where the device includes:
at least one processor;
at least one memory for storing at least one program;
the smart lock unlocking method as described in the previous embodiment is implemented when at least one of the programs is executed by at least one of the processors.
In addition, the application further provides an intelligent lock, which comprises the intelligent lock circuit.
Similarly, the content in the above method embodiment is applicable to the embodiment of the present device, and the functions specifically implemented by the embodiment of the present device are the same as those of the embodiment of the above method, and the beneficial effects achieved by the embodiment of the above method are the same as those achieved by the embodiment of the above method.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present application are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the application is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the functions and/or features may be integrated in a single physical device and/or software module or may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present application. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the application as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the application, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (5)
1. The intelligent lock circuit is characterized by comprising a signal transmission processing circuit and a detection circuit,
the detection circuit comprises a first capacitor, a first resistor and a second resistor, wherein the first capacitor and the first resistor are connected in parallel, a first end of the first capacitor is connected with a main control pin, a second end of the first capacitor is grounded, a first end of the second resistor is connected with a first end of the first capacitor, and a second end of the second resistor is connected with the signal transmission processing circuit;
the signal transmission processing circuit comprises a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a diode;
the third capacitor, the fourth capacitor and the fifth capacitor are connected in parallel, the first end of the sixth capacitor is connected with the first end of the second capacitor, the second end of the sixth capacitor is connected with the first end of the third capacitor, the first end of the second capacitor is connected with the main control pin, the second ends of the second capacitor and the third capacitor are connected with the first end of the third resistor, and the second end of the third resistor is grounded; the fourth resistor is connected in parallel with the seventh capacitor, the first end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the first end of the eighth resistor and the first end of the ninth resistor, the second end of the ninth resistor is connected with the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor is connected with the first end of the eighth resistor and the second end of the tenth resistor, the first end of the tenth resistor is connected with the second end of the sixth resistor, the second ends of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the second end of the eighth resistor is connected with a power supply;
the first end of the seventh resistor is connected with the first radio frequency antenna connecting wire, and the second end of the seventh resistor is connected with the second radio frequency antenna connecting wire;
the second end of the sixth capacitor is connected with the positive electrode of the diode, and the negative electrode of the diode is connected with the first end of the fifth resistor;
the second end of the second resistor is connected with the first end of the eighth capacitor;
the circuit also comprises a main control module, wherein the main control module transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna;
the main control module detects feedback analog signals through the detection circuit and the radio frequency antenna;
the main control module converts the feedback analog signal into a digital signal;
the intelligent lock circuit is used for:
acquiring a feedback AD value;
if the absolute value difference value between the feedback AD value and the reference value is smaller than a first preset difference value, updating the reference value according to the feedback AD value;
the reference value is a feedback AD value obtained by testing in a card-free approaching state;
the obtaining the feedback AD value further includes:
detecting a feedback analog signal;
the feedback analog signal is converted into a feedback AD value.
2. An intelligent lock unlocking method applied to the intelligent lock circuit as claimed in claim 1, comprising:
obtaining the feedback AD value twice;
if the difference value between the feedback AD value obtained for the first time and the reference value is larger than or equal to a second preset difference value, and the difference value between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is larger than or equal to a third preset difference value, and the duration time is smaller than or equal to the first preset time, judging that the card is approaching slowly at present.
3. The smart lock unlocking method according to claim 2, wherein the method comprises:
if the difference value between the feedback AD value and the reference value is larger than or equal to a fourth preset difference value and the duration time is smaller than or equal to a second preset time, the current card is judged to be fast approaching, and the system is awakened to read the card.
4. Intelligent lock unlocking device, its characterized in that, the device includes:
at least one processor;
at least one memory for storing at least one program;
a smart lock unlocking method according to any one of claims 2-3, when at least one of said programs is executed by at least one of said processors.
5. A smart lock, wherein the smart lock comprises the smart lock circuit of claim 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210898552.3A CN115424372B (en) | 2022-09-21 | 2022-09-21 | Intelligent lock circuit, unlocking method and device and intelligent lock |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210898552.3A CN115424372B (en) | 2022-09-21 | 2022-09-21 | Intelligent lock circuit, unlocking method and device and intelligent lock |
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| CN115424372A CN115424372A (en) | 2022-12-02 |
| CN115424372B true CN115424372B (en) | 2023-10-20 |
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| CN115424372A (en) | 2022-12-02 |
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