CN115422604A - Data security processing method for nonvolatile memory, memory controller and system - Google Patents

Data security processing method for nonvolatile memory, memory controller and system Download PDF

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Publication number
CN115422604A
CN115422604A CN202210979822.3A CN202210979822A CN115422604A CN 115422604 A CN115422604 A CN 115422604A CN 202210979822 A CN202210979822 A CN 202210979822A CN 115422604 A CN115422604 A CN 115422604A
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bmt
fore
node
updating
region
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王芳
冯丹
雷梦雅
帅晓雨
曹郁超
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Huazhong University of Science and Technology
Shenzhen Huazhong University of Science and Technology Research Institute
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Huazhong University of Science and Technology
Shenzhen Huazhong University of Science and Technology Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The invention discloses a data security processing method, a memory controller and a system for a nonvolatile memory, belonging to the technical field of memory security and comprising the following steps: constructing a traditional BMT as a Back _ BMT, constructing the BMT as a Fore _ BMT by taking a certain layer of nodes as leaf nodes, wherein the Back _ BMT subtree and the NVM space corresponding to the leaf nodes are a Region _ BMT and an area respectively; when the data block B is written Back to the NVM from the CPU, reading a counter of the B from the Back _ BMT and updating, then updating a Region R corresponding to the B, and adding the Region BMT into the Fore _ BMT for protection; b is encrypted and then written into NVM; adding Region _ BMT to Fore _ BMT protection, comprising: if the Fore _ BMT does not have the leaf node corresponding to the Fore _ BMT, an idle or synchronized leaf node is preferentially allocated from the Fore _ BMT, if the allocation is unsuccessful, a leaf node Fore _ Vistim is selected from the Fore _ BMT, and after the Back _ BMT is updated according to the Fore _ Vistim, the Fore _ BMT is updated by using the Region _ BMT. The method and the device can ensure that the metadata in the safe NVM can be recovered after being crashed, and reduce the cost of updating the BMT root node.

Description

Data security processing method for nonvolatile memory, memory controller and system
Technical Field
The present invention belongs to the technical field of memory security, and more particularly, to a data security processing method for a nonvolatile memory, a memory controller, and a system.
Background
Non-volatile memory (NVM) has attracted much attention from memory system researchers because of its excellent characteristics such as high density, byte-addressable, and persistent data storage. Unlike a volatile Dynamic Random Access Memory (DRAM), data stored on the NVM is not lost after the system is powered off, which makes it easier for an attacker to destroy the security of the data on the NVM through data theft, malicious modification, and other means, and thus efficient security assurance is essential for the NVM Memory system.
In a secure NVM system, any data on the CPU chip is considered secure and trusted, while any data off-chip, which mainly includes data on the NVM memory and the memory bus, is considered untrusted. Data confidentiality and integrity are two main aspects of memory data security, and are respectively guaranteed by Counter Mode Encryption (CME) and Bonsai Merkle Tree (BMT) verification in current secure NVM designs. As shown in FIG. 1, in CME, there is a corresponding counter for each data cache line. Whenever a data cache line is written to or read from the NVM, it is encrypted or decrypted by xoring it with a unique One Time Pad (OTP) generated using the corresponding encryption counter, data address and other elements of the data cache line. When the same data block is encrypted, the counter is automatically increased to ensure the time uniqueness of the OTP. As shown in fig. 2 (a), the BMT is a high-level integrity tree structure constructed by layer-by-layer hash calculation using encryption counters in the CME as leaf nodes. The BMT root node (root node) is used to reflect the latest state of all counters in NVM, which is stored in an on-chip secure persistent register. The counter read from memory must first be verified by the BMT root. To improve the performance of the secure NVM, conventional secure NVM designs typically add a volatile secure metadata cache in the on-chip memory controller to cache more frequently accessed BMT leaf counter nodes and other BMT intermediate nodes.
However, it is not easy to implement CME and BMT in a secure NVM because the non-volatility of NVM makes memory immediate recovery possible, which requires that the secure metadata BMT (including leaf counter nodes and other intermediate nodes) recover correctly and quickly after a system crash. For this reason, the update of the root node of the BMT needs to be completed with the data write request atomically, so as to ensure the correctness of the BMT recovery and the security of the system. The number of BMT nodes increases as the NVM memory size increases. The larger the NVM, the higher the BMT hierarchy and the higher the update overhead of the BMT root. When any data cache line is written back from the CPU cache to the NVM, the entire BMT path corresponding to the data cache line needs to be updated to the root node, as shown in (b) of fig. 2, which is very unfriendly for the NVM that is sensitive to write performance. For example, for a 16GB secure NVM, the BMT can reach 9 layers. When using an 80CPU clock cycle hash calculation engine, 720 CPU clock cycles are required to complete the BMT root update for each data write request. For TB level NVM, BMTroot atomic update overhead would be higher.
Some work has been devoted to implementing secure NVM systems with secure metadata crash recovery guarantees. However, these efforts still suffer from the following drawbacks:
1) Partial work only considers how to realize crash recovery of the BMT, reduces the persistent overhead brought by a crash recovery mechanism, and ignores the overhead problem of updating the BMT root atoms;
2) Partial work reduces BMT root updating overhead caused by hot pages through hot-spot trees with fewer layers, but has higher hot and cold page identification and tree node replacement overhead;
3) In order to achieve fast system recovery, existing work often requires long recovery time or relatively large NVM write traffic overhead.
In general, how to reduce the overhead of BMT root update on the premise of realizing fast security metadata crash recovery in a nonvolatile memory system is a problem to be studied.
Disclosure of Invention
Aiming at the defects and improvement requirements in the prior art, the invention provides a data security processing method, a memory controller and a system for a nonvolatile memory, aiming at reducing the updating overhead of a BMT root node on the premise of ensuring the recovery of metadata in a security NVM after breakdown.
To achieve the above object, according to an aspect of the present invention, there is provided a data security processing method for a nonvolatile memory, including:
an initialization step, comprising: constructing a Merck tree with counters of data cache lines as leaf nodes as Back _ BMT, taking a subtree with nodes in a specified layer as root nodes as Region _ BMT, and taking a nonvolatile memory space corresponding to each Region _ BMT as a Region; initializing another Merckel tree, recording the Merckel tree as Fore _ BMT, wherein leaf nodes of the Merckel tree are root nodes of the Region _ BMT, and the total number of the leaf nodes does not exceed a threshold value N;
a BMT updating step, comprising:
(S1) judging whether a Region _ BMT (RBMTB) needing to be added with Fore _ BMT protection exists in the Fore _ BMT or not, if so, turning to a step (S3); otherwise, go to step (S2);
(S2) judging whether idle leaf nodes or leaf nodes synchronized to Back _ BMT exist in the Fore _ BMT, if yes, allocating one leaf node for RBMTB from the leaf nodes, and turning to the step (S3); otherwise, allocating a leaf node as a Fore _ Vistim for the RBMTB, and after updating Back _ BMT according to the Fore _ Vistim, turning to the step (S3);
(S3) updating the Fore _ BMT by using RBMTB;
and a write-back step, comprising: when the data block B is written Back to the nonvolatile memory from the CPU, reading a counter of the data block B to be written from the Back _ BMT and updating, then updating a Region R corresponding to the data block B, and adding the Region BMT into the Fore _ BMT for protection through a BMT updating step; and encrypting the data block B by using the updated counter, and writing the obtained ciphertext into the nonvolatile memory.
With the operation of the system, the number and the data address of data written back to the memory from the CPU cache are different in different time periods, and the data block written back by applying at a certain time does not occupy all the memory space, especially for the NVM at TB level, the private data written back by the user mostly only occupies a small proportion of the memory; according to the method, a Back _ BMT is constructed by adopting a traditional BMT construction mode, on the basis, a region (usually the size of a plurality of cache lines) is used as an allocation granularity, a Fore _ BMT is constructed and used for storing a counter corresponding to a data block recently written Back by a current system, only the Fore _ BMT is constructed and modified dynamically along with a memory writing request of a user, and the whole Back _ BMT does not need to be updated every time data is written Back, so that the Fore _ BMT only covers a memory region which is requested to be accessed before current writing as much as possible, the BMT level is effectively reduced, and updating of a BMT root is accelerated on the premise of ensuring recovery of metadata collapse in a safe NVM.
Further, the data security processing method for the nonvolatile memory provided by the present invention further includes: maintaining a specified number of cache line counters in an on-chip persistence register;
in the write-Back step, before reading the counter of the data block B to be written from Back _ BMT, the method further includes:
(T1) searching a counter of the data block B from the persistent register, and if the counter is hit, turning to the step (T4); otherwise, turning to the step (T2);
(T2) selecting a cache line Reg _ Visim to be replaced from the persistence register, and reading a leaf node where a counter of the data block B is located from Back _ BMT to perform atomic replacement on the Reg _ Visim;
(T3) updating the corresponding Region _ BMT by utilizing the Reg _ Vistim, and adding the Region _ BMT into the form _ BMT for protection by utilizing a BMT updating step;
and (T4) updating the counter of the data block B in the persistent register, encrypting the data block B by using the updated counter, writing the obtained ciphertext into the nonvolatile memory, and ending the write-back step.
The invention maintains the counters of partial cache lines in the persistent register, preferentially searches the corresponding counters from the persistent register when data is written back, and directly updates the counters in the persistent register without updating BMT nodes in the persistent memory under the condition of hit, thereby effectively reducing the times of accessing the nonvolatile memory in the data writing back process and improving the execution efficiency of the data writing back. In addition, in the secure NVM, the write-back of adjacent data will cause the update of adjacent counters, and the update of adjacent counters will cause the update of a large number of identical BMT nodes, and due to the load locality and the CPU cache, the memory data write requests show strong spatial locality, so that these repeated BMT update operations usually occur in consecutive write requests.
Further, the data security processing method for the nonvolatile memory provided by the present invention further includes:
a node recovery step, comprising:
for the lost node in the Back _ BMT or the Fore _ BMT, if the lost node is a leaf node, the lost node is recovered in a system crash recovery stage by using ECC;
if the node is the intermediate node, postponing the recovery until a replay attack is detected after the system is restarted; when the system accesses an intermediate node to be recovered after restarting, a root node stored on a chip can detect replay attack; at this time, the node is recovered; during recovery, recalculating the hash value of each node on the path by using the current counter on the accessed path until reaching the root node, comparing the calculated root node with the root node stored on the chip, and if the calculated root node and the root node are consistent, recovering the intermediate node on the path by using the calculated node value; if the two are not consistent, the system is judged to have real replay attack.
The invention delays the recovery of the lost intermediate node in the BMT until the system detects the attack after restarting, thereby reducing the recovery operation required after the system crashes and restarts, reducing the recovery time and ensuring the availability of the system after crashing and restarting.
Further, the data security processing method for the nonvolatile memory provided by the present invention further includes:
an advance synchronization step, comprising: identifying leaf nodes which are not accessed in continuous M times of memory writing requests in the Fore _ BMT, and adding the leaf nodes to a synchronous queue; when the BMT engine is not occupied by the foreground memory read-write request, synchronizing the Fore _ BMT leaf nodes in the synchronization queue to the root node of the Back _ BMT by using the BMT engine, and if memory access occurs in the synchronization process, terminating synchronization;
wherein M is a preset positive integer.
In the safety NVM, only when the counter cache is not hit due to a few read requests and the batch update register is not hit due to write requests, the BMT engine is requested to be used by the foreground, and at other times, the BMT engine is in an unused state; in the advanced synchronization step, leaf nodes which are not accessed in continuous M times of memory write requests in the Fore _ BMT are identified and added into a synchronization queue, and the Fore _ BMT leaf nodes in the synchronization queue are synchronized to a root node of the Back _ BMT when a BMT engine is not occupied by foreground memory read-write requests, so that the utilization rate of the BMT engine can be well improved, the Fore _ BMT leaf nodes which are not used for too long time are synchronized to the Back _ BMT in advance under the condition of not influencing the memory read-write requests, the Fore _ BMT root can be updated only on a critical path of the write requests at a high probability when the write requests are processed subsequently, the Back _ BMT root does not need to be updated, the delay of the BMT update in the write request process is further reduced, and the system performance is improved.
Further, the initializing step further includes: establishing a leaf node state table for recording the state information of each leaf node in the Fore _ BMT; the state information comprises an area number corresponding to the leaf node, the total number of memory write requests of the system during the last update and a state flag bit, wherein the state flag bit is used for indicating whether the leaf node is idle and synchronized to Back _ BMT;
in the advance synchronization step, the Fore _ BMT leaf nodes which are not accessed in the continuous M times of memory writing requests are identified in a mode of regularly scanning the leaf node state table.
The invention establishes a leaf node state table for recording the state information of each leaf node in the Fore _ BMT, so that the leaf nodes which are not used for a long time can be conveniently and quickly identified by regularly scanning the state table in the advance synchronization step; in addition, in the data write-Back process, whether idle or synchronized to the leaf node of Back _ BMT exists in the form _ BMT can be conveniently and quickly judged by inquiring the state table.
Further, in step (S2) of updating the BMT, if there is no leaf node in the form _ BMT that is idle or has been synchronized to the Back _ BMT, the manner of allocating one leaf node as form _ view to the RBMTB is as follows:
randomly reading K continuous state information entries from a leaf node state table, identifying a Fore _ BMT leaf node which is not updated for the longest time from the K continuous state information entries, and allocating the Fore _ BMT leaf node as a Fore _ Vistim to the RBMTB; k is a preset positive integer.
Because the time locality of access is low, the possibility of subsequent access of leaf nodes which are not updated in the Fore _ BMT for the longest time is low, when the Fore _ BMT does not have idle leaf nodes or leaf nodes which are synchronized to the Back _ BMT, the leaf node state table is scanned to identify the Fore _ BMT leaf nodes which are not updated for the longest time from partial continuous entries to be used as alternative nodes, the time locality of access can be fully utilized, the counter corresponding to the data block written Back recently by the current system is ensured to be protected by the Fore _ BMT, and the exchange frequency of the Fore _ BMT and the Back _ BMT is reduced.
Further, the initializing step further includes: establishing a region index table for recording the protection information of each region in the nonvolatile memory; the protection information includes: the Fore/Back identification bit is used for indicating whether the area is protected by Fore _ BMT or not, and the Fore _ BMT leaf node sequence corresponding to the area;
in addition, in the BMT updating step (S1), for the Region _ BMT, that is, RBMTB, to which the form _ BMT protection needs to be added, the manner of determining whether a leaf node corresponding to the Region _ BMT exists in the form _ BMT includes:
determining an area corresponding to the RBMTB, searching an entry corresponding to the area in an area index table, if the Fore/Back identification bit indicates that the area is protected by Fore _ BMT, judging that a leaf node corresponding to the Fore _ BMT exists in the Fore _ BMT, otherwise, judging that the leaf node corresponding to the Fore _ BMT does not exist in the Fore _ BMT.
In the invention, the storage sequence of Back _ BMT is determined, and the order and the corresponding data area of the leaf node of Fore _ BMT are dynamically changed along with the memory writing request, and when the data is written Back to the NVM area, the positioning process of the corresponding Fore _ BTM leaf node directly influences the writing performance; according to the invention, whether each region in the nonvolatile memory is protected by the Fore _ BMT and the corresponding Fore _ BTM leaf node sequence are recorded by establishing the region index table, so that when data are written back to the NVM, the corresponding Fore _ BTM leaf node can be quickly positioned by inquiring the region index table, and the writing performance of the system is effectively improved.
According to another aspect of the present invention, there is provided a memory controller for a nonvolatile memory, including: the system comprises an initialization module, a BMT updating module and a write-back module;
an initialization module for performing an initialization step; the initialization step comprises: constructing a Merck tree by taking counters of all data blocks as leaf nodes, recording the Merck tree as Back _ BMT, taking a subtree in which nodes in a specified layer are taken as root nodes as Region _ BMT, and taking a nonvolatile memory space corresponding to each Region _ BMT as a Region; initializing another Mercker tree, recording the Mercker tree as Fore _ BMT, wherein leaf nodes of the Mercker tree are root nodes of the Region _ BMT, and the total number of the leaf nodes does not exceed a threshold value N;
a BMT updating module for executing the BMT updating step; the BMT updating step comprises the following steps:
(S1) judging whether a Region _ BMT (RBMTB) needing to be added with Fore _ BMT protection exists in the Fore _ BMT or not, if so, turning to a step (S3); otherwise, go to step (S2);
(S2) judging whether idle leaf nodes or leaf nodes synchronized to Back _ BMT exist in the Fore _ BMT, if yes, allocating one leaf node for RBMTB from the leaf nodes, and turning to the step (S3); otherwise, allocating a leaf node as a Fore _ Vistim for the RBMTB, and after updating Back _ BMT according to the Fore _ Vistim, turning to the step (S3);
(S3) updating the Fore _ BMT by using RBMTB;
a write-back module for performing a write-back step; a write back step, comprising: when the data block B is written Back to the nonvolatile memory from the CPU, reading a counter of the data block B to be written from the Back _ BMT and updating, then updating a Region R corresponding to the data block B, and adding the Region BMT into the Fore _ BMT for protection through a BMT updating step; and encrypting the data block B by using the updated counter, and writing the obtained ciphertext into the nonvolatile memory.
Further, the memory controller for a nonvolatile memory provided by the present invention further includes: a persistence register to cache a specified number of cache line counters;
in the write-Back step, before reading the counter of the data block B to be written from Back _ BMT, the method further includes:
(T1) searching a counter of the data block B from the persistent register, and if the counter is hit, turning to the step (T4); otherwise, turning to the step (T2);
(T2) selecting a cache line Reg _ Victim to be replaced from the persistence register, and reading a leaf node where a counter of the data block B is located from Back _ BMT to perform atomic replacement on the Reg _ Victim;
(T3) updating the corresponding Region _ BMT by utilizing the Reg _ Vistim, and adding the Region _ BMT into the form _ BMT for protection by utilizing a BMT updating step;
and (T4) updating the counter of the data block B in the persistent register, encrypting the data block B by using the updated counter, writing the obtained ciphertext into the nonvolatile memory, and ending the write-back step.
According to still another aspect of the present invention, there is provided a secure processing system for a nonvolatile memory, including: the nonvolatile memory and the memory controller provided by the invention;
the nonvolatile memory is divided into a DR metadata storage area, a BMT node storage area and a safe user data storage area; a DR metadata storage area for storing DR metadata including a leaf node status table and an area index table; the BMT node storage area is used for storing BMT nodes, and the BMT nodes are nodes in Fore _ BMT or Back _ BMT; a secure user data storage area for storing encrypted user data;
the memory controller further comprises: a CPU cache, a security engine, a security metadata cache, a DR cache and a battery-backed NVM write queue;
the safety metadata cache is used for caching partial BMT nodes;
a DR cache for caching a part of DR metadata;
the CPU cache is used for caching the plaintext and outputting the plaintext to the security engine or reading the plaintext from the security engine;
the safety engine is used for receiving the plaintext output by the CPU cache when a data write request is made, encrypting the plaintext according to the counter, outputting the ciphertext to the NVM write queue supported by the battery, and updating the BMT node according to the counter;
the safety engine is also used for reading the ciphertext from the NVM writing queue when a data reading request is made, decrypting the plaintext according to the counter and outputting the plaintext to the CPU for caching; in the encryption and decryption processes, if the required counter is obtained from the security metadata cache, the counter is directly used for data encryption and decryption, and if the counter is obtained from the NVM, BMT verification is firstly carried out;
the battery-supported NVM write queue is used for receiving the ciphertext output by the security engine and outputting encrypted user data to a secure user data storage area in the NVM;
the battery-supported NVM writing queue is also used for receiving BMT nodes output by the security metadata cache and outputting the BMT to a BMT node storage area in the NVM;
the battery-supported NVM write queue is also used for receiving DR metadata output by the DR cache and outputting the DR metadata to a DR metadata storage area in the NVM;
the leaf node state table is used for recording the state information of each leaf node in the Fore _ BMT; the state information comprises an area number corresponding to the leaf node, the total number of memory write requests of the system during the last update and a state flag bit, wherein the state flag bit is used for indicating whether the leaf node is idle and synchronized to Back _ BMT; the area index table is used for recording the protection information of each area in the nonvolatile memory; the protection information includes: the Fore/Back flag bit is used for indicating whether the area is protected by Fore _ BMT or not, and the Fore _ BMT leaf node sequence corresponding to the area.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) The invention provides a user memory requirement-based dynamically recoverable BMT structure, the updating mode of the structure is adaptive to the load access characteristic, the problem that the existing safe NVM system has high BMT root atom updating overhead or the method for reducing the BMT root atom updating overhead has high complexity is effectively solved, and the overhead and the complexity of BMT root atom updating are greatly reduced.
(2) The quick BMT recovery method based on delayed recovery effectively solves the problems that the existing safe NVM system has long recovery time or the NVM write flow cost is large in a method for accelerating the system recovery, and realizes the quick recovery of the safe NVM system while reducing the write flow cost.
Drawings
FIG. 1 is a diagram of a conventional Counter Mode Encryption (CME);
FIG. 2 is a schematic diagram of a conventional Bonsai Merkle Tree (BMT) and a data write-back process in a conventional secure NVM; wherein, (a) is a conventional BMT schematic diagram, and (b) is a data write-back flow schematic diagram based on the BMT shown in (a);
FIG. 3 is a schematic diagram of a Fore _ BMT according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a Region _ BMT, back _ BMT, and Fore _ BMT according to an embodiment of the present invention;
FIG. 5 is a representation of a leaf node state table and an area index provided by an embodiment of the present invention; wherein, (a) is a leaf node state representation intention, (b) is a region index representation intention;
fig. 6 is a schematic diagram illustrating a data write-back process according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a secure processing system for a non-volatile memory according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the respective embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the present application, the terms "first," "second," and the like (if any) in the description and the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In order to reduce BMT root update overhead on the premise of realizing rapid safe metadata crash recovery in a nonvolatile memory system, the invention provides a data safety processing method, a memory controller and a system aiming at a nonvolatile memory, and the whole thought of the method is as follows: and modifying the BMT structure and the updating mode based on the application memory requirement and the access characteristic, and enabling the BMT to only cover the memory area which is accessed by the current request before writing as much as possible so as to reduce the BMT level and accelerate the updating of the BMT root.
The following are examples.
Example 1:
a data security processing method for a nonvolatile memory, which is specifically shown in fig. 3, in this embodiment, a conventional BMT structure is modified based on an application memory requirement and an access characteristic.
In the embodiment, two BMTs, namely Back _ BMT and Fore _ BMT are constructed, wherein the Back _ BMT is similar to the BMT in the traditional safety NVM, and is a high-level integrity tree structure constructed by taking a counter of a cache line as a leaf node and performing hash calculation layer by layer; it should be noted that, in the NVM, data is stored in the form of data blocks, each data block has its corresponding counter, and a cache line is composed of a plurality of data blocks.
With the operation of the system, the number and address of data written back to the memory from the CPU cache are not the same in different time periods, and more importantly, the data block written back by the application at a certain time does not occupy all the memory space, especially for the TB-level NVM, the private data written back by the user mostly occupies a small proportion of the memory. Based on this characteristic of the secure NVM, this embodiment constructs a form _ BMT on the basis of Back _ BMT, which is used to perform integrity protection on the data block recently written Back by the current system. Node switching exists between the Fore _ BMT and the Back _ BMT, in order to reduce the switching frequency, the embodiment updates the leaf nodes of the Fore _ BMT by taking a Region (Region) as an allocation granularity, specifically, one layer in the Back _ BMT is designated as an allocation layer, a subtree taking the node in the allocation layer as a root node is taken as the Region _ BMT, an NVM storage space corresponding to the leaf node of one Region _ BMT is a Region, and one leaf node of the Fore _ BMT is the root node of one Region _ BMT; when the load memory write request exceeds the current area, the increase of the nodes of the Fore _ BMT is triggered, so that the exchange between the Fore _ BMT and the Back _ BMT can be caused; optionally, in this embodiment, the area size is 32KB, and the form _ BMT adopts a coarse-grained allocation scheme compared to the Back _ BMT, and in order to effectively reduce the BMT hierarchy, in this embodiment, the number of leaf nodes of the form _ BMT is limited to not more than 512. In this embodiment, the storage of Region _ BMT, form _ BMT, and Back _ BMT in the NVM memory is shown in fig. 4.
For the BMT structures shown in fig. 3 and fig. 4, this embodiment correspondingly proposes a BMT updating step, which specifically includes:
a BMT updating step, comprising:
(S1) recording a Region _ BMT needing to be protected by the Fore _ BMT as RBMTB, judging whether leaf nodes corresponding to the Region _ BMT exist in the Fore _ BMT, if so, indicating that the Region corresponding to the Region _ BMT is protected by the Fore _ BMT, and then turning to a step (S3); otherwise, the area corresponding to the Region _ BMT is not protected by the Fore _ BMT, and the step (S2) is carried out;
(S2) judging whether idle leaf nodes or leaf nodes synchronized to Back _ BMT exist in the Fore _ BMT, if yes, allocating one leaf node for RBMTB from the leaf nodes, and turning to the step (S3); otherwise, allocating a leaf node as a Fore _ Vistim for the RBMTB, and after updating Back _ BMT according to the Fore _ Vistim, turning to the step (S3);
(S3) updating the Fore _ BMT by using RBMTB; specifically, the value of the corresponding leaf node in the form _ BMT is updated to the hash value of the root node of the RBMTB, and then the node hash value on the path from the leaf node to the form _ BMT root is updated in a layer-by-layer hash manner until the root node of the form _ BMT is updated.
Based on the BMT updating step, in this embodiment, the writing back step of writing back the data from the CPU to the NVM includes: when the data block B is written Back to the nonvolatile memory from the CPU, reading a counter of the data block B to be written from the Back _ BMT and updating, then updating a Region R corresponding to the data block B, and adding the Region BMT into the Fore _ BMT for protection through a BMT updating step; and encrypting the data block B by using the updated counter, and writing the obtained ciphertext into the nonvolatile memory.
In this embodiment, since the form _ BMT is constructed only for the data block recently written Back by the current system for integrity protection, compared with the Back _ BMT, the levels of the form _ BMT are greatly reduced, taking fig. 3 as an example, the hash calculation of 5 times in the conventional BMT is reduced to 3 times for BMT root update caused by each write Back data write, thereby effectively reducing the overhead of BMT root update; it should be noted that the allocation granularity of the Fore _ BMT and the allocation layer in the Back _ BMT can be flexibly set according to the actual load characteristics.
In the above write-Back step, when performing the replacement of the Fore _ BMT, the embodiment preferentially selects the Fore _ BMT leaf node which is not used or has been synchronized to the Back _ BMT, so that on the critical path for performing the data write request, only the update of the Fore-BMT root will occur with a high probability, and no update of the Back _ BMT root occurs, thereby being capable of effectively reducing the exchange overhead. In addition, in the secure NVM system, there is a security engine specifically including an encryption engine for data encryption and decryption and a BMT engine for BMT verification, and only when a few read requests cause a miss of a counter buffer and a write request causes a miss of a batch update register, the BMT engine is used by a foreground request. In this embodiment, the advance synchronization step includes: identifying leaf nodes which are not accessed in continuous M memory writing requests in the Fore _ BMT, and adding the leaf nodes into a synchronous queue; when the BMT engine is not occupied by the foreground memory read-write request, synchronizing the Fore _ BMT leaf nodes in the synchronization queue to the root node of the Back _ BMT by using the BMT engine, and if memory access occurs in the synchronization process, terminating synchronization;
wherein M is a preset positive integer; optionally, in this embodiment, M =64; through the advanced synchronization step, when a new Fore-BMT leaf node is allocated, the leaf node which is synchronized is evicted, so that the utilization rate of the BMT engine can be improved, and the updating times of the Back _ BMT root during Fore _ BMT replacement can be reduced.
In order to support the advanced synchronization step to be completed conveniently and quickly, in this embodiment, a leaf node state table shown in (a) in fig. 5 is designed for the foree _ BMT, and is used for recording state information of each leaf node in the foree _ BMT; the state information includes: the area number corresponding to the leaf node is represented by R _ num; the total number of memory write requests of the system when the leaf node is updated last time is represented by tick; a state flag bit for indicating whether the leaf node is idle and synchronized to Back _ BMT, in this embodiment, the state flag bit is specifically represented by 2bits of data, 00 represents unused, 01 represents used but synchronized to Back _ BMT, and 10 represents used but not synchronized to Back _ BMT; for each leaf node, recording R _ num and Tick in a form of R _ num-Tick pairs, wherein each R _ num-Tick pair occupies 64bits;
based on the maintained leaf node state table, in the advance synchronization step in this embodiment, the form _ BMT leaf nodes that are not accessed in the continuous 64-time memory write requests are identified in a manner of periodically scanning the leaf node state table;
when a leaf node with a state flag bit of 10 is not accessed in 64 consecutive memory write requests, the leaf node will be added into the synchronization queue and synchronized into Back _ BMT by the background synchronization process, and after synchronization is completed, the corresponding state flag bit will be modified to 01 to indicate that the forebmt leaf node is in use but synchronized to Back _ BMT.
Since Fore-BMT leaf nodes are limited (default is no more than 512), the storage overhead of the leaf node state table is small;
based on the maintained leaf node state table, in (S2) of the BMT updating step of this embodiment, when there is no leaf node in the form _ BMT that is idle or has been synchronized to the Back _ BMT, a way of allocating one leaf node as form _ Victim to the RBMTB is as follows:
randomly reading K continuous state information entries from a leaf node state table, identifying a Fore _ BMT leaf node which is not updated for the longest time, namely the leaf node corresponding to the entry with the minimum Tick, and allocating the Fore _ BMT leaf node as a Fore _ Vistim to the RBMTB; k is a preset positive integer, and preferably, a specific value of K is set according to the size of data read by the read request at most and the size of a single state information entry, so as to ensure that required K consecutive state information entries can be obtained through one-time reading operation; optionally, in this embodiment, the value of K is 8.
Because the access time locality is low, the possibility of subsequent access of the leaf node which is not updated for the longest time in the Fore _ BMT is low, when the Fore _ BMT does not have idle or is synchronized to the leaf node of the Back _ BMT, the leaf node state table is scanned, the leaf node of the Fore _ BMT which is not updated for the longest time is identified from partial continuous entries to be used as a replaced node, the access time locality can be fully utilized, the counter corresponding to the data block written Back recently by the current system is ensured to be protected by the Fore _ BMT, and the exchange frequency of the Fore _ BMT and the Back _ BMT is reduced.
In this embodiment, unlike the determination of the storage sequence of Back _ BMT and the binding with the corresponding data block, the sequence of the leaf nodes of the form _ BMT and the corresponding data area dynamically change with the memory write request, and when the data is written Back to the NVM area, the positioning process of the corresponding form _ BMT leaf nodes directly affects the write performance; to solve this problem, the present embodiment further designs a region index table as shown in (b) in fig. 5, which is used to record protection information of each region in the nonvolatile memory, where "region" represents a region; the protection information includes: the Fore/Back flag bit is used for indicating whether an area is protected by Fore _ BMT, in the embodiment, the Fore/Back flag bit occupies 1bit, when an area is protected by Fore _ BMT, the Fore/Back flag bit is set to 1, and when an area is evicted from Fore _ BMT, the Fore/Back flag bit is set to 0; in the embodiment, DR-Index is used for representing the information, the DR-Index occupies at most 9 bits, and the information has practical significance only when the area is protected by Fore _ BMT.
Based on the designed area index table, in this embodiment, in the BMT updating step (S1), for the Region _ BMT, that is, RBMTB, to which the form _ BMT protection needs to be added, the manner of determining whether the leaf node corresponding to the Region _ BMT exists in the form _ BMT includes:
determining a region corresponding to the RBMTB, searching an entry corresponding to the region in a region index table, if the form/Back flag bit in the region indicates that the region is protected by form _ BMT, that is, form/Back =1, determining that a leaf node corresponding to the region exists in the form _ BMT, otherwise, that is, form/Back =0, determining that a leaf node corresponding to the region does not exist in the form _ BMT.
In the NVM system, the above-mentioned leaf node status table and local index table may be cached on-chip as DR metadata to speed up its access, and the DR metadata is directly stored in plaintext as the security metadata. To ensure correct recovery, modifications to R _ num in the leaf node state table need to be written back to NVM.
It is easy to understand that, during the data write-Back process, the Fore _ BMT and Back _ BMT will be updated, and when the BMT is updated, the related information in the leaf node status table and the area index table will be updated synchronously.
In order to solve the problem that the existing secure NVM system has a long recovery time or the overhead of NVM write traffic is large in a method for accelerating the system recovery, in the node recovery step adopted in this embodiment, the recovery of a lost intermediate node is delayed until the attack is detected after the system is restarted; the node recovery step specifically includes:
for the lost node in the Back _ BMT or the Fore _ BMT, if the lost node is a leaf node, the lost node is recovered in a system crash recovery stage by using ECC;
if the node is the intermediate node, postponing the recovery until the system is restarted and then detecting the replay attack; when the system accesses an intermediate node to be recovered after restarting, a root node stored on a chip can detect replay attack; at this time, the node is recovered; during recovery, recalculating the hash value of each node on the path by using the current counter on the accessed path until reaching the root node, comparing the calculated root node with the root node stored on the chip, and if the calculated root node and the root node are consistent, recovering the intermediate node on the path by using the calculated node value; if the two are not consistent, the system is judged to have real replay attack; if the real replay attack is detected, suspending the system service and reporting an attack report;
the embodiment delays the recovery of the lost intermediate node in the BMT until the attack is detected after the system is restarted, thereby reducing the recovery operation required after the system is crashed and restarted, reducing the recovery time and ensuring the availability of the system after the system is crashed and restarted.
Example 2:
a data security processing method for a nonvolatile memory, which is similar to embodiment 1, but the embodiment further includes maintaining a specified number of cache line counters in an on-chip persistent register, preferentially searching a corresponding counter from the persistent register when data is written back, and directly updating the counter in the persistent register and encrypting and writing back the data in case of hit; in case of a miss, then read the required counter from Back _ BMT and evict a cache line counter from the persistent register to cache the read counter, the evicted cache line counter from the persistent register will be added to the Fore _ BMT protection; as shown in fig. 6, the write-back step of the present embodiment specifically includes:
(1) checking whether the corresponding counter hits in the batch update persistence register;
(2) if the data hit in the persistent register, only the counters in the persistent register and the metadata cache need to be updated, and then the data are encrypted and written back;
(3) if the persistence register is missed, reading a needed counter from Back _ BMT and caching the counter to the persistence register, meanwhile, expelling a counter node Reg _ Vistim from the persistence register, updating Region-BMT according to Reg _ Vistim, and inquiring an area index table to judge whether the Reg _ Vistim belongs to Fore _ BMT protection;
(4) if the Reg _ Vistim belongs to the Fore _ BMT protection, updating a Fore _ BMT root by an atom, then updating a counter in a persistent register, encrypting data and writing back the data;
(5) if the Reg _ Vistim belongs to Fore _ BMT protection, fore-BMT replacement occurs; during replacement, a leaf node state table is firstly inquired to judge whether a leaf node which is idle or synchronized to Back _ BMT exists in the Fore _ BMT can be used as a replacement node Fore _ Vistim;
(6) if a leaf node which is idle or is synchronized to Back _ BMT can be used as a replacement node Fore _ Vistim, directly modifying an area index table and a leaf node state table for replacement, wherein R _ num in the state needs to be written Back to the NVM to ensure recovery;
(7) if the leaf node which is not idle or is synchronized to the Back _ BMT can be used as a substitute node Fore _ Vistim, 8 continuous entries in a leaf node state table are randomly read, the Fore _ BMT leaf node with the minimum Tick is selected as the Fore _ Vistim, and the Back _ BMT root atom caused by the Fore _ Vistim is triggered to be updated at the moment; and when the Fore _ BMT is replaced, updating the Fore-BMT according to the Reg _ Vistim, finally updating a counter in the persistent register, encrypting the data and then writing back the data.
Compared with the conventional BMT, the embodiment greatly reduces the hash calculation times required by BMT root update brought by data writing.
In the embodiment, the counters of a part of cache lines are maintained in the persistent register, and when data is written back, the corresponding counters are preferentially searched from the persistent register, and in the case of hit, the counters are directly updated in the persistent register without updating the BMT node in the persistent memory, so that the number of times of accessing the nonvolatile memory in the data writing back process can be effectively reduced, and the execution efficiency of the data writing back is improved. In addition, in the secure NVM, adjacent data write-back will cause adjacent counter updating, and adjacent counter updating will cause a large number of same BMT node updating, and due to load locality and CPU cache, memory data write requests show strong spatial locality, so that these repeated BMT update operations usually occur in consecutive write requests.
Example 3:
a memory controller for a nonvolatile memory, which is configured to perform the steps of embodiment 2; the embodiment comprises the following steps: the system comprises a persistence register, an initialization module, a BMT updating module and a write-back module;
a persistence register to cache a specified number of cache line counters;
an initialization module, configured to perform the initialization step in embodiment 2 above;
a BMT update module configured to perform the BMT update step in embodiment 2;
a write-back module, configured to perform the write-back step in embodiment 2 above;
in this embodiment, the specific implementation of each module can refer to the description in embodiment 2, and will not be repeated here.
Example 3:
a secure processing system for non-volatile memory, as shown in fig. 7, comprising: a nonvolatile memory and the memory controller provided in embodiment 2 above;
as shown in fig. 7, in the present embodiment, the nonvolatile memory is divided into a DR metadata storage area, a BMT node storage area, and a secure user data storage area; a DR metadata storage area for storing DR metadata including a leaf node status table and an area index table; the BMT node storage area is used for storing BMT nodes, and the BMT nodes are nodes in Fore _ BMT or Back _ BMT; a secure user data storage area for storing encrypted user data;
in this embodiment, the memory controller further includes: a CPU cache, a security engine, a security metadata cache, a DR cache and a battery-backed NVM write queue;
the safety metadata cache is used for caching partial BMT nodes;
a DR cache for caching a part of DR metadata;
the CPU cache is used for caching the plaintext and outputting the plaintext to the security engine or reading the plaintext from the security engine;
the security engine comprises an encryption engine for encrypting and decrypting data and a BMT engine for BMT verification;
the safety engine is used for receiving the plaintext output by the CPU cache when a data write request is made, encrypting the plaintext according to the counter, outputting the ciphertext to the NVM write queue supported by the battery, and updating the BMT node according to the counter;
the security engine is also used for reading the ciphertext from the NVM write queue when a data read request is carried out, decrypting the plaintext according to the counter and outputting the plaintext to the CPU for caching; in the encryption and decryption processes, if the required counter is obtained from the security metadata cache, the counter is directly used for data encryption and decryption, and if the counter is obtained from the NVM, BMT verification is firstly carried out;
the battery-supported NVM write queue is used for receiving the ciphertext output by the security engine and outputting encrypted user data to a secure user data storage area in the NVM;
the battery-supported NVM writing queue is also used for receiving BMT nodes output by the security metadata cache and outputting the BMT to a BMT node storage area in the NVM;
the battery-supported NVM write queue is further configured to receive DR metadata output by the DR cache and output the DR metadata to a DR metadata storage area in the NVM.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A data security processing method for a nonvolatile memory is characterized by comprising the following steps:
an initialization step, comprising: constructing a Merck tree with counters of data cache lines as leaf nodes as Back _ BMT, taking a subtree with nodes in a specified layer as root nodes as Region _ BMT, and taking a nonvolatile memory space corresponding to each Region _ BMT as a Region; initializing another Mercker tree, recording the Mercker tree as Fore _ BMT, wherein leaf nodes of the Mercker tree are root nodes of the Region _ BMT, and the total number of the leaf nodes does not exceed a threshold value N;
a BMT updating step, comprising:
(S1) judging whether a leaf node corresponding to a Region _ BMT (RBMTB) needing to be added with the Fore _ BMT protection exists in the Fore _ BMT, if so, turning to the step (S3); otherwise, go to step (S2);
(S2) judging whether idle leaf nodes or leaf nodes synchronized to Back _ BMT exist in the Fore _ BMT, if yes, allocating one leaf node for RBMTB from the leaf nodes, and turning to the step (S3); otherwise, allocating a leaf node as a Fore _ Vistim for the RBMTB, and after updating Back _ BMT according to the Fore _ Vistim, turning to the step (S3);
(S3) updating the Fore _ BMT by using RBMTB;
and a write-back step, comprising: when the data block B is written Back to the nonvolatile memory from the CPU, reading a counter of the data block B to be written from the Back _ BMT and updating, then updating a Region R corresponding to the data block B, and adding the Region BMT into the Fore _ BMT for protection through the BMT updating step; and encrypting the data block B by using the updated counter, and writing the obtained ciphertext into the nonvolatile memory.
2. The data security processing method for the nonvolatile memory as claimed in claim 1, further comprising: maintaining a specified number of cache line counters in an on-chip persistence register;
in the write-Back step, before reading the counter of the data block B to be written from Back _ BMT, the method further includes:
(T1) searching a counter of the data block B from the persistent register, and if the counter is hit, turning to the step (T4); otherwise, turning to the step (T2);
(T2) selecting a cache line Reg _ Victim to be replaced from the persistence register, and reading a leaf node where a counter of the data block B is located from Back _ BMT to perform atomic replacement on the Reg _ Victim;
(T3) updating the corresponding Region _ BMT by utilizing the Reg _ Vistim, and adding the Region _ BMT into the form _ BMT for protection by utilizing the BMT updating step;
and (T4) updating a counter of the data block B in the persistent register, encrypting the data block B by using the updated counter, writing the obtained ciphertext into the nonvolatile memory, and finishing the write-back step.
3. The data security processing method for the nonvolatile memory according to claim 1 or 2, further comprising:
a node recovery step, comprising:
for the lost node in the Back _ BMT or the Fore _ BMT, if the lost node is a leaf node, the lost node is recovered in a system crash recovery stage by using ECC;
if the node is the intermediate node, postponing the recovery until the system is restarted and then detecting the replay attack; during recovery, recalculating the hash value of each node on the path by using the current counter on the accessed path until reaching the root node, comparing the calculated root node with the root node stored on the chip, and if the calculated root node and the root node are consistent, recovering the intermediate node on the path by using the calculated node value; if the two are not consistent, the system is judged to have real replay attack.
4. The data security processing method for the nonvolatile memory according to claim 3, further comprising:
an advance synchronization step, comprising: identifying leaf nodes which are not accessed in continuous M memory writing requests in the Fore _ BMT, and adding the leaf nodes into a synchronous queue; when the BMT engine is not occupied by a foreground memory read-write request, synchronizing Fore _ BMT leaf nodes in the synchronization queue to a Back _ BMT root node by using the BMT engine, and if memory access occurs in the synchronization process, terminating synchronization;
wherein M is a preset positive integer.
5. The data security processing method for the nonvolatile memory according to claim 4, wherein the initializing step further includes: establishing a leaf node state table for recording the state information of each leaf node in the Fore _ BMT; the state information comprises an area number corresponding to the leaf node, the total number of memory write requests of the system during the last updating and a state flag bit, wherein the state flag bit is used for indicating whether the leaf node is idle and is synchronized to Back _ BMT;
and in the advance synchronization step, identifying Fore _ BMT leaf nodes which are not accessed in the continuous M memory write requests in a mode of regularly scanning the leaf node state table.
6. The data security processing method for the nonvolatile memory as claimed in claim 5, wherein in the step (S2) of updating the BMT, if there is no leaf node in the form _ BMT that is idle or synchronized to the Back _ BMT, the way to allocate a leaf node as form _ view to the RBMTB is:
randomly reading K continuous state information entries from the leaf node state table, identifying a Fore _ BMT leaf node which is not updated for the longest time from the K continuous state information entries, and allocating the Fore _ BMT leaf node as a Fore _ Vistim to the RBMTB; k is a preset positive integer.
7. The data security processing method for a nonvolatile memory according to claim 6, wherein the initializing step further includes: establishing a region index table for recording the protection information of each region in the nonvolatile memory; the protection information includes: the Fore/Back identification bit is used for indicating whether the area is protected by Fore _ BMT or not, and the Fore _ BMT leaf node sequence corresponding to the area;
in step (S1) of the BMT update step, for the Region _ BMT, that is, RBMTB, to which the form _ BMT protection needs to be added, a manner of determining whether a leaf node corresponding to the Region _ BMT exists in the form _ BMT includes:
determining an area corresponding to the RBMTB, searching an entry corresponding to the area in the area index table, if the Fore/Back identification bit indicates that the area is protected by Fore _ BMT, judging that a leaf node corresponding to the area exists in the Fore _ BMT, otherwise, judging that the leaf node corresponding to the area does not exist in the Fore _ BMT.
8. A memory controller for a non-volatile memory, comprising: the system comprises an initialization module, a BMT updating module and a write-back module;
the initialization module is used for executing an initialization step; the initialization step includes: constructing a Merck tree by taking counters of all data blocks as leaf nodes, recording the Merck tree as Back _ BMT, taking a subtree in which nodes in a specified layer are taken as root nodes as Region _ BMT, and taking a nonvolatile memory space corresponding to each Region _ BMT as a Region; initializing another Mercker tree, recording the Mercker tree as Fore _ BMT, wherein leaf nodes of the Mercker tree are root nodes of the Region _ BMT, and the total number of the leaf nodes does not exceed a threshold value N;
the BMT updating module is used for executing a BMT updating step; the BMT updating step comprises the following steps:
(S1) judging whether a Region _ BMT (RBMTB) needing to be added with Fore _ BMT protection exists in the Fore _ BMT or not, if so, turning to a step (S3); otherwise, go to step (S2);
(S2) judging whether idle leaf nodes or leaf nodes synchronized to Back _ BMT exist in the Fore _ BMT, if yes, allocating one leaf node for RBMTB from the leaf nodes, and turning to the step (S3); otherwise, allocating a leaf node as a Fore _ Vistim for the RBMTB, and after updating Back _ BMT according to the Fore _ Vistim, turning to the step (S3);
(S3) updating the Fore _ BMT by using RBMTB;
the write-back module is used for executing the write-back step; the write back step includes: when the data block B is written Back to the nonvolatile memory from the CPU, reading a counter of the data block B to be written from Back _ BMT and updating, then updating a Region R corresponding to the data block B, and adding the Region BMT into Fore _ BMT protection through the BMT updating step; and encrypting the data block B by using the updated counter, and writing the obtained ciphertext into the nonvolatile memory.
9. The memory controller for a non-volatile memory as claimed in claim 8, further comprising: a persistence register to cache a specified number of cache line counters;
in the write-Back step, before reading the counter of the data block B to be written from Back _ BMT, the method further includes:
(T1) searching a counter of the data block B from the persistent register, and if the counter is hit, turning to the step (T4); otherwise, turning to the step (T2);
(T2) selecting a cache line Reg _ Visim to be replaced from the persistence register, and reading a leaf node where a counter of the data block B is located from Back _ BMT to perform atomic replacement on the Reg _ Visim;
(T3) updating the corresponding Region _ BMT by utilizing the Reg _ Vistim, and adding the Region _ BMT into the form _ BMT for protection by utilizing the BMT updating step;
and (T4) updating a counter of the data block B in the persistent register, encrypting the data block B by using the updated counter, writing the obtained ciphertext into the nonvolatile memory, and finishing the write-back step.
10. A secure processing system for non-volatile memory, comprising: a non-volatile memory and the memory controller of claim 9;
the nonvolatile memory is divided into a DR metadata storage area, a BMT node storage area and a safe user data storage area; the DR metadata storage area is used for storing DR metadata, and the DR metadata comprises a leaf node state table and an area index table; the BMT node storage area is used for storing BMT nodes, and the BMT nodes are nodes in Fore _ BMT or Back _ BMT; the safe user data storage area is used for storing encrypted user data;
the memory controller further comprises: a CPU cache, a security engine, a security metadata cache, a DR cache and a battery-backed NVM write queue;
the safety metadata cache is used for caching partial BMT nodes;
the DR cache is used for caching partial DR metadata;
the CPU cache is used for caching the plaintext and outputting the plaintext to the security engine or reading the plaintext from the security engine;
the security engine is used for receiving the plaintext output by the CPU cache when a data write request is made, encrypting the plaintext according to the counter, outputting the ciphertext to the NVM write queue supported by the battery, and updating the BMT node according to the counter;
the security engine is also used for reading a ciphertext from the NVM write queue when a data read request is made, decrypting the plaintext according to the counter and outputting the plaintext to the CPU for caching; in the encryption and decryption processes, if the required counter is obtained from the security metadata cache, the counter is directly used for data encryption and decryption, and if the counter is obtained from the NVM, BMT verification is firstly carried out;
the battery-supported NVM write queue is used for receiving the ciphertext output by the security engine and outputting encrypted user data to a secure user data storage area in the NVM;
the battery-supported NVM write queue is also used for receiving BMT nodes output by the security metadata cache and outputting the BMT to a BMT node storage area in the NVM;
the battery-supported NVM write queue is also used for receiving DR metadata output by the DR cache and outputting the DR metadata to a DR metadata storage area in the NVM;
the leaf node state table is used for recording the state information of each leaf node in the Fore _ BMT; the state information comprises an area number corresponding to the leaf node, the total number of memory write requests of the system during the last updating and a state flag bit, wherein the state flag bit is used for indicating whether the leaf node is idle and is synchronized to Back _ BMT; the area index table is used for recording the protection information of each area in the nonvolatile memory; the protection information includes: the Fore/Back flag bit is used for indicating whether the area is protected by Fore _ BMT or not, and the Fore _ BMT leaf node sequence corresponding to the area.
CN202210979822.3A 2022-08-16 2022-08-16 Data security processing method for nonvolatile memory, memory controller and system Pending CN115422604A (en)

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Publication number Priority date Publication date Assignee Title
CN117609314A (en) * 2024-01-22 2024-02-27 北京象帝先计算技术有限公司 Cache data processing method, cache controller, chip and electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117609314A (en) * 2024-01-22 2024-02-27 北京象帝先计算技术有限公司 Cache data processing method, cache controller, chip and electronic equipment

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