CN115421795A

CN115421795A - Software and hardware cooperative multi-port storage acceleration system

Info

Publication number: CN115421795A
Application number: CN202211000470.9A
Authority: CN
Inventors: 郑俊飞; 吴睿振
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-12-02

Abstract

The invention provides a software and hardware cooperative multiport storage accelerating system, which comprises: the system comprises a host, an accelerating device and a storage disc, wherein the host is used for providing a running environment of system software and is in communication connection with the accelerating device through a virtual protocol host end in the host; the acceleration device comprises a hardware unit and a firmware unit, wherein the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and device ports, the firmware unit is used for providing multiple storage disk controller drives and storage protocols, providing a virtual protocol device end interface communicated with a virtual protocol host end in a host, and combining the storage protocol interfaces of different types of storage disks into a unified storage protocol interface; the storage disk is connected to a hardware bus hung under the port of the accelerating device and used as data sent by the terminal device storage host, and therefore the utilization rate of a processor, the overall performance of the system and the portability of the system in the multi-port storage accelerating system are effectively improved.

Description

Software and hardware cooperative multi-port storage acceleration system

Technical Field

The invention relates to the field of server storage, in particular to a software and hardware cooperative multi-port storage acceleration system.

Background

The software and hardware cooperative design is a design method combining software and hardware, which makes full use of parallelism of hardware circuit and flexibility of software, divides service functions according to characteristics of processing flow, is suitable for parallel execution and is realized by handing modules irrelevant to service to hardware, thereby improving transmission performance, reducing CPU utilization rate, being suitable for serial execution, and handing modules with large service difference to software for realization, thereby customizing software flow according to actual service, and designing optimal software and hardware interfaces by reasonably dividing software and hardware modules.

With the development of information technologies such as artificial intelligence, internet of things and cloud computing, more and more intelligent hardware is developed, the service data volume related to the intelligent hardware also rises exponentially, the storage capacity requirement on a data center server is higher and higher, and in order to improve the data storage capacity of the system, researchers design a plurality of storage systems based on multiple ports, so that parallel data transmission can be performed on a plurality of storage disks based on reading of the multiple ports, the data transmission performance of the system is improved, and the storage capacity of the system is also improved.

At present, a common design method of a multi-port storage system is to design a plurality of hardware ports on a motherboard of a host, or to design a plurality of ports on an expansion board of the motherboard, and then connect the expansion board to the motherboard of the host, and then insert a plurality of storage disks into different ports, after the system is powered on, run an open source operating system such as Linux, and then load storage disk controller drivers of various interfaces and corresponding storage protocol software, thereby implementing large-capacity data storage and parallel data transmission based on a plurality of storage ports.

This approach can effectively design a multi-port memory system, but still suffers from the following problems:

the utilization rate of the processor is high; since all storage disk drives and storage protocols are run in the Host operating system, when there are many kinds of storage interfaces integrated on the Host motherboard, such as an integrated AHCI (Advanced Host Controller Interface), which is a PCI-based hardware Interface standard, a local native queue is implemented on the basis of a PCI BAR (address mapping register of a configuration space, software maps a device-defined register space to a chip processor address space by writing the register, and then software reads and writes the processor address to configure or read the device-defined register), hardware conforming to the Interface standard has various hardware interfaces such as device control, status, command table, and the like, a PCIe (peripheral component interconnect express, a high-speed Serial computer expansion bus standard), a communication protocol implementing a tree topology on a hardware level is divided into a transaction layer, a data link layer, a physical layer, a link training layer, a data transmission layer, a flow control, a power management, an interrupt control layer, and the like, and a storage Interface based on a PCIe-Host bus driver (SATA), and a storage Interface for providing a storage Interface for a higher-based on a read-write-Host bus protocol (e) and a storage Interface for providing a higher-based on a storage frequency-based on a PCI-express (e-express) storage Interface) Commands such as refreshing, resetting, managing name space and the like, and high-performance data transmission is ensured in the form of a single management queue and a plurality of input/output queues) and the like, and when the data transmission quantity is large, the utilization rate of a host processor is high;

the overall performance of the system is low; because the data storage of the host occupies higher processor utilization rate, other software and hardware modules on the system, such as network protocol stack packaging/unpacking, audio coding and decoding, graphic image rendering, artificial intelligence algorithm, compression and deletion algorithm and the like, have low data transmission or calculation performance due to insufficient processor resources, and therefore the overall performance of the system is lower;

the difficulty of application and development is high; because different driving software needs to be developed for different storage interfaces, when the host is an embedded bare computer without an operating system, a complete storage controller drive and a corresponding storage protocol need to be developed from the beginning, the requirement on the skills of software developers is high, the rapid construction of software system prototypes is not facilitated, and the development iteration cycle of software and hardware products is increased;

the software redundancy is high; in order to enable the same memory controller interface to be adaptive to chip hardware of different manufacturers in a traditional mode, each manufacturer usually adopts an open source operating system such as Linux and integrates respective drivers into the operating system, so that although code multiplexing is facilitated, the code is more complicated and disordered and is deeply coupled with system calling of the operating system;

the system portability is poor; because different controller drivers need to be developed for different storage controller interfaces, and the configuration of the controller interfaces, such as the width of a PCIe port, cannot be changed along with a user scene, when a hardware scheme is changed due to the change of system requirements, the controller driver software needs to be correspondingly modified and the storage protocol software needs to be transplanted, so that the portability of system software is poor;

the real-time performance of the system is poor; because hardware of a specific scene is not specially optimized, and a bottom half interrupt mechanism of an open source operating system such as Linux is usually adopted, the system interrupt processing flow is usually put into the bottom half of the system with a slower execution speed for interrupt execution, and when an event occurs in equipment hot plug or equipment abnormal state interrupt, the real-time performance of the system on corresponding event processing is poor;

the hybrid topology cannot be shown; because a uniform storage controller driving model does not exist, different controllers have different driving software, and bus equipment hung under different controllers is not numbered uniformly, a specific network topology display interface is needed based on the driving of a specific controller, so that a system cannot provide a uniform mixed bus topology display interface when various types of interfaces are mixed;

the system is inconvenient to debug; because the system is not provided with a debugging interface and a testing interface, when the system fails, the problem is not positioned by an effective means, a large amount of manpower and material resources are consumed for positioning the system problem, and the system development and maintenance cost is indirectly increased.

In view of the above problems, the present invention provides a multi-port memory acceleration system with software and hardware cooperation, which solves some or all of the above problems.

Disclosure of Invention

The invention aims to solve the problems in the prior art, innovatively provides a software and hardware coordinated multi-port storage accelerating system, effectively solves the problems of high processor utilization rate, low system overall performance, high system application development difficulty and poor system portability in the multi-port storage accelerating system in the prior art, effectively improves the processor utilization rate, the system overall performance and the system portability in the multi-port storage accelerating system, and reduces the system application development difficulty.

The invention provides a software and hardware coordinated multi-port storage acceleration system, which comprises: the system comprises a host, an accelerating device and a storage disc, wherein the host is used for providing a running environment of system software and is in communication connection with the accelerating device through a virtual protocol host end in the host; the acceleration device comprises a hardware unit and a firmware unit, wherein the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and device ports, the firmware unit is used for providing multiple storage disk controller drives and storage protocols, providing a virtual protocol device end interface communicated with a virtual protocol host end in a host, and combining the storage protocol interfaces of different types of storage disks into a unified storage protocol interface; the storage disk is connected to a hardware bus hung below the port of the acceleration equipment and used as data sent by the terminal equipment storage host.

Optionally, the system software includes an application system, a configuration tool, a debugging tool, and a virtual protocol host, where the configuration tool is used to provide a configuration interface driven by the application system, a storage protocol, and a storage disk controller; the debugging tool provides a debugging and testing interface for an application system, a storage protocol and a drive of a storage disk controller; the application system is an application system facing different industries; the virtual protocol host side is in communication connection with the virtual protocol device side in the firmware unit through a virtual protocol device side interface provided by the firmware unit, and is used for transmitting host data to the storage disk.

Optionally, the hardware unit includes a controller, a crossbar switch, a port, and a Flash chip, where the controller is used to provide access to a configuration space register of the bus device, link management, DMA transmission, status detection, and interrupt control; the cross bar switch is used for providing a configuration register interface of a physical cable connection relation between the controller and the port; the port is a device connectable port of the hardware bus and provides different transmission performances according to the width of a port cable; the Flash chip is used for storing the configuration parameters provided by the configuration tool.

Optionally, the firmware unit includes a physical layer driver, a virtual protocol device end, a storage disk controller driver, and a storage protocol module, where the physical layer driver is used to configure a crossbar switch in the hardware unit, implement connection of a physical cable between a controller and a device port, and construct device ports with different widths; the virtual protocol equipment end is used for packaging storage protocols of different types of storage disks into a uniform storage interface, caching data by using a cache space and transmitting the data to the disks in batches at the later stage; the storage protocol module is used for providing a command interface of the storage disk based on a data storage protocol realized by a drive of one storage disk controller; the controller driver is used for driving the corresponding hardware controller, realizing the connection relation of the storage disk devices on the controller lower hanging bus by configuring the controller register, and distributing bus addresses for the storage disk devices based on the connection relation of the storage disk devices on the controller lower hanging bus.

Further, the physical layer driver comprises a configuration module and a first initialization module, wherein the configuration module is used for reading or writing configuration parameters provided by the physical layer driver from or into the Flash chip by a configuration tool; the first initialization module is used for configuring a physical cable connection relationship between a controller and a port; the callback interface of the registered storage protocol module is used for notifying the storage protocol module when a corresponding hardware event occurs; all bus controllers are initialized.

Optionally, the controller driver includes a second initialization module, a disk control module, an interrupt processing module, and a debugging module, where the second initialization module is configured to detect connection relationships of all storage disk devices on the controller lower-hanging bus; under the condition that the insertion of the storage disk device is detected, a storage protocol disk is informed to be inserted into a port, and the storage disk starts to be read and written; the disk control module is used for reading and writing a storage disk register and a port register connected with the storage disk; removing the disk from the bus, rescanning the disk to hang it to the bus; resetting the storage disk on the bus to restore the storage disk to a default state; the interrupt processing module is used for the interrupt processing of data transmission completion, hardware state abnormity and hot plug of the storage disk; the debugging module is used for acquiring the connection relation of hardware storage disk equipment on the bus; reading and writing a storage disk register and resetting a storage disk; inquiring the working state of the storage disk and the state of the drive software; and simulating the behavior of the hardware storage disk, and testing the functions and the performances of the driving software.

Further, the initializing of the first initialization module in the physical layer driver specifically includes:

reading module configuration parameters from a Flash chip;

configuring a cross switch according to the module configuration parameters read from the Flash chip, and determining the connection relation between the controller and the port cable;

initializing a controller descriptor table, wherein the index of an entry in the controller descriptor table is a controller number; each table entry of the controller descriptor table comprises: controller type, device descriptor, topology print interface; wherein the device descriptor includes: whether the table entry is allocated to the controller, the device type, the bus address, the parent device pointer, the child device linked list and the right brother pointer;

and controlling all controllers to initialize, and transmitting a controller descriptor pointer for recording the descriptor table information of the controllers and a callback interface of the storage protocol module.

Further, in an initialization phase of the descriptor table of the controllers, configuring the device descriptor corresponding to each controller to: the controller, the controller role and the bus address space reserved by the controller chip are allocated, the parent device pointer is null, the child device linked list is null, and the right brother pointer is null.

Optionally, the initializing of the second initialization module in the controller drive specifically includes:

initializing a device descriptor table according to a controller descriptor pointer and a callback interface of a storage protocol module;

initializing a disk descriptor table according to the device descriptor table; each entry in the disk descriptor table includes: whether the table entry is allocated to a storage disk, a disk device pointer, and a port device pointer;

enumerating the bus topology in a depth-first algorithm;

and traversing the disk descriptor table, for the non-empty table entry of each port device pointer, executing disk insertion callback interface, transmitting a disk number and a disk device descriptor pointer for recording disk descriptor table information, and notifying a storage protocol module to start reading and writing the disk.

Further, initializing the device descriptor table specifically is: configuring each device descriptor to: unallocated to disk, type 0, bus address 0, parent device pointer null, child device pointer null, right sibling pointer null.

Optionally, the initialized disk descriptor table is specifically: the disk device pointer is null and the port device pointer is null, which are not allocated to the storage disk.

Optionally, enumerating the bus topology by using a depth-first algorithm specifically includes:

fetching a device descriptor from a controller descriptor table pointed to by the controller descriptor pointer, fetching an address space of the entire bus from the device descriptor, all devices on the bus allocating bus addresses from the address space;

allocating a device descriptor for each detected bus device from the device descriptor table, and updating information such as a device type, a parent device pointer, a child device pointer, a right brother pointer and the like of the device descriptor according to the bus topology;

allocating a table item for each port from a disk descriptor table, wherein the index of the table item is a disk number;

distributing and enabling a hot plug interrupt vector number for each port, distributing a table entry for each port from a preset interrupt mapping table according to the hot plug interrupt vector number, establishing mapping between the hot plug interrupt number based on the hot plug interrupt vector number and a disk number, and acquiring the disk number of the hot plug by inquiring the table when the interrupt occurs subsequently.

Further, the interrupt processing of hot plug in the interrupt processing module specifically includes: interrupt handling for disk pull-out and interrupt handling for disk insertion; wherein, the interruption processing of disk pulling specifically includes:

determining the interrupt number of the disk pulling according to the hot plug interrupt vector number and the interrupt state register;

searching a disk number corresponding to the extracted interrupt number of the disk in a preset interrupt mapping table, and searching a corresponding disk descriptor in a disk descriptor table according to the searched disk number;

determining a corresponding disk device pointer and a port device pointer according to the disk descriptor, and setting a sub-device chain table of the device descriptor pointed by the port device pointer to be null;

calling an execution disk pull-out callback interface, and transmitting a disk number and a disk device pointer;

waiting for the hardware link state machine to enter an idle state; if the link state machine enters an idle state, ending interrupt processing of disk pulling, otherwise calling a disk link exception callback interface, transmitting a disk number and a disk equipment pointer, informing a storage protocol module that the storage disk is abnormal, and ending interrupt processing of disk pulling;

the interruption processing of the disc insertion specifically includes:

waiting for the hardware link state machine to start entering a working state; if the link state machine does not enter the working state, ending interrupt processing of disk pull-out, otherwise calling a disk link exception callback interface, transmitting a disk number and a disk equipment pointer, informing a storage protocol module that the storage disk is abnormal, and ending interrupt processing of disk insertion; if the link state machine enters a working state, determining a corresponding disk device pointer and a corresponding port device pointer according to the disk descriptor, and configuring address mapping from a disk register to a processor in the acceleration device according to device descriptor information pointed by the disk device pointer;

adding a disk device pointer to a child device linked list of port device descriptors;

and calling the execution disk insertion callback interface and transmitting the execution disk insertion callback interface to a disk device pointer for informing the storage protocol module to start reading and writing the disk.

Optionally, the reading and writing of the storage disk register and the port register to which the storage disk is connected specifically include:

acquiring a disc number and an offset address;

searching a disk device pointer and a port device pointer corresponding to the disk number in a disk descriptor table;

searching bus addresses respectively corresponding to a storage disk register and a port register in a disk device descriptor and a port device descriptor;

and reading and writing the corresponding storage disk register according to the bus address and the offset address corresponding to the storage disk register, and reading and writing the corresponding port register according to the bus address and the offset address corresponding to the port register.

Optionally, resetting the storage disk on the bus to restore the storage disk to the default state specifically includes:

acquiring a disc number;

searching a disk device pointer corresponding to the disk number and a port device pointer of a port connected with a storage disk corresponding to the disk number in a disk descriptor table;

and triggering and resetting the reset register corresponding to the storage disk at the bus address corresponding to the storage disk register, and triggering and resetting the reset register corresponding to the port connected with the storage disk at the bus address corresponding to the port register.

The technical scheme adopted by the invention comprises the following technical effects:

1. the invention is based on the software and hardware cooperation angle, the multiport storage accelerating system includes: the system comprises a host, an accelerating device and a storage disc, wherein the host is used for providing a running environment of system software; the acceleration device comprises a hardware unit and a firmware unit, wherein the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and device ports, the firmware unit is used for providing multiple storage disk controller drives and storage protocols, providing a virtual protocol device end interface communicated with a virtual protocol host end in a host, and combining the storage protocol interfaces of different types of storage disks into a uniform storage protocol interface; the storage disk is connected to a hardware bus hung below a port of the acceleration equipment and used as terminal equipment for storing data issued by a host, and the differences between the controller and the storage protocol are shielded through a unified controller driving frame, a virtual storage protocol interface, a hardware cross switch and other interfaces, so that the driving and protocol development amount of the host is reduced; the problems of high processor utilization rate, low system overall performance, high system application development difficulty and poor system portability in the multi-port storage acceleration system in the prior art are effectively solved, the processor utilization rate, the system overall performance and the system portability in the multi-port storage acceleration system are effectively improved, and the system application development difficulty is reduced.

2. In the technical scheme of the invention, all the storage disk drives and the storage protocols are operated on the accelerating equipment, when the types of the storage interfaces integrated by the system are more, such as a plurality of controller interfaces integrated by AHCI, PCIe and the like, the host does not need to operate the bus drive and the storage protocols such as SATA, NVMe and the like, and when the data transmission quantity is large, the utilization rate of the host processor is greatly reduced.

3. In the technical scheme of the invention, as the data storage of the host occupies lower processor utilization rate, and other software and hardware modules of the system, such as network protocol stack processing, audio coding and decoding, graphic image rendering, artificial intelligence algorithm and compression erasure correction algorithm, have more processor resources, thereby correspondingly improving the data transmission or calculation performance, and the overall performance of the system is higher.

4. According to the technical scheme, different driving software does not need to be developed for different storage controllers, when an operating system is not used by a host, for example, the host is an embedded bare computer, application software only needs to be developed based on a simple virtual protocol interface, a complete controller driving and storage protocol does not need to be developed from beginning, the requirement on the skill of a developer is low, and the system prototype can be built quickly.

5. In the technical scheme of the invention, different driving software does not need to be developed for different storage controllers, the connection relation between the controllers and the ports can be modified along with the user scene, when the hardware scheme is changed due to the change of the system software requirement, only the configuration files corresponding to the configuration interfaces of the application system, the storage protocol and the storage disk controller driver need to be modified through the configuration tool, and the controller driver and the storage protocol software do not need to be modified, so that the software portability is better.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of a system according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating functional use provided by a physical layer driver and a controller driver in a system according to an embodiment of the present invention;

FIG. 3 is a block diagram of a software and hardware design module of an acceleration device in a system according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating initialization of a physical layer in a system according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating controller initialization in a system according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating disc numbering rules in a system according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating a process for hot plug interrupt of a disk in a system according to an embodiment of the present invention;

fig. 8 is a flowchart illustrating a read/write process of a port/disk register and a disk reset process in a system according to an embodiment of the present invention.

Detailed Description

In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.

Example one

As shown in fig. 1, the present invention provides a software and hardware coordinated multi-port storage acceleration system, which divides the whole system into 3 layers of host, acceleration device and storage disk according to functions, that is, the system includes: the system comprises a host (S001), an accelerating device (S007) and a storage disk (a type 1 disk or a type 2 disk), wherein the host is used for providing a running environment of system software (S002) and is in communication connection with the accelerating device (S007) through a virtual protocol host end (S006) inside the host; the acceleration device (S007) comprises a hardware unit (S013) and a firmware unit (S008), wherein the hardware unit (S013) is used for providing configuration registers of physical cable connection relations of different types of controllers (S014, controller 1 or controller 2) and device ports (S016), the firmware unit (S008) is used for providing a plurality of storage disk controller drivers (S012, controller 1 driver or controller 2 driver), storage protocols (S011, storage protocol 1 and storage protocol 2), and a virtual protocol device end (S010) interface which is used for providing communication with a virtual protocol host end inside the host and combining the storage protocol interfaces of different types of storage disks into a unified storage protocol interface; the storage disk is connected to a hardware bus (S017, namely a storage bus) hung under a port (S016) of the acceleration device (S007) and used as a terminal device for storing data issued by the host.

The system software (S002) in the host (S001) comprises an application system (S005), a configuration tool (S003), a debugging tool (S004) and a virtual protocol host end (S006), wherein the configuration tool (S003) is used for providing configuration interfaces of the application system (S005), a storage protocol (S011, a storage protocol 1 and a storage protocol 2), and a storage disk controller driver (S012, a controller driver 1 and a controller driver 2); the debugging tool (S004) is used for providing debugging and testing interfaces of the application system (S005), the storage protocol (S011, the storage protocol 1 and the storage protocol 2) and the storage disk controller driver (S012, the controller driver 1 and the controller driver 2); the application system (S005) is an application system facing different industries; and the virtual protocol host end (S006) is in communication connection with the virtual protocol equipment end (S010) in the firmware unit (S008) through a virtual protocol equipment end (S010) interface provided by the firmware unit (S008) and is used for transmitting the data of the host (S001) to the storage disk.

The hardware unit (S013) includes a controller (S014, controller 1 and controller 2), a crossbar switch (S015), a port (S016), and a Flash chip (not shown in fig. 1, as shown in fig. 3), where the controller (S014, controller 1 and controller 2) is configured to provide configuration space register access, link management, DMA transfer, status detection, and interrupt control for the bus device; in this embodiment, the controller is a controller (e.g., AHCI or PCIe) of a specific hardware bus, that is, a hardware adapter module, and is configured to implement a data transmission protocol based on the specific hardware bus, simplify a register configuration flow of devices on the hardware bus, reduce coding complexity of software, and do not need software to implement the bus transmission protocol again. A crossbar (S015) for providing a configuration register interface for a physical cable connection between the controller (S014) and the port (S016); the port (S016) is a device connectable port of a hardware bus, and provides different transmission performance according to the width of a port cable; the Flash chip is used for storing the configuration parameters provided by the configuration tool (S003).

Specifically, the firmware unit (S008) includes a physical layer driver (S009), a virtual protocol device terminal (S010), a storage disk controller driver (S012, i.e. controller 1 driver and controller driver 2), and a storage protocol module (S011, i.e. storage protocol 1 and storage protocol 2), where the physical layer driver (S009) is used to configure a crossbar switch (S015) in the hardware unit (S013), implement connection of physical cables between the controller and the device ports, and construct device ports (S016) with different widths; the virtual protocol equipment end (S010) is used for packaging storage protocols of different types of storage disks into a uniform storage interface, caching data by using a cache space and transmitting the data to the disks in batches at the later stage; the storage protocol module ((S011, namely the storage protocol 1 and the storage protocol 2)) is used for providing a command interface of the storage disk based on a data storage protocol realized by a drive of one storage disk controller; the storage protocol module (storage protocol) in this embodiment is specifically a software adapter module, and is used to encapsulate a software and hardware communication protocol on the basis of a controller register, so as to implement simpler reliability/security management of a device read-write interface and a link, and simplify the coding complexity of application software; the controller driver (S012) is used for driving a corresponding hardware controller (S014), realizes the connection relation of the storage disk devices on the bus under the controller (S014) by configuring a controller register, and allocates the bus address of the storage bus (S017) to the storage disk devices based on the connection relation of the storage disk devices on the bus under the controller (S014).

Specifically, as shown in fig. 2 to fig. 3, the physical layer driver includes a configuration module and a first initialization module, where the configuration module is used to read or write configuration parameters provided by the physical layer driver from or into the Flash chip by a configuration tool; the first initialization module is used for configuring a physical cable connection relation between the controller and the port; the callback interface of the registered storage protocol module is used for notifying the storage protocol module when a corresponding hardware event occurs; all bus controllers are initialized.

The controller driver comprises a second initialization module, a disk control module, an interrupt processing module and a debugging and testing module, wherein the second initialization module is used for detecting the connection relation of all storage disk devices on the controller down-hanging bus; under the condition that the insertion of the storage disk device is detected, a storage protocol disk is informed to be inserted into a port, and the storage disk starts to be read and written; the disk control module is used for reading and writing the storage disk register and the port register connected with the storage disk; removing the disk from the bus, rescanning the disk to hang it to the bus; resetting the storage disk on the bus to restore the storage disk to a default state; the interrupt processing module is used for the interrupt processing of data transmission completion, hardware state abnormity and hot plug of the storage disk; the debugging module is used for acquiring the connection relation of hardware storage disk equipment on the bus; reading and writing a storage disk register and resetting a storage disk; inquiring the working state of the storage disk and the state of the drive software; and simulating the behavior of the hardware storage disk, and testing the functions and the performances of the driving software.

Specifically, the physical layer driver and the controller driver provide the following functions:

1. and (4) controlling the disc. The method is further divided into:

(1) Disk/port register reads and writes. Reading and writing a storage disk and a register of a port connected with the storage disk;

(2) And (6) topology enumeration. Detecting the connection relation of devices on a bus under a controller to construct a bus topological graph and distributing bus addresses for the devices (namely mapping a register space of the devices to a physical address space of a processor of an accelerating device);

(3) Disc removal/rescanning. Removing the disk from the bus, rescanning the disk to hang it to the bus;

(4) The disk is reset, resetting the disk on the bus to restore it to a default state.

2. And (4) carrying out asynchronous processing. The method is further divided into:

(1) The disc transfer completes the processing. Completing interrupt processing of data transmission of the disk;

(2) And (4) processing disc exception. Interrupt processing of hardware state exception of the disk;

(3) And (5) carrying out hot plug processing on the disk. And interrupting the hot plug of the disk.

3. And (5) module configuration. The method is further divided into:

and writing the configuration parameters. Writing the module configuration parameters into the Flash chip;

and reading the configuration parameters. And reading the module configuration parameters from the Flash chip.

4. And (5) adjusting and testing the module. The method is further divided into:

and (6) topology acquisition. Acquiring a connection relation of hardware equipment on a bus;

and (4) controlling the disc. Read-write disk registers, reset disks, etc.;

and querying the state. Inquiring the working state of the disk, and inquiring the state of the driving software such as a global variable value and the like;

and (5) piling testing. And simulating hardware behaviors such as disk hot plug and the like, and testing the functions and the performances of the driving software.

In order to implement the above functions, the acceleration device is implemented by two parts, namely hardware (hardware unit) and software (firmware unit).

The hardware provides the following functions:

1. and (5) a Flash chip. The method is further divided into: and the parameter configuration can provide a parameter configuration interface of the acceleration equipment, such as an i2c bus interface of a read-write EEPROM chip.

2. A controller and a lower hanging bus thereof. The method is further divided into:

(1) And a cross switch: a physical cable connection relationship configuration register interface of the controller and the device port is provided.

(2) And (3) address mapping: bus device internal space (e.g., PCIe configuration space, BAR space registers) registers are mapped to the accelerator device processor address space for the accelerator device firmware to access the bus device registers via the processor addresses.

(3) And (3) link training: the functions of bus equipment discovery, bandwidth negotiation of equipment at two ends of a link, link state machine maintenance and the like are provided.

(4) DMA transfer: providing DMA transfer configuration functions between host memory and device internal memory.

(5) And (3) state detection: and detecting the hardware state of the equipment on the bus, such as whether the link is abnormal or not, whether hot plug occurs or not and the like.

(6) And (3) interrupt control: an interrupt signal is triggered when a link status exception is detected or when a DMA transfer between the host and the device is completed.

The software provides the following functions:

1. and driving by a physical layer. The method is further divided into:

(1) And (4) configuring. The method is further divided into: reading parameters, namely reading configuration parameters of the module from the Flash chip; and writing parameters, namely writing the configuration parameters of the module into the Flash chip.

(2) And (5) initializing. The method is further divided into the following steps:

1) Port configuration: configuring a physical cable connection relationship between a controller and a port;

2) Callback interface registration: registering a callback interface of the storage protocol, such as a callback interface for completing data transmission, abnormal equipment state and notifying hot plug of the equipment, and notifying the storage protocol when a corresponding hardware event occurs;

3) The controller is initialized: initializing all bus controllers;

2. a controller (e.g., PCIe RC) driver. The method is further divided into:

(1) And (5) initializing. The method is further divided into the following steps:

1) And (6) topology enumeration. Detecting the connection relation of all devices on a lower hanging bus of the controller;

2) Disc insertion is notified. Informing the storage protocol disk to be inserted into the port, and starting to read and write the disk;

an example flow of software and hardware module interaction is shown in FIG. 3:

the configuration tool writes module configuration parameters (such as user scene identification describing the physical cable connection relation between a controller and a port) into a Flash chip through a parameter write-in interface provided by a physical layer driver;

the physical layer driving initialization module calls a parameter reading interface to read the module configuration parameters from the Flash chip, and then registers a callback interface of a storage protocol, such as data transmission completion, equipment state abnormity, equipment hot plug notification and the like;

the physical layer driving initialization module calls a controller initialization interface to initialize all hardware bus controllers;

the controller initialization module calls a topology enumeration interface, accesses a device configuration space register through an address mapping mechanism, and detects whether devices corresponding to a specific bus number and a device number exist or not so as to confirm the connection relation of each device on the bus;

calling a storage protocol callback interface to notify a storage protocol that the disk can be read or written when the existence of the storage disk is detected;

the hardware triggers an interrupt signal to notify the firmware when detecting that the disk link state is abnormal, the DMA transmission is finished and the disk is hot-plugged, and the firmware calls a corresponding callback interface to notify a storage protocol after preprocessing (such as clearing an interrupt state register);

the debugging tool calls a debugging interface (topology acquisition, disk control, state query and piling test) to execute debugging;

the debugging interface calls a disk control interface (read-write port/disk register, disk removal/rescan/reset, etc.) control disk;

and the debugging interface returns the execution result of the debugging interface to the debugging tool.

Further, as shown in fig. 4, the initializing of the first initialization module in the physical layer driver specifically includes:

reading module (physical layer) configuration parameters from a Flash chip; wherein, the specific configuration parameters include:

1. the system comprises a scene identifier, a port identifier and a controller, wherein the scene identifier is used for identifying different user scenes, and each user scene represents a specific controller and port cable connection relation;

2. the controller bus address space, i.e. the bus address space of each controller, includes:

(1) Type (2): controller types such as AHCI, PCIe, etc.;

(2) Start/end address: the method comprises the following steps that a controller hangs down an accelerating device processor address space which can be mapped by all devices of a bus;

(3) An address unit: the method comprises the following steps that a controller hangs down a maximum processor address space which can be mapped by each device of a bus;

initializing a controller descriptor table, wherein the index of an entry in the controller descriptor table is a controller number; each table entry of the controller descriptor table comprises: controller type (controller type such as AHCI, PCIe, etc.), device descriptor, topology print interface (topology print interface for a particular controller); wherein the device descriptor includes: whether an entry is allocated to a controller (indicating whether the entry is allocated to a certain controller), a device type (indicating a device role, including a type 1 controller (a controller of a certain interface such as PCIe), a type 2 controller, a cascade device (a device for expanding the number of bus ports such as PCIe Switch), a port (a device for connecting a disk), a type 1 disk (a disk of a certain interface, corresponding to the type 1 controller), a type 2 disk, a device may have multiple roles at the same time, such as a root bus device of a direct connection disk is both a controller and a port), a bus address (an accelerated device processor physical address that can be mapped to a device register, after address mapping is established, firmware may indirectly read and write a device register by reading and writing the address), a parent device pointer (a device descriptor pointer (a memory address) of a device at a previous level of a certain device on the bus), a child device linked list (a device descriptor pointer linked list of a device pointer of a device at a next level of a certain device on the bus), and a right sibling pointer (a device descriptor pointer at a right side of a device at the same level of a certain device on the bus);

Specifically, the initializing of the second initialization module in the controller driver specifically includes:

initializing a disk descriptor table according to the device descriptor table; each entry in the disk descriptor table includes: whether the disk is inserted into the port, the device descriptor pointer of the disk is added to a sub-device linked list of the device descriptor of the port when the disk is inserted into the port, the disk is a sub-device of the port, and the disk is not added to the sub-device linked list, the port device pointer (the device descriptor pointer of the port connected with the disk and the device descriptor pointer for recording the port device information, the port device pointer of a table corresponding to a certain disk number is null, the port does not exist, such as PCIe Switch is not connected);

enumerating the bus topology with a depth-first algorithm;

Further, initializing the device descriptor table specifically is: configuring each device descriptor to: unallocated to the disk, type 0, bus address 0, parent device pointer null, child device pointer null, right sibling pointer null.

Further, the initialized disk descriptor table specifically is: the disk device pointer is null and the port device pointer is null, which are not allocated to the storage disk.

Specifically, enumerating the bus topology by the depth-first algorithm specifically includes:

allocating a table item for each port from a disk descriptor table, wherein the index of the table item is a disk number; the disc numbering rules are as shown in fig. 6;

allocating and enabling a hot plug interrupt vector number for each port, allocating a table entry for each port from a preset interrupt mapping table according to the hot plug interrupt vector number, establishing mapping between the hot plug interrupt number (for example, the hot plug interrupt number may be the hot plug interrupt vector number + the interrupt status register bit number) and the disk number based on the hot plug interrupt vector number, and acquiring the disk number of the hot plug by querying the table when the interrupt occurs subsequently.

Further, as shown in fig. 7, the interrupt processing of hot plug in the interrupt processing module specifically includes: interrupt handling for disk pull-out and interrupt handling for disk insertion; wherein, the interruption processing of disk pull-out specifically includes:

determining the interrupt number of the disk pulling according to the hot plug interrupt vector number and the interrupt state register; each bit in the interrupt status register indicates that a port disk is pulled out or inserted, the interrupt number can be an interrupt vector number + an interrupt status register bit number, namely the interrupt number can be the sum of the interrupt vector number and the interrupt status register bit number, or the sum of the interrupt vector number and the number of bits of the interrupt status register bit number can be directly added, and the invention is not limited herein;

searching a disk number (disk _ num) corresponding to an interrupt number of the pulled disk in a preset interrupt mapping table, and searching a corresponding disk descriptor in a disk descriptor table according to the searched disk number;

determining a corresponding disk device pointer and a port device pointer according to the disk descriptor, and setting a sub-device link list of the device descriptor pointed by the port device pointer to be null (namely indicating that the port has no external disk);

calling an execution disk pull-out callback interface, transmitting a disk number and a disk device pointer, and notifying a storage protocol to stop reading and writing the disk;

waiting for the hardware link state machine to enter an idle state; the method specifically comprises the following steps: the controller is related to, for example, a PCIe controller can configure a space register through an inquiry port, if the link state machine enters an idle state, interrupt processing of disk pulling is ended, otherwise, a disk link exception callback interface is called and a disk number and a disk device pointer are transmitted, a storage protocol module is notified that the storage disk is abnormal, and the interrupt processing of disk pulling is ended;

the interruption processing of the disc insertion specifically includes:

waiting for the hardware link state machine to start entering a working state; if the link state machine does not enter the working state, ending interrupt processing of disk pull-out, otherwise calling a disk link exception callback interface, transmitting a disk number and a disk equipment pointer, informing a storage protocol module that the storage disk is abnormal, and ending interrupt processing of disk insertion; if the link state machine enters a working state, determining a corresponding disk device pointer and a corresponding port device pointer according to the disk descriptor, and configuring address mapping from a disk register to a processor in the acceleration device according to device descriptor information pointed by the disk device pointer (according to device descriptor information pointed by the disk device pointer, such as a bus address, and the like, by writing a bus address to an address mapping register of a disk configuration space, such as a PCIe BAR register, mapping the disk custom register space to the processor address space of the acceleration device is realized, and the disk custom register can be read and written by firmware through the processor address space in the following process);

adding a disk device pointer to a child device linked list of port device descriptors, i.e., indicating that the disk is a child device of a port;

and calling the execution disk to insert the callback interface and transmitting the callback interface to a disk device pointer for informing the storage protocol module to start reading and writing the disk.

Further, as shown in fig. 8, the read/write memory disk register and the port register to which the memory disk is connected specifically include:

acquiring a disc number and an offset address;

Resetting the storage disk on the bus to restore the storage disk to the default state specifically includes:

acquiring a disc number;

searching a disk device pointer corresponding to a disk number and a port device pointer of a port connected with a storage disk corresponding to the disk number in a disk descriptor table;

The invention is based on the software and hardware cooperation angle, the multiport storage accelerating system includes: the system comprises a host, an accelerating device and a storage disc, wherein the host is used for providing a running environment of system software; the acceleration device comprises a hardware unit and a firmware unit, wherein the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and device ports, the firmware unit is used for providing multiple storage disk controller drives and storage protocols, providing a virtual protocol device end interface communicated with a virtual protocol host end in a host, and combining the storage protocol interfaces of different types of storage disks into a uniform storage protocol interface; the storage disk is connected to a hardware bus hung below a port of the acceleration equipment and used as terminal equipment for storing data issued by a host, and the differences between the controller and the storage protocol are shielded through a unified controller driving frame, a virtual storage protocol interface, a hardware cross switch and other interfaces, so that the driving and protocol development amount of the host is reduced; the problems of high processor utilization rate, low system overall performance, high system application development difficulty and poor system portability in the multi-port storage acceleration system in the prior art are effectively solved, the processor utilization rate, the system overall performance and the system portability in the multi-port storage acceleration system are effectively improved, and the system application development difficulty is reduced.

In the technical scheme of the invention, all the storage disk drives and the storage protocols are operated on the accelerating equipment, when the types of the storage interfaces integrated by the system are more, such as a plurality of controller interfaces integrated by AHCI, PCIe and the like, the host does not need to operate the bus drive and the storage protocols such as SATA, NVMe and the like, and when the data transmission quantity is large, the utilization rate of the host processor is greatly reduced.

In the technical scheme of the invention, as the data storage of the host occupies lower processor utilization rate, and other software and hardware modules of the system, such as network protocol stack processing, audio coding and decoding, graphic image rendering, artificial intelligence algorithm and compression erasure correction algorithm, have more processor resources, thereby correspondingly improving the data transmission or calculation performance, and the overall performance of the system is higher.

According to the technical scheme, different driving software does not need to be developed for different storage controllers, when the host does not use an operating system, for example, the host is an embedded bare computer, application software only needs to be developed based on a simple virtual protocol interface, a complete controller driving and storage protocol does not need to be developed from beginning, the requirement on the skills of developers is low, and the system prototype can be built quickly.

In the technical scheme of the invention, different driving software does not need to be developed for different storage controllers, the connection relation between the controllers and the ports can be modified along with the user scene, when the hardware scheme is changed due to the change of the system software requirement, only the configuration files corresponding to the configuration interfaces of the application system, the storage protocol and the storage disk controller driver need to be modified through the configuration tool, and the controller driver and the storage protocol software do not need to be modified, so that the software portability is better.

In the technical scheme of the invention, the controller drivers of all manufacturers are integrated into the same operating system such as Linux (firmware unit in accelerating equipment) without adapting the same type of controller driver to controller chips of different manufacturers, and the controller drivers are developed based on a specific programming language such as GNU C without depending on any operating system interface, so that the code is concise and decoupled from the operating system, and therefore, the software redundancy is lower.

In the technical scheme of the invention, because a bottom half interrupt mechanism of an open source operating system such as Linux is not adopted, the interrupt processing flow of the system is not put into the interruption of the bottom half of the system with lower execution speed but is executed by an interrupt processing module in a controller drive, when hot plug or abnormal interrupt of the equipment state occurs, the interrupt processing module can quickly process the interruption of disk read-write completion/hot plug/abnormal link and the like by inquiring an interrupt mapping table, a disk descriptor table based on an interrupt mapping table, a disk descriptor table, a disk read-write completion/hot plug/abnormal link callback interface and the unified disk numbers of various controller buses, so the real-time performance of the interrupt processing of the system is better.

In the technical scheme of the invention, because different types of controllers have uniform controller driving frameworks (controller driving internal function modules) and have uniformly numbered all devices of the bus, the topology display interfaces of a specific controller are uniformly registered in the controller descriptors corresponding to the specific controller, and when the various types of controllers are mixed, the bus topologies of all the controllers can be displayed by using the uniform interfaces.

In the technical scheme of the invention, because the system is provided with the reserved debugging and testing interface and the debugging and testing tool is arranged in the host, when the system fails, the problem of the system can be positioned, a large amount of manpower and material resources cannot be consumed for positioning the problem of the system, and the development and maintenance cost of the system is indirectly reduced.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims

1. A hardware and software cooperative multiport memory acceleration system is characterized by comprising: the system comprises a host, an accelerating device and a storage disc, wherein the host is used for providing a running environment of system software and is in communication connection with the accelerating device through a virtual protocol host end in the host; the acceleration device comprises a hardware unit and a firmware unit, wherein the hardware unit is used for providing configuration registers of physical cable connection relations of different types of controllers and device ports, the firmware unit is used for providing multiple storage disk controller drives and storage protocols, providing a virtual protocol device end interface communicated with a virtual protocol host end in a host, and combining the storage protocol interfaces of different types of storage disks into a uniform storage protocol interface; the storage disk is connected to a hardware bus hung below the port of the acceleration equipment and used as data sent by the terminal equipment storage host.

2. The system software comprises an application system, a configuration tool, a debugging tool and a virtual protocol host end, wherein the configuration tool is used for providing a configuration interface driven by the application system, a storage protocol and a storage disk controller; the debugging tool provides a debugging and testing interface for an application system, a storage protocol and a drive of a storage disk controller; the application systems are application systems facing different industries; the virtual protocol host side is in communication connection with the virtual protocol device side in the firmware unit through a virtual protocol device side interface provided by the firmware unit, and is used for transmitting host data to the storage disk.

3. The system of claim 1, wherein the hardware unit comprises a controller, a crossbar switch, a port and a Flash chip, and the controller is used for providing access to configuration space registers, link management, DMA transmission, state detection and interrupt control of the bus device; the cross bar switch is used for providing a configuration register interface of a physical cable connection relation between the controller and the port; the port is a device connectable port of a hardware bus and provides different transmission performances according to the width of a port cable; the Flash chip is used for storing the configuration parameters provided by the configuration tool.

4. The system according to claim 1, wherein the firmware unit comprises a physical layer driver, a virtual protocol device side, a storage disk controller driver, and a storage protocol module, the physical layer driver is used for configuring a crossbar switch in the hardware unit, implementing connection of physical cables between the controller and the device ports, and constructing device ports with different widths; the virtual protocol equipment end is used for packaging storage protocols of different types of storage disks into a uniform storage interface, caching data by using a cache space and transmitting the data to the disks in batches at the later stage; the storage protocol module is used for providing a command interface of the storage disk based on a data storage protocol realized by a drive of one storage disk controller; the controller driver is used for driving the corresponding hardware controller, realizing the connection relation of the storage disk devices on the controller lower hanging bus by configuring the controller register, and distributing bus addresses for the storage disk devices based on the connection relation of the storage disk devices on the controller lower hanging bus.

5. The system according to claim 4, wherein the physical layer driver comprises a configuration module and a first initialization module, the configuration module is used for reading or writing configuration parameters provided by the physical layer driver from or into a Flash chip by a configuration tool; the first initialization module is used for configuring a physical cable connection relationship between a controller and a port; the callback interface of the registered storage protocol module is used for notifying the storage protocol module when a corresponding hardware event occurs; all bus controllers are initialized.

6. The software and hardware cooperative multi-port storage acceleration system of claim 4, wherein the controller driver comprises a second initialization module, a disk control module, an interrupt processing module and a debugging module, wherein the second initialization module is used for detecting the connection relationship of all storage disk devices on the controller under-hanging bus; under the condition that the insertion of the storage disk device is detected, a storage protocol disk is informed to be inserted into a port, and the storage disk starts to be read and written; the disk control module is used for reading and writing a storage disk register and a port register connected with the storage disk; removing the disk from the bus, rescanning the disk to hang it to the bus; resetting the storage disk on the bus to restore the storage disk to a default state; the interrupt processing module is used for the interrupt processing of data transmission completion, hardware state abnormity and hot plug of the storage disk; the debugging module is used for acquiring the connection relation of hardware storage disk equipment on the bus; reading and writing a storage disk register and resetting a storage disk; inquiring the working state of the storage disk and the state of the drive software; and simulating the behavior of the hardware storage disk, and testing the functions and the performances of the driving software.

7. The hardware-software multi-port memory acceleration system of claim 6, wherein the initialization of the first initialization module in the physical layer driver specifically comprises:

reading module configuration parameters from a Flash chip;

8. The software and hardware coordinated multi-port memory acceleration system of claim 7, wherein in the initialization phase of the descriptor table of the controller, the device descriptor corresponding to each controller is configured to: the controller, the controller role and the bus address space reserved by the controller chip are allocated, the parent device pointer is null, the child device linked list is null, and the right brother pointer is null.

9. The software and hardware coordinated multi-port memory acceleration system of claim 6, wherein the initialization of the second initialization module in the controller driver specifically comprises:

enumerating the bus topology with a depth-first algorithm;

10. The software and hardware coordinated multi-port memory acceleration system of claim 9, wherein the initialization device descriptor table is specifically: configuring each device descriptor to: unallocated to disk, type 0, bus address 0, parent device pointer null, child device pointer null, right sibling pointer null.

11. A software and hardware coordinated multi-port memory acceleration system according to claim 9, characterized in that the initialization disk descriptor tables are in particular: the disk device pointer is null and the port device pointer is null, which are not allocated to the storage disk.

12. The system of claim 9, wherein enumerating the bus topology by a depth-first algorithm comprises:

distributing and enabling a hot plug interrupt vector number for each port, distributing a table entry for each port from a preset interrupt mapping table according to the hot plug interrupt vector number, establishing mapping between the hot plug interrupt number and a disk number based on the hot plug interrupt vector number, and acquiring the disk number of the hot plug by inquiring the table when interrupt occurs subsequently.

13. The software and hardware coordinated multi-port memory acceleration system of claim 12, wherein the hot-plug interrupt handling in the interrupt handling module specifically comprises: interrupt handling for disk pull-out and interrupt handling for disk insertion; wherein, the interruption processing of disk pull-out specifically includes:

determining the interrupt number of the disk pulling out according to the hot plug interrupt vector number and the interrupt state register;

the interruption processing of the disc insertion specifically includes:

14. The software and hardware coordinated multi-port memory acceleration system of claim 12, wherein the read-write disk register and the port register to which the disk is connected specifically include:

acquiring a disc number and an offset address;

15. A software and hardware coordinated multi-port memory acceleration system according to claim 12, wherein resetting the memory disk on the bus to restore the memory disk to a default state comprises:

acquiring a disc number;