CN115412407B

CN115412407B - Channel estimation method, device and related equipment

Info

Publication number: CN115412407B
Application number: CN202110587587.0A
Authority: CN
Inventors: 朱清; 刘晟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2024-05-17
Anticipated expiration: 2041-05-27
Also published as: CN115412407A

Abstract

The present application relates to the field of optical communications, and in particular, to a channel estimation method, apparatus, and related device. The method comprises the following steps: the electrical chip obtains a channel correlation matrix of the target wireless channel and determines a first inverse of a diagonal element matrix of the channel correlation matrix. The electrical chip determines a first matrix to be multiplied according to the channel correlation matrix, and determines a preset value of a first parameter matrix according to a first inverse matrix. The electric chip and the optical chip cooperatively calculate to obtain a first product of the first to-be-multiplied matrix and the first parameter matrix. And the electrical chip determines a target inverse matrix corresponding to the channel correlation matrix according to the first product. And the electric chip determines the transmitting vector of the target wireless channel according to the target inverse matrix and the receiving vector of the target wireless channel. By the embodiment of the application, the efficiency of channel estimation can be improved and the power consumption can be reduced.

Description

Channel estimation method, device and related equipment

Technical Field

The present application relates to the field of communications, and in particular, to a channel estimation method, apparatus, and related devices.

Background

With the continuous development of communication technology, communication systems have developed in a trend of large capacity, high efficiency and high throughput. In practical applications, multiple wireless channels may be used for signal transmission between a signal sender and a signal receiver in a communication system. Cross talk, etc. may exist between different wireless channels, so that signals are cracked, thereby affecting the performance of the communication system. In order to improve performance of a communication system, channel estimation is generally performed on a wireless channel in the communication system, and operations such as channel compensation are performed according to a result of the channel estimation to improve channel capacity, thereby improving performance of the communication system. Since the result of channel estimation directly determines whether channel compensation and other operations are effective, there is an increasing concern about the efficiency and accuracy of channel estimation.

In the prior art, the entire channel estimation process is typically performed on digital integrated circuits such as graphics processing units (GRAPHICAL PROCESSING UNITS, GPUs), programmable gate arrays (field programmable GATE ARRAYS, FPGAs), application-specific integrated circuits (ASICs), and the like. However, due to slow development of moore's law, the existing digital integrated circuit has problems of large power consumption and slow calculation speed, and in a communication scenario such as wireless large-scale multiple-input multiple-output (MIMO) communication, a large amount of data operation operations are involved in a channel estimation process of a wireless channel, so that the efficiency is low and the power consumption is large when the channel estimation is performed through the digital integrated circuit, and the performance of the communication system is seriously affected.

Disclosure of Invention

In order to solve the above problems, the present application provides a channel estimation method, apparatus and related devices, which can improve the efficiency of channel estimation and reduce power consumption, and can improve the performance of a communication system.

In a first aspect, an embodiment of the present application provides a channel estimation method. The channel estimation method may be applied to a channel estimation device, which may include an electrical chip and an optical chip connected to each other. The method comprises the following steps: and acquiring a channel incidence matrix of the target wireless channel through the electric chip, and determining a first inverse matrix of a diagonal element matrix of the channel incidence matrix. And determining a first matrix to be multiplied according to the channel incidence matrix through the electric chip, and determining a preset value of a first parameter matrix according to the first inverse matrix. And normalizing the first to-be-multiplied matrix through the electric chip to obtain a first conversion matrix, and transmitting the first conversion matrix to the optical chip. Wherein, the absolute value of the value of any matrix element in the first conversion matrix is smaller than or equal to 1. And carrying out normalization processing on m column vectors of the first parameter matrix through the electric chip to obtain m first column vectors. Wherein the absolute value of the value of any vector element of each first column vector in the m first column vectors is less than or equal to 1, and m is an integer greater than or equal to 2. Transmitting any first column vector j of the m first column vectors to the optical chip by the electrical chip. And multiplying the first conversion matrix and the first column vector j by the optical chip to obtain a multiplication result of the first conversion matrix and the first column vector j, and transmitting the multiplication result of the first conversion matrix and the first column vector j to the electrical chip. And determining a first product of the first matrix to be multiplied and the first parameter matrix by the electric chip according to the multiplication result of the first conversion matrix and each first column vector in the m first column vectors. And determining a target inverse matrix corresponding to the channel correlation matrix according to the first product through the electric chip. And determining the transmitting vector of the target wireless channel by the electric chip according to the target inverse matrix and the receiving vector of the target wireless channel.

In the implementation, the target inverse matrix of the channel correlation matrix is obtained through the cooperative calculation of the electric chip and the optical chip, and then the emission vector x of the target wireless channel is obtained through the calculation according to the target inverse matrix and the receiving vector y of the target wireless channel, so that the channel estimation of the target wireless channel is completed. The multiplication of matrix and vector involved in the whole calculation process is mainly realized by an optical chip. Because the time required by multiplication operation through the optical chip is short and the power consumption is low, compared with the existing mode of carrying out wireless communication arrival estimation through the digital integrated circuit, the mode of carrying out wireless channel estimation by adopting the electric chip and the optical chip in a cooperative way has faster speed and lower power consumption, can effectively improve the efficiency of channel estimation and reduce the power consumption, and further can improve the performance of a communication system where the channel estimation device is positioned.

With reference to the first aspect, in a possible implementation manner, the channel correlation matrix and the first inverse matrix are complex matrices, and the first to-be-multiplied matrix includes a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix. The real and imaginary matrices of the channel correlation matrix may be determined by the electrical chip. And partitioning a real part matrix of the channel correlation matrix by the electric chip to obtain the first to-be-multiplied submatrix. And blocking the imaginary matrix of the channel correlation matrix by the electric chip to obtain the second submatrix to be multiplied.

With reference to the first aspect, in a possible implementation manner, a real matrix of the first inverse matrix may be determined by the electrical chip. And determining a real part matrix of the first inverse matrix as a preset value of a first parameter matrix through the electric chip.

With reference to the first aspect, in a possible implementation manner, the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix, and the first product includes a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of the second to-be-multiplied block matrix and the first parameter matrix. The imaginary part matrix of the first inverse matrix can be determined through the electric chip, and the imaginary part matrix of the first inverse matrix is determined to be the value of a preset second parameter matrix. And carrying out normalization processing on m column vectors of the second parameter matrix through the electric chip to obtain m second column vectors. Wherein, the absolute value of the value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1. And sequentially transmitting each second column vector in the m second column vectors to the optical chip through the electrical chip. And multiplying the first conversion submatrix and the second conversion submatrix with the second column vectors respectively through the optical chip to obtain multiplication results of the first conversion submatrix and the second column vectors, and multiplication results of the second conversion submatrix and the second column vectors, and transmitting the multiplication results of the first conversion submatrix and the second column vectors to the electric chip. And determining a third sub-product of the first submatrix to be multiplied and the second parameter matrix by the electric chip according to the multiplication result of the first conversion submatrix and each second column vector, and determining a fourth sub-product of the second submatrix to be multiplied and the second parameter matrix according to the multiplication result of the second conversion submatrix and each second column vector. And determining a target inverse matrix corresponding to the channel correlation matrix by the electric chip according to the first sub-product, the second sub-product, the third sub-product and the fourth sub-product.

With reference to the first aspect, in a possible implementation manner, a portion of the real part matrix of the channel correlation matrix except for the first to-be-multiplied submatrix may be determined as a third to-be-multiplied submatrix by the electrical chip. And determining the part except the second submatrix to be multiplied in the imaginary part matrix of the channel correlation matrix as a fourth submatrix to be multiplied by the electric chip. And respectively carrying out normalization processing on the third to-be-multiplied submatrix and the fourth to-be-multiplied submatrix through the electric chip to obtain a third conversion submatrix and a fourth to-be-multiplied submatrix. And the absolute value of the value of any matrix element in the third conversion submatrix and the fourth submatrix to be multiplied is smaller than or equal to 1. Transmitting the third and fourth conversion sub-matrices to the optical chip via the electrical chip. And sequentially transmitting each first column vector to the optical chip through the electrical chip. And multiplying the third conversion sub-matrix and the fourth conversion sub-matrix with the first column vectors respectively through the optical chip to obtain a multiplication result of the third conversion sub-matrix and the first column vectors and a multiplication result of the fourth conversion sub-matrix and the first column vectors, and transmitting the multiplication result of the third conversion sub-matrix and the first column vectors and the multiplication result of the fourth conversion sub-matrix and the first column vectors to the electrical chip. And determining a fifth sub-product of the third to-be-multiplied sub-matrix and the first parameter matrix according to the multiplication result of the third conversion sub-matrix and each first column vector through the electric chip, and determining a sixth sub-product of the fourth to-be-multiplied sub-matrix and the first parameter matrix according to the multiplication result of the fourth conversion sub-matrix and each first column vector. And determining a target inverse matrix corresponding to the channel correlation matrix by the electric chip according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product and the sixth sub-product.

With reference to the first aspect, in a possible implementation manner, the second column vectors may be sequentially transmitted to the optical chip through the electrical chip. And multiplying the third conversion sub-matrix and the fourth conversion sub-matrix with each second column vector through the optical chip to obtain a multiplication result of the third conversion sub-matrix and each second column vector and a multiplication result of the fourth conversion sub-matrix and each second column vector, and transmitting the multiplication result of the third conversion sub-matrix and each second column vector and the multiplication result of the fourth conversion sub-matrix and each second column vector to the electrical chip. And determining a seventh sub-product of the third conversion sub-matrix and the second parameter matrix according to the multiplication result of the third conversion sub-matrix and each second column vector through the electric chip, and determining an eighth sub-product of the fourth to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the fourth conversion sub-matrix and each second column vector. And determining a target inverse matrix corresponding to the channel incidence matrix through the electric chip according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-matrix and the eighth sub-matrix.

In the implementation, in the subsequent calculation process of the values of the third matrix parameter and the fourth matrix parameter to be calculated or in the cross multiplication between a plurality of matrices and a plurality of vectors, in order to simplify the steps, two different matrices which need to be multiplied by the same vector are segmented and the segmented matrices of the two matrices are loaded on the optical chip at the same time, then the corresponding multiplication operation (such as the calculation process of the eighth sub-product of the first sub-product) is completed by adopting a vector cyclic refreshing loading mode, and then the segmented calculation results are spliced to obtain the values of the third parameter matrix and the fourth parameter matrix, so that compared with the mode of sequentially multiplying a single matrix and a single vector, the occupation of the storage space of the electrical chip 21 can be effectively reduced, and the performance requirement on the electrical chip 21 can be reduced.

With reference to the first aspect, in a possible implementation manner, a first sub-value of a preset third parameter matrix may be determined by the electrical chip according to the first sub-product and the fourth sub-product. And determining a first sub-value of a preset fourth parameter matrix according to the second sub-product and the third sub-product through the electric chip. And determining a second subvalue of the third parameter matrix according to the fifth subproduct and the eighth subproduct through the electric chip. And determining a second subvalue of the fourth parameter matrix by the electric chip according to the sixth subproduct and the seventh subproduct. And determining the value of the third parameter matrix through the electric chip according to the first subvalue and the third subvalue. And determining the value of the fourth parameter matrix through the electric chip according to the second subvalue and the fourth subvalue. And determining a value of a real part iteration result by the electric chip according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset first iteration formula. Wherein the first iterative formula comprises:

D_R＝2×R-R×J+T×K

wherein D _R is the real part iteration result, R is the first parameter matrix, T is the second parameter matrix, J is the third parameter matrix, and K is the fourth parameter matrix.

The value of the virtual part iteration result can be determined and obtained through the electrical chip according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset second iteration formula, wherein the second iteration formula comprises:

D_T＝2×T-R×K-T×J

Wherein D _T is the imaginary iteration result; and the electric chip adds 1 to the value of the preset iteration frequency parameter.

Before the value of the iteration number parameter is determined to be not equal to the preset iteration number t by the electrical chip, repeating the following operations: and determining the value of the real part iteration result obtained by the last time according to the first iteration formula as a new value of the first parameter matrix through the electric chip, and determining the value of the imaginary part iteration result obtained by the last time according to the second iteration formula as a new value of the second parameter matrix. And re-determining the new values of the third parameter matrix and the fourth parameter matrix according to the first parameter matrix with the new values, the second parameter matrix with the new values and the real part and the imaginary part of the normalized channel correlation matrix through the electric chip. And determining the new value of the real part iteration result through the electric chip according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the first iteration formula. And determining and obtaining the new value of the virtual part iteration result through the electrical chip according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the second iteration formula. And adding 1 to the value of the iteration frequency parameter through the electric chip. And determining the target inverse matrix of the channel correlation matrix according to the value of the real part iteration result and the value of the imaginary part iteration result obtained at the t time until the value of the iteration number parameter is equal to the preset iteration number t through the electric chip.

In the implementation, the inversion process of the channel correlation matrix is converted into the operation processes of multiplication, addition and subtraction among a plurality of matrixes through the preset first iteration formula and the preset second iteration formula, and feasibility is provided for the electric chip and the optical chip to cooperatively calculate the target inverse matrix of the channel correlation matrix. And in the case that the channel correlation matrix is a complex matrix, the processes of cross multiplication of a plurality of matrixes involved in the whole inversion process are simplified through matrix blocking, vector cyclic assignment and other modes, the memory space occupation of an electric chip is reduced, the increase of calculation amount caused by repeated assignment and calculation of the matrixes and the vectors of the optical chip is avoided, and the efficiency of channel estimation can be improved.

With reference to the first aspect, in a possible implementation manner, the channel correlation matrix and the first inverse matrix are complex matrices, and the first to-be-multiplied matrix includes a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix. The real and imaginary matrices of the channel correlation matrix may be determined by the electrical chip. And determining a real part matrix of the channel correlation matrix as the first submatrix to be multiplied by the electric chip, and determining an imaginary part matrix of the first channel correlation matrix as the second submatrix to be multiplied by the electric chip. And determining a real part matrix of the first inverse matrix through the electric chip. And determining a real part matrix of the first inverse matrix as a preset value of a first parameter matrix through the electric chip.

With reference to the first aspect, in a possible implementation manner, the optical chip includes a first sub-optical chip and a second sub-optical chip, where the first sub-optical chip and the second sub-optical chip are connected with the electrical chip, the first product includes a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of the second to-be-multiplied sub-matrix and the first parameter matrix, and the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix.

The imaginary matrix of the first inverse matrix can be determined by the electrical chip as a preset value of the second matrix parameter. And carrying out normalization processing on m column vectors of the second parameter matrix through the electric chip to obtain m second column vectors. Wherein, the absolute value of the value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1. And transmitting each second column vector in the m second column vectors to the first sub-optical chip and the second sub-optical chip through the electric chip. And multiplying the first conversion submatrix and each second column vector by the first sub-optical chip to obtain a multiplication result of the first conversion submatrix and each second column vector, and transmitting the multiplication result of the first conversion submatrix and each second column vector to the electric chip. And multiplying the second conversion submatrix with each second column vector through the second sub-optical chip to obtain a multiplication result of the second conversion submatrix and each second column vector, and transmitting the multiplication result of the second conversion submatrix and each second column vector to the electric chip. And determining a third sub-product of the first submatrix to be multiplied and the second matrix parameter by the electric chip according to the multiplication result of the first conversion submatrix and each second column vector, and determining a fourth sub-product of the second submatrix to be multiplied and the second matrix parameter according to the multiplication result of the second conversion submatrix and each second column vector. And determining a target inverse matrix corresponding to the channel correlation matrix by the electric chip according to the first sub-product, the second sub-product, the third sub-product and the fourth sub-product.

With reference to the first aspect, in a possible implementation manner, the value of the preset third parameter matrix may be determined by the electrical chip according to the first sub-product and the third sub-product. And determining a preset value of a fourth parameter matrix according to the second sub-product and the fourth sub-product through the electric chip. Determining, by the electrical chip, a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix, and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

Determining, by the electrical chip, a value of an imaginary part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix, and a preset second iteration formula, where the second iteration formula includes:

D_R＝2×T-R×K-T×J

In the implementation, the inversion process of the channel correlation matrix is converted into the operation processes of multiplication, addition and subtraction among a plurality of matrixes through the preset first iteration formula and the preset second iteration formula, and feasibility is provided for the electric chip and the optical chip to cooperatively calculate the target inverse matrix of the channel correlation matrix. And under the condition that the channel incidence matrix is a complex matrix and the optical chip is a composite electric chip, the electric chip and the optical chip can calculate the product of at least two matrices and vectors simultaneously, so that on one hand, the repeated assignment of the matrices and the vectors and the increase of calculation amount caused by calculation can be avoided, the efficiency of channel estimation can be improved, and on the other hand, the calculation resource of the optical chip can be fully utilized.

With reference to the first aspect, in a possible implementation manner, the third parameter matrix satisfies the following relation:

J＝P×R-Q×T

The fourth parameter matrix satisfies the following relation:

K＝P×T+Q×R

wherein P is the real part of the channel correlation matrix, and Q is the imaginary part of the channel correlation matrix.

With reference to the first aspect, in a feasible implementation manner, the channel correlation matrix and the first inverse matrix are real numbers, the first to-be-multiplied matrix is the channel correlation matrix, and the value of the first parameter matrix is the first inverse matrix.

With reference to the first aspect, in a possible implementation manner, the electrical chip may determine, according to the first parameter matrix, the first product, and a preset third iteration formula, a value of an inversion iteration result, where the third iteration formula includes:

D＝R×(2I-A×R)

Wherein D is the inversion iteration result, R is the first parameter matrix, I is the identity matrix, a is the channel correlation matrix, and a×r is the first product. And adding 1 to the value of the preset iteration frequency parameter through the electric chip. Before the value of the iteration number parameter is determined to be not equal to the preset iteration number t by the electrical chip, repeating the following operations: and determining the value of the inversion iteration result obtained by the last time according to the third iteration formula as a new value of the first parameter matrix through the electric chip. And determining a new product of the first to-be-multiplied matrix and the newly valued first parameter matrix through the electric chip. And determining and obtaining the new value of the inversion iteration result through the electrical chip according to the first parameter matrix of the new value, the new product and the third iteration formula. And adding 1 to the value of the iteration frequency parameter through the electric chip. And determining a target inverse matrix of the channel correlation matrix according to the value of the inversion iteration result obtained at the t time until the value of the iteration number parameter is equal to the preset iteration number t through the electric chip.

In the implementation, the inversion process of the channel correlation matrix is converted into the operation processes of multiplication, addition and subtraction among a plurality of matrixes through a preset third iteration formula, and feasibility is provided for cooperatively calculating the target inverse matrix of the channel correlation matrix for the electric chip and the optical chip. Then, under the condition that the channel correlation matrix is a real number matrix, the target inverse matrix of the channel correlation matrix is calculated rapidly and with low power consumption through cooperation of the electric chip and the optical chip, so that the efficiency of channel estimation can be improved, the power consumption can be reduced, and the performance of a communication system to which the channel estimation device belongs can be improved.

With reference to the first aspect, in a possible implementation manner, any first column vector j of the m first column vectors may be decomposed into a first positive column vector j1 and a first negative column vector j2 by the electrical chip. The sum of the first positive column vector j1 and the first negative column vector j2 is equal to the first column vector j, the value of any vector element in the first positive column vector j1 is a positive number or 0, and the value of any vector element in the first negative column vector j2 is a negative value or 0. And determining a first opposite column vector j3 according to the first negative column vector j2 by the electric chip. Wherein the sum of the first negative column vector j2 and the first opposite column vector j3 is 0. The first positive column vector j1 and the first negative column vector j3 are transmitted to the photo chip by the photo chip.

In the above implementation, in the case where the first column vector j has both positive vector elements and negative vector elements, since the optical chip 22 cannot implement multiplication of negative numbers, the electrical chip 21 may first decompose the first column vector j into the first positive column vector j1 and the first opposite column vector j3 that do not include the negative vector elements, and transmit the first positive column vector j1 and the first opposite column vector j3 to the optical chip, so that the subsequent optical chip can calculate the multiplication result of some matrices and the first column vector j.

With reference to the first aspect, in a possible implementation manner, the multiplication result of the first conversion matrix and the first column vector j includes a multiplication result of the first conversion matrix and the first positive column vector j1 and a multiplication result of the first conversion matrix and the first opposite column vector j 3. The first conversion matrix and the first positive column vector j1 can be multiplied by the optical chip to obtain a multiplication result of the first conversion matrix and the first positive column vector j 1. The first conversion matrix and the first opposite column vector j3 may be multiplied by the optical chip to obtain a multiplication result of the first conversion matrix and the first opposite column vector j 3.

In the above implementation, the electrical chip and the optical chip may cooperatively perform the multiplication of the first conversion matrix and the first positive column vector j1 and the multiplication of the first conversion matrix and the first opposite column vector j3, and the multiplication of the first conversion matrix and the first positive column vector j1 and the multiplication of the first conversion matrix and the first opposite column vector j3 are the multiplication of the first conversion matrix and the first column vector j. Through the mode, the electric chip and the optical chip can cooperatively complete the multiplication operation of the matrix and the column vector containing the negative vector elements, the cooperative processing capacity of the electric chip and the optical chip can be improved, and the applicability and the practicability of the channel estimation method are improved.

With reference to the first aspect, in a possible implementation manner, a difference between a result of multiplying a first conversion matrix by the first positive column vector j1 and a result of multiplying the first conversion matrix by the first opposite column vector j3 may be used to determine a product of the first conversion matrix and the first column vector j.

With reference to the first aspect, in a possible implementation manner, the optical chip includes a first multiplier array and a second multiplier array, where any multiplier array includes a plurality of multipliers. The first conversion matrix can be decomposed into a first positive conversion matrix and a first negative conversion matrix through the electric chip, wherein the sum of the first positive conversion matrix and the first negative conversion matrix is the first matrix to be formed, the value of any matrix element in the first positive conversion matrix is positive number or 0, and the value of any matrix element in the first negative conversion matrix is negative number or 0. And determining a first inverse transformation matrix corresponding to the first negative transformation matrix through the electric chip, wherein the sum of the first inverse transformation matrix and the first negative transformation matrix is 0. The first positive conversion matrix is transmitted to the first multiplier array by the electrical chip such that the first multiplier array carries the first positive conversion matrix. Wherein one of the multipliers of the first multiplier array carries a value of a matrix element of the first positive transition matrix. The first inverse transformation matrix is transmitted to the second multiplier array by the electrical chip such that the second multiplier array carries the first inverse transformation matrix. Wherein one of the multipliers of the second multiplier array carries a value of a matrix element of the first inverse transformation matrix.

In the above implementation, in the case that the first conversion matrix has both positive matrix elements and negative matrix elements, since the optical chip cannot implement multiplication of negative numbers, the electrical chip may first decompose the first conversion matrix A1 into a first positive conversion matrix and a first negative conversion matrix that do not include negative matrix elements, so that the subsequent optical chip may be enabled to thereby complete multiplication operations of the first conversion matrix and certain vectors.

With reference to the first aspect, in a possible implementation manner, the electrical chip further includes a first photoelectric receiving module and a second photoelectric receiving module, where the first photoelectric receiving module is connected to the first optical multiplier array, and the second photoelectric receiving module is connected to the second optical multiplier array. The multiplication result of the first conversion matrix and the first column vector j includes the multiplication result of the first positive conversion matrix and the first column vector j and the multiplication result of the first inverse conversion matrix and the first column vector j. The multiplication operation can be performed on the first positive conversion matrix and the first column vector j through the first multiplier array and the first photoelectric receiving module by the optical chip so as to obtain a multiplication result of the first positive conversion matrix and the first column vector j. And multiplying the first inverse transformation matrix and the first column vector j through the optical chip by the second multiplier array and the second photoelectric receiving module to obtain a multiplication result of the first inverse transformation matrix and the first column vector j.

In the above implementation, the electrical chip and the optical chip may calculate a multiplication operation of the first positive conversion matrix and the first column vector j and a multiplication operation of the first inverse conversion matrix and the first column vector j, and a multiplication result of the first positive conversion matrix and the first column vector j and a multiplication result of the first inverse conversion matrix and the first column vector j are multiplication results of the first conversion matrix and the first column vector j. Through the mode, the electric chip and the optical chip can cooperatively complete multiplication operation of the matrix containing the negative matrix elements and the column vector, the cooperative processing capacity of the electric chip and the optical chip can be improved, and the applicability and the practicability of the channel estimation method are improved.

With reference to the first aspect, in one possible implementation, a difference between a result of multiplying the first positive conversion matrix by the first column vector j and a result of multiplying the first inverse conversion matrix by the first column vector j may be used to determine a product of the first conversion matrix and the first column vector j.

With reference to the first aspect, in a possible implementation manner, any optical multiplier carries the value of any matrix element through the refractive index of the any optical multiplier.

With reference to the first aspect, in one possible implementation manner, the optical multiplier includes one or more of: mach-Zehnder interferometers, directional couplers, and micro-rings.

In a second aspect, an embodiment of the present application provides a channel estimation apparatus. The channel estimation device may be a channel estimation device as described in the first aspect. The channel estimation device may include an electrical chip and an optical chip. The electrical chip is connected with the optical chip. The electrical chip is used for acquiring a channel incidence matrix of a target wireless channel and determining a first inverse matrix of a diagonal element matrix of the channel incidence matrix. The electric chip also determines a first to-be-multiplied matrix according to the channel incidence matrix, and determines the value of a preset first parameter matrix according to the first inverse matrix. The electrical chip is further configured to normalize the first to-be-multiplied matrix to obtain a first conversion matrix, and transmit the first conversion matrix to the optical chip. Wherein, the absolute value of the value of any matrix element in the first conversion matrix is smaller than or equal to 1. The electrical chip is further configured to perform the normalization processing on m column vectors of the first parameter matrix to obtain m first column vectors. Wherein the absolute value of the value of any vector element of each first column vector in the m first column vectors is less than or equal to 1, and m is an integer greater than or equal to 2. The electrical chip is further configured to transmit any first column vector j of the m first column vectors to the optical chip. The optical chip is used for multiplying the first conversion matrix with the first column vector j to obtain a multiplication result of the first conversion matrix and the first column vector j, and transmitting the multiplication result of the first conversion matrix and the first column vector j to the electrical chip. The electric chip is further used for determining a first product of the first matrix to be multiplied and the first parameter matrix according to a multiplication result of the first conversion matrix and each first column vector in the m first column vectors. And the electrical chip is also used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first product. The electric chip is also used for determining the transmitting vector of the target wireless channel according to the target inverse matrix and the receiving vector of the target wireless channel.

With reference to the second aspect, in one possible implementation manner, the channel correlation matrix and the first inverse matrix are complex matrices, and the first to-be-multiplied matrix includes a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix. The electrical chip is used for determining a real part matrix and an imaginary part matrix of the channel correlation matrix. The electrical chip is further configured to block a real matrix of the channel correlation matrix to obtain the first to-be-multiplied sub-matrix. The electric chip is further used for partitioning an imaginary matrix of the channel correlation matrix to obtain the second submatrix to be multiplied.

With reference to the second aspect, in a possible implementation manner, the electrical chip is further configured to determine a real matrix of the first inverse matrix. The electric chip is also used for determining the real part matrix of the first inverse matrix as a preset value of a first parameter matrix.

With reference to the second aspect, in one possible implementation manner, the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix, and the first product includes a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of the second to-be-multiplied block matrix and the first parameter matrix. The electric chip is also used for determining an imaginary matrix of the first inverse matrix and determining the imaginary matrix of the first inverse matrix as a preset value of a second parameter matrix. The electrical chip is further configured to perform the normalization processing on m column vectors of the second parameter matrix to obtain m second column vectors, where an absolute value of a value of any vector element of each second column vector in the m second column vectors is less than or equal to 1. The electrical chip is further configured to sequentially transmit each of the m second column vectors to the optical chip. The optical chip is further configured to multiply the first conversion sub-matrix and the second conversion sub-matrix with the second column vectors respectively to obtain a multiplication result of the first conversion sub-matrix and the second column vectors, and a multiplication result of the second conversion sub-matrix and the second column vectors, and transmit the multiplication result of the first conversion sub-matrix and the second column vectors to the electrical chip. The electric chip is further used for determining a third sub-product of the first to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the first conversion sub-matrix and each second column vector, and determining a fourth sub-product of the second to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the second conversion sub-matrix and each second column vector. The electric chip is further configured to determine a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, and the fourth sub-product.

With reference to the second aspect, in a possible implementation manner, the electrical chip is further configured to determine a portion of the real matrix of the channel correlation matrix other than the first to-be-multiplied sub-matrix as a third to-be-multiplied sub-matrix. The electrical chip is further configured to determine a portion of the imaginary matrix of the channel correlation matrix other than the second to-be-multiplied sub-matrix as a fourth to-be-multiplied sub-matrix. The electrical chip is further configured to perform the normalization processing on the third to-be-multiplied submatrix and the fourth to-be-multiplied submatrix to obtain a third conversion submatrix and a fourth to-be-multiplied submatrix. And the absolute value of the value of any matrix element in the third conversion submatrix and the fourth submatrix to be multiplied is smaller than or equal to 1. The electrical chip is further configured to transmit the third conversion sub-matrix and the fourth conversion sub-matrix to the optical chip. The electrical chip is further configured to sequentially transmit the first column vectors to the optical chip. The optical chip is further configured to multiply the third conversion sub-matrix and the fourth conversion sub-matrix with the first column vectors respectively to obtain a multiplication result of the third conversion sub-matrix and the first column vectors and a multiplication result of the fourth conversion sub-matrix and the first column vectors, and transmit the multiplication result of the third conversion sub-matrix and the first column vectors and the multiplication result of the fourth conversion sub-matrix and the first column vectors to the electrical chip. The electric chip is further configured to determine a fifth sub-product of the third to-be-multiplied sub-matrix and the first parameter matrix according to a multiplication result of the third conversion sub-matrix and each first column vector, and determine a sixth sub-product of the fourth to-be-multiplied sub-matrix and the first parameter matrix according to a multiplication result of the fourth conversion sub-matrix and each first column vector. The electric chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product and the sixth sub-product.

With reference to the second aspect, in a possible implementation manner, the electrical chip is further configured to sequentially transmit the second column vectors to the optical chip. The optical chip is further configured to multiply the third conversion sub-matrix and the fourth conversion sub-matrix with the second column vectors respectively to obtain a multiplication result of the third conversion sub-matrix and the second column vectors and a multiplication result of the fourth conversion sub-matrix and the second column vectors, and transmit the multiplication result of the third conversion sub-matrix and the second column vectors and the multiplication result of the fourth conversion sub-matrix and the second column vectors to the electrical chip. The electric chip is further used for determining a seventh sub-product of the third conversion sub-matrix and the second parameter matrix according to the multiplication result of the third conversion sub-matrix and each second column vector, and determining an eighth sub-product of the fourth to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the fourth conversion sub-matrix and each second column vector. The electric chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-matrix and the eighth sub-matrix.

With reference to the second aspect, in one possible implementation manner, the electrical chip is further configured to determine a first subvalue of a preset third parameter matrix according to the first subproduct and the fourth subproduct. The electrical chip is further configured to determine a first subvalue of a preset fourth parameter matrix according to the second subproduct and the third subproduct. The electrical chip is further configured to determine a second subvalue of the third parameter matrix according to the fifth subproduct and the eighth subproduct. The electrical chip is further configured to determine a second subvalue of the fourth parameter matrix according to the sixth subproduct and the seventh subproduct. The electrical chip is further configured to determine a value of the third parameter matrix according to the first sub-value and the third sub-value. And the electrical chip also determines the value of the fourth parameter matrix according to the second subvalue and the fourth subvalue. The electrical chip is further configured to determine a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

Wherein D _R is the real part iteration result, R is the first parameter matrix, T is the second parameter matrix, J is the third parameter matrix, and K is the fourth parameter matrix. The electrical chip is further specifically configured to determine a value of an imaginary part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix, and a preset second iteration formula, where the second iteration formula includes:

D_T＝2×T-R×K-T×J

wherein D _T is the imaginary iteration result; and the electric chip adds 1 to the value of the preset iteration frequency parameter. Before the electrical chip determines that the value of the iteration number parameter is not equal to the preset iteration number t, the electrical chip is further configured to repeatedly perform the following operations: and determining the value of the real part iteration result obtained by the last time according to the first iteration formula as a new value of the first parameter matrix, and determining the value of the imaginary part iteration result obtained by the last time according to the second iteration formula as a new value of the second parameter matrix. And re-determining the new values of the third parameter matrix and the fourth parameter matrix according to the new value first parameter matrix, the new value second parameter matrix and the real part and the imaginary part of the normalized channel correlation matrix. And determining the new value of the real part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the first iteration formula. And determining and obtaining the new value of the virtual part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the second iteration formula. And adding 1 to the value of the iteration frequency parameter. And the electric chip is used for determining the target inverse matrix of the channel correlation matrix according to the value of the real part iteration result and the value of the imaginary part iteration result obtained at the t time until the value of the iteration frequency parameter is equal to the preset iteration frequency t.

With reference to the second aspect, in one possible implementation manner, the channel correlation matrix and the first inverse matrix are complex matrices, and the first to-be-multiplied matrix includes a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix. The electrical chip is used for determining a real part matrix and an imaginary part matrix of the channel correlation matrix. The electrical chip is configured to determine a real matrix of the channel correlation matrix as the first to-be-multiplied sub-matrix and determine an imaginary matrix of the first channel correlation matrix as the second to-be-multiplied sub-matrix. The electrical chip is configured to determine a real matrix of the first inverse matrix. The electric chip is used for determining the real part matrix of the first inverse matrix as a preset value of a first parameter matrix.

With reference to the second aspect, in one possible implementation manner, the optical chip includes a first sub-optical chip and a second sub-optical chip, where the first sub-optical chip and the second sub-optical chip are connected with the electrical chip, the first product includes a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix, and a second sub-product of the second to-be-multiplied sub-matrix and the first parameter matrix, and the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix. The electrical chip is used for determining an imaginary matrix of the first inverse matrix as a preset value of a second matrix parameter. The electrical chip is further configured to perform the normalization processing on m column vectors of the second parameter matrix to obtain m second column vectors. Wherein, the absolute value of the value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1. The electrical chip is further configured to transmit each of the m second column vectors to the first sub-optical chip and the second sub-optical chip. The first sub-optical chip is further configured to multiply the first conversion sub-matrix with the second column vectors to obtain a multiplication result of the first conversion sub-matrix with the second column vectors, and transmit the multiplication result of the first conversion sub-matrix with the second column vectors to the electrical chip. The second sub-optical chip is further configured to multiply the second conversion sub-matrix with each second column vector to obtain a multiplication result of the second conversion sub-matrix with each second column vector, and transmit the multiplication result of the second conversion sub-matrix with each second column vector to the electrical chip. The electric chip is used for determining a third sub-product of the first sub-matrix to be multiplied and the second matrix parameters according to the multiplication result of the first conversion sub-matrix and each second column vector, and determining a fourth sub-product of the second sub-matrix to be multiplied and the second matrix parameters according to the multiplication result of the second conversion sub-matrix and each second column vector. The electric chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product and the fourth sub-product.

With reference to the second aspect, in a possible implementation manner, the electrical chip may be configured to determine a value of a preset third parameter matrix according to the first sub-product and the third sub-product. The electrical chip is further configured to determine a value of a fourth parameter matrix according to the second sub-product and the fourth sub-product. The electrical chip is further configured to determine a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

The electrical chip is further configured to determine a value of an imaginary part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix, and a preset second iteration formula, where the second iteration formula includes:

D_T＝2×T-R×K-T×J

wherein D _T is the result of the imaginary iteration. And the electric chip adds 1 to the value of the preset iteration frequency parameter.

Before determining that the value of the iteration number parameter is not equal to the preset iteration number t, the electrical chip is further configured to repeatedly perform the following operations: and determining the value of the real part iteration result obtained by the last time according to the first iteration formula as a new value of the first parameter matrix, and determining the value of the imaginary part iteration result obtained by the last time according to the second iteration formula as a new value of the second parameter matrix. And re-determining the new values of the third parameter matrix and the fourth parameter matrix according to the new value first parameter matrix, the new value second parameter matrix and the real part and the imaginary part of the normalized channel correlation matrix. And determining the new value of the real part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the first iteration formula. And determining and obtaining the new value of the virtual part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the second iteration formula. And adding 1 to the value of the iteration frequency parameter. And the electric chip is also used for determining the target inverse matrix of the channel correlation matrix according to the value of the real part iteration result and the value of the imaginary part iteration result obtained at the t time until the value of the iteration frequency parameter is equal to the preset iteration frequency t.

With reference to the second aspect, in one possible implementation manner, the third parameter matrix satisfies the following relation:

J＝P×R-Q×T

The fourth parameter matrix satisfies the following relation:

K＝P×T+Q×R

With reference to the second aspect, in one possible implementation manner, the channel correlation matrix and the first inverse matrix are real numbers, the first to-be-multiplied matrix is the channel correlation matrix, and the value of the first parameter matrix is the first inverse matrix.

With reference to the second aspect, in one possible implementation manner, the electrical chip is configured to determine a value of an inversion iteration result according to the first parameter matrix, the first product, and a preset third iteration formula. Wherein the third iterative formula comprises:

D＝R×(2I-A×R)

wherein D is the inversion iteration result, R is the first parameter matrix, I is the identity matrix, a is the channel correlation matrix, and a×r is the first product. The electric chip is also used for adding 1 to the value of the preset iteration frequency parameter. The electrical chip is further configured to repeatedly perform the following operations before determining that the value of the iteration number parameter is not equal to the preset iteration number t: and determining the value of the inversion iteration result obtained by the last time according to the third iteration formula as a new value of the first parameter matrix. And determining a new product of the first to-be-multiplied matrix and the newly valued first parameter matrix. And determining and obtaining a new value of the inversion iteration result according to the first parameter matrix with the new value, the new product and the third iteration formula. And adding 1 to the value of the iteration frequency parameter. And the method is further specifically used for determining a target inverse matrix of the channel correlation matrix according to the value of the inversion iteration result obtained at the t time until the value of the iteration number parameter is equal to the preset iteration number t through the electrical chip.

With reference to the second aspect, in one possible implementation manner, the electrical chip is further configured to: and decomposing any first column vector j in the m first column vectors into a first positive column vector j1 and a first negative column vector j2. The sum of the first positive column vector j1 and the first negative column vector j2 is equal to the first column vector j, the value of any vector element in the first positive column vector j1 is a positive number or 0, and the value of any vector element in the first negative column vector j2 is a negative value or 0. And determining a first opposite column vector j3 according to the first negative column vector j2, wherein the sum of the first negative column vector j2 and the first opposite column vector j3 is 0. The first positive column vector j1 and the first negative column vector j3 are transmitted to the photo chip.

With reference to the second aspect, in one possible implementation manner, the multiplication result of the first conversion matrix and the first column vector j includes a multiplication result of the first conversion matrix and the first positive column vector j1 and a multiplication result of the first conversion matrix and the first opposite column vector j 3. The optical chip is used for: and multiplying the first conversion matrix with the first positive column vector j1 to obtain a multiplication result of the first conversion matrix and the first positive column vector j 1. And multiplying the first conversion matrix with the first opposite column vector j3 to obtain a multiplication result of the first conversion matrix and the first opposite column vector j 3.

With reference to the second aspect, in one possible implementation manner, a difference between a result of multiplying a first conversion matrix by the first positive column vector j1 and a result of multiplying the first conversion matrix by the first opposite column vector j3 may be used to determine a product of the first conversion matrix and the first column vector j.

With reference to the second aspect, in one possible implementation manner, the optical chip includes a first multiplier array and a second multiplier array, where any multiplier array includes a plurality of multipliers. The electrical chip is further configured to decompose the first conversion matrix into a first positive conversion matrix and a first negative conversion matrix. The sum of the first positive conversion matrix and the first negative conversion matrix is the first matrix to be formed, the value of any matrix element in the first positive conversion matrix is positive number or 0, and the value of any matrix element in the first negative conversion matrix is negative number or 0. The electrical chip is further configured to determine a first inverse transformation matrix corresponding to the first negative transformation matrix. Wherein the sum of the first inverse transformation matrix and the first negative transformation matrix is 0. The electrical chip is further configured to transmit the first positive transition matrix to the first multiplier array such that the first multiplier array carries the first positive transition matrix. Wherein one of the multipliers of the first multiplier array carries a value of a matrix element of the first positive transition matrix. The electrical chip is further configured to transmit the first inverse transformation matrix to the second multiplier array such that the second multiplier array carries the first inverse transformation matrix. Wherein one of the multipliers of the second multiplier array carries a value of a matrix element of the first inverse transformation matrix.

With reference to the second aspect, in one possible implementation manner, the electrical chip further includes a first photoelectric receiving module and a second photoelectric receiving module, where the first photoelectric receiving module is connected to the first optical multiplier array, the second photoelectric receiving module is connected to the second optical multiplier array, and a multiplication result of the first conversion matrix and the first column vector j includes a multiplication result of the first positive conversion matrix and the first column vector j and a multiplication result of the first opposite conversion matrix and the first column vector j. The optical chip is also for: and multiplying the first positive conversion matrix and the first column vector j by the first multiplier array and the first photoelectric receiving module to obtain a multiplication result of the first positive conversion matrix and the first column vector j. And multiplying the first inverse transformation matrix and the first column vector j by the second multiplier array and the second photoelectric receiving module to obtain a multiplication result of the first inverse transformation matrix and the first column vector j.

With reference to the second aspect, in one possible implementation manner, a difference between a result of multiplying the first positive conversion matrix by the first column vector j and a result of multiplying the first inverse conversion matrix by the first column vector j may be used to determine a product of the first conversion matrix and the first column vector j.

With reference to the second aspect, in a possible implementation manner, any optical multiplier carries the value of any matrix element through the refractive index of the any optical multiplier.

With reference to the second aspect, in one possible implementation manner, the optical multiplier includes one or more of the following: mach-Zehnder interferometers, directional couplers, and micro-rings.

In a third aspect, an embodiment of the present application provides an electronic device, including: a channel estimation apparatus as claimed in any one of the first or second aspects above, and a discrete device coupled to the channel estimation apparatus.

In a fourth aspect, an embodiment of the present application provides an electronic device. The electronic device includes a memory and a processor. Wherein the processor is configured to invoke the code stored in the memory to perform the channel estimation method provided in any one of the possible implementations of the first aspect.

In a fifth aspect, the present application provides a computer-readable storage medium having instructions stored therein. The instructions, when executed by a processor, implement the channel estimation method of any of the first aspects above.

In a sixth aspect, the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the channel estimation method of the first aspect described above.

In a seventh aspect, the present application provides a chip system including an optical chip and an electrical chip for supporting an apparatus for mounting the chip system to implement the channel estimation method provided in the first aspect. The chip system can be composed of an optical chip and an electric chip, and can also comprise other discrete devices.

The solutions provided in the second aspect to the seventh aspect are used to implement or cooperate to implement the channel estimation method provided in the first aspect, so that the same or corresponding beneficial effects as those in the first aspect can be achieved, and no further description is given here.

In summary, by adopting the method provided by the embodiment of the application, the efficiency of channel estimation can be improved, the power consumption can be reduced, and the performance of a communication system can be improved.

Drawings

Fig. 1 is a schematic structural diagram of a wireless massive MIMO communication system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a channel estimation device according to an embodiment of the present application;

Fig. 3 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application;

Fig. 4 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application;

fig. 5 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application;

Fig. 6 is a schematic flow chart of a channel estimation method according to an embodiment of the present application;

fig. 7 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application;

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

Fig. 9 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings provided by the embodiments of the present application.

In practical applications, the channel estimation apparatus and the channel estimation method provided in the embodiments of the present application are applicable to various wireless communication systems involving channel estimation procedures, such as a wireless massive MIMO communication system, a code division multiple access (code division multiple access, CDMA) system, a wideband code division multiple access (wideband code division multiple access, WCDMA) system, a general packet radio service (GENERAL PACKET radio service, GPRS), a long term evolution (long term evolution, LTE) system, an LTE frequency division duplex (frequency division duplex, FDD) system, an LTE time division duplex (time division duplex, TDD) system, a universal mobile telecommunications (universal mobile telecommunications system, UMTS) system, an enhanced data rate GSM evolution (ENHANCED DATA RATE for GSM evolution, EDGE) system, a worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX) system, and the like. It will be appreciated that the channel estimation apparatus and method provided in the embodiments of the present application may also be applied to other wireless communication systems that may involve a channel estimation procedure, such as a public land mobile network (public land mobile network, PLMN) system, a fifth generation (5th generation,5G) system, or a 5G later communication system, or a New Radio (NR), etc., the 5G mobile communication system of the present application includes a non-independent networking (non-standalone, NSA) 5G mobile communication system and/or an independent networking (standalone, SA) 5G mobile communication system. The channel estimation device and the channel estimation method provided by the application can be also applied to future communication systems, such as a sixth generation mobile communication system. A communication system to which the channel estimation apparatus and the channel estimation method provided by the present application are applied will be described below by taking a wireless massive MIMO communication system as an example.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a wireless massive MIMO communication system according to an embodiment of the present application. As shown in fig. 1, the wireless massive MIMO communication system may mainly include one or more transmitting end devices (such as the transmitting end device 10 in fig. 1) and a receiving end device (such as the receiving end device 11 in fig. 1) that establishes a communication connection with the one or more transmitting end devices. In the actual transmission process, after the transmitting end device 10 acquires the data stream to be transmitted, the signal coding and modulation mapping module 101 may be included to perform signal coding and modulation mapping on the data stream to obtain a corresponding signal. The resulting signal is then serial-to-parallel converted by serial-to-parallel conversion module 102 to obtain a multi-path parallel baseband signal. The multiple parallel baseband signals then arrive at multiple modulation modules (here, modulation module 103 and modulation module 104 are taken as examples) included in transmitting device 10, respectively. The modulation modules 103 and 104 respectively perform signal modulation on the input baseband signals to obtain corresponding modulated signals, and respectively transmit the corresponding modulated signals to the antenna array 105 of the transmitting end device 10, and transmit the modulated signals through the antenna array 105. The receiving end device 11 may receive the multiplexed signal transmitted by the transmitting end device 10 through the antenna array 115 carried by the receiving end device and transmit the multiplexed signal to a plurality of demodulation modules (here, the demodulation module 113 and the demodulation module 114 are exemplified) and a channel estimation module 116 included in the multiplexed signal. The channel estimation module 116 may perform channel estimation on the currently used wireless channel according to the received multipath modulation signal to obtain a corresponding channel estimation result, and then transmit the channel estimation result to the MIMO signal detection module 117 on the receiving end device 11. Meanwhile, the demodulation module 113 and the demodulation module 114 also demodulate the received modulated signal to obtain a corresponding multipath demodulated signal, and transmit the multipath demodulated signal to the MIMO signal detection module 117. The MIMO signal detection module 117 may perform signal detection on the multiple demodulation signals according to the signal estimation result obtained by the channel estimation module 116 to obtain multiple baseband signals, and transmit the multiple baseband signals to the parallel-to-serial conversion module 112 in the receiving apparatus. The parallel-to-serial conversion module 112 may perform parallel-to-serial conversion on the multiple baseband signals to obtain corresponding serial signals, and transmit the serial signals to the signal decoding and demapping module 111 in the receiving end device 11. The signal decoding and demapping module 111 can perform signal decoding and demapping on the serial signal, so as to restore the data stream transmitted by the transmitting end device 10. The antenna array provided by the application comprises a plurality of antennas, and each antenna can transmit or receive one path of modulation signal at the same time.

It should be noted that, in the communication system shown in fig. 1, only the receiving end device 11 includes a channel estimation module, and in practical implementation, the transmitting end device 10 may perform the same channel estimation process when performing transmit precoding. In practical applications, a channel estimation module may be present in both the transmitting end device 10 and the receiving end device 11, which is not limited by the present application.

Here, the receiving end device 11 may be a terminal device, and the transmitting end device 12 may be a network device. Or the receiving end device 11 may be a network device, and the transmitting end device 12 may be a terminal device.

The terminal device is a device having a communication function, and may be a user device, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user apparatus.

By way of example, and not limitation, in embodiments of the present application, the terminal device may also be a wearable device. The wearable device can also be called as a wearable intelligent device, and is a generic name for intelligently designing daily wear by applying wearable technology and developing wearable devices, such as glasses, gloves, watches, clothes, shoes and the like. The wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also can realize a powerful function through software support, data interaction and cloud interaction. The generalized wearable intelligent device includes full functionality, large size, and may not rely on the smart phone to implement complete or partial functionality, such as: smart watches or smart glasses, etc., and focus on only certain types of application functions, and need to be used in combination with other devices, such as smart phones, for example, various smart bracelets, smart jewelry, etc. for physical sign monitoring.

In addition, in the embodiment of the application, the terminal equipment can also be terminal equipment in an internet of things (internet of things, ioT) system, and the IoT is an important component of the development of future information technology, and the main technical characteristics are that the object is connected with the network through a communication technology, so that the man-machine interconnection and the intelligent network of the internet of things are realized. In the embodiment of the application, the IOT technology can achieve mass connection, deep coverage and terminal power saving through a Narrow Band (NB) technology, for example.

In addition, in the embodiment of the application, the terminal equipment can also comprise sensors such as an intelligent printer, a train detector, a gas station and the like, and the main functions comprise collecting data (part of the terminal equipment), receiving control information and downlink data of the network equipment, sending electromagnetic waves and transmitting the uplink data to the network equipment.

The network device may be a device for communicating with a terminal device, which may be a base station (base transceiver station, BTS) in a global system for mobile communications (global system formobile communications, GSM) system or code division multiple access (codedivision multiple access, CDMA), a base station (NodeB, NB) in a wideband code division multiple access (wideband code division multiple access, WCDMA) system, an evolved NodeB (eNB or eNodeB) in an LTE system, a radio controller in a cloud radio access network (cloud radio access network, CRAN) scenario, or a relay station, an access point, a vehicle device, a wearable device, a network device in a future 5G network, or a network device in a future evolved PLMN network, etc.

The network device may also be a device in a wireless network, such as a radio access network (radio access network, RAN) node that accesses the terminal device to the wireless network. Currently, some examples of RAN nodes are: a base station, a next generation base station gNB, a transmission and reception point (transmission reception point, TRP), an evolved Node B (eNB), a home base station, a baseband unit (BBU), or an Access Point (AP) in a WiFi system, etc. In one network architecture, the network devices may include a centralized unit (centralized unit, CU) node, or a Distributed Unit (DU) node, or a RAN device including a CU node and a DU node.

In the embodiment of the application, the terminal equipment or the network equipment comprises a hardware layer, an operating system layer running on the hardware layer and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (central processing unit, CPU), a memory management unit (memory management unit, MMU), and a memory (also referred to as a main memory). The operating system may be any one or more computer operating systems that implement business processes through processes (processes), such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a windows operating system. The application layer comprises applications such as a browser, an address book, word processing software, instant messaging software and the like. Further, the embodiment of the present application is not particularly limited to the specific structure of the execution body of the method provided by the embodiment of the present application, as long as the communication can be performed by the method provided according to the embodiment of the present application by running the program recorded with the code of the method provided by the embodiment of the present application, and for example, the execution body of the method provided by the embodiment of the present application may be a terminal device or a network device, or a functional module in the terminal device or the network device that can call the program and execute the program.

In practical applications, in the communication system shown in fig. 1, a plurality of wireless channels are used for transmitting signals between a signal sender (i.e. a transmitting end device 10) and a signal receiver (i.e. a receiving end device 11). Cross talk, etc. may exist between different wireless channels, so that signals are cracked, thereby affecting the performance of the communication system. Therefore, in order to improve the performance of the communication system, the signal receiving party performs channel estimation on the wireless channel in the communication system when receiving the signal, and performs operations such as channel compensation according to the result of the channel estimation to improve the channel capacity, thereby improving the performance of the communication system. For example, in the wireless massive MIMO communication structure shown in fig. 1, the receiving device 11 performs signal estimation through the channel estimation module 116 to perform operations such as channel compensation.

In practice, the channel estimation module 116 generally uses a zero forcing (zero foring, ZF) method, a minimum mean square error (minimum mean squared error, MMSE) method, and the like to perform channel estimation on a wireless channel (for distinction, a target wireless signal will be replaced with a description below). The MIMO reception vector y of the target wireless channel determined by the channel estimation module 116 satisfies the following relation (1):

y＝H×x+n (1)

Wherein x is the emission vector of the target wireless channel, H is the channel matrix of the target wireless channel, and n is Gaussian white noise. When the channel estimation module 116 performs channel estimation using the zero forcing method, the channel estimation module may calculate the transmit vector x according to the following relation (2) after obtaining the receive vector y. The relation (2) is as follows:

x＝W_ZF×y (2)

Wherein W _ZF is a zero forcing matrix of the target wireless channel, and the zero forcing matrix W _ZF satisfies the following relation (3):

W_ZF＝A^-1×H^H (3)

wherein matrix a ^-1 is the inverse of matrix a. Matrix H ^H is the conjugate transpose of channel matrix H. Here, the matrix a is a matrix determined by the channel matrix H, and for convenience of understanding, the description will be uniformly replaced by the channel correlation matrix. In a specific implementation, the channel estimation module 116 may calculate the channel correlation matrix a according to the following relation (4).

A＝H^H×H (4)

When the channel estimation module 116 performs channel estimation using the minimum mean square error method, the channel estimation module may calculate the transmit vector x according to the following relation (5) after obtaining the receive vector y. The relation (5) is as follows:

x＝W_MMSE×y (5)

Wherein W _MMSE is a minimum mean square error matrix of the wireless channel, and the minimum mean square error matrix W _MMSE satisfies the following relation (6):

W_MMSE＝A^-1×H^H (6)

In this case, the channel estimation module 116 may calculate the channel correlation matrix a by the following relation (7).

A＝H^H×H+σ²×I (7)

Wherein, sigma is standard deviation matrix I of Gaussian white noise n is identity matrix.

In the prior art, the channel estimation module 116 is typically implemented in the form of a digital integrated circuit such as GPUs, FPGAs, ASICs. However, since moore's law is slow to develop, the existing digital integrated circuit has the problems of large power consumption, slow calculation speed and the like. In addition, as shown in the foregoing, in a communication system such as wireless massive MIMO communication, a large number of matrices are involved in the channel estimation process, which results in the problem of low efficiency and large system power consumption in the channel estimation method by using a digital integrated circuit, and seriously affects the performance of the communication system.

Therefore, the technical problems to be solved by the application are as follows: how to realize the channel estimation aiming at the wireless channel quickly and with low energy consumption, thereby improving the performance of the communication system.

In order to solve the above problems, an embodiment of the present application provides a channel estimation method and a channel estimation apparatus using the same. The channel estimation device may implement the channel estimation function implemented by the channel estimation module 116 in fig. 1. The channel estimation device can comprise an electric chip and an optical chip, and the channel estimation method provided by the application can be executed through the electric chip and the optical chip, so that the problems of low efficiency and high power consumption caused by adopting a digital integrated circuit to perform channel estimation can be effectively solved, and the performance of a communication system can be improved. Since the channel estimation device performs multiplication of matrix and vector several times through cooperation of the electrical chip and the optical chip in the channel estimation method provided by the present application, for convenience of description of specific procedures of the channel estimation method provided by the present application, the structure of the channel estimation device 20 provided by the present application and specific procedures of performing multiplication of matrix and vector once will be described in detail.

Referring to fig. 2, fig. 2 is a schematic diagram of a channel estimation apparatus according to an embodiment of the present application. The channel estimation device 20 may be applied to the receiving end device 11 shown in fig. 1 (i.e., corresponding to the channel estimation module 116). As shown in fig. 2, the channel estimation device 20 may specifically include an electrical chip 21 and an optical chip 22. Wherein the electrical chip 21 and the optical chip 22 are connected to each other. The channel estimation device 20 may be a chip or a chip set or a circuit board on which the chip or the chip set is mounted. The chip or chip set or the circuit board on which the chip or chip set is mounted may be operated under the necessary software drive. The electric chip 21 is a chip that performs data processing and signal transmission by means of electric current. The optical chip 22 is a chip that performs data processing and signal transmission by means of light. In practical applications, the channel estimation device 20 can perform multiplication of the matrix and the vector cooperatively through the above-mentioned electrical chip 21 and optical chip 22. The specific structure of the electrical chip 21 and the optical chip 22, and how the electrical chip 21 and the optical chip 22 cooperatively calculate the product (here, C) of the first conversion matrix A1 and the first column vector j will be described in detail below by taking the first conversion matrix (here, A1) and the first column vector j as an example.

Here, it is assumed that the first conversion matrix A1 is a square matrix of m rows and m columns, and satisfies the following relational expression (8):

Assuming that the number of rows of the first column vector j is m, the following relational expression (9) is satisfied:

Assume that the product C of the first conversion matrix A1 and the first column vector j is a column vector of m rows, and satisfies the following relation (10):

referring to fig. 3, fig. 3 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the application. As shown in fig. 3, the optical chip 22 may specifically include an optical signal source 23, an optical signal adjustment module 24, an optical multiplier array 25, and an optical-electrical receiving module 26. The optical signal source 23, the optical signal adjustment module 24, the optical multiplier array 25, and the optical-electrical receiving module 26 are optically connected to each other, and the optical signal source 23, the optical multiplier array 25, and the optical-electrical receiving module 26 are electrically connected to the electrical chip 21.

In the process that the electric chip 21 and the optical chip 22 cooperate to complete the multiplication operation of the first conversion matrix A1 and the first column vector j, after determining the first column vector j, the electric chip 21 may generate a first electric signal corresponding to the first column vector j according to the values of the vector elements in the first column vector j, and transmit the first electric signal to the optical signal source 23. After receiving the first electrical signal, the optical signal source 23 may generate m paths of first signal lights (assuming that the first signal lights L11 and L12 are included respectively and up to the first signal light L1 m) according to the first electrical signal, and transmit the m paths of first signal lights to the optical signal adjustment module 24. The optical power value of each path of first signal light in the m paths of first signal light corresponds to the value of one vector element in the first column vector j, and the wavelength of each path of first signal light is different. For example, the optical power value of the first signal light L11 in the m paths of first signal light corresponds to the value b1 indicating the 1 st vector element in the first column vector j, and the wavelength of the first signal light L11 is λ1. The optical power value of the first signal light L12 corresponds to the value b2 indicating the 2 nd vector element in the first column vector j, and the wavelength of the first signal light L12 is λ2. And so on, the optical power value of the first signal light L1m corresponds to the value bm of the mth vector element in the first column vector j, and the wavelength of the first signal light L1m is λm. After receiving the m first signal lights, the optical signal adjustment module 24 may adjust the m first signal lights to obtain m second signal lights (assuming that the second signal lights L21 and L22 are respectively included up to the second signal light L2 m), and transmit the m second signal lights to the optical multiplier array 25. Wherein each of the m paths of second signal light includes the m paths of first signal light with reduced optical power values by m times, and the optical power values of each path of second signal light are the same. For example, the second signal light L21 includes a first signal light L11 whose optical power is reduced by m times, a first signal light L12 whose optical power is reduced by m times, a first signal light L1m whose optical power is reduced by m times, the second signal light L22 includes a first signal light L11 whose optical power is reduced by m times, a first signal light L12 whose optical power is reduced by m times, a first signal light L1m whose optical power is reduced by m times, and the like, and the second signal light L2m includes a first signal light L11 whose optical power is reduced by m times, a first signal light L12 whose optical power is reduced by m times, and a first signal light L1m whose optical power is reduced by m times. In other words, each of the second signal lights is a polychromatic light, and the second signal light includes the first signal light whose m paths are monochromatic light after the optical power is reduced by m times.

In addition, after determining the first conversion matrix A1, the electrical chip 21 may generate a second electrical signal corresponding to the first conversion matrix A1 according to the values of the matrix elements in the first conversion matrix A1, and transmit the second electrical signal to the optical multiplier array 25. After receiving the second electrical signal and the m second signal lights, the optical multiplier array 25 may adjust the optical power values of the m second signal lights according to the second electrical signal to obtain m third signal lights (here, it is assumed that the third signal lights L31 and L32 are included up to the third signal light L3 m), and transmit the m third signal lights to the optical-electrical receiving module 26. And one path of second signal light in the m paths of second signal light is correspondingly adjusted to obtain one path of third signal light in the m paths of third signal light. The optical power value of one third signal light in the m third signal lights is the multiplication result of one row vector and the first column vector j of the first conversion matrix A1. For example, the optical power value of the first third signal light outputted by the optical multiplier array 25 is the multiplication result of the 1 st row vector [ a11, a12, a13, …, A1m ] and the first column vector j of the first conversion matrix A1, the optical power value of the second third signal light outputted by the optical multiplier array 25 is the multiplication result of the 2 nd row vector [ a21, a22, a23, …, a2m ] and the first column vector j of the first conversion matrix A1, and the optical power of the m-th third signal light outputted by the optical multiplier array 25 is the multiplication result of the m-th row vector [ am1, am2, am3, …, amm ] and the first column vector j of the first conversion matrix A1.

The optical receiving module 26 may detect the optical power value of each of the m third signal lights, so as to obtain optical power values of m third signal lights, where the optical power values of the m third signal lights are the multiplication result of the first conversion matrix A1 and the first column vector j calculated by the optical chip 22. Then, the photoelectric receiving module 26 may generate a third electric signal based on the multiplication result of the first conversion matrix A1 and the first column vector j, and transmit the multiplication result of the first conversion matrix A1 and the first column vector j to the electric chip 21 through the third electric signal. After receiving the multiplication result of the first transformation matrix A1 and the first column vector j through the third electrical signal, the electrical chip 21 can obtain the product C of the first transformation matrix A1 and the first column vector j according to the multiplication result of the first transformation matrix A1 and the first column vector j. Thus, the electric chip 21 and the optical chip 22 cooperate to complete the multiplication of the first conversion matrix A1 and the first column vector j, and the product C of the first conversion matrix A1 and the first column vector j is obtained.

In some alternative implementations, please refer to fig. 4, fig. 4 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application. As shown in fig. 4, the optical signal source 23 specifically includes m light sources (light source 1, light source 2 up to light source m as shown in fig. 4) and m light modulators (light modulator 1, light modulator 2 up to light modulator m as shown in fig. 4). One end of any one of the m optical modulators is connected to one of the m optical sources, the other end thereof is connected to the optical signal adjustment module 24, and the other end thereof is connected to the electrical chip 21. For example, one end of the optical modulator 1 is connected to the light source 1, the other end of the optical modulator 1 is connected to the optical signal adjustment module 24, and the other end of the optical modulator 1 is connected to the electrical chip 21.

In practical application, each of the m light sources outputs a continuous light with a fixed wavelength. For example, the light source 1 outputs the 1 st continuous light of the wavelength λ1, and the light source 2 outputs the 2 nd continuous light of the wavelength λ2. In the embodiment of the present application, the light output from the light source that has not undergone any processing is referred to as continuous light, and the continuous light that has undergone processing by optical devices such as a beam splitter and a power splitter is referred to as signal light. The first electrical signal generated by the electrical chip 21 according to the first column vector j includes m first adjustment signals (here, it is assumed that the first adjustment signals 1 and 2 are included until the first adjustment signal m) corresponding to m vector elements of the first column vector j. Wherein one vector element in the first column vector j corresponds to one of the m first adjustment signals. One of the m optical modulators receives a first adjustment signal correspondingly, and adjusts the optical power value of the continuous light received by the optical modulator according to the first adjustment signal received by the optical modulator, so that the optical power value of the first signal light output by the optical modulator can be corresponding to the value of a vector element indicating the first column vector j. For example, the light source 1 outputs the 1 st continuous light having the wavelength λ1 to the light modulator 1. The optical modulator 1 may receive the first adjustment signal 1 corresponding to the vector element b1 in the first column vector j, and modulate the optical power of the 1 st continuous light according to the first adjustment signal 1 to obtain the first signal light L11, where the optical power value of the first signal light L11 is the value corresponding to the indication vector element b 1. It is also understood that the vector element b1 is carried on the first signal light L11. In this way, the optical modulators 1 to n can modulate and output the first signal light L11 and the first signal light L12 to the optical signal adjustment module 24 until the first signal light L1m. Wherein the m first signal lights respectively carry m vector elements b1, b2 to bm of the first column vector j.

The optical signal adjusting module 24 may specifically include a combiner 241 and a power divider 242. The beam combiner 241 is connected to the m optical modulators one by one, the beam combiner 241 is further connected to the power divider 242, and the power divider 242 is further connected to the optical multiplier array 25.

In practical applications, the beam combiner 241 may receive m paths of first signal lights from the m optical modulators, perform beam combining processing on the m paths of first signal lights to obtain a path of fourth signal light, and transmit the fourth signal light to the power divider 242. Here, the n paths of the first signal light are included in the fourth signal light, and an optical power value of the fourth signal light is equal to a sum of optical power values of the m paths of the first signal light. After receiving the fourth signal light, the power divider 242 may perform m-way power processing on the fourth signal light to obtain m-way second signal lights with the same optical power, and transmit the m-way second signal lights to the optical multiplier array 25. Here, similar to the fourth signal light, each of the m second signal lights may include m power-divided first signal lights, and the optical power of each of the m power-divided first signal lights is equal to one-m times the optical power of the first signal light before the power division (i.e., the optical power value of the first signal light in the second signal light is reduced by m times). For example, assuming that the optical powers corresponding to the first signal light L11 and the second signal light L12 up to the first signal light L1m in the m paths of first signal light are respectively K11, K12, K13, …, and K1m, the optical powers corresponding to the second signal light L21 in the m paths of second signal light, i.e., the first signal light L11 subjected to power division and the first signal light L12 subjected to power division up to the first signal light L1m subjected to power division, are respectively K11, K12, K13, …, and K1mI.e. the optical power value of each path of second signal light is equal to/>In other words, the fourth signal light carries a first column vector j, i.e., [ b1, b2, b3, …, bm ] ^T, and each of the second signal light carries a divisor of the first column vector j and m (for convenience of understanding, the description is replaced by a first column vector (j, m) hereinafter), the first column vector (j, m) is equal to

The optical multiplier array 25 may specifically include m optical multiplier modules (such as the optical multiplier module 1, the optical multiplier module 2, and up to the optical multiplier module m shown in fig. 4), where each of the m optical multiplier modules includes m parallel optical multipliers (such as the optical multiplier module 1 includes the parallel optical multipliers 11, the optical multiplier 12, and up to the optical multiplier 1 m), so as to form an optical multiplier array of m rows and m columns. In practical applications, an optical multiplier module can be used for adjusting the optical power value of one path of second optical signal to obtain one path of third signal light. The process is equivalent to the multiplication of a row vector and a first column vector (j, m) of the first conversion matrix A1, and the optical power value of the third signal light output by the optical multiplier module is the multiplication result of the row vector and the first column vector (j, m).

The structure and function of the optical multiplier module 1 among the m optical multiplier modules will be described in detail below. As shown in fig. 4, the optical multiplier module 1 includes m optical multipliers 11, 12 to 1m optical multipliers, where each optical multiplier of the m optical multipliers includes a straight waveguide, a micro-ring resonator coupled to the straight waveguide, and a metal electrode connected to the micro-ring resonator. It should be noted that, in practical design, m parallel optical multipliers in one optical multiplier module share the same straight waveguide for simplifying the structure. The straight waveguide common to the m optical multipliers is connected at one end to the power divider 242 and at the other end to the optoelectronic receiving module 26, and the metal electrode of each optical multiplier is connected to the electrical chip 21. The function and structure of each optical multiplier will be described below taking the optical multiplier 12 in the optical multiplier module 1 as an example. As shown in fig. 4, the optical multiplier 12 includes a micro-ring resonator 121, a metal electrode 122 connected to the micro-ring resonator 121, and a straight waveguide 1 coupled to the micro-ring resonator 121. Wherein all optical multipliers in the optical multiplier module 1 share the straight waveguide 1. One end of the straight waveguide 1 is connected to one end of the power divider 242, and the other end of the straight waveguide 1 is connected to the photoelectric receiving module 26. The metal electrode 122 is connected to the electrical chip 21. It should be noted that the radii of the micro-ring resonators included in the m optical multipliers are all different. For example, the micro-ring resonator of the optical multiplier 11 may have a radius r1, the micro-ring resonator of the optical multiplier 12 may have a radius r2, and so on, and the micro-ring resonator of the optical multiplier 1n may have a radius rm. Since the radius of the micro-ring resonant cavity determines the resonant frequency of the micro-ring resonant cavity, the optical multiplier to which the micro-ring resonant cavity with a certain radius belongs can only adjust the optical power of the signal light with a certain specific wavelength. For example, if the micro-ring resonator of the optical multiplier 11 has a radius r1 and a resonance frequency f1, and the wavelength obtained by converting the resonance frequency f1 is λ1, the optical multiplier 11 can adjust only the signal light having the wavelength λ1. Similarly, in actual use, the optical multiplier 12 can adjust only the signal light having the wavelength λ2.

In practical applications, the second electrical signal generated by the electrical chip 21 may include m×m second adjustment signals corresponding to m×m matrix elements in the first conversion matrix A1, where one matrix element corresponds to one second adjustment signal. The metal electrode 122 of the optical multiplier 12 may receive one of the m second adjustment signals (s is assumed here), and change the refractive index of the micro-ring resonator 121 according to the second adjustment signal s, so that the refractive index of the micro-ring resonator 121 corresponds to the value of the matrix element corresponding to the second adjustment signal s. This process can also be understood as the fact that the electrical chip 21 loads the matrix elements corresponding to the second adjustment signals s in the first conversion matrix A1 onto the above-mentioned optical multipliers 12. Similarly, the metal electrodes of the optical multipliers 11 and 12 up to the optical multiplier 1m may receive m second adjustment signals included in the second electrical signal, respectively (it is assumed here that the m second adjustment signals correspond to m matrix elements in one row vector a11 in the first conversion matrix A1). The m optical multipliers may then set the refractive index of the respective micro-ring resonators according to the m second adjustment signals, such that the m optical multipliers carry m matrix elements in the row vector a 11. Then, one end of the straight waveguide 1 in the optical multiplier module 1 may receive one path of the second signal light (for convenience of description, it is assumed here that the second signal light L21) from the power divider 242. In the transmission process of the straight waveguide 1, when the second signal light L21 passes through the optical multiplier 11, the micro-ring resonant cavity of the optical multiplier 11 adjusts the optical power value of the first signal light L11 with the wavelength λ1 after power division in the second signal light L21 according to the refractive index thereof, so that the optical power value of the first signal light L11 after micro-ring adjustment can correspondingly indicate the multiplication result of the matrix element carried by the optical multiplier 11 and the vector element carried by the first signal light L11 (it can be understood herein that the optical power value of the first signal light L11 after micro-ring adjustment is one m-th of the product of the matrix element carried by the optical multiplier 11 and the vector element carried by the first signal light L11). Similarly, the micro-ring resonator of the optical multiplier 12 adjusts the optical power of the first signal light L12 with the wavelength λ2 in the second signal light L21 according to the refractive index thereof, the micro-ring resonator of the optical multiplier 13 adjusts the optical power of the first signal light L13 with the wavelength λ3 in the second signal light L21 according to the refractive index thereof, and so on until the micro-ring resonator of the optical multiplier 1m adjusts the optical power of the first signal light L1n with the wavelength λm in the second signal light L21 according to the refractive index thereof, the second signal light L21 is converted into the third signal light L31 by the optical multiplier module 1, and is output to the photoelectric receiving module 26 from the other end of the straight waveguide 1. The optical power value of the third signal light L31 is the multiplication result of the row vector a11 and the first column vector j, and specifically, the optical power value of the third signal light L31 is equal to one m times the multiplication result of the row vector a11 and the first column vector j. For example, assuming that m optical multipliers in the optical multiplier module 1 bear the first row vector [ a11, a12, a13, …, A1m ] of the first conversion matrix A1, the optical power value (here, G31 is assumed to be a fraction m of the product of the first row vector [ a11, a12, a13, …, A1m ] and the first column vector j. That is, the power value of the third signal light L31 satisfies the following relational expression (11):

Similarly, the remaining m-1 optical multiplier modules in the m optical multiplier modules have the same structure and function as the optical multiplier module 1, and can also perform multiplication operation of the same row vector and the first column vector j, so as to obtain m-1 paths of third signal light corresponding to m-1 row vectors except the row vector a11 in the first conversion matrix A1. The optical multiplier array 25 can obtain and output m paths of third signal lights to the photoelectric receiving module 26, and the optical power value of any one path of third signal light in the m paths of third signal lights is the multiplication result of one row vector and one first column vector j in the first conversion matrix A1.

Further, the above-mentioned photo-electric receiving module 26 may include m photo-electric receivers (such as photo-electric receiver 1 and photo-electric receiver 2 shown in fig. 4 up to photo-electric receiver m), and one end of any one of the m photo-electric receivers is connected to one end of the straight waveguide in one optical multiplier module, and the other end is connected to the electrical chip 21. In practical applications, the m photo-receivers may receive the m third signal lights from the optical multiplier array 25, and each photo-receiver may detect and determine an optical power value of one third signal light, so that the m photo-receivers may obtain the optical power values of the m third signal lights. It should be understood that, for any one of the above optical multiplier modules, when it carries a certain row vector in the first conversion matrix A1, the optical power value of the third signal light detected by the connected optical receiver is the multiplication result of the row vector and the first column vector j. The optical power values of the m third signal lights are the multiplication result of the first conversion matrix A1 and the first column vector j calculated by the optical chip 22. Here, assuming that the optical power values of the m third signal lights are G31, G32 to G3m, respectively, the optical power values of the m third signal lights satisfy the following relationship (12):

Further, after the optical power values of the m third signal lights are obtained by the optical-electrical receiving module 26, a third electrical signal may be generated, and the optical power values of the m third signal lights are transmitted to the electrical chip 21 through the third electrical signal. After receiving the optical power values of the m third signal lights through the third electrical signal, the electrical chip 21 may perform a combination process on the optical power values of the m third signal lights according to the positions of the row vectors corresponding to each of the m third signal lights in the first conversion matrix A1 to obtain a first intermediate product vector, i.e., [ G31, G32, G33, …, G3m ] ^T. Then, the electrical chip 21 may calculate the product of the first intermediate product vector and m, and determine the product of the first intermediate product vector and m as the product C of the first conversion matrix A1 and the first column vector j. Thus, the electric chip 21 and the optical chip 22 cooperate to complete the multiplication of the first conversion matrix A1 and the first column vector j.

It should be noted that, the optical multiplier shown in fig. 4 adopts a micro-ring structure, and in practical application, the specific structure of the optical multiplier may also be a directional coupler, a mach-zehnder interferometer, etc. Since the working principles of the optical multipliers under different structures are the same, for convenience of understanding, the present application uses the scenario that the optical multipliers adopt the micro-ring structure as an example to describe the structure and the working principles of the optical multiplier array 25. The light source may be a laser or the like in various implementations, the optical modulator may be an electro-optical modulator or the like in various implementations, and the photodetector may be a photodetector (photoelectric detector, PD) in various implementations.

Here, the electric chip 21 is an analog electric chip, the optical chip 22 is an analog optical chip, and data transmission is performed between the two chips by an analog electric signal. With such an integrated architecture, the requirements of an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) of the channel estimation device 20 can be greatly reduced, and the structure of the channel estimation device 20 can be simplified.

In the above implementation, the electrical chip 21 in the channel estimation device 20 transmits the matrix and the vector to be multiplied to the optical chip 22, the optical chip 22 can calculate the multiplication result of the matrix and the vector and transmit the multiplication result to the electrical chip 21, and then the electrical chip 21 finally processes the multiplication result of the matrix and the vector to obtain the product of the matrix and the vector. Since the optical chip 22 requires a short time and low power consumption, the channel estimation device 20 can effectively improve the efficiency of multiplying the matrix and the vector by adopting the mode of cooperatively calculating the product of the matrix and the vector by the electrical chip 21 and the optical chip 22, and reduce the power consumption.

In an alternative implementation, the vector elements with positive values (for convenience of description, positive vector elements will be replaced by description) and the vector elements with negative values (for convenience of description, negative vector elements will be replaced by description) may exist in the first column vector j at the same time, and in this case, the electrical chip 21 and the optical chip 22 may cooperatively calculate the product C of the first conversion matrix A1 and the first column vector j in a time division manner. The structure and function of the optical chip 22 are described above.

In practical applications, after the obtained first column vector j, when determining that the positive vector element and the negative vector element exist in the first column vector j at the same time, the electrical chip 21 may first decompose the first positive column vector (here, j 1) and the first negative column vector (here, j 2) according to the first column vector j. Here, the sum of the first positive column vector j1 and the first negative column vector j2 is equal to the first column vector j, and the value of any one of the vector elements in the first positive column vector j1 is a positive number or 0, and the value of any one of the vector elements in the first negative column vector j2 is a negative number or 0. That is, the first positive column vector j1 includes all positive vector elements in the first column vector j, and the first negative column vector j2 includes all negative vector elements in the first column vector j. The electrical chip may then determine a first opposite column vector (here assumed to be j 3) corresponding to the first negative column vector j2 from the first negative column vector j2. Here, the sum of the first opposite vector j3 and the first negative column vector j2 is 0, that is, the first opposite vector j3 and the first negative column vector j2 are opposite vectors to each other. For example, the electrical chip 21 may first adjust the values of all negative vector elements in the first column vector j to 0, and the values of the positive vector elements remain unchanged, and determine the column vector obtained by the adjustment as the first positive column vector j1. Then, the electronic chip 21 may also adjust the values of all positive vector elements in the first column vector j to 0, the values of negative vector elements remain unchanged, and determine the column vector obtained by the adjustment as the first negative column vector j2. The electrical chip 21 may then calculate the inverse of the first negative column vector j2 and determine the inverse of the first negative column vector j2 as the first inverse vector j3.

Further, the electrical chip 21 may transmit the first conversion matrix A1 to the optical multiplier array 25 in the optical chip 22, and transmit the first positive column vector j1 to the optical signal source 23 in the optical chip 22. Here, the process of transmitting the first conversion matrix A1 and the first column vector j1 by the electrical chip 21 for the optical chip 22 can be referred to as the specific process of transmitting the first conversion matrix A1 and the first column vector j by the electrical chip 21 for the optical chip 22 described above, which is not described herein. After receiving the first conversion matrix A1 and the first positive column vector j1, the optical chip 22 may perform multiplication operation on the first conversion matrix A1 and the first positive column vector j1 to obtain a multiplication result of the first conversion matrix A1 and the first positive column vector j1, and transmit the multiplication result of the first conversion matrix and the first positive column vector j to the electrical chip 21. Here, the specific process of multiplying the first conversion matrix A1 and the first column vector j1 by the optical chip 22 to obtain the multiplication result of the first conversion matrix A1 and the first column vector j1 may be referred to the process of multiplying the first conversion matrix A1 and the first column vector j by the optical chip 22 to obtain the multiplication result of the first conversion matrix A1 and the first column vector j described above, which will not be described herein. Similarly, the electrical chip may also transmit the first opposite column vector j3 to the optical chip 22, and the optical chip 22 may calculate a multiplication result of the first conversion matrix A1 and the first opposite column vector j3, and transmit the multiplication result of the first conversion matrix A1 and the first opposite column vector j3 to the electrical chip 21. It will be understood that the multiplication result of the first conversion matrix A1 and the first positive column vector j1 and the multiplication result of the first conversion matrix A1 and the first negative column vector j3 are the multiplication result of the first conversion matrix A1 and the first column vector j calculated by the optical chip 22. Then, the electrical chip 21 can determine the product C of the first transformation matrix A1 and the first column vector j according to the multiplication result of the first transformation matrix A1 and the first positive column vector j1 and the multiplication result of the first transformation matrix A1 and the first opposite column vector j 3. Specifically, after the result of multiplying the first conversion matrix A1 by the first positive column vector j1 and the result of multiplying the first conversion matrix A1 by the first negative column vector j3 are obtained, the electrical chip 21 may process to obtain a second intermediate product vector according to the result of multiplying the first conversion matrix A1 by the first positive column vector j1, and obtain a third intermediate product vector according to the result of multiplying the first conversion matrix A1 by the first negative column vector j3, and for a specific process, reference is made to the process of determining the first intermediate product vector by the electrical chip 21 according to the result of multiplying the first conversion matrix A1 by the first negative column vector j described above, which will not be described herein. Then, the electrical chip 21 may calculate the difference between the second intermediate product vector and the third intermediate product vector, and determine the product of the sum m of the differences between the second intermediate product vector and the third intermediate product vector as the product C of the first conversion matrix A1 and the first column vector j.

In the above implementation, in the case where the first column vector j has both positive vector elements and negative vector elements, since the optical chip 22 cannot implement the multiplication of the negative numbers, the electrical chip 21 first decomposes the first column vector j into the first positive column vector j1 and the first opposite column vector j3 that do not include the negative vector elements, and then completes the multiplication of the first conversion matrix A1 and the first positive column vector j1 and the multiplication of the first conversion matrix A1 and the first opposite column vector j3 by combining with the optical chip 22, and the multiplication of the first conversion matrix A1 and the first positive column vector j1 and the multiplication of the first conversion matrix A1 and the first opposite column vector j3 are the multiplication of the first conversion matrix A1 and the first column vector j. By the above mode, the electric chip 21 and the optical chip 22 can cooperatively complete the multiplication operation of the matrix and the column vector containing the negative vector elements, the cooperative processing capacity of the electric chip 21 and the optical chip 22 can be improved, and the applicability and the practicability of the channel estimation method are improved.

In another alternative implementation, the matrix elements with positive values (for convenience of description, positive matrix elements will be replaced by description) and the matrix elements with negative values (for convenience of description, negative matrix elements will be replaced by description) may exist in the first conversion matrix A1 at the same time, and in this case, the optical chip 22 may take the form of a differential multiplier array to calculate the product C of the first conversion matrix A1 and the first column vector j in cooperation with the electrical chip 21.

Referring to fig. 5, fig. 5 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the application. As shown in fig. 5, the optical chip 22 specifically includes an optical signal source 23, an optical signal adjusting module 24, a first optical multiplier array 271, a second optical multiplier array 272, a first optical receiving module 281, and a second optical receiving module 282. One end of the optical signal source 23 is connected to the electrical chip 21, and the other end is connected to the optical signal adjusting module 24. The optical signal adjustment module is further connected to the first optical multiplier array 271 and the second optical multiplier array 272, respectively. The first optical multiplier array 271 is also connected to a first photo-reception module 281, and the first photo-reception module 281 is also connected to the electric chip 21. The second optical multiplier array 272 is further coupled to the opto-electronic receiving module 282 and the opto-electronic receiving module 282 is further coupled to the electrical chip 21. In a specific implementation, the specific structure and function of the optical signal source 23 may be referred to together with the specific structure and function of the optical signal source 23 described above based on fig. 4, which is not repeated here. The specific structure and function of the optical signal adjustment module 24 are substantially the same as those described above based on fig. 4, and the main difference is that in the present implementation, the optical signal adjustment module 24 outputs 2m second signal lights, where m second signal lights in the 2m second signal lights are transmitted to the first optical multiplier array 271, and the other m second signal lights are transmitted to the second optical multiplier array 272. It will be appreciated, therefore, that in this implementation, each of the 2m second signal lights carries no more than a first column vector (j, m), but rather the outputs of the first column vectors j and 2m (here assumed to be the first column vector (j, 2 m)), where the first column vector (j, 2 m) is equal toThe specific structure and function of the first optical multiplier array 271 and the second optical multiplier array 272 described above may be referred to together with the structure and function of the optical multiplier array 25 described above based on fig. 4, and will not be repeated here. The specific structure and function of the first and second photo-reception modules 281 and 282 described above may be referred to together with the structure and function of the photo-reception module 26 described above based on fig. 4, and the description thereof will not be repeated here. In the following, a process of obtaining the product of the first conversion matrix A1 and the first column vector j by the co-calculation of the electrical chip 21 and the optical chip 22 in the case where the positive matrix element and the negative matrix element are simultaneously present in the first conversion matrix A1 will be described in detail with reference to the structure shown in fig. 5.

In practical applications, after the electrical chip 21 obtains the first conversion matrix A1, when determining that there are negative matrix elements in the first conversion matrix A1, the electrical chip 21 may first decompose the first conversion matrix A1 into a first positive conversion matrix and a first negative conversion matrix. The sum of the first positive conversion matrix and the first negative conversion matrix is the first conversion matrix A1, the value of any matrix element in the first positive conversion matrix is positive number or 0, and the value of any matrix element in the first negative conversion matrix is negative number or 0. For example, the electrical chip 21 may adjust all negative matrix elements in the first conversion matrix A1 to 0 and determine the adjusted first conversion matrix A1 as the first positive conversion matrix. The electrical chip 21 may also adjust all positive matrix elements in the first conversion matrix A1 to 0 and determine the adjusted first conversion matrix A1 as the first negative conversion matrix. The electrical chip 21 may then also determine a first inverse transformation matrix corresponding to the first negative transformation matrix. Wherein the sum of the first inverse transformation matrix and the first negative transformation matrix is 0. For example, the electrical chip 21 may determine the product of the first negative conversion matrix and the value-1 as a first inverse conversion matrix corresponding to the first negative conversion matrix. The electrical chip 21 may then transmit the first positive conversion matrix to the first optical multiplier array 271 such that the first optical multiplier array 271 is capable of carrying the first positive conversion matrix. Specifically, the electrical chip 21 may generate a fifth electrical signal corresponding to the first positive conversion matrix according to the values of m×m matrix elements included in the first positive conversion matrix, and transmit the fifth electrical signal to the first optical multiplier array 271, and the first optical multiplier array 271 may adjust the refractive index of each optical multiplier included in the fifth electrical signal according to the fifth electrical signal, so as to complete the bearing of the first conversion matrix. Here, the detailed process may refer to the process that the electrical chip 21 transmits the first conversion matrix A1 to the optical chip 22, and the optical chip 22 carries the first conversion matrix A1, which is not described herein again. Similarly, the electrical chip 21 may generate a sixth electrical signal corresponding to the first inverse transformation matrix according to the values of the m×m matrix elements included in the first inverse transformation matrix, and transmit the sixth electrical signal to the second optical multiplier array 272. The optical multiplier array 272 may perform the loading of the first inverse transformation matrix by the sixth electrical signal.

After the first column vector j is obtained, the electrical chip 21 may generate a first electrical signal corresponding to the first column vector j from the values of the vector elements in the first column vector j, and transmit the first electrical signal to the optical signal source 23. The optical signal source 23 may generate and output m paths of first signal light from the first electric signal. Here, the description of the m paths of the first signal light may be specifically referred to the foregoing, and will not be repeated herein. After receiving the m paths of first signal lights, the optical signal adjustment module 24 may perform beam combination and power processing on the m paths of first signal lights, thereby obtaining 2m paths of second signal lights. Here, each of the 2m second signal lights carries a first column vector (j, 2 m). Here, the specific process of generating the m paths of the first signal lights by the optical signal source 23 and generating the 2m paths of the second signal lights by the optical signal adjustment module may refer to the process of generating the m paths of the first signal lights by the optical signal source 23 and generating the m paths of the second signal lights by the optical signal adjustment module described above, which will not be described herein. Then, the optical signal adjustment module 24 may transmit m second signal lights of the 2m second signal lights to the first optical multiplier array 271 and transmit the remaining m second signal lights to the second optical multiplier array 272. After receiving the m paths of second signal lights, the first optical multiplier array 271 may adjust optical power of the m paths of second signal lights by using each optical multiplier included in the m paths of second signal lights, so as to obtain m paths of fifth signal lights. The optical power value of each of the m fifth signal lights may correspond to a multiplication result indicating each row vector in the first positive conversion matrix and the first column vector j. Here, the specific process of the first optical multiplier array 271 to obtain the m fifth signal lights may be referred to the process of the optical multiplier array 25 to obtain the m third signal lights, which is described above, and will not be described herein. Then, the first optical multiplier array 271 may transmit the m fifth signal lights to the optical receiving module 281, and the optical receiving module 281 may detect an optical power value of each of the m fifth signal lights. Here, the optical power values of the m fifth signal lights are the multiplication result of the first positive conversion matrix calculated by the optical chip 22 and the first column vector j. Then, the photoelectric receiving module 281 may generate a corresponding seventh electrical signal according to the optical power value of the m fifth signal lights, and transmit the multiplication result of the first positive conversion matrix and the first column vector j to the electrical chip 21 through the seventh electrical signal. Similarly, after receiving the m paths of second signal lights, the second optical multiplier array 272 may adjust optical power of the m paths of second signal lights to obtain m paths of sixth signal lights. Here, the optical power of each of the m sixth signal lights may correspond to a multiplication result indicating each row vector and the first column vector j in the first inverse transformation matrix. Then, the second optical multiplier array 272 may transmit the m sixth signal lights to the second optical receiving module 282, and the optical receiving module 282 may detect an optical power value of each of the m sixth signal lights. Here, the optical power values of the m sixth signal lights are the multiplication result of the first inverse transformation matrix calculated by the optical chip 22 and the first column vector j. Then, the photoelectric receiving module 281 may generate a corresponding eighth electrical signal according to the optical power value of the m sixth signal lights, and transmit the multiplication result of the first positive conversion matrix and the first column vector j to the electrical chip 21 through the eighth electrical signal. At this time, the result of the multiplication of the first positive conversion matrix and the first column vector j and the result of the multiplication of the first negative conversion matrix and the first column vector j are the result of the multiplication of the first conversion matrix A1 and the first column vector j. After obtaining the multiplication result of the first positive conversion matrix and the first column vector j and the multiplication result of the first inverse conversion matrix and the first column vector j, the electrical chip 21 can determine and obtain the product of the first conversion matrix A1 and the first column vector j according to the multiplication result of the first positive conversion matrix and the first column vector j and the multiplication result of the first inverse conversion matrix and the first column vector j. Specifically, the electrical chip 21 may obtain the fourth intermediate product vector according to the multiplication result of the first positive conversion matrix and the first column vector j, and the specific process may refer to the process of determining the first intermediate product vector by the electrical chip 21 according to the multiplication result of the first conversion matrix A1 and the first column vector j, which is not described herein. Similarly, the electrical chip 21 may obtain a fifth intermediate product vector according to the multiplication result of the first inverse transformation matrix and the first column vector j. Then, the electrical chip 21 may calculate the difference between the fourth intermediate product vector and the fifth intermediate product vector, and determine the product of the difference between the fourth intermediate product vector and the fifth intermediate product vector and 2m as the product B of the first conversion matrix A1 and the first column vector j. Thus, the electric chip 21 and the optical chip 22 cooperate to perform the multiplication operation of the first conversion matrix A1 and the first column vector j.

In the above implementation, in the case where the first conversion matrix A1 has both positive matrix elements and negative matrix elements, since the optical chip 22 cannot implement multiplication of negative numbers, the electrical chip 21 first decomposes the first conversion matrix A1 into a first positive conversion matrix and a first negative conversion matrix that do not include negative matrix elements, and then completes multiplication of the first positive conversion matrix with the first column vector j and multiplication of the first negative conversion matrix with the first column vector j in combination with the optical chip 22, and multiplication of the first positive conversion matrix with the first column vector j and multiplication of the first negative conversion matrix with the first column vector j are the multiplication of the first conversion matrix A1 with the first column vector j. By the above mode, the electric chip 21 and the optical chip 22 can cooperatively complete the multiplication operation of the matrix containing the negative matrix elements and the column vector, the cooperative processing capacity of the electric chip 21 and the optical chip 22 can be improved, and the applicability and the practicability of the channel estimation method provided by the application are improved.

It should be noted here that, when there are negative matrix elements in the first conversion matrix A1 and at the same time, there are negative vector elements in the first column vector j, the above two different implementations may be combined together to use the above two different implementations together, so that the electric chip 21 and the optical chip 22 can cooperatively complete multiplication between the matrix containing the negative matrix elements and the column vector containing the negative vector elements, thereby further improving the cooperative processing capability of the electric chip 21 and the optical chip 22, and improving the applicability and practicality of the channel estimation method provided by the present application.

The foregoing describes the specific process of multiplying the first conversion matrix A1 by the first column vector j by the channel estimation device 20 through the electrical chip 21 and the optical chip 22, and the detailed description of a channel estimation method applicable to the channel estimation device 20 provided by the present application will be described below with reference to the various structures of the channel estimation device 20 and the process of multiplying the matrix by the vector.

Referring to fig. 6, fig. 6 is a flowchart of a channel estimation method according to an embodiment of the present application. As shown in fig. 6, the channel estimation method provided by the present application may include the following steps:

s601, the electric chip acquires a channel incidence matrix of a target wireless channel and determines a first inverse matrix of a diagonal element matrix of the channel incidence matrix.

In some possible implementations, when the channel estimation device 20 determines that channel estimation needs to be performed on the target wireless channel, the electrical chip 21 may acquire the channel correlation matrix (i.e. the matrix a described above, which will be collectively described by the channel correlation matrix a below) corresponding to the target wireless channel. For example, in the case of channel estimation based on the zero forcing method, the electrical chip 21 may calculate the channel correlation matrix a from the channel matrix H of the target wireless channel according to the formula (4) described above. For another example, in the case of channel estimation based on the minimum mean square error method, the chip 21 may calculate the channel correlation matrix a from the channel matrix H of the target wireless channel according to the above-described formula (7). For convenience of description, this scenario of channel estimation based on the zero forcing method will be described later as an example. After the electrical chip 21 obtains the channel correlation matrix a of the target wireless channel, the diagonal element matrix of the channel correlation matrix a may be determined, and then the inverse matrix of the diagonal element matrix of the channel correlation matrix a is obtained by combining the characteristic calculation of the diagonal element matrix (for convenience of distinction, the description will be replaced by the first inverse matrix, which is assumed to be B here). Here, it should be noted that, in the embodiment of the present application, the channel correlation matrix a is a square matrix, and the number of rows and columns are m.

S602, the electric chip determines a first matrix to be multiplied according to the channel incidence matrix, and determines a preset value of a first parameter matrix according to a first inverse matrix.

S603, the electrical chip performs normalization processing on the first to-be-multiplied matrix to obtain a first conversion matrix, and transmits the first conversion matrix to the optical chip.

S604, the electrical chip normalizes m column vectors of the first parameter matrix to obtain m first column vectors.

S605, the electrical chip transmits any first column vector j of the m first column vectors to the optical chip.

S606, the optical chip multiplies the first conversion matrix by the first column vector j to obtain a multiplication result of the first conversion matrix and the first column vector j, and transmits the multiplication result of the first conversion matrix and the first column vector j to the electrical chip.

S607, the electrical chip determines a first product of the first to-be-multiplied matrix and the first parameter matrix according to the multiplication result of the first conversion matrix and each first column vector of the m first column vectors.

S608, the electric chip determines a target inverse matrix corresponding to the channel correlation matrix according to the first product.

It should be noted that, the present application provides various application scenarios for different implementation forms of the channel correlation matrix a and different structures of the optical chip 22, and the specific implementation processes of the steps S602 to S608 are different in different application scenarios. Therefore, the specific implementation procedures of the above steps S602 to S608 will be described in detail according to different application scenarios.

Application scenario one:

In the application scenario, a channel correlation matrix A of the target wireless channel and a first inverse matrix B corresponding to the channel correlation matrix A are complex matrices. The optical chip 22 is a separate optical chip, and includes only one set of the optical signal source 23, the optical signal adjustment module 24, the optical multiplier array 25, and the optical-electrical receiving module 26 shown in fig. 3 or fig. 4, or includes only one set of the optical signal source 23, the optical signal adjustment module 24, the first optical multiplier array 271, the second optical multiplier array 272, the first optical-electrical module 281, and the second optical-electrical receiving module 282 shown in fig. 5. The first conversion matrix specifically comprises a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix, and the first conversion matrix comprises a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix. The first product of the first conversion matrix and the first parameter matrix specifically comprises a first sub-product of a first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of a second to-be-multiplied sub-matrix and the first parameter matrix.

For the above step S602, in the present application scenario, the first to-be-multiplied matrix (assumed to be A2 here) may specifically include the first to-be-multiplied sub-matrix (assumed to be a matrix P _u here) and the second to-be-multiplied sub-matrix (assumed to be a matrix Q _u here). After obtaining the channel correlation matrix a and the first inverse matrix B, the electrical chip 21 may determine a first to-be-multiplied submatrix P _u and a second to-be-multiplied submatrix Q _u included in the first to-be-multiplied matrix A2 according to the channel correlation matrix a. Specifically, the electrical chip 21 may determine a real matrix (here assumed to be P) and an imaginary matrix (here assumed to be Q) of the channel correlation matrix a. Here, the channel correlation matrix a should satisfy the following relation (13):

A＝P+i×Q (13)

where i is an imaginary number. The real matrix P and the imaginary matrix Q are also square matrices of m rows and m columns.

Then, the electrical chip 21 blocks the real matrix P to obtain the above-mentioned first to-be-multiplied sub-matrix P _u. The electrical chip 21 may also block the imaginary matrix Q to obtain the second matrix Q _u. Here, the columns of the first to-be-multiplied submatrix P _u and the second to-be-multiplied submatrix Q _u obtained by the electrical chip 21 should be equal to m, and the sum of the number of rows of the first to-be-multiplied submatrix P _u and the number of rows of the second to-be-multiplied submatrix Q _u should be equal to m. For example, the chip 21 may separate out the 1 st to m1 st row vectors in the real matrix P and serve as the first to-be-multiplied submatrix P _u. Wherein m1 is a positive number greater than 0 and less than m. The chip 21 may also separate the m1+1st through mth row vectors in the imaginary matrix and serve as the second matrix to be multiplied Q _u. After the above-described first inverse matrix B is acquired by the electric chip 21, the electric chip 21 can determine a real matrix (for convenience of distinction, the matrix R0 will be replaced with description) and an imaginary matrix (for convenience of distinction, the matrix T0 will be replaced with description). Here, b=r0+i×t0. The electrical chip 21 can then determine the real matrix R0 as a first value of the first parametric matrix (here assumed to be the parameter R). Here, the description of the first parameter matrix R is specifically made in the foregoing, and the value of the first parameter matrix R is kept as the real matrix R0 until the electronic chip 21 determines other values than the first value described above.

For the above step S603, since the refractive index corresponding to each optical multiplier in the optical chip 22 is between 0 and 1, in order to meet the data carrying requirement of the optical chip 22, the electrical chip 21 may perform normalization processing on the first to-be-multiplied submatrix P _u and the second to-be-multiplied submatrix Q _u to obtain a first conversion submatrix (here, assumed to be P1 _u) corresponding to the first to-be-multiplied submatrix P _u and a second conversion submatrix (here, assumed to be Q1 _u) corresponding to the second conversion submatrix Q _u, respectively. Here, the absolute value of the value of any one matrix element in the first conversion sub-matrix P1 _u and the second conversion sub-matrix Q1 _u is less than or equal to 1. Here, it should be noted that, the normalization process according to the present application is mainly used to limit the absolute value of the element included in the matrix or the vector to be between 0 and 1, so that the subsequent optical chip 22 can accurately carry the matrix or the vector. Alternatively, before the above normalization processing is performed on each matrix or vector, the electrical chip 21 may determine whether the absolute value of the values of all the elements included in the matrix or vector is less than or equal to 1. If the electrical chip 21 determines that the absolute value of the values of all the elements contained in this matrix or vector is less than or equal to 1, it can be determined that normalization of this matrix or vector is not necessary. If the electrical chip 21 determines that the absolute value of the value of at least one element in the matrix or vector is greater than 1, it determines that normalization of the matrix or vector is required. Taking the first to-be-multiplied sub-matrix P _u as an example, after the first to-be-multiplied sub-matrix P _u is obtained, the electrical chip 21 may determine the matrix element (here, it is assumed that a1 _max) with the largest absolute value included in the first to-be-multiplied sub-matrix P _u, and then determine the divisor of the first to-be-multiplied sub-matrix P _u and a1 _max as the first conversion sub-matrix P1 _u. Here, it can be understood that P _u＝a1_max×P1_u. Optionally, before the electrical chip 21 performs the normalization processing on the first to-be-multiplied sub-matrix P _u, the electrical chip 21 may determine whether the absolute values of all matrix elements included in the first to-be-multiplied sub-matrix P _u are less than or equal to 1. If yes, it may be determined that normalization processing for the first to-be-multiplied submatrix P _u is not required. In this case, the subsequent electrical chip 21 and optical chip 22 may directly calculate the multiplication result of the first to-be-multiplied submatrix P _u and each first column vector. If not, it may be determined to perform the normalization process on the first to-be-multiplied submatrix P _u to obtain a first transformed submatrix P _u. In this case, the electrical chip 21 and the optical chip 22 may calculate the multiplication result of the first transformation matrix P1 _u and each first column vector, and further reduce the multiplication result of the first to-be-multiplied matrix P _u and each first column vector. For convenience of explanation, the scenario in which the first to-be-multiplied submatrix P _u needs to be normalized will be described hereinafter. Similarly, the electrical chip 21 may also perform the same normalization process on the second submatrix Q _u to obtain a second conversion submatrix Q1 _u corresponding to the second submatrix Q _u. The specific process is similar to that of the aforementioned electrical chip 21 for determining whether it is necessary, and, in the case of determining the necessary scene, the normalization process is performed on the first to-be-multiplied sub-matrix P1 _u to obtain the first conversion sub-matrix P1 _u, and the description thereof will not be repeated here. After the first conversion sub-matrix P1 _u and the second conversion sub-matrix Q1 _u are obtained, the electrical chip 21 may transmit the first conversion sub-matrix P1 _u and the second conversion sub-matrix Q1 _u to the optical chip 22, respectively, so that the optical chip 22 carries the first conversion sub-matrix P1 _u and the second conversion sub-matrix Q1 _u at the same time.

For the above step S604, since the light intensity of each light source included in the optical chip 22 is a fixed value Z, and the light intensity of each first signal light in the m paths of first signal light outputted by the optical signal source 23 is required not to exceed the fixed value Z, the column vector transmitted to the optical chip 22 by the electrical chip 21 should ensure that the absolute value of the value of each vector element included therein is between 0 and 1, so that the optical chip 22 can accurately carry each vector from the electrical chip 21. After acquiring the first value of the first parameter matrix R, the electrical chip 21 may perform the normalization processing on the m column vectors included in the first parameter matrix to obtain m first column vectors corresponding to the m column vectors. Wherein the absolute value of the vector element of each of the m first column vectors is less than or equal to 1. It should be understood that, in actual operation, the electrical chip 21 may determine whether the absolute value of the vector element included in the first column vector is less than or equal to 1. If yes, determining to normalize the first column vector. If not, determining that normalization processing is not needed for the first column vector. For convenience of description, a scenario in which each column vector of the first parameter matrix R at the first value needs to be normalized will be described as an example. The column vector jc of the m column vectors of the first parametric matrix R is taken as an example. The microchip 21 may first determine the value of the vector element (here, e 1) with the largest absolute value contained in the column vector jc, and then determine the divisor of the column vector jc and the value e1 as the first column vector j, that is, jc=e1×j. The chip 21 performs the normalization processing described above for each of the m column vectors, and obtains m first column vectors. It will be appreciated that, in the foregoing, the first parametric matrix R is divided into m column vectors, and then the m column vectors are normalized respectively to obtain m first column vectors corresponding to the m column vectors. In practical application, the electrical chip 21 may perform normalization processing on the assigned first parameter matrix R to obtain a normalized first parameter matrix R. Here, for a specific process of normalizing the first parameter matrix R, reference may be made to the foregoing process of normalizing the first to-be-multiplied sub-matrix P _u to obtain the first conversion sub-matrix P1 _u, which is not repeated here. Here, the absolute value of the value of any matrix element in the first parameter matrix R after normalization is less than or equal to 1. The electrical chip 21 may then separate each column vector in the normalized first parametric matrix R to obtain m first column vectors.

For the above steps S605 and S606, after the m first column vectors are acquired, the electronic chip 21 may transmit any one of the m first column vectors, i.e., the first column vector j, to the optical chip 22. Then, the optical chip 22 may calculate the result of the multiplication of the first conversion sub-matrix P1 _u and the first column vector j and the result of the multiplication of the second conversion sub-matrix Q1 _u and the first column vector j, respectively, and transmit the result of the multiplication of the first conversion sub-matrix P1 _u and the first column vector j and the result of the multiplication of the second conversion sub-matrix Q1 _u and the first column vector j to the electrical chip 21 as the result of the multiplication of the first conversion matrix A1 and the first column vector j. Here, the specific process of the co-calculation of the electrical chip 21 and the optical chip 22 to obtain the result of the multiplication of the first conversion sub-matrix P1 _u and the first column vector j and the result of the multiplication of the second conversion sub-matrix Q1 _u and the first column vector j may be referred to the process of the co-calculation of the electrical chip 21 and the optical chip 22 to obtain the result of the multiplication of the first conversion matrix A1 and the first column vector j described above, which will not be repeated here.

Further, the electrical chip 21 may sequentially transmit m-1 first column vectors other than the first column vector j among the m first column vectors to the optical chip 22. The optical chip 22 may sequentially calculate the multiplication result of the first conversion sub-matrix P1 _u and the m-1 first column vectors, and the multiplication result of the second conversion sub-matrix Q1 _u and the m-1 first column vectors, and transmit the multiplication result of the first conversion sub-matrix P1 _u and the m-1 first column vectors, and the multiplication result of the second conversion sub-matrix Q1 _u and the m-1 first column vectors to the electrical chip 21.

For the above step S607, after obtaining the multiplication result of the first conversion sub-matrix P1 _u and each of the m first column vectors, the electrical chip 21 may obtain the product of the first conversion sub-matrix P1 _u and each of the first column vectors according to the multiplication result of the first conversion sub-matrix P1 _u and each of the first column vectors. Here, the process of obtaining the product of the first conversion sub-matrix P1 _u and each first column vector by the electrical chip 21 according to the multiplication result processing of the first conversion sub-matrix P1 _u and each first column vector may be referred to together with the process of obtaining the product of the first conversion matrix A1 and the first column vector j by the electrical chip 21 according to the multiplication result processing of the first conversion matrix A1 and the first column vector j described in the previous example, which will not be described herein. Then, the electrical chip 21 may perform normalization reduction processing corresponding to the normalization processing for the product of the first sub-matrix P1 _u and each first column vector to obtain the product of the first sub-matrix P _u and each first column vector. It should be understood that the normalization reduction process according to the embodiment of the present application is an inverse process of the normalization process, and is mainly used for reducing the matrix and the vector obtained after the normalization process to the matrix and the vector which are not normalized. For the first sub-matrix P1 _u, a normalization reduction process may be used to reduce the first sub-matrix P1 _u to the first to-be-multiplied sub-matrix P _u. Therefore, the electrical chip 21 can process the product of the first sub-matrix P1 _u and the m first column vectors into the product of the first sub-matrix P _u and the m first column vectors through the normalization reduction process. For example, in combination with the foregoing example of the normalization process, P _u＝a1_max×P1_u, the electrical chip 21 multiplies the product of the first matrix P1 _u and each first column vector by the value a1 _max to obtain the product of the first matrix P _u and each first column vector. After determining to obtain the product of the first to-be-multiplied sub-matrix P _u and each first column vector, the electrical chip 21 may further perform normalization reduction processing on the product of the first to-be-multiplied sub-matrix P _u and each first column vector to obtain the product of the first to-be-multiplied sub-matrix P _u and each column vector in the first parameter matrix R. It will be appreciated here that the second normalization reduction process described above is mainly used to reduce m first column vectors to m column vectors contained in the first parametric matrix R. For example, in combination with the foregoing normalization of the column vectors jc to obtain the first column vector j, jc=e1×j, the electrical chip 21 may multiply the product of the first submatrix P _u and the first column vector j by e1 to obtain the product of the first submatrix P _u and the column vector jc in the first parametric matrix R. Further, after obtaining the product of the first to-be-multiplied submatrix P _u and each column vector in the first parametric matrix R, the electrical chip 21 may combine the product of the first to-be-multiplied submatrix P _u and each column vector according to the arrangement position of each column vector in the first parametric matrix R to obtain the first sub-product of the first to-be-multiplied submatrix P _u and the first parametric matrix R. Similarly, after obtaining the multiplication result of the second conversion sub-matrix Q1 _u and each of the m first column vectors, the electrical chip 21 may also perform corresponding processing to obtain a second sub-product of the second to-be-multiplied sub-matrix Q _u and the first parameter matrix R. The specific process may refer to the process of the chip 21 for obtaining the first sub-product according to the multiplication result of the first conversion sub-matrix P1 _u and each of the m first column vectors, which is not described herein. Thus, the electrical chip 21 obtains a first product comprising a first sub-product and a second sub-product.

For the step S608, after the electrical chip 21 obtains the first and second sub-products, the target inverse matrix a ^-1 of the channel correlation matrix a may be determined according to the first and second sub-products.

In particular, the electrical chip 21 may determine the imaginary matrix T0 of the first inverse matrix B as a predetermined value of the second parametric matrix (here, the matrix parameter T is assumed), which will be replaced by the second value T0 for convenience of distinction. Similar to the first parametric matrix R described above, the second parametric matrix T is also a square matrix of m rows and m columns. The second parameter matrix T is also a matrix-type parameter preset by the electrical chip 21, the value of which is also updated by the electrical chip 21 continuously and iteratively. It should also be understood that after the electrical chip 21 determines a certain value of the second parameter matrix T, the value of the second parameter matrix T remains at this value until after the electrical chip 21 determines a new value, the value of the second parameter matrix T does not change to the new value. The value of the second parameter matrix T will remain at the above-mentioned second value T0 until the electrical chip 21 does not determine a new value of the second parameter matrix T.

Further, after assigning the second parameter matrix T according to the second value T0, the electrical chip 21 may perform normalization processing on the m column vectors included in the second parameter matrix to obtain m second column vectors corresponding to the m column vectors, similar to the process of determining to obtain the m first column vectors by the electrical chip 21 described above. Wherein the absolute value of the vector element of each of the m second column vectors is less than or 1. The column vector kc of the m column vectors of the second parametric matrix T is taken as an example. The microchip 21 may determine the value of the vector element (here, assuming e 2) having the largest absolute value in the column vector kc, then divide the column vector kc by the value e2, and determine the column vector kc divided by the value e2 as the second column vector k, that is, kc=e2×k. Alternatively, the chip 21 may normalize the column vector kc only if it is determined that the column vector kc contains a vector element having an absolute value greater than 1, as in the foregoing, or the chip 21 may directly determine the column vector kc as the second column vector k. For convenience of description, a scenario in which normalization processing is required for each column vector in the second parameter matrix T will be described in detail. Further, the electrical chip 21 performs the above normalization operation on each of the m column vectors in the second parameter matrix T, so as to obtain m second column vectors.

The electrical chip 21 may then transmit each of the m second column vectors to the optical chip 22, respectively. It should be noted that, since the electrical chip 21 has already transmitted the new second column vector to the optical chip 22, the column vector carried on the optical chip 22 is changed from the original first column vector to the current second column vector, and the electrical chip 21 does not transmit the new matrix to the optical chip 22, so that the first conversion sub-matrix P1 _u and the second conversion sub-matrix Q1 _u are still carried on the optical chip 22. Then, the optical chip 22 may calculate the multiplication result of the first conversion sub-matrix P1 _u and each of the m second column vectors, and the multiplication result of the second conversion sub-matrix Q1 _u and each of the second column vectors, and transmit the multiplication result of the first conversion sub-matrix P1 _u and each of the second column vectors, and the multiplication result of the second conversion sub-matrix Q1 _u and each of the second column vectors, to the electrical chip 21.

After receiving the multiplication result of the first conversion sub-matrix P1 _u and each second column vector, the electrical chip 21 can obtain the product of the first conversion sub-matrix P1 _u and each second column vector according to the multiplication result of the first conversion sub-matrix P1 _u and each second column vector. Then, the electrical chip 21 may perform a first reduction process on the product of the first conversion sub-matrix P1 _u and each of the second column vectors to obtain a product of the first to-be-multiplied sub-matrix P _u and each of the second column vectors. Here, the specific processing procedure may refer to the above-described process that the electrical chip 21 obtains the product of the first submatrix P _u and each second column vector according to the multiplication result of the first conversion submatrix P1 _u and each second column vector, which is not described herein again.

After determining to obtain the product of the first to-be-multiplied sub-matrix P _u and each second column vector, the electrical chip 21 may further perform the normalization reduction process on the product of the first to-be-multiplied sub-matrix P _u and each second column vector to obtain the product of the first to-be-multiplied sub-matrix P _u and each column vector in the second parameter matrix T. Here, the m second column vectors described above can be restored to m column vectors included in the second parameter matrix T by the normalization restoration process. Thus, the electrical chip 21 may process the product of the first to-be-multiplied submatrix P _u and each of the second column vectors into the product of the first to-be-multiplied submatrix P _u and each of the column vectors in the second parametric matrix T by a normalization reduction process. For example, in combination with the foregoing example, kc=e2×k, the electrical chip 21 multiplies the product of the first to-be-multiplied submatrix P _u and the second column vector k by the value e2 to obtain the product of the first to-be-multiplied submatrix P _u and the column vector kc in the second parameter matrix T. Further, after obtaining the product of each column vector in the first to-be-multiplied submatrix P _u and the second parametric matrix T, the electrical chip 21 may combine the product of the first to-be-multiplied submatrix P _u and each column vector according to the arrangement position of each column vector in the second parametric matrix T to obtain a third sub-product of the first to-be-multiplied submatrix P _u and the second parametric matrix T. Similarly, after obtaining the multiplication result of the second conversion sub-matrix Q1 _u and each of the m second column vectors, the electrical chip 21 may also perform corresponding processing to obtain a fourth sub-product of the second to-be-multiplied sub-matrix Q _u and the second parameter matrix T. The specific process may refer to the process of the aforementioned electrical chip 21 for obtaining the third sub-product according to the multiplication result of the first conversion sub-matrix P1 _u and each of the m second column vectors, which is not described herein. Thus, the electrical chip 21 can obtain the first, second, third and fourth sub-products.

Further, the electrical chip 21 may determine a portion of the real matrix P other than the first to-be-multiplied sub-matrix P _u as a third to-be-multiplied sub-matrix (here, P _d), and determine a portion of the real matrix Q other than the second to-be-multiplied sub-matrix Q _u as a fourth to-be-multiplied sub-matrix (here, Q _d). In connection with the previous example, the electrical chip 21 may separate out the m1+1th row vector to the mth row vector in the real matrix P and serve as the third to-be-multiplied sub-matrix P _d. The chip 21 may also separate the 1 st row vector to the m1 st row vector in the imaginary matrix Q as a fourth to-be-multiplied sub-matrix Q _d. Then, similar to the first to-be-multiplied sub-matrix P _u and the second to-be-multiplied sub-matrix Q _u, the electrical chip 21 may normalize the third to-be-multiplied sub-matrix P _d and the fourth to-be-multiplied sub-matrix Q _d to obtain a third conversion sub-matrix (here, P1 _d) corresponding to the third to-be-multiplied sub-matrix P _d and a fourth conversion sub-matrix (here, Q1 _d) corresponding to the fourth conversion sub-matrix Q _d, respectively. Here, the absolute value of the value of any one matrix element in the third conversion sub-matrix P1 _d and the fourth conversion sub-matrix Q1 _d is less than or equal to 1. Taking the third to-be-multiplied sub-matrix P _d as an example, the electrical chip 21 may determine the matrix element (here, a2 _max is assumed) with the largest absolute value included in the third to-be-multiplied sub-matrix P _d, and then determine the divisors of the third to-be-multiplied sub-matrices P _d and a2 _max as the third conversion sub-matrix P1 _d. I.e., P _d＝a2_max×P1_d. Similarly, the electrical chip 21 may perform the same normalization process on the fourth to-be-multiplied sub-matrix Q _d to obtain a corresponding fourth conversion sub-matrix Q1 _d.

The electrical chip 21 may then transmit the third conversion sub-matrix P1 _d and the fourth conversion sub-matrix Q1 _d to the optical chip 22, where the optical chip 22 carries the third conversion sub-matrix P1 _d and the fourth conversion sub-matrix Q1 _d. Then, the electrical chip 21 may sequentially transmit the m first column vectors to the optical chip 22, and the optical chip 22 may calculate the multiplication result of the third conversion sub-matrix P1 _d and each first column vector, and the multiplication result of the fourth conversion sub-matrix Q1 _d and each first column vector, and transmit the multiplication result of the third conversion sub-matrix P1 _d and each first column vector, and the multiplication result of the fourth conversion sub-matrix Q1 _d and each first column vector, to the electrical chip 21. After receiving the multiplication result of the third conversion sub-matrix P1 _d and each first column vector, the electrical chip 21 can process according to the multiplication result of the third conversion sub-matrix P1 _d and each first column vector to obtain the product of the third to-be-multiplied sub-matrix P _d and each first column vector.

After the electric chip 21 obtains the multiplication result of each first column vector of the third conversion sub-matrix P1 _d, the product of the third conversion sub-matrix P1 _d and each first column vector can be obtained according to the multiplication result of the third conversion sub-matrix P1 _d and each first column vector. Here, the process of obtaining the product of the third conversion sub-matrix P1 _d and each first column vector by the electrical chip 21 according to the multiplication result processing of the third conversion sub-matrix P1 _d and each first column vector may be referred to together with the process of obtaining the product of the first conversion matrix A1 and the first column vector j by the electrical chip 21 according to the multiplication result processing of the first conversion matrix A1 and the first column vector j described in the previous example, which will not be described herein.

Then, the electrical chip 21 may perform a normalization reduction process on the product of the third conversion sub-matrix P1 _d and each first column vector to obtain the product of the third to-be-multiplied sub-matrix P _d and each first column vector. Here, the electrical chip 21 may process the product of the third conversion sub-matrix P1 _d and the m first column vectors into the product of the third to-be-multiplied sub-matrix P _d and the m first column vectors through the normalization reduction process. For example, in combination with the previous example, P _d＝a2_max×P1_d, the chip 21 multiplies the product of the third conversion sub-matrix P1 _d and each first column vector by the value a2 _max to obtain the product of the third to-be-multiplied sub-matrix P _d and each first column vector. After determining to obtain the product of the third to-be-multiplied sub-matrix P _d and each first column vector, the electrical chip 21 may further perform normalization reduction processing on the product of the third to-be-multiplied sub-matrix P _d and each first column vector to obtain the product of the third to-be-multiplied sub-matrix P _d and each column vector in the first parameter matrix R. For a specific process, reference may be made to the above-described process of obtaining the product of the first to-be-multiplied submatrix P _u and each column vector in the first parameter matrix R through the normalization reduction process, which will not be described herein. Further, after obtaining the product of the third to-be-multiplied submatrix P _d and each column vector in the first parameter matrix R, the electrical chip 21 may combine the product of the third to-be-multiplied submatrix P _d and each column vector according to the arrangement position of each column vector in the first parameter matrix R to obtain a fifth submatrix of the third to-be-multiplied submatrix P _d and the first parameter matrix R. Similarly, after obtaining the multiplication result of the fourth conversion sub-matrix Q1 _d and each of the m first column vectors, the electrical chip 21 may also perform corresponding processing to obtain a sixth sub-product of the fourth to-be-multiplied sub-matrix Q _d and the first parameter matrix R. The specific process may refer to the process of the aforementioned electrical chip 21 for obtaining the sixth sub-product according to the multiplication result of the third conversion sub-matrix P1 _d and each of the m first column vectors, which is not described herein. To this end, the electrical chip 21 may obtain a first block product, a second block product, a third block product, a fourth block product, a fifth block product, and a sixth block product.

Further, the electrical chip 21 may sequentially transmit the m second column vectors to the optical chip 22, and the optical chip 22 may calculate the multiplication result of the third conversion sub-matrix P1 _d and each second column vector, and the multiplication result of the fourth conversion sub-matrix Q _1d and each second column vector, and transmit the multiplication result of the third conversion sub-matrix P1 _d and each second column vector, and the multiplication result of the fourth conversion sub-matrix Q1 _d and each second column vector, to the electrical chip 21.

After receiving the multiplication result of the third conversion sub-matrix P1 _d and each second column vector, the electrical chip 21 may perform the normalization reduction processing described above on the multiplication result of the third conversion sub-matrix P1 _d and each second column vector, so as to obtain the product of the third to-be-multiplied sub-matrix P _d and m column vectors in the second parameter matrix T. The specific process refers to the process of normalization reduction treatment described above, and will not be described here again. After obtaining the product of the third to-be-multiplied submatrix P _d and each second column vector, the electrical chip 21 may combine the product of the third to-be-multiplied submatrix P _d and each second column vector according to the arrangement position of each second column vector in the second parameter matrix T to obtain a seventh block product of the third to-be-multiplied submatrix P _d and the second parameter matrix T. Similarly, after the multiplication result of the fourth conversion sub-matrix Q _1d and each second column vector is obtained, the electrical chip 21 may also process to obtain the product of the fourth to-be-multiplied sub-matrix Q _d and each second column vector according to the multiplication result of the fourth conversion sub-matrix Q1 _d and each second column vector, and then process to obtain the eighth block product of the fourth to-be-multiplied sub-matrix Q _d and the second parameter matrix T according to the product of the fourth to-be-multiplied sub-matrix Q _d and each second column vector. Thus, the electrical chip 21 can obtain a first sub-product, a second sub-product, a third sub-product, a fourth sub-product, a fifth sub-product, a sixth sub-product, a seventh sub-product and an eighth sub-product.

In practical applications, the process of co-calculating the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-product, and the eighth sub-product by the electrical chip 21 and the optical chip 22 is not particularly limited in time sequence.

After the first, second, third, fourth, fifth, sixth, seventh and eighth sub-products are obtained, the electrical chip 21 may further cooperate with the optical chip 22 to determine the target inverse matrix a ^-1 corresponding to the target channel-associated matrix a according to the first, second, third, fourth, fifth, sixth, seventh and eighth sub-products.

Here, for convenience of explanation, it is assumed that the first sub-product is a matrix F1, the second sub-product is a matrix F2, the third sub-product is a matrix F3, the fourth sub-product is a matrix F4, the fifth sub-product is a matrix F5, the sixth sub-product is a matrix F6, the seventh sub-product is a matrix F7, and the eighth sub-product is a matrix F8.

In practical implementations, the electrical chip 21 may determine a first subvalue (here, the matrix J0 _u) of the predetermined third parameter matrix (here, the matrix J is assumed) according to the first subproduct and the fourth subproduct. Here, the third parameter matrix J, which is similar to the first parameter matrix R or the second parameter matrix T described above, is also a parameter of a matrix form preset by the electrical chip 21, the value of which is determined and updated by the electrical chip 21. Specifically, the electrical chip 21 may determine the difference between the first and fourth sub-products as the first sub-value J0 _u, that is, J _u =f1-F4. The electrical chip 21 may also determine a second sub-value (here assumed to be J0 _d) of the third parametric matrix based on the fifth sub-product and the eighth sub-product. Specifically, the electrical chip 21 may determine the difference between the fifth and eighth sub-products as the second sub-value, i.e., J _d =f5-F8. After the first subvalue J0 _u and the second subvalue J0 _d are obtained, the electrical chip 21 may perform matrix splicing on the first subvalue J0 _u and the second subvalue J0 _d, so as to obtain the value of the third matrix parameter J (for convenience of distinction, the third subvalue J0 will be replaced for description later). In this embodiment of the present application, the third matrix parameter J satisfies the following relation (14):

J＝P×R-Q×T(14)

The first to-be-multiplied sub-matrix P _u and the third to-be-multiplied sub-matrix P _d are obtained by partitioning the real matrix P, and the second to-be-multiplied matrix Q _u and the fourth to-be-multiplied matrix Q _d are obtained by partitioning the imaginary matrix Q. Therefore, as can be seen from the blocking characteristics of the matrix, the first sub-value J0 _u calculated by the first sub-product F1 and the fourth sub-product F4 is substantially one blocking matrix of the third value J0, and the second sub-value J0 _d calculated by the fifth sub-product F5 and the eighth sub-product F8 is substantially another blocking matrix of the third value J0, so the electrical chip 21 can directly splice the third value J0 according to the first sub-value J0 _u and the second sub-value J0 _d.

In addition, the electrical chip 21 may determine a first subvalue (K0 _u in this case) of the fourth parameter matrix (K in this case) according to the second subproduct and the third subproduct. Here, the fourth parameter matrix K, which is similar to the first parameter matrix R, the second parameter matrix T and the third parameter matrix J described above, is also a parameter of a matrix form preset by the electric chip 21, whose value is determined and updated by the electric chip 21. Specifically, the electrical chip 21 may determine the sum of the second and third sub-products as the first sub-value K0 _u, that is, K _u =f2+f3. The electrical chip 21 may also determine a second sub-value (here assumed to be K0 _d) of the fourth parameter matrix K based on the sixth sub-product and the seventh sub-product. Specifically, the electrical chip 21 may determine the sum of the sixth and seventh sub-products as the second sub-value K0 _d of the fourth parameter matrix K, i.e., K _d =f6+f7. After the first subvalue K0 _u and the second subvalue K0 _d are obtained, the electrical chip 21 can perform matrix splicing on the first subvalue K0 _u and the second subvalue K0 _d, so as to obtain the value of the fourth parameter matrix K (for convenience of distinction, the fourth subvalue K0 is described instead of the description). In this embodiment of the present application, the fourth matrix parameter K satisfies the following relation (15):

K＝P×T+Q×R(15)

the second to-be-multiplied sub-matrix P _u and the third to-be-multiplied sub-matrix P _d are obtained by partitioning the real matrix P, and the second to-be-multiplied matrix Q _u and the fourth to-be-multiplied matrix Q _d are obtained by partitioning the imaginary matrix Q. Therefore, as can be seen from the block characteristics of the matrix, the first sub-value K0 _u calculated by the second sub-product F2 and the third sub-product F3 is substantially one block matrix of the fourth value K0, and the second sub-value K0 _d calculated by the sixth sub-product F6 and the seventh sub-product F7 is substantially another block matrix of the fourth value K0, so the electrical chip 21 can directly splice the fourth value K0 according to the first sub-value K0 _u and the second sub-value K0 _d.

Here, in the calculation process of the values of the third matrix parameter J and the fourth matrix parameter K or the process related to cross multiplication between a plurality of matrices and a plurality of vectors is complex, so in the implementation, two different matrices which need to be multiplied by the same vector are segmented and simultaneously the segmented matrices of the two matrices are loaded on the optical chip, and then the corresponding multiplication operation is completed by adopting a vector cyclic refresh loading mode, so that compared with the mode of multiplying the two matrices with one vector successively, the occupation of the memory space of the electrical chip 21 can be effectively reduced, and the performance requirement on the electrical chip 21 can be reduced.

Further, after determining the first value R0, the second value T0, the third value J0, and the fourth value K corresponding to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, and the fourth parameter matrix K, the electrical chip 21 may calculate the value of the real part iteration result (assumed to be D _R here) according to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, and the fourth parameter matrix K and the preset first iteration formula under each value (for convenience of distinction, the fifth value D _R0 will be used instead). It should be noted that, the real part iteration result D _R is similar to the above 4 preset parameter matrices, and is also a matrix parameter preset by the electric chip 21, and its value is also calculated and updated by the electric chip 21. The first iterative formula may be specifically the following relation (16):

D_R＝2×R-R×J+T×K (16)

That is, d _R0 =2×r0-r0×j0+t0×k0. Here, the first iterative formula (16) will be described in detail later.

Meanwhile, the electrical chip 21 may also calculate the value of the imaginary part iteration result (here, assumed to be D _T) according to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, the fourth parameter matrix K, and the preset second iteration formula under the above values (for convenience of distinction, the sixth value D _T0 will be used instead). It should be noted that, the imaginary part iteration result D _T is similar to the above-mentioned 4 preset parameter matrices, and is also a matrix parameter preset by the electric chip 21, and its value is also calculated and updated by the electric chip 21. The second iterative formula may specifically be the following relation (17):

D_T＝2×T-R×K-T×J (17)

That is, d _T0 =2×t0-r0×k0-t0×j0. Here, the second iteration formula (17) will be described collectively later.

In a specific implementation, after assigning values to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J and the fourth parameter matrix K, the electrical chip 21 may perform a blocking process on the first parameter matrix R to obtain a first sub-parameter matrix (here, R _u is assumed) and a second sub-parameter matrix (here, R _d) corresponding to the first parameter matrix R. Meanwhile, the electrical chip 21 may further perform a blocking process on the second parameter matrix T to obtain a third sub-parameter matrix (here, T _u) and a fourth sub-parameter matrix (here, T _d) corresponding to the second parameter matrix T. Here, the sum of the rows of the first sub-parameter matrix R _u and the third sub-parameter matrix T _u is m, and the columns of the first sub-parameter matrix R _u and the third sub-parameter matrix T _u are m. The sum of the rows of the second sub-parameter matrix R _d and the fourth sub-parameter matrix T _d is m, and the columns of the second sub-parameter matrix R _d and the fourth sub-parameter matrix T _d are m. Here, the specific process of the electric chip 21 to obtain the first sub-parameter matrix R _u and the second sub-parameter matrix R _d by blocking and the specific process of obtaining the third sub-parameter matrix R _d and the fourth sub-parameter matrix T _d by blocking may be referred to together with the description of the process of obtaining the first to-be-multiplied sub-matrix P _u and the third to-be-multiplied sub-matrix P _d by blocking for the electric chip 21, which is not repeated herein.

After the first sub-parameter matrix R _u and the third sub-parameter matrix T _u are obtained, the electrical chip 21 may cooperate with the optical chip 22 to calculate a ninth sub-product of the first sub-parameter matrix R _u and the third parameter matrix J and a tenth sub-product of the third sub-parameter matrix T _u and the third parameter matrix J, respectively. Here, for a specific process of calculating the ninth and tenth sub-products by the electric chip 21 and the optical chip 22, respectively, reference may be made to the specific process of calculating the first and second sub-products by the electric chip 21 and the optical chip 22, respectively, which are described above, and will not be repeated here. Similarly, the electrical chip 21 may also cooperate with the optical chip 22 to calculate an eleventh sub-product of the first sub-parameter matrix R _u and the fourth parameter matrix K, and a twelfth sub-product of the third sub-parameter matrix T _u and the fourth parameter matrix K, respectively.

After the second sub-parameter matrix R _d and the fourth sub-parameter matrix T _d are obtained, the electrical chip 21 may also cooperate with the optical chip 22 to calculate the thirteenth sub-product of the second sub-parameter matrix R _d and the third parameter matrix J and the fourteenth sub-product of the fourth sub-parameter matrix T _d and the third parameter matrix J, respectively. Here, the specific process of the electric chip 21 and the optical chip 22 to calculate the thirteenth and fourteenth sub-products respectively may also refer to the specific process of the electric chip 21 and the optical chip 22 to calculate the first and second sub-products respectively, which are not described herein. Similarly, the electrical chip 21 may also cooperate with the optical chip 22 to calculate a fifteenth sub-product of the second sub-parameter matrix R _d and the fourth parameter matrix K, and a sixteenth sub-product of the fourth sub-parameter matrix T _d and the fourth parameter matrix K, respectively.

Here, for convenience of explanation, it is assumed that the ninth sub-product is a matrix F9, the tenth sub-product is a matrix F10, the eleventh sub-product is a matrix F11, the twelfth sub-product is a matrix F12, the thirteenth sub-product is a matrix F13, the fourteenth sub-product is a matrix F14, the fifteenth sub-product is a matrix F15, and the sixteenth sub-product is a matrix F16.

After obtaining the ninth to sixteenth sub-products F9 to F16, the chip 21 may calculate a fifth sub-value (herein, assumed to be (d _R1)_u)) corresponding to the fifth value d _R1 according to the first sub-parameter matrix R _u, the ninth sub-product F9, the twelfth sub-product F12, and the first iterative formula, where the fifth sub-value (d _R1)_u) satisfies the following relation (18):

(d_R1)_u＝2×R_u-F9+F12 (18)

Meanwhile, the electrical chip 21 may calculate a sixth sub-value (herein, assumed to be (d _R1)_d)) corresponding to the fifth value d _R1 according to the second sub-parameter matrix R _d, the thirteenth sub-product F13, the sixteenth sub-product F16, and the first iterative formula, where the sixth sub-value (d _R1)_d) satisfies the following relation (19):

(d_R1)_d＝2×R_d-F13+F16 (19)

Meanwhile, the electrical chip 21 may calculate a seventh subvalue (herein, assumed to be (d _T1)_u)) corresponding to the sixth value d _T1 according to the third subparameter matrix T _u, the tenth subproduct F10, the eleventh subproduct F11, and the second iterative formula, where the seventh subvalue (d _T1)_u) satisfies the following relation (20):

(d_T1)_u＝2×T_u-F10-F11 (20)

Meanwhile, the electrical chip 21 may calculate an eighth subvalue (herein, assumed to be (d _T1)_d)) corresponding to the sixth value d _T1 according to the fourth subparameter matrix T _d, the fifteenth subproduct F15, the fourteenth subproduct F14, and the second iterative formula, where the eighth subvalue (d _T1)_d) satisfies the following relation (21):

(d_T1)_d＝2×T_d-F14-F15 (21)

The electrical chip 21 can then obtain the fifth sub-value d _R1 based on the fifth sub-value (d _R1)_u and sixth sub-value (d _R1)_d are combined to obtain the fifth sub-value d _R1. Here, since the first sub-parameter matrix R _u and the second sub-parameter matrix R _d are obtained by dividing the first parameter matrix R into blocks, and the third sub-parameter matrix T _u and the fourth sub-parameter matrix T _d are obtained by dividing the second parameter matrix T, the electrical chip 21 can also obtain the fifth sub-value d _R1 based on the seventh sub-value (d _T1)_u is substantially one block matrix of the fifth sub-value d _R1 and the sixth sub-value (d _R1)_d is substantially the other block matrix of the fifth sub-value d _R1) based on the fifth sub-value (d _R1)_u and the sixth sub-value (d _R1)_d are combined to obtain the fifth sub-value d _R1. Similarly, the electrical chip 21 can also obtain the seventh sub-value (d 3792 is combined to obtain the eighth sub-value d _T1)_d).

Here, similarly to the foregoing, since the process of cross multiplication between a plurality of matrices and a plurality of vectors is involved in the calculation process of the fifth value D _R1 of the partial iteration result D _R and the sixth value D _T1 of the imaginary iteration result D _T, the process is complex, and the corresponding multiplication operation is completed in the mode of matrix partitioning and vector cyclic refresh loading, so that the occupation of the storage space of the electric chip 21 can be further reduced, thereby further reducing the performance requirement on the electric chip 21.

Further, after obtaining the fifth value D _R1 of the real part iteration result D _R and the sixth value D _T1 of the imaginary part iteration result D _T, the electrical chip 21 may add 1 to the value of the preset iteration number parameter (here, it is assumed that the parameter g is an integer greater than or equal to 0). Thus, the electrical chip 21 and the optical chip 22 complete a complete value iteration process for the real part iteration result D _R and the imaginary part iteration result D _T. Then, the electrical chip 21 may determine whether the current value of the iteration number parameter g is equal to the preset iteration number t. It should be noted that, the initial value of the iteration number parameter g is smaller than the preset iteration number t, and t is a positive integer. Preferably, when the initial value of the iteration number parameter g is 0, the value of the preset iteration number t is greater than or equal to 4.

If the electrical chip 21 determines that the current value of the iteration number parameter g is equal to the preset iteration number t, the electrical chip 21 may determine the target inverse matrix a ^-1 of the channel correlation matrix a according to the fifth value d _R1 and the sixth value d _T1. Specifically, the electrical chip 21 may determine a complex matrix with d _R1 as a real matrix and d _T1 as an imaginary matrix, and determine the complex matrix as the target inverse matrix a ^-1. I.e., a ^-1＝d_R1+i×d_T1.

If the current value of the iteration number parameter g is determined by the electrical chip 21 to be smaller than the preset iteration number t, the electrical chip 21 and the optical chip 22 may repeat the value iteration process described above for the real part iteration result D _R and the imaginary part iteration result D _T again. Specifically, the electrical chip 21 may determine the fifth value D _R0 of the real part iteration result D _R as the new value of the first parameter matrix R (i.e., the value of the first parameter matrix R is then the fifth value D _R1), and determine the sixth value D _T0 of the imaginary part iteration result D _T as the new value of the second parameter matrix T (i.e., the value of the first parameter matrix R is then the sixth value D _T1). Then, the electrical chip 21 and the optical chip 22 may calculate a new value (J1 here) of the third parameter matrix R and a new value (K1 here) of the fourth parameter matrix T according to the first parameter matrix R, the second parameter matrix T, and the real part matrix P and the imaginary part matrix Q of the channel correlation matrix a. Here, the specific process of cooperatively calculating the third parameter matrix J and the fourth parameter matrix K by the electrical chip 21 and the optical chip 22 may be referred to as the process of cooperatively calculating the third parameter matrix J0 and the fourth parameter matrix K by the electrical chip 21 and the optical chip 22 described above, which will not be described herein. Then, the electrical chip 21 and the optical chip 22 can calculate the new value (here, D _R2) of the real part iteration result D _R and the new value (here, D _T2) of the imaginary part iteration result D _T according to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, and the fourth parameter matrix K. The above-mentioned fifth value d _R1 and sixth value d _T1 can be obtained by the above-mentioned co-calculation of the electrical chip 21 and optical chip 22 together for the specific process ,d_R2＝2×d_R1-d_R1×J1+d_T1×K1,d_T2＝2×d_T1-d_R1×K1-d_T1×J1., which will not be described here. Then, the electrical chip 21 may continue to determine whether the current value of the iteration number parameter g is equal to the preset iteration number t. If the electrical chip 21 determines that the current value of the iteration number parameter g is equal to the preset iteration number t, the electrical chip 21 may determine the target inverse matrix a ^-1 of the channel correlation matrix a according to the value d _R2 and the value d _T2. Specifically, the electrical chip 21 may determine a complex matrix with d _R2 as a real matrix and d _T2 as an imaginary matrix, and determine the complex matrix as the target inverse matrix a ^-1. I.e., a ^-1＝d_R2+i×d_T2. If the electrical chip 21 determines that the current value of the iteration number parameter g is still smaller than the preset iteration number T, the electrical chip 21 may determine the value D _R2 as a new value of the first parameter matrix R, determine the value D _T2 as a new value of the second parameter matrix T, and repeat the foregoing value iteration process for the real part iteration result D _R and the imaginary part iteration result D _t again according to the first parameter matrix R and the second parameter matrix T of the new value. Until the electric chip 21 determines that the value of the accumulated iteration number parameter is equal to the preset iteration number t, the electric chip can determine the target inverse matrix a ^-1 of the channel correlation matrix a according to the value of the real part iteration result D _R (here, D _Rt) and the value of the imaginary part iteration result D _T (here, D _Tt) obtained at the t time.

In other words, before the electrical chip 21 determines that the value of the iteration number parameter is not equal to the preset iteration number (herein, it is assumed that t times), the electrical chip 21 and the optical chip 22 repeatedly perform the following operations of the iteration process for the real part iteration result D _R and the imaginary part iteration result D _t:

the electrical chip 21 determines the value of the real part iteration result D _R obtained by the last determination according to the first iteration formula as the new value of the first parameter matrix R (that is, the value of the first parameter matrix R is updated to the value of the real part iteration result D _R obtained by the last determination according to the first iteration formula (16) of the electrical chip 21), and determines the value of the imaginary part iteration result D _T obtained by the last determination according to the second iteration formula (17) as the new value of the second parameter matrix T (that is, the value of the second parameter matrix T is updated to the value of the imaginary part iteration result D _T obtained by the last determination according to the second iteration formula (17) of the electrical chip 21). Then, the electrical chip 21 and the optical chip 22 recalculate the new values of the third parameter matrix J and the fourth parameter matrix K according to the new value of the first parameter matrix R, the new value of the second parameter matrix T, and the real part matrix P and the imaginary part matrix Q of the channel correlation matrix a. Then, the electrical chip 21 and the optical chip 22 may determine the new value of the real part iteration result D _R according to the first parameter matrix R of the new value, the second parameter matrix T of the new value, the third parameter matrix J of the new value, the fourth parameter matrix K of the new value, and the first iteration formula (16) described above. The electrical chip 21 and the optical chip 22 may also determine the new value of the imaginary part iteration result D _T according to the new value of the first parameter matrix R, the new value of the second parameter matrix T, the new value of the third parameter matrix J, the new value of the fourth parameter matrix K, and the second iteration formula (17). The electrical chip 21 may then also increment the value of the iterated number of times parameter by 1.

Until the electric chip 21 determines that the value of the accumulated iteration number parameter is equal to the preset iteration number t, the electric chip can determine the target inverse matrix a ^-1 of the channel correlation matrix a according to the value of the real part iteration result D _R (here, D _Rt) and the value of the imaginary part iteration result D _T (here, D _Tt) obtained at the t time. Specifically, the electrical chip 21 may determine a complex matrix with d _Rt as a real matrix and d _Tt as an imaginary matrix, and determine the complex matrix as the target inverse matrix a ^-1. I.e., a ^-1＝d_Rt+i×d_Tt.

In practical application, especially in the wireless massive MIMO communication scenario, the absolute values of the matrix elements in the fifth value d _R1 and the sixth value d _T1 are all smaller than or equal to 1, so that in the subsequent iteration process based on the fifth value d _R1 and the sixth value d _T1, the electrical chip 21 does not need to perform the normalization processing on the reassigned first parameter matrix R and second parameter matrix T, which can improve the calculation efficiency.

In the above implementation, the inversion process for the channel correlation matrix a is converted into the operation processes of multiplication, addition and subtraction among a plurality of matrices by the preset first iteration formula and second iteration formula, so as to provide feasibility for the co-calculation of the target inverse matrix a ^-1 of the channel correlation matrix a by the electrical chip 21 and the optical chip 22. In addition, when the channel correlation matrix A is a complex matrix, the processes of cross multiplication of a plurality of matrixes involved in the whole inversion process are simplified through matrix blocking, vector cyclic assignment and other modes, the occupied amount of the storage space of the electric chip 21 is reduced, the repeated assignment of the matrixes and the vectors by the optical chip 22 and the increase of the calculated amount caused by calculation are avoided, and the efficiency of channel estimation can be improved.

And (2) an application scene II:

in this application scenario, the channel correlation matrix a of the target wireless channel and the first inverse matrix (here, B) corresponding to the channel correlation matrix a are both complex matrices. The optical chip 22 is a composite optical chip. For example, referring to fig. 7, fig. 7 is a schematic diagram of another structure of a channel estimation apparatus according to an embodiment of the present application. As shown in fig. 7, the optical chip 22 specifically includes a first sub-optical chip 221 and a second sub-optical chip 222. The specific structure and function of the first sub-optical chip 221 and the second sub-optical chip 222 are the same as those of the optical chip 22 described above, that is, the first sub-optical chip 221 and the second sub-optical chip 222 each include a set of the optical signal source 23, the optical signal adjustment module 24, the optical multiplier array 25 and the optical-electrical receiving module 26 shown in fig. 3 or fig. 4, or each include a set of the optical signal source 23, the optical signal adjustment module 24, the first optical multiplier array 271, the second optical multiplier array 272, the first optical-electrical module 281 and the second optical-electrical receiving module 282 shown in fig. 5. Here, the description of the specific structure, function, and connection relationship with the electrical chip 21 for the first sub-optical chip 221 and the second sub-optical chip 222 may be given to the description of the specific structure, function, and connection relationship with the electrical chip 21 for the optical chip 22 hereinabove, and will not be repeated here. In addition, in the present application scenario, the first to-be-multiplied matrix (hereinafter, the description will be given below, that is, the first to-be-multiplied matrix A1) specifically includes a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix, and the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix. The first product of the first to-be-multiplied matrix and the first parameter matrix specifically comprises a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of the second to-be-multiplied sub-matrix and the first parameter matrix.

For the above step S602, in the present application scenario, the first to-be-multiplied matrix A1 may specifically include a first to-be-multiplied sub-matrix (here, assumed to be a matrix Pz) and a second to-be-multiplied sub-matrix (here, assumed to be a matrix Qz). After the channel correlation matrix a and the first inverse matrix B are obtained, the electrical chip 21 may determine the first to-be-multiplied submatrix Pz and the second to-be-multiplied submatrix Qz included in the first to-be-multiplied matrix A1 according to the channel correlation matrix a. Specifically, the electrical chip 21 may determine a real matrix (here assumed to be P) and an imaginary matrix (here assumed to be Q) of the channel correlation matrix a. The specific process is described in the first application scenario, and will not be described herein. Then, the electrical chip 21 may determine the real matrix P as a first to-be-multiplied sub-matrix Pz and the imaginary matrix Q as a second to-be-multiplied sub-matrix Qz. The electrical chip 21 can then determine the real matrix (here R0) and the imaginary matrix (here T0) of the above-mentioned first inverse matrix B, where b=r0+i×t0. The electrical chip 21 can then determine the real matrix R0 as a first value of the first parametric matrix (here assumed to be the parameter R). Here, the description of the first parameter matrix R is specifically made in the foregoing, and the value of the first parameter matrix R is kept as the real matrix R0 until the electronic chip 21 determines other values than the first value described above.

For the above step S603, the electrical chip 21 may perform normalization processing on the first to-be-multiplied submatrix Pz and the second to-be-multiplied submatrix Qz to obtain a first conversion submatrix (assumed herein to be Pz 1) corresponding to the first to-be-multiplied submatrix Pz and a second conversion submatrix (assumed herein to be Qz 1) corresponding to the second to-be-multiplied submatrix Qz. The specific process of normalizing the first to-be-multiplied submatrix Pz and the second to-be-multiplied submatrix Qz by the electrical chip 21 to obtain the first to-be-multiplied submatrix Pz1 and the first to-be-multiplied submatrix Qz1 can be referred to the specific process of normalizing the first to-be-multiplied submatrix P _u and the second to-be-multiplied submatrix Q _u by the electrical chip 21 to obtain the first to-be-multiplied submatrix P1 _u and the second to-be-multiplied submatrix Q1 _u described in the application scenario one above. After the electric chip 21 acquires the first conversion sub-matrix P1z and the second conversion sub-matrix Q1z, the electric chip 21 may transmit the first conversion sub-matrix P1z to the first sub-optical chip 221 in the optical chip 22, and the first sub-optical chip 221 carries the first conversion sub-matrix P1z. Meanwhile, the electrical chip 21 may transmit the second conversion sub-matrix Q1z to the second sub-optical chip 222 in the optical chip 22, and the second sub-optical chip 222 carries the second conversion sub-matrix Q1z.

For the step S604, after the first value of the first parameter matrix R is obtained and assigned, the electrical chip 21 may normalize the m column vectors in the first parameter matrix R to obtain m first column vectors corresponding to the m column vectors. Here, the specific process that the electrical chip 21 performs normalization processing on the m column vectors in the first parameter matrix R to obtain m first column vectors may refer to the specific process that the electrical chip 21 performs normalization processing on the m column vectors in the first parameter matrix R to obtain m first column vectors described in the first application scenario, which is not described herein again.

For the above steps S605 and S606, after the m first column vectors are acquired, the electrical chip 21 may transmit any one of the m first column vectors to the first sub-optical chip 221 and the second sub-optical chip 222. Then, the first sub-optical chip 221 may calculate a multiplication result of the first conversion sub-matrix P1z and the first column vector j and transmit the multiplication result of the first conversion sub-matrix P1z and the first column vector j to the electrical chip 21. Here, the specific process of cooperatively calculating the multiplication result of the first conversion sub-matrix P1z and the first column vector j by the electrical chip 21 and the first sub-optical chip 221 may be referred to as the process of cooperatively calculating the multiplication result of the first conversion matrix A1 and the first column vector j by the electrical chip 21 and the optical chip 22 described above, which will not be described herein. Similarly, the second sub-optical chip 222 may also calculate a multiplication result of the second conversion sub-matrix Q1z and the first column vector j, and transmit the multiplication result of the second conversion sub-matrix Q1z and the first column vector j to the electrical chip 21.

Further, the electrical chip 21 may sequentially transmit m-1 first column vectors except for the first column vector j among the m first column vectors to the first sub-optical chip 221 and the second sub-optical chip 222, the first sub-optical chip 221 may sequentially calculate a multiplication result of the first conversion sub-matrix P1z and the m-1 first column vectors and transmit the multiplication result to the electrical chip 21, and the second sub-optical chip 222 may sequentially calculate a multiplication result of the second conversion sub-matrix Q1z and the m-1 first column vectors and transmit the multiplication result to the electrical chip 21.

For the above step S607, after obtaining the multiplication result of the first conversion sub-matrix P1z and each first column vector of the m first column vectors, the electrical chip 21 may obtain the product of the first to-be-multiplied sub-matrix Pz and each first column vector according to the multiplication result processing of the first conversion sub-matrix P1z and each first column vector. Here, the process of the electric chip 21 to obtain the product of the first to-be-multiplied submatrix Pz and each first column vector according to the multiplication result processing of the first to-be-multiplied submatrix P1z and each first column vector may refer to the process of the electric chip 21 to obtain the product of the first to-be-multiplied submatrix P _u and each first column vector according to the multiplication result processing of the first to-be-multiplied submatrix P1 _u and each first column vector described in the first application scenario, which will not be described herein. After determining to obtain the product of the first to-be-multiplied submatrix Pz and each first column vector, the electrical chip 21 may combine the product of the first to-be-multiplied submatrix Pz and each first column vector according to the arrangement position of each first column vector in the first parameter matrix R, so as to obtain the first sub-product of the first to-be-multiplied submatrix Pz and the first parameter matrix R. Similarly, after receiving the multiplication result of the second conversion sub-matrix Q1z and each first column vector, the electrical chip 21 may also process to obtain a second sub-product of the second to-be-multiplied sub-matrix Qz and the first parameter matrix R according to the multiplication result of the second conversion sub-matrix Q1z and each first column vector. Thus, the electrical chip 21 obtains a first product comprising a first sub-product and a second sub-product.

In particular, the electrical chip 21 may determine the imaginary matrix T0 of the first inverse matrix as a preset value of the second parametric matrix (here, the matrix parameter T is assumed to be a value of the matrix parameter T) (for convenience of distinction, the second value will be replaced with a description later). Similar to the first parametric matrix R described above, the second parametric matrix T is also a square matrix of m rows and m columns. The second parameter matrix is also a parameter of the matrix form preset by the electrical chip 21, the value of which is also constantly updated by the electrical chip 21. It should also be understood that after the electrical chip 21 determines a certain value of the second parameter matrix T, the value of the second parameter matrix T remains at this value until after the electrical chip 21 determines a new value, the value of the second parameter matrix T does not change to the new value. The value of the second parameter matrix T will remain the above-mentioned imaginary matrix T0 until the electrical chip 21 has not determined a new value of the second parameter matrix T.

After obtaining the second value T0 of the second parameter matrix T and assigning the value, the electrical chip 21 may respectively normalize m column vectors included in the second parameter matrix T to obtain m second column vectors corresponding to the m column vectors. Here, the specific process that the electrical chip 21 performs normalization processing on the m column vectors included in the second parameter matrix T to obtain m second column vectors may refer to the specific process that the electrical chip 21 performs normalization processing on the m column vectors included in the second parameter matrix T to obtain m second column vectors, which is described in the first application scenario, and will not be described herein again. The electrical chip 21 may then transmit each of the m second column vectors to the first sub-optical chip 221 and the second sub-optical chip 222 of the optical chip 22, respectively. Here, since the electrical chip 21 does not transmit the new matrix to the first sub-optical chip 221 and the second sub-optical chip 222, the first sub-optical chip 221 still carries the first conversion sub-matrix P1z, and the second sub-optical chip 222 still carries the second conversion sub-matrix Q1z.

Then, the first sub-optical chip 221 may calculate a multiplication result of the first sub-matrix P1z and each of the m second column vectors, and transmit the multiplication result of the first sub-matrix P1z and each of the m second column vectors to the electrical chip 21. Meanwhile, the second sub-optical chip 222 may also calculate a multiplication result of the second conversion sub-matrix Q1z and each of the m second column vectors, and transmit the multiplication result of the second conversion sub-matrix Q1z and each of the second column vectors to the electrical chip 21. After receiving the multiplication result of the first sub-matrix P1z and each second column vector, the electrical chip 21 can obtain the product of the first sub-matrix to be multiplied Pz and m column vectors in the second parameter matrix T according to the multiplication result of the first sub-matrix P1z and each second column vector. For a specific process, refer to the process of the electrical chip 21 described in the application scenario one for obtaining the product of the first transformation sub-matrix P _u and m column vectors in the second parameter matrix T according to the multiplication result of the first transformation sub-matrix P _1u and each second column vector, which will not be described herein. After obtaining the product of m column vectors in the first to-be-multiplied submatrix Pz and the second parameter matrix T, the electrical chip 21 may combine the product of the first to-be-multiplied submatrix Pz and each column vector according to the arrangement position of each column vector in the second parameter matrix T, so as to obtain a third sub-product of the first to-be-multiplied submatrix Pz and the second parameter matrix T. Similarly, after receiving the multiplication result of the second conversion sub-matrix Q1z and each second column vector, the electrical chip 21 may also process according to the multiplication result of the second conversion sub-matrix Q1z and each second column vector to obtain a fourth sub-product of the second to-be-multiplied sub-matrix Qz and the second parameter matrix T. Thus, the electrical chip 21 can obtain the first, second, third and fourth sub-products.

Here, in practical applications, the process of the electric chip 21 and the first sub-optical chip 221 and the second sub-optical chip 222 cooperatively calculating the first sub-product, the second sub-product, the third sub-product and the fourth sub-product is not particularly limited in time sequence.

After the first, second, third and fourth sub-products are obtained, the electrical chip 21 may further cooperate with the optical chip 22 to determine the target inverse matrix a ^-1 corresponding to the target channel correlation matrix a according to the first, second, third and fourth sub-products. Here, for convenience of explanation, it is assumed that the first sub-product is a matrix F1, the second sub-product is a matrix F2, the third sub-product is a matrix F3, and the fourth sub-product is a matrix F4.

In a specific implementation, the electrical chip 21 may determine a preset third parameter matrix (here, assumed to be J) according to the first sub-product F1 and the fourth sub-product F4 (for convenience of distinction, the third parameter matrix will be described in detail with a third value J0). Here, the third parameter matrix J, which is similar to the first parameter matrix R or the second parameter matrix T described above, is also a parameter of a matrix form preset by the electrical chip 21, the value of which is determined and updated by the electrical chip 21. Specifically, the electrical chip 21 may determine the difference between the first sub-product F1 and the fourth sub-product F4 as the third value J0, that is, j0=f1 to F4. It will be understood that, since the first sub-product F1 is the product of the first sub-matrix to be multiplied Pz (whose value is the real matrix P) and the first parameter matrix R, and the fourth sub-product F4 is the product of the second sub-matrix to be multiplied (whose value is the imaginary matrix Q) and the second parameter matrix T, the relationship between the third value J0 and the first sub-product F1 and the fourth sub-product F4 can be known that the relationship between the third parameter matrix J and the real matrix P, the imaginary matrix Q, the first parameter matrix R, and the second parameter matrix T also satisfies the relationship (14). At the same time, the electrical chip 21 can also determine a predetermined fourth parameter matrix (K) from the second and third partial products F2 and F3. The fourth parameter matrix K, which is similar to the first parameter matrix R or the second parameter matrix T described above, is also a parameter of the matrix form preset by the electrical chip 21, the value of which is determined and updated by the electrical chip 21. Specifically, the electrical chip 21 may determine the sum of the second sub-product F2 and the third sub-product F3 as the fourth value K0 described above, that is, k0=f2+f3. It will be appreciated that, since the first sub-product F1 is the product of the first sub-matrix to be multiplied Pz (whose value is the real matrix P) and the first parameter matrix R, and the fourth sub-product F4 is the product of the second sub-matrix to be multiplied (whose value is the imaginary matrix Q) and the second parameter matrix T, the relationship between the fourth value K0 and the second word product F2 and the third sub-product F3 is known that the relationship between the third parameter matrix J and the real matrix P, the imaginary matrix Q, the first parameter matrix R and the second parameter matrix T also satisfies the relationship (15).

Further, after determining the first value R0, the second value T0, the third value J0, and the fourth value K corresponding to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, and the fourth parameter matrix K, the electrical chip 21 may calculate the value of the real part iteration result (assumed to be D _R here) according to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, and the fourth parameter matrix K and the preset first iteration formula under each value (for convenience of distinction, the fifth value D _R1 will be used instead). It should be noted that, the real part iteration result D _R is similar to the above 4 preset parameter matrices, and is also a matrix parameter preset by the electric chip 21, and its value is also calculated and updated by the electric chip 21. For details of the first iterative formula, reference may be made to the relation (16) in the first application scenario for description of the first iterative formula.

Meanwhile, the electrical chip 21 may also calculate the value of the imaginary part iteration result (here, assumed to be D _T) according to the first parameter matrix R, the second parameter matrix T, the third parameter matrix J, the fourth parameter matrix K, and the preset second iteration formula under the above values (for convenience of distinction, the sixth value D _T1 will be used instead). It should be noted that, the imaginary part iteration result D _T is similar to the above-mentioned 4 preset parameter matrices, and is also a matrix parameter preset by the electric chip 21, and its value is also calculated and updated by the electric chip 21. For the details of the second iterative formula, reference may also be made to the description of the second iterative formula in relation 17 in application scenario one.

After obtaining the fifth value D _R1 of the real part iteration result D _R and the sixth value D _T1 of the imaginary part iteration result D _T, the electrical chip 21 may add 1 to the value of the preset iteration number parameter (here, it is assumed that the parameter g is an integer greater than or equal to 0). Then, when the current value of the iteration frequency parameter g is still smaller than the preset iteration frequency t, the electric chip 21 may repeat the real part iteration result D _R and the imaginary part iteration result D _T for a plurality of iterations according to the fifth value D _R1 and the sixth value D _T1 until the value of the iteration frequency parameter is equal to the preset iteration frequency t. Here, the specific process of multiple iterations may refer to the iterative process for the real part iteration result D _R and the imaginary part iteration result D _t described in the application scenario one, which is not repeated here. Until the electric chip 21 determines that the value of the accumulated iteration number parameter is equal to the preset iteration number t, the electric chip can determine the target inverse matrix a ^-1 of the channel correlation matrix a according to the value of the real part iteration result D _R (here, D _Rt) and the value of the imaginary part iteration result D _T (here, D _Tt) obtained at the t time. Specifically, the electrical chip 21 may determine a complex matrix with d _Rt as a real matrix and d _Tt as an imaginary matrix, and determine the complex matrix as the target inverse matrix a ^-1. I.e., a ^-1＝d_Rt+i×d_Tt.

It should be understood that, in the foregoing description, the scenario in which the electrical chip 21 includes 2 sub-optical chips is taken as an example, in practical applications, 3 or more sub-optical chips may be included in the electrical chip 21, and in these scenarios, the electrical chip 21 may perform multiplication operations of multiple matrices and vectors through the multiple sub-optical chips at the same time. For example, when the electrical chip 21 includes 4 sub-optical chips, the electrical chip 21 may determine the first to-be-multiplied sub-matrix Pz, the second to-be-multiplied sub-matrix Qz, the first matrix parameter R, and the second matrix parameter T. Then, the product of the first submatrix Pz to be multiplied by the first parameter matrix parameter R, the product of the first submatrix Pz to be multiplied by the second parameter matrix parameter T, the product of the second submatrix Qz to be multiplied by the first parameter matrix parameter R and the product of the second submatrix Qz to be multiplied by the second parameter matrix parameter T are simultaneously calculated through the 4 submounts. The specific implementation process is similar to the implementation process under the scenario of the 2 sub-optical chips described above, and will not be described here again. Thus, the efficiency of channel estimation can be further improved.

In the same manner as in the first application scenario, especially in the wireless massive MIMO communication scenario, the absolute values of the matrix elements in the fifth value d _R1 and the sixth value d _T1 are all smaller than or equal to 1, so that in the subsequent iteration process based on the fifth value d _R1 and the sixth value d _T1, the electrical chip 21 does not need to perform the normalization processing on the first parameter matrix R and the second parameter matrix T after reassignment, which can improve the calculation efficiency.

In the above implementation, the inversion process for the channel correlation matrix a is converted into the operation processes of multiplication, addition and subtraction among a plurality of matrices by the preset first iteration formula and second iteration formula, so as to provide feasibility for the co-calculation of the target inverse matrix a ^-1 of the channel correlation matrix a by the electrical chip 21 and the optical chip 22. And in the case that the channel correlation matrix a is a complex matrix and the optical chip 22 is a composite electrical chip, the electrical chip 21 and the optical chip 22 can calculate the product of at least two matrices and vectors simultaneously, so that on one hand, the repeated assignment of the matrices and the vectors and the increase of calculation amount caused by calculation can be avoided, the efficiency of channel estimation can be improved, and on the other hand, the calculation resource of the optical chip 22 can be fully utilized.

And (3) an application scene III:

In this application scenario, the channel correlation matrix a of the target wireless channel and the first inverse matrix (here, B is assumed) corresponding to the channel correlation matrix a are real matrices. The optical chip 22 is a separate optical chip. Which contains only one set of optical signal source 23, optical signal adjustment module 24, optical multiplier array 25, and opto-electronic receiving module 26 as shown in fig. 3 or fig. 4, or only one set of optical signal source 23, optical signal adjustment module 24, first optical multiplier array 271, second optical multiplier array 272, first opto-electronic module 281, and second opto-electronic receiving module 282 as shown in fig. 5. Here, the description of the specific structure, function and connection relation with the electrical chip 21 of the optical chip 22 may be referred to the description of the specific structure, function and connection relation with the electrical chip 21 of the optical chip 22 in the foregoing application scenario, and will not be repeated here.

For the above step S602, after obtaining the channel correlation matrix a and the first inverse matrix B, the electrical chip 21 may determine the channel correlation matrix a as a first to-be-multiplied matrix A2, and determine the first inverse matrix B as a value of a first parameter matrix (assumed to be R here) (for convenience of distinction, the first value will be replaced with a description later). Here, the description of the first parameter matrix R may be specifically referred to the foregoing description, and will not be repeated herein. In the following, the values of the first parameter matrix R remain the first inverse matrix B until the electrical chip 21 determines other values than the first value.

For the step S603, after the first to-be-multiplied matrix A2 is obtained, the electrical chip 21 may perform normalization processing on the first to-be-multiplied matrix A1 to obtain a first conversion matrix (here, A1) corresponding to the first to-be-multiplied matrix A2. For a specific processing procedure, the electrical chip 21 described in the first application scenario one performs normalization processing on the first to-be-multiplied sub-matrix P _u to obtain a specific process of the first conversion sub-matrix P1 _u, which is not described herein again. The electrical chip 21 may then transmit the first conversion matrix A1 to the optical chip 22, and the optical chip 22 may then carry the first conversion matrix A1.

For the step S604, after assigning the first parameter matrix R according to the first value, the electrical chip 21 may separate the m column vectors included in the first parameter matrix R, and then normalize the m column vectors to obtain m second column vectors. Wherein, one column vector in the m column vectors is normalized to obtain a first column vector. Here, for a specific process of performing normalization processing on the m column vectors to obtain m first column vectors, reference may be made to the specific process of performing normalization processing on the m column vectors included in the first parameter matrix R by the electrical chip 21 described in the first application scenario one to obtain m first column vectors, which is not described herein again.

For the above steps S605 and S606, after the m first column vectors are acquired, the electronic chip 21 may transmit any one of the m first column vectors to the optical chip 22. Then, the optical chip 22 may calculate a multiplication result of the first conversion matrix A1 and the first column vector j, and transmit the multiplication result of the first conversion matrix A1 and the first column vector j to the electrical chip 21. Here, the specific process of the co-calculation of the electrical chip 21 and the optical chip 22 to obtain the result of the multiplication of the first conversion matrix A1 and the first column vector j may be referred to the specific process of the co-calculation of the electrical chip 21 and the optical chip 22 to obtain the result of the multiplication of the first conversion matrix A1 and the first column vector j described in the previous example, which will not be described herein.

Further, the electrical chip 21 may sequentially transmit m-1 first column vectors other than the first column vector j among the m first column vectors to the optical chip 22. The optical chip 22 may sequentially calculate the multiplication result of the first conversion matrix A1 and the m-1 first column vectors, and transmit the multiplication result of the first conversion matrix A1 and the m-1 first column vectors to the electrical chip 21.

For the above step S607, after obtaining the multiplication result of the first transformation matrix A1 and each first column vector of the m first column vectors, the electrical chip 21 can obtain the product of the first transformation matrix A1 and each first column vector according to the multiplication result processing of the first transformation matrix A1 and each first column vector. Here, the specific process of the electrical chip 21 for obtaining the product of the first transformation matrix A1 and each first column vector according to the multiplication result processing of the first transformation matrix A1 and each first column vector can be referred to the process of the electrical chip 21 for obtaining the product of the first transformation matrix A1 and the first column vector j according to the multiplication result processing of the first transformation matrix A1 and the first column vector j described above, which will not be described herein. After determining to obtain the product of the first transformation matrix A1 and each first column vector, the electrical chip 21 may obtain the product of the first to-be-multiplied matrix A2 and m column vectors included in the first parameter matrix R according to the product processing of the first transformation matrix A1 and each first column vector. For a specific process, the electrical chip 21 described in the application scenario two may be referred to as a specific process of obtaining the product of the first to-be-multiplied sub-matrix Pz and m column vectors included in the first parameter matrix R according to the product processing of the first conversion sub-matrix P1z and each first column vector, which will not be described herein. After obtaining the product of the first to-be-multiplied matrix A2 and the m column vectors included in the first parametric matrix R, the electrical chip 21 may combine the product of the first to-be-multiplied matrix A2 and the m column vectors included in the first parametric matrix R according to the arrangement position of each column vector in the first parametric matrix R, so as to obtain the product of the first conversion matrix A2 and the first parametric matrix R. Here, since the first to-be-multiplied matrix A2 is the channel correlation matrix a, the first value of the first parameter matrix R is the first inverse matrix B, and the first product of the first to-be-multiplied matrix A2 and the first parameter matrix R is the axr.

For the above step S608, after obtaining the first value of the first parameter matrix R and the first product a×r, the electrical chip 21 may calculate a value of the inversion iteration result (here, assumed to be D) by combining with a preset third iteration formula (for convenience of distinction, a seventh value D1 will be replaced with the description below). It should be noted that, the inversion iteration result D is similar to the first parameter matrix, the second parameter matrix, and the like described above, and is also a matrix parameter preset by the electrical chip 21, and the value of the matrix parameter is also updated by the electrical chip 21 continuously and iteratively. The third iterative formula satisfies the following relation (22):

D＝R×(2I-A×R) (22)

wherein I is an identity matrix. It should be noted that the above relation (22) may also be referred to as newton's iterative formula.

In particular implementations, the electrical chip 21 may first calculate the difference between 2I and the first product axr (here assumed to be CA). The electrical chip 21 and the optical chip 22 may then cooperatively calculate the product of the first parametric matrix R and the difference CA. Here, the specific procedure of the co-calculation of the product of the first parametric matrix R and the difference CA by the electric chip 21 and the optical chip 22 is similar to the procedure of the co-calculation of the first to-be-multiplied matrix A2 and the first parametric matrix R by the electric chip 21 and the optical chip 22 described above, and the description thereof will not be repeated here. The electrical chip 21 may then determine the product of the first parameter matrix R and the difference CA as the seventh value d1 of the inversion iteration result.

Further, after obtaining the seventh value D ₁ of the inversion iteration result D, the electrical chip 21 may add 1 to the value of the preset iteration number parameter g. Thus, the electrical chip 21 and the optical chip 22 complete a complete value iteration process for the inversion iteration result D. Then, the electrical chip 21 may determine whether the current value of the iteration number parameter g is equal to the preset iteration number t. It should be noted that, the initial value of the iteration number parameter g is smaller than the preset iteration number t.

If the electrical chip 21 determines that the current value of the iteration number parameter g is equal to the preset iteration number t, the electrical chip 21 may determine the seventh value d ₁ as the target inverse matrix a ^-1 of the correlation matrix a. I.e., a ^-1＝d₁.

If the current value of the iteration number parameter g determined by the electrical chip 21 is smaller than the preset iteration number t, the electrical chip 21 and the optical chip 22 may repeat the value iteration process for the inversion iteration result D described above again. Specifically, the electrical chip 21 may determine the seventh value d ₁ of the inversion iteration matrix as the new value of the first parameter matrix R. Then, the electrical chip 21 and the optical chip 22 can calculate the new value of the inversion iteration matrix D (here, D ₂) according to the first parameter matrix R of the new value and the third iteration formula (22). Wherein d ₂＝d₁×(2I-A×d₁). The detailed process of the seventh value d ₁ obtained by the cooperative calculation of the electrical chip 21 and the optical chip 22 is referred to as the above-mentioned detailed process, and will not be described here. The electrical chip 21 can then again increment the iteration number parameter g by 1. Then, the electrical chip 21 may continue to determine whether the current value of the iteration number parameter g is equal to the preset iteration number t. If the electrical chip 21 determines that the current value of the iteration number parameter g is equal to the preset iteration number t, the electrical chip 21 may determine the value d ₂ as the target inverse matrix a ^-1 of the channel correlation matrix a. If the electrical chip 21 determines that the current value of the iteration number parameter g is still smaller than the preset iteration number t, the electrical chip 21 may determine the value D ₂ as a new value of the first parameter matrix R, and repeat the foregoing value iteration process for the inversion iteration result D again according to the first parameter matrix R and the third iteration formula with new values. Until the electric chip 21 determines that the value of the accumulated iteration number parameter is equal to the preset iteration number t, the electric chip may determine that the value of the inversion iteration result D obtained at the t-th time (here, D _t is assumed to be a target inverse matrix a ^-1 of the channel correlation matrix a. I.e., a ^-1＝d_t.

In the same manner as in the first application scenario, especially in the wireless massive MIMO communication scenario, the absolute value of each matrix element in the seventh value d ₁ is smaller than or equal to 1, so that in the subsequent process of each iteration based on the seventh value d ₁, the electrical chip 21 does not need to perform the normalization processing on the first parameter matrix R and the second parameter matrix T after reassignment, which can improve the calculation efficiency.

In the above implementation, the inversion process for the channel correlation matrix a is converted into the operation processes of multiplication, addition and subtraction among a plurality of matrices by the preset third iteration formula, so as to provide feasibility for cooperatively calculating the target inverse matrix a ^-1 of the channel correlation matrix a by the electrical chip 21 and the optical chip 22. Then, under the condition that the channel correlation matrix a is a real number matrix, the target inverse matrix a ^-1 of the channel correlation matrix a is calculated rapidly and with low power consumption through cooperation of the electric chip 21 and the optical chip 22, so that the efficiency of channel estimation can be improved, the power consumption can be reduced, and the performance of a communication system to which the channel estimation device belongs can be improved.

S609, the electric chip determines the transmitting vector of the target wireless channel according to the target inverse matrix and the receiving vector of the target wireless channel.

In some possible implementations, after acquiring the target inverse matrix a ^-1, the electrical chip 21 may further acquire a MIMO receiving vector y of the target wireless channel, and then calculate a transmitting vector x of the target wireless channel according to the target inverse matrix a ^-1 and the MIMO receiving vector y.

Alternatively, in the case where the channel estimation device 20 performs channel estimation by using the zero forcing method, the electrical chip 21 may obtain the conjugate transpose matrix H ^H of the channel matrix H, and then calculate the zero forcing matrix W _ZF according to the above-mentioned relation (3), the target inverse matrix a ^-1, and the conjugate transpose matrix H ^H of the channel matrix H. Then, the electrical chip 21 may obtain the MIMO receiving vector y, and calculate the transmitting vector x of the target wireless channel according to the MIMO receiving vector y, the zero forcing matrix W _ZF and the above relation (2), thereby completing the channel estimation for the target wireless channel.

Alternatively, in the case where the channel estimation device 20 performs channel estimation by using the minimum mean square error method, the electrical chip 21 may obtain the conjugate transpose matrix H ^H of the channel matrix H, and then calculate the minimum mean square error matrix W _ZF according to the above-mentioned relation (6), the target inverse matrix a ^-1, and the conjugate transpose matrix H ^H of the channel matrix H. Then, the electrical chip 21 may obtain the MIMO receiving vector y, and calculate the transmitting vector x of the target wireless channel according to the MIMO receiving vector y, the minimum mean square error matrix W _ZF and the above formula (5), thereby completing the channel estimation for the target wireless channel.

It should be noted that, in the process of calculating the zero forcing matrix W _ZF or the minimum mean square error matrix W _ZF, the multiplication operation of the matrix and the matrix involved can be quickly completed through the electric chip 21 and the optical chip 22, so that the efficiency of channel estimation can be further improved.

In the embodiment of the present application, the channel estimation device 20 calculates the target inverse matrix a ^-1 of the a of the channel correlation matrix through the co-operation of the electrical chip 21 and the optical chip 22, and then calculates the emission vector x of the target wireless channel according to the target inverse matrix a ^-1 and the receiving vector y of the target wireless channel by further combining with the ZF method, the MMSE method, and other algorithms, thereby completing the channel estimation of the target wireless channel. The multiplication of the matrix and the vector involved in the whole calculation is mainly realized by the optical chip 22. Because the optical chip 22 requires a short time and low power consumption, the method of performing wireless channel estimation by the cooperation of the electrical chip 21 and the optical chip 22 is faster and lower in power consumption than the conventional method of performing wireless channel estimation by a digital integrated circuit, so that the efficiency of channel estimation can be effectively improved, the power consumption can be reduced, and the performance of the communication system in which the channel estimation device 20 is located can be improved.

The embodiment of the present application also provides a channel estimation device 20 for performing the above channel estimation method, please refer to the structure described in fig. 2. The channel estimation device 20 mainly comprises an electrical chip 21 and an optical chip 22 connected to each other. In a specific implementation, the electrical chip is configured to obtain a channel correlation matrix of a target wireless channel, and determine a first inverse matrix of a diagonal element matrix of the channel correlation matrix. The electric chip is used for determining a first matrix to be multiplied according to the channel incidence matrix, and determining a preset value of a first parameter matrix according to the first inverse matrix. The electrical chip is further configured to normalize the first to-be-multiplied matrix to obtain a first conversion matrix, and transmit the first conversion matrix to the optical chip. Wherein, the absolute value of the value of any matrix element in the first conversion matrix is smaller than or equal to 1. The electrical chip is further used for carrying out normalization processing on m column vectors of the first parameter matrix to obtain m first column vectors. Wherein the absolute value of the value of any vector element of each first column vector in the m first column vectors is less than or equal to 1, and m is an integer greater than or equal to 2. The electrical chip is further configured to transmit any first column vector j of the m first column vectors to the optical chip. The optical chip is used for multiplying the first conversion matrix with the first column vector j to obtain a multiplication result of the first conversion matrix and the first column vector j, and transmitting the multiplication result of the first conversion matrix and the first column vector j to the electrical chip. The electric chip is further used for determining a first product of the first matrix to be multiplied and the first parameter matrix according to a multiplication result of the first conversion matrix and each first column vector in the m first column vectors. And the electrical chip is also used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first product. The electric chip is further used for determining the transmitting vector of the target wireless channel according to the target inverse matrix and the receiving vector of the target wireless channel.

In one possible implementation, the channel correlation matrix and the first inverse matrix are complex matrices, and the first to-be-multiplied matrix includes a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix. The electrical chip is used for determining a real part matrix and an imaginary part matrix of the channel correlation matrix. The electrical chip is further configured to block a real matrix of the channel correlation matrix to obtain the first to-be-multiplied sub-matrix. The electric chip is further used for partitioning an imaginary matrix of the channel correlation matrix to obtain the second submatrix to be multiplied.

In a possible implementation, the electrical chip is further configured to determine a real matrix of the first inverse matrix. The electric chip is also used for determining the real part matrix of the first inverse matrix as a preset value of a first parameter matrix.

In one possible implementation, the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix, and the first product includes a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of the second to-be-multiplied block matrix and the first parameter matrix. The electric chip is also used for determining an imaginary matrix of the first inverse matrix and determining the imaginary matrix of the first inverse matrix as a preset value of a second parameter matrix. The electric chip is further used for carrying out normalization processing on m column vectors of the second parameter matrix to obtain m second column vectors, wherein the absolute value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1. The electrical chip is further configured to sequentially transmit each of the m second column vectors to the optical chip. The optical chip is further configured to multiply the first conversion sub-matrix and the second conversion sub-matrix with the second column vectors respectively to obtain a multiplication result of the first conversion sub-matrix and the second column vectors, and a multiplication result of the second conversion sub-matrix and the second column vectors, and transmit the multiplication result of the first conversion sub-matrix and the second column vectors to the electrical chip. The electric chip is further used for determining a third sub-product of the first to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the first conversion sub-matrix and each second column vector, and determining a fourth sub-product of the second to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the second conversion sub-matrix and each second column vector. The electric chip is further configured to determine a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, and the fourth sub-product.

In one possible implementation, the electrical chip is further configured to determine a portion of the real matrix of the channel correlation matrix other than the first to-be-multiplied sub-matrix as a third to-be-multiplied sub-matrix. The electrical chip is further configured to determine a portion of the imaginary matrix of the channel correlation matrix other than the second to-be-multiplied sub-matrix as a fourth to-be-multiplied sub-matrix. The electric chip is further used for respectively carrying out normalization processing on the third to-be-multiplied submatrix and the fourth to-be-multiplied submatrix to obtain a third conversion submatrix and a fourth to-be-multiplied submatrix. And the absolute value of the value of any matrix element in the third conversion submatrix and the fourth submatrix to be multiplied is smaller than or equal to 1. The electrical chip is further configured to transmit the third conversion sub-matrix and the fourth conversion sub-matrix to the optical chip. The electrical chip is further configured to sequentially transmit the first column vectors to the optical chip. The optical chip is further configured to multiply the third conversion sub-matrix and the fourth conversion sub-matrix with the first column vectors respectively to obtain a multiplication result of the third conversion sub-matrix and the first column vectors and a multiplication result of the fourth conversion sub-matrix and the first column vectors, and transmit the multiplication result of the third conversion sub-matrix and the first column vectors and the multiplication result of the fourth conversion sub-matrix and the first column vectors to the electrical chip. The electric chip is further configured to determine a fifth sub-product of the third to-be-multiplied sub-matrix and the first parameter matrix according to a multiplication result of the third conversion sub-matrix and each first column vector, and determine a sixth sub-product of the fourth to-be-multiplied sub-matrix and the first parameter matrix according to a multiplication result of the fourth conversion sub-matrix and each first column vector. The electric chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product and the sixth sub-product.

In one possible implementation, the electrical chip is further configured to sequentially transmit the second column vectors to the optical chip. The optical chip is further configured to multiply the third conversion sub-matrix and the fourth conversion sub-matrix with the second column vectors respectively to obtain a multiplication result of the third conversion sub-matrix and the second column vectors and a multiplication result of the fourth conversion sub-matrix and the second column vectors, and transmit the multiplication result of the third conversion sub-matrix and the second column vectors and the multiplication result of the fourth conversion sub-matrix and the second column vectors to the electrical chip. The electric chip is further used for determining a seventh sub-product of the third conversion sub-matrix and the second parameter matrix according to the multiplication result of the third conversion sub-matrix and each second column vector, and determining an eighth sub-product of the fourth to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the fourth conversion sub-matrix and each second column vector. The electric chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-matrix and the eighth sub-matrix.

In one possible implementation, the electrical chip is further configured to determine a first subvalue of a preset third parameter matrix according to the first subproduct and the fourth subproduct. The electrical chip is further configured to determine a first subvalue of a preset fourth parameter matrix according to the second subproduct and the third subproduct. The electrical chip is further configured to determine a second subvalue of the third parameter matrix according to the fifth subproduct and the eighth subproduct. The electrical chip is further configured to determine a second subvalue of the fourth parameter matrix according to the sixth subproduct and the seventh subproduct. The electrical chip is further configured to determine a value of the third parameter matrix according to the first sub-value and the third sub-value. And the electrical chip also determines the value of the fourth parameter matrix according to the second subvalue and the fourth subvalue. The electrical chip is further configured to determine a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

The electrical chip is further specifically configured to determine a value of an imaginary part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix, and a preset second iteration formula, where the second iteration formula includes:

D_R＝2×T-R×K-T×J

Before the electrical chip determines that the value of the iteration number parameter is not equal to the preset iteration number t, the electrical chip is further configured to repeatedly perform the following operations: and determining the value of the real part iteration result obtained by the last time according to the first iteration formula as a new value of the first parameter matrix, and determining the value of the imaginary part iteration result obtained by the last time according to the second iteration formula as a new value of the second parameter matrix. And re-determining the new values of the third parameter matrix and the fourth parameter matrix according to the new value first parameter matrix, the new value second parameter matrix and the real part and the imaginary part of the normalized channel correlation matrix. And determining the new value of the real part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the first iteration formula. And determining and obtaining the new value of the virtual part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the second iteration formula. And adding 1 to the value of the iteration frequency parameter. And the electric chip is used for determining the target inverse matrix of the channel correlation matrix according to the value of the real part iteration result and the value of the imaginary part iteration result obtained at the t time until the value of the iteration frequency parameter is equal to the preset iteration frequency t.

The channel correlation matrix and the first inverse matrix are complex matrices, and the first to-be-multiplied matrix comprises a first to-be-multiplied submatrix and a second to-be-multiplied submatrix. The electrical chip is used for determining a real part matrix and an imaginary part matrix of the channel correlation matrix. The electrical chip is configured to determine a real matrix of the channel correlation matrix as the first to-be-multiplied sub-matrix and determine an imaginary matrix of the first channel correlation matrix as the second to-be-multiplied sub-matrix. The electrical chip is configured to determine a real matrix of the first inverse matrix. The electric chip is used for determining the real part matrix of the first inverse matrix as a preset value of a first parameter matrix.

In one possible implementation, the optical chip includes a first sub-optical chip and a second sub-optical chip, the first sub-optical chip and the second sub-optical chip are connected with the electrical chip, the first product includes a first sub-product of the first to-be-multiplied sub-matrix and the first parameter matrix and a second sub-product of the second to-be-multiplied sub-matrix and the first parameter matrix, and the first conversion matrix includes a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix. The electrical chip is used for determining an imaginary matrix of the first inverse matrix as a preset value of a second matrix parameter. The electrical chip is further configured to perform the normalization processing on m column vectors of the second parameter matrix to obtain m second column vectors. Wherein, the absolute value of the value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1. The electrical chip is further configured to transmit each of the m second column vectors to the first sub-optical chip and the second sub-optical chip. The first sub-optical chip is further configured to multiply the first conversion sub-matrix with the second column vectors to obtain a multiplication result of the first conversion sub-matrix with the second column vectors, and transmit the multiplication result of the first conversion sub-matrix with the second column vectors to the electrical chip. The second sub-optical chip is further configured to multiply the second conversion sub-matrix with each second column vector to obtain a multiplication result of the second conversion sub-matrix with each second column vector, and transmit the multiplication result of the second conversion sub-matrix with each second column vector to the electrical chip. The electric chip is used for determining a third sub-product of the first sub-matrix to be multiplied and the second matrix parameters according to the multiplication result of the first conversion sub-matrix and each second column vector, and determining a fourth sub-product of the second sub-matrix to be multiplied and the second matrix parameters according to the multiplication result of the second conversion sub-matrix and each second column vector. The electric chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product and the fourth sub-product.

In one possible implementation, the electrical chip may be configured to determine a value of a predetermined third parameter matrix from the first and third sub-products. The electrical chip is further configured to determine a value of a fourth parameter matrix according to the second sub-product and the fourth sub-product. The electrical chip is further configured to determine a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

D_T＝2×T-R×K-T×J

In one possible implementation, the third parameter matrix satisfies the following relation:

J＝P×R-Q×T

The fourth parameter matrix satisfies the following relation:

K＝P×T+Q×R

In one possible implementation manner, the channel correlation matrix and the first inverse matrix are real matrices, the first to-be-multiplied matrix is the channel correlation matrix, and the value of the first parameter matrix is the first inverse matrix.

In one possible implementation manner, the electrical chip is configured to determine a value of an inversion iteration result according to the first parameter matrix, the first product and a preset third iteration formula. Wherein the third iterative formula comprises:

D＝R×(2I-A×R)

In one possible implementation, the electrical chip is further configured to: and decomposing any first column vector j in the m first column vectors into a first positive column vector j1 and a first negative column vector j2. The sum of the first positive column vector j1 and the first negative column vector j2 is equal to the first column vector j, the value of any vector element in the first positive column vector j1 is a positive number or 0, and the value of any vector element in the first negative column vector j2 is a negative value or 0. And determining a first opposite column vector j3 according to the first negative column vector j2, wherein the sum of the first negative column vector j2 and the first opposite column vector j3 is 0. The first positive column vector j1 and the first negative column vector j3 are transmitted to the photo chip.

In one possible implementation, the multiplication result of the first conversion matrix and the first column vector j includes the multiplication result of the first conversion matrix and the first positive column vector j1 and the multiplication result of the first conversion matrix and the first opposite column vector j 3. The optical chip is used for: and multiplying the first conversion matrix with the first positive column vector j1 to obtain a multiplication result of the first conversion matrix and the first positive column vector j 1. And multiplying the first conversion matrix with the first opposite column vector j3 to obtain a multiplication result of the first conversion matrix and the first opposite column vector j 3.

In one possible implementation, a difference between a result of multiplying a first conversion matrix by the first positive column vector j1 and a result of multiplying the first conversion matrix by the first negative column vector j3 may be used to determine a product of the first conversion matrix and the first column vector j.

In one possible implementation, the optical chip includes a first multiplier array and a second multiplier array, with each multiplier array including a plurality of multipliers. The electrical chip is further configured to decompose the first conversion matrix into a first positive conversion matrix and a first negative conversion matrix. The sum of the first positive conversion matrix and the first negative conversion matrix is the first matrix to be formed, the value of any matrix element in the first positive conversion matrix is positive number or 0, and the value of any matrix element in the first negative conversion matrix is negative number or 0. The electrical chip is further configured to determine a first inverse transformation matrix corresponding to the first negative transformation matrix. Wherein the sum of the first inverse transformation matrix and the first negative transformation matrix is 0. The electrical chip is further configured to transmit the first positive transition matrix to the first multiplier array such that the first multiplier array carries the first positive transition matrix. Wherein one of the multipliers of the first multiplier array carries a value of a matrix element of the first positive transition matrix. The electrical chip is further configured to transmit the first inverse transformation matrix to the second multiplier array such that the second multiplier array carries the first inverse transformation matrix. Wherein one of the multipliers of the second multiplier array carries a value of a matrix element of the first inverse transformation matrix.

In one possible implementation manner, the electrical chip further includes a first photoelectric receiving module and a second photoelectric receiving module, the first photoelectric receiving module is connected to the first optical multiplier array, the second photoelectric receiving module is connected to the second optical multiplier array, and the multiplication result of the first conversion matrix and the first column vector j includes the multiplication result of the first positive conversion matrix and the first column vector j and the multiplication result of the first inverse conversion matrix and the first column vector j. The optical chip is also for: and multiplying the first positive conversion matrix and the first column vector j by the first multiplier array and the first photoelectric receiving module to obtain a multiplication result of the first positive conversion matrix and the first column vector j. And multiplying the first inverse transformation matrix and the first column vector j by the second multiplier array and the second photoelectric receiving module to obtain a multiplication result of the first inverse transformation matrix and the first column vector j.

In one possible implementation, a difference between a result of multiplying the first positive conversion matrix by the first column vector j and a result of multiplying the first inverse conversion matrix by the first column vector j may be used to determine a product of the first conversion matrix and the first column vector j.

In one possible implementation, any one of the optical multipliers carries the value of any one of the matrix elements by the refractive index of the any one of the optical multipliers.

In one possible implementation, the optical multiplier includes one or more of the following: mach-Zehnder interferometers, directional couplers, and micro-rings.

Here, specific processes of the electrical chip and the optical chip to perform the functions in the above various possible implementations may be referred to the foregoing, and will not be described herein.

Referring to fig. 8, fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the application. The electronic device may be configured to implement the channel estimation method implemented by the channel estimation device 20 described above. The device comprises: a processor 81 and a memory 82.

Memory 82 includes, but is not limited to, RAM, ROM, EPROM or CD-ROM, which memory 82 is used to store related instructions and data. The memory 82 stores the following elements, executable modules or data structures, or a subset thereof, or an extended set thereof:

operation instructions: including various operational instructions for carrying out various operations.

Operating system: including various system programs for implementing various basic services and handling hardware-based tasks.

Only one memory is shown in fig. 8, but a plurality of memories may be provided as needed.

The processor 81 may be a controller, CPU, general purpose processor, DSP, ASIC, FPGA or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules and circuits described in connection with the disclosure of embodiments of the application. The processor 81 may also be a combination implementing computing functions, e.g. comprising one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

Alternatively, the various components in the electronic device may be coupled together by a bus system that may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus.

In practical applications, the memory 82 is configured to store program codes required for executing the channel estimation method implemented by the channel estimation device 20 in the above embodiment, and the processor 81 is configured to execute the program codes stored in the memory 82 to implement the channel estimation method implemented by the channel estimation device 20 in the above embodiment.

Referring to fig. 9, fig. 9 is a schematic diagram of a channel estimation apparatus according to another embodiment of the present application. As can be seen from fig. 9, the electrical chip 21 and the optical chip 22 may be in a three-dimensional package structure, that is, the electrical chip 21 and the optical chip 22 are not on the same plane, the optical chip 22 may be disposed above the electrical chip 21, or the electrical chip 21 may be disposed above the optical chip 22, and the electrical chip 21 and the optical chip 22 are connected by a metal wire. It will be appreciated that in practical applications, the optical chip 22 and the electrical chip 21 may be planar packages, and the three-dimensional packages shown in fig. 9 may be used as well, which is not particularly limited by the present application.

The embodiment of the application also provides electronic equipment, which comprises: a channel estimation device 20 as described above, and a discrete component coupled to the channel estimation device 20.

The embodiment of the present application also provides a computer-readable medium having stored thereon a computer program which, when executed by a computer, implements the methods or steps performed by the electrical chip 21 and the optical chip 22 in the above-described embodiments.

Embodiments of the present application also provide a computer program product which, when executed by a computer, implements the methods or steps performed by the electrical chip 21 and the optical chip 22 in the above embodiments.

The embodiment of the application also provides a chip system, which comprises an optical chip and an electric chip, and is used for supporting a device for installing the chip system to realize the channel estimation method provided by the first aspect. The chip system can be composed of an optical chip and an electric chip, and can also comprise other discrete devices.

The embodiment of the application also provides a photoelectric hybrid processor, which is used for being coupled with a memory, wherein the memory stores instructions, and when the photoelectric hybrid processor runs the instructions, the processor is caused to execute the channel estimation method provided in the embodiment.

Furthermore, various aspects or features of the application may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein encompasses a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media can include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, or magnetic strips, etc.), optical disks (e.g., compact disk, CD, digital versatile disk, DIGITAL VERSATILE DISC, DVD, etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory, EPROM), cards, sticks, key drives, etc. Additionally, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

In the embodiments provided in the present application, it should be understood that the disclosed system, apparatus, or method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disk (DIGITAL VERSATILE DISC, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing is merely exemplary of the invention and those skilled in the art may make various modifications or alterations to the invention as disclosed herein without departing from the spirit and scope of the invention. For example, the specific shape or structure of each component in the drawings of the embodiment of the invention can be adjusted according to the actual application scene.

Claims

1. A channel estimation method, wherein the method is applied to a channel estimation device, the channel estimation device comprises an electric chip and an optical chip, and the electric chip and the optical chip are connected;

The method comprises the following steps:

acquiring a channel incidence matrix of a target wireless channel through the electric chip, and determining a first inverse matrix of a diagonal element matrix of the channel incidence matrix;

Determining a first matrix to be multiplied according to the channel incidence matrix through the electric chip, and determining a value of a preset first parameter matrix according to the first inverse matrix;

Normalizing the first matrix to be multiplied by the electric chip to obtain a first conversion matrix, and transmitting the first conversion matrix to the optical chip, wherein the absolute value of the value of any matrix element in the first conversion matrix is smaller than or equal to 1;

The normalization processing is carried out on m column vectors of the first parameter matrix through the electric chip to obtain m first column vectors, wherein the absolute value of the value of any vector element of each first column vector in the m first column vectors is smaller than or equal to 1, and m is an integer larger than or equal to 2;

Transmitting any first column vector j of the m first column vectors to the optical chip through the electrical chip;

Multiplying the first conversion matrix and the first column vector j by the optical chip to obtain a multiplication result of the first conversion matrix and the first column vector j, and transmitting the multiplication result of the first conversion matrix and the first column vector j to the electrical chip;

determining, by the electrical chip, a first product of the first matrix to be multiplied and the first parameter matrix according to a multiplication result of the first conversion matrix and each first column vector of the m first column vectors;

determining a target inverse matrix corresponding to the channel correlation matrix according to the first product by the electrical chip;

And determining the transmitting vector of the target wireless channel by the electric chip according to the target inverse matrix and the receiving vector of the target wireless channel.

2. The method of claim 1, wherein the channel correlation matrix and the first inverse matrix are complex matrices, the first to-be-multiplied matrix comprising a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix;

the determining, by the electrical chip, a first to-be-multiplied matrix according to the channel correlation matrix includes:

Determining a real part matrix and an imaginary part matrix of the channel correlation matrix by the electric chip;

Partitioning a real matrix of the channel correlation matrix by the electrical chip to obtain the first submatrix to be multiplied;

And blocking the imaginary matrix of the channel correlation matrix by the electric chip to obtain the second submatrix to be multiplied.

3. The method of claim 2, wherein determining, by the electrical chip, a value of a preset first parametric matrix from the first inverse matrix comprises:

Determining, by the electrical chip, a real matrix of the first inverse matrix;

And determining a real part matrix of the first inverse matrix as a preset value of a first parameter matrix through the electric chip.

4. The method of claim 3, wherein the first conversion matrix comprises a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix, the first product comprising a first sub-product of the first to-be-multiplied sub-matrix and the first parametric matrix and a second sub-product of the second to-be-multiplied sub-matrix and the first parametric matrix;

The method further comprises the steps of:

Determining an imaginary matrix of the first inverse matrix through the electric chip, and determining the imaginary matrix of the first inverse matrix as a value of a preset second parameter matrix;

The normalization processing is carried out on m column vectors of the second parameter matrix through the electric chip so as to obtain m second column vectors, wherein the absolute value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1;

sequentially transmitting each second column vector of the m second column vectors to the optical chip through the electrical chip;

Multiplying the first conversion sub-matrix and the second conversion sub-matrix with each second column vector through the optical chip to obtain a multiplication result of the first conversion sub-matrix and each second column vector, and multiplying the second conversion sub-matrix with each second column vector, and transmitting the multiplication result of the first conversion sub-matrix and each second column vector to the electrical chip;

Determining a third sub-product of the first submatrix to be multiplied by the second parameter matrix according to the multiplication result of the first conversion submatrix and each second column vector by the electric chip, and determining a fourth sub-product of the second submatrix to be multiplied by the second parameter matrix according to the multiplication result of the second conversion submatrix and each second column vector;

the determining, by the electrical chip, a target inverse matrix corresponding to the channel correlation matrix according to the first product, including:

And determining a target inverse matrix corresponding to the channel correlation matrix by the electric chip according to the first sub-product, the second sub-product, the third sub-product and the fourth sub-product.

5. The method according to claim 4, wherein the method further comprises:

Determining, by the electrical chip, a portion of the real part matrix of the channel correlation matrix other than the first submatrix to be multiplied as a third submatrix to be multiplied;

determining a part except the second submatrix to be multiplied in an imaginary matrix of the channel correlation matrix as a fourth submatrix to be multiplied by the electrical chip;

The electrical chip is used for respectively carrying out the normalization processing on the third submatrix to be multiplied and the fourth submatrix to be multiplied to obtain a third conversion submatrix and a fourth conversion submatrix, wherein the absolute value of the value of any matrix element in the third conversion submatrix and the fourth conversion submatrix is smaller than or equal to 1;

Transmitting the third and fourth conversion sub-matrices to the optical chip via the electrical chip;

Transmitting each first column vector to the optical chip sequentially through the electrical chip;

Multiplying the third conversion sub-matrix and the fourth conversion sub-matrix with the first column vectors respectively through the optical chip to obtain a multiplication result of the third conversion sub-matrix and the first column vectors and a multiplication result of the fourth conversion sub-matrix and the first column vectors, and transmitting the multiplication result of the third conversion sub-matrix and the first column vectors and the multiplication result of the fourth conversion sub-matrix and the first column vectors to the electrical chip;

Determining a fifth sub-product of the third to-be-multiplied sub-matrix and the first parameter matrix according to the multiplication result of the third conversion sub-matrix and each first column vector through the electric chip, and determining a sixth sub-product of the fourth to-be-multiplied sub-matrix and the first parameter matrix according to the multiplication result of the fourth conversion sub-matrix and each first column vector;

The determining, by the electrical chip, a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, and the fourth sub-product, including:

And determining a target inverse matrix corresponding to the channel correlation matrix by the electric chip according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product and the sixth sub-product.

6. The method of claim 5, wherein the method further comprises:

Transmitting each second column vector to the optical chip sequentially through the electrical chip;

Multiplying the third conversion sub-matrix and the fourth conversion sub-matrix with each second column vector through the optical chip to obtain a multiplication result of the third conversion sub-matrix and each second column vector and a multiplication result of the fourth conversion sub-matrix and each second column vector, and transmitting the multiplication result of the third conversion sub-matrix and each second column vector and the multiplication result of the fourth conversion sub-matrix and each second column vector to the electrical chip;

determining a seventh sub-product of the third conversion sub-matrix and the second parameter matrix according to the multiplication result of the third conversion sub-matrix and the second column vectors through the electric chip, and determining an eighth sub-product of the fourth to-be-multiplied sub-matrix and the second parameter matrix according to the multiplication result of the fourth conversion sub-matrix and the second column vectors;

the determining, by the electrical chip, a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, and the sixth sub-product, includes:

And determining a target inverse matrix corresponding to the channel correlation matrix by the electric chip according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-product and the eighth sub-product.

7. The method of claim 6, wherein the determining, by the electrical chip, a target inverse matrix for the channel correlation matrix based on the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-product, and the eighth sub-product comprises:

Determining a first sub-value of a preset third parameter matrix according to the first sub-product and the fourth sub-product through the electric chip;

Determining a first sub-value of a preset fourth parameter matrix according to the second sub-product and the third sub-product through the electric chip;

determining, by the electrical chip, a second subvalue of the third parametric matrix from the fifth subproduct and the eighth subproduct;

determining, by the electrical chip, a second subvalue of the fourth parameter matrix from the sixth subproduct and the seventh subproduct;

determining the value of the third parameter matrix through the electrical chip according to the first sub-value and the second sub-value of the third parameter matrix;

Determining the value of the fourth parameter matrix through the electrical chip according to the first sub-value and the second sub-value of the fourth parameter matrix;

determining, by the electrical chip, a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix, and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

wherein D _R is the real part iteration result, R is the first parameter matrix, T is the second parameter matrix, J is the third parameter matrix, and K is the fourth parameter matrix;

D_T＝2×T-R×K-T×J

wherein D _T is the imaginary iteration result; the electric chip adds 1 to the value of the preset iteration frequency parameter;

before the value of the iteration number parameter is determined to be not equal to the preset iteration number t by the electrical chip, repeating the following operations:

Determining, by the electrical chip, a value of a real part iteration result obtained by last determination according to the first iteration formula as a new value of the first parameter matrix, and determining a value of an imaginary part iteration result obtained by last determination according to the second iteration formula as a new value of the second parameter matrix;

The new values of the third parameter matrix and the fourth parameter matrix are redetermined by the electrical chip according to the first parameter matrix with the new value, the second parameter matrix with the new value and the real part and the imaginary part of the normalized channel correlation matrix;

Determining a new value of the real part iteration result through the electrical chip according to a first parameter matrix of the new value, a second parameter matrix of the new value, a third parameter matrix of the new value, a fourth parameter matrix of the new value and the first iteration formula;

Determining a new value of the imaginary part iteration result by the electrical chip according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the second iteration formula;

Adding 1 to the value of the iteration frequency parameter through the electric chip;

and determining the target inverse matrix of the channel correlation matrix according to the value of the real part iteration result and the value of the imaginary part iteration result obtained at the t time until the value of the iteration number parameter is equal to the preset iteration number t through the electric chip.

8. The method of claim 1, wherein the channel correlation matrix and the first inverse matrix are complex matrices, the first to-be-multiplied matrix comprising a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix;

the determining, by the electrical chip, a first to-be-multiplied matrix from the channel correlation matrix includes:

Determining, by the electrical chip, a real matrix of the channel correlation matrix as the first submatrix to be multiplied and an imaginary matrix of the channel correlation matrix as the second submatrix to be multiplied;

the determining, by the electrical chip, a value of a preset first parameter matrix according to the first inverse matrix includes:

Determining, by the electrical chip, a real matrix of the first inverse matrix;

9. The method of claim 8, wherein the optical chip comprises a first sub-optical chip and a second sub-optical chip, the first sub-optical chip and the second sub-optical chip being coupled to the electrical chip, the first product comprising a first sub-product of the first to-be-multiplied sub-matrix and the first parametric matrix and a second sub-product of the second to-be-multiplied sub-matrix and the first parametric matrix, the first conversion matrix comprising a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix;

The method further comprises the steps of:

determining an imaginary matrix of the first inverse matrix as a preset value of a second parameter matrix through the electric chip;

Normalizing the m column vectors of the second parameter matrix through the electric chip to obtain m second column vectors, wherein the absolute value of any vector element of each second column vector in the m second column vectors is smaller than or equal to 1;

Transmitting each second column vector of the m second column vectors to the first sub-optical chip and the second sub-optical chip through the electrical chip;

Multiplying the first conversion submatrix and each second column vector by the first sub-optical chip to obtain a multiplication result of the first conversion submatrix and each second column vector, and transmitting the multiplication result of the first conversion submatrix and each second column vector to the electric chip;

multiplying the second conversion sub-matrix and each second column vector by the second sub-optical chip to obtain a multiplication result of the second conversion sub-matrix and each second column vector, and transmitting the multiplication result of the second conversion sub-matrix and each second column vector to the electrical chip;

10. The method of claim 9, wherein the determining, by the electrical chip, a target inverse matrix corresponding to the channel correlation matrix based on the first sub-product, the second sub-product, the third sub-product, and the fourth sub-product comprises:

determining a value of a preset third parameter matrix according to the first sub-product and the third sub-product through the electric chip;

determining a preset value of a fourth parameter matrix according to the second sub-product and the fourth sub-product through the electric chip;

D_R＝2×R-R×J+T×K

D_T＝2×T-R×K-T×J

11. The method according to claim 7 or 10, characterized in that the third parametric matrix satisfies the following relation:

J＝P×R-Q×T

The fourth parameter matrix satisfies the following relation:

K＝P×T+Q×R

12. The method of claim 1, wherein the channel correlation matrix and the first inverse matrix are real matrices, the first to-be-multiplied matrix is the channel correlation matrix, and the first parametric matrix is the first inverse matrix.

13. The method of claim 12, wherein the determining, by the electrical chip, a target inverse matrix corresponding to the channel correlation matrix based on the first product comprises:

Determining, by the electrical chip, a value of an inversion iteration result according to the first parameter matrix, the first product, and a preset third iteration formula, where the third iteration formula includes:

D＝R×(2I-A×R)

Wherein D is the inversion iteration result, R is the first parameter matrix, I is the identity matrix, A is the channel correlation matrix, and A multiplied by R is the first product;

adding 1 to the value of a preset iteration number parameter through the electric chip;

determining the value of the inversion iteration result obtained by the last time according to the third iteration formula as a new value of the first parameter matrix through the electric chip;

determining a new product of the first to-be-multiplied matrix and the newly valued first parameter matrix through the electric chip;

Determining a new value of the inversion iteration result through the electrical chip according to the first parameter matrix of the new value, the new product and the third iteration formula;

And determining a target inverse matrix of the channel correlation matrix according to the value of the inversion iteration result obtained at the t time until the value of the iteration number parameter is equal to the preset iteration number t through the electric chip.

14. The method according to any one of claims 1-13, wherein said transmitting any first column vector j of said m first column vectors to said optical chip by said electrical chip comprises:

Decomposing any first column vector j of the m first column vectors into a first positive column vector j1 and a first negative column vector j2 through the electric chip, wherein the sum of the first positive column vector j1 and the first negative column vector j2 is equal to the first column vector j, the value of any vector element in the first positive column vector j1 is a positive number or 0, and the value of any vector element in the first negative column vector j2 is a negative value or 0;

Determining, by the electrical chip, a first opposite column vector j3 according to the first negative column vector j2, wherein a sum of the first negative column vector j2 and the first opposite column vector j3 is 0;

The first positive column vector j1 and the first negative column vector j3 are transmitted to the photo chip by the photo chip.

15. The method of claim 14, wherein the multiplication result of the first transformation matrix and the first column vector j comprises the multiplication result of the first transformation matrix and the first positive column vector j1 and the multiplication result of the first transformation matrix and the first opposite column vector j 3;

the multiplying the first conversion matrix by the first column vector j by the optical chip to obtain a multiplication result of the first conversion matrix and the first column vector j includes:

Multiplying the first conversion matrix and the first positive column vector j1 by the optical chip to obtain a multiplication result of the first conversion matrix and the first positive column vector j 1;

and multiplying the first conversion matrix and the first opposite column vector j3 through the optical chip to obtain a multiplication result of the first conversion matrix and the first opposite column vector j 3.

16. The method of any one of claims 1-14, wherein the optical chip comprises a first optical multiplier array and a second optical multiplier array, any one of the optical multiplier arrays comprising a plurality of multipliers;

said transmitting said first conversion matrix to said optical chip by said electrical chip comprising:

Decomposing the first conversion matrix into a first positive conversion matrix and a first negative conversion matrix through the electric chip, wherein the sum of the first positive conversion matrix and the first negative conversion matrix is the first to-be-multiplied matrix, the value of any matrix element in the first positive conversion matrix is positive number or 0, and the value of any matrix element in the first negative conversion matrix is negative number or 0;

Determining a first inverse transformation matrix corresponding to the first negative transformation matrix through the electric chip, wherein the sum of the first inverse transformation matrix and the first negative transformation matrix is 0;

Transmitting the first positive conversion matrix to the first optical multiplier array through the electrical chip, so that the first optical multiplier array carries the first positive conversion matrix, wherein one multiplier of a plurality of multipliers of the first optical multiplier array carries a value of a matrix element in the first positive conversion matrix;

transmitting the first inverse transformation matrix to the second optical multiplier array through the electrical chip, so that the second optical multiplier array carries the first inverse transformation matrix, wherein one multiplier of a plurality of multipliers of the second optical multiplier array carries a value of a matrix element of the first inverse transformation matrix.

17. The method of claim 16, wherein the electrical chip further comprises a first optoelectronic receiving module and a second optoelectronic receiving module, the first optoelectronic receiving module coupled to the first optical multiplier array and the second optoelectronic receiving module coupled to the second optical multiplier array, the multiplication of the first conversion matrix with the first column vector j comprising the multiplication of the first positive conversion matrix with the first column vector j and the multiplication of the first inverse conversion matrix with the first column vector j;

the multiplying the first conversion matrix with the first column vector j by the optical chip to obtain a multiplication result of the first conversion matrix and the first column vector j includes:

Multiplying the first positive conversion matrix and the first column vector j through the optical chip by the first optical multiplier array and the first photoelectric receiving module to obtain a multiplication result of the first positive conversion matrix and the first column vector j;

and multiplying the first inverse conversion matrix and the first column vector j through the optical chip by the second optical multiplier array and the second photoelectric receiving module to obtain a multiplication result of the first inverse conversion matrix and the first column vector j.

18. A channel estimation device, characterized in that the channel estimation device comprises an electrical chip and an optical chip, the electrical chip and the optical chip are connected;

The electrical chip is used for acquiring a channel incidence matrix of a target wireless channel and determining a first inverse matrix of a diagonal element matrix of the channel incidence matrix;

the electric chip also determines a first matrix to be multiplied according to the channel incidence matrix, and determines the value of a preset first parameter matrix according to the first inverse matrix;

The electrical chip is further used for carrying out normalization processing on the first matrix to be multiplied to obtain a first conversion matrix, and transmitting the first conversion matrix to the optical chip, wherein the absolute value of the value of any matrix element in the first conversion matrix is smaller than or equal to 1;

the electrical chip is further configured to perform the normalization processing on m column vectors of the first parameter matrix to obtain m first column vectors, where an absolute value of a value of any vector element of each first column vector in the m first column vectors is less than or equal to 1, and m is an integer greater than or equal to 2;

The electrical chip is further configured to transmit any first column vector j of the m first column vectors to the optical chip;

The optical chip is used for multiplying the first conversion matrix with the first column vector j to obtain a multiplication result of the first conversion matrix and the first column vector j, and transmitting the multiplication result of the first conversion matrix and the first column vector j to the electrical chip;

the electric chip is further used for determining a first product of the first matrix to be multiplied and the first parameter matrix according to a multiplication result of the first conversion matrix and each first column vector in the m first column vectors;

The electrical chip is further used for determining a target inverse matrix corresponding to the channel correlation matrix according to the first product;

the electric chip is further used for determining the transmitting vector of the target wireless channel according to the target inverse matrix and the receiving vector of the target wireless channel.

19. The channel estimation device of claim 18 wherein the channel correlation matrix and the first inverse matrix are complex matrices, the first to-be-multiplied matrix comprising a first to-be-multiplied sub-matrix and a second to-be-multiplied sub-matrix;

The electric chip is used for determining a real part matrix and an imaginary part matrix of the channel correlation matrix;

the electrical chip is further configured to block a real matrix of the channel correlation matrix to obtain the first to-be-multiplied submatrix;

The electrical chip is further configured to block an imaginary matrix of the channel correlation matrix to obtain the second to-be-multiplied submatrix.

20. The channel estimation device of claim 19 wherein said electrical chip is further configured to determine a real matrix of said first inverse matrix;

The electric chip is also used for determining the real part matrix of the first inverse matrix as a preset value of a first parameter matrix.

21. The channel estimation device of claim 20 wherein the first conversion matrix comprises a first conversion sub-matrix corresponding to the first to-be-multiplied sub-matrix and a second conversion sub-matrix corresponding to the second to-be-multiplied sub-matrix, the first product comprising a first sub-product of the first to-be-multiplied sub-matrix and the first parametric matrix and a second sub-product of the second to-be-multiplied sub-matrix and the first parametric matrix;

The electric chip is further used for determining an imaginary matrix of the first inverse matrix and determining the imaginary matrix of the first inverse matrix as a value of a preset second parameter matrix;

The electrical chip is further configured to perform the normalization processing on m column vectors of the second parameter matrix to obtain m second column vectors, where an absolute value of a value of any vector element of each second column vector in the m second column vectors is less than or equal to 1;

the electric chip is further used for sequentially transmitting each second column vector in the m second column vectors to the optical chip;

The optical chip is further configured to multiply the first conversion sub-matrix and the second conversion sub-matrix with the second column vectors respectively to obtain a multiplication result of the first conversion sub-matrix and the second column vectors, and a multiplication result of the second conversion sub-matrix and the second column vectors, and transmit the multiplication result of the first conversion sub-matrix and the second column vectors to the electrical chip;

the electrical chip is further configured to determine a third sub-product of the first to-be-multiplied sub-matrix and the second parameter matrix according to a multiplication result of the first conversion sub-matrix and each second column vector, and determine a fourth sub-product of the second to-be-multiplied sub-matrix and the second parameter matrix according to a multiplication result of the second conversion sub-matrix and each second column vector;

the electric chip is further configured to determine a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, and the fourth sub-product.

22. The channel estimation device of claim 21 wherein the electrical chip is further configured to determine a portion of the real matrix of the channel correlation matrix other than the first to-be-multiplied sub-matrix as a third to-be-multiplied sub-matrix;

the electric chip is further used for determining the part except the second submatrix to be multiplied in the imaginary part matrix of the channel correlation matrix as a fourth submatrix to be multiplied;

The electrical chip is further configured to perform the normalization processing on the third to-be-multiplied submatrix and the fourth to-be-multiplied submatrix to obtain a third conversion submatrix and a fourth conversion submatrix, where an absolute value of a value of any matrix element in the third conversion submatrix and the fourth conversion submatrix is less than or equal to 1;

The electrical chip is further configured to transmit the third conversion sub-matrix and the fourth conversion sub-matrix to the optical chip;

the electric chip is also used for sequentially transmitting each first column vector to the optical chip;

The optical chip is further configured to multiply the third conversion sub-matrix and the fourth conversion sub-matrix with the first column vectors respectively to obtain a multiplication result of the third conversion sub-matrix and the first column vectors and a multiplication result of the fourth conversion sub-matrix and the first column vectors, and transmit the multiplication result of the third conversion sub-matrix and the first column vectors and the multiplication result of the fourth conversion sub-matrix and the first column vectors to the electrical chip;

the electrical chip is further configured to determine a fifth sub-product of the third to-be-multiplied sub-matrix and the first parameter matrix according to a multiplication result of the third conversion sub-matrix and the first column vectors, and determine a sixth sub-product of the fourth to-be-multiplied sub-matrix and the first parameter matrix according to a multiplication result of the fourth conversion sub-matrix and the first column vectors;

The electric chip is further configured to determine a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, and the sixth sub-product.

23. The channel estimation device of claim 22 wherein said electrical chip is further configured to sequentially transmit said second column vectors to said optical chip;

the optical chip is further configured to multiply the third conversion sub-matrix and the fourth conversion sub-matrix with the second column vectors respectively to obtain a multiplication result of the third conversion sub-matrix and the second column vectors and a multiplication result of the fourth conversion sub-matrix and the second column vectors, and transmit the multiplication result of the third conversion sub-matrix and the second column vectors and the multiplication result of the fourth conversion sub-matrix and the second column vectors to the electrical chip;

The electrical chip is further configured to determine a seventh sub-product of the third conversion sub-matrix and the second parameter matrix according to a multiplication result of the third conversion sub-matrix and the second column vectors, and determine an eighth sub-product of the fourth to-be-multiplied sub-matrix and the second parameter matrix according to a multiplication result of the fourth conversion sub-matrix and the second column vectors;

the electric chip is further configured to determine a target inverse matrix corresponding to the channel correlation matrix according to the first sub-product, the second sub-product, the third sub-product, the fourth sub-product, the fifth sub-product, the sixth sub-product, the seventh sub-product, and the eighth sub-product.

24. The channel estimation device of claim 23 wherein the electrical chip is further configured to determine a first sub-value of a predetermined third parameter matrix based on the first sub-product and the fourth sub-product;

the electrical chip is further used for determining a first sub-value of a preset fourth parameter matrix according to the second sub-product and the third sub-product;

The electrical chip is further configured to determine a second subvalue of the third parameter matrix according to the fifth subproduct and the eighth subproduct;

the electrical chip is further configured to determine a second subvalue of the fourth parameter matrix according to the sixth subproduct and the seventh subproduct;

the electrical chip is further used for determining the value of the third parameter matrix according to the first sub-value and the second sub-value of the third parameter matrix;

The electrical chip also determines the value of the fourth parameter matrix according to the first sub-value and the second sub-value of the fourth parameter matrix;

The electrical chip is further configured to determine a value of a real part iteration result according to the first parameter matrix, the second parameter matrix, the third parameter matrix, the fourth parameter matrix and a preset first iteration formula, where the first iteration formula includes:

D_R＝2×R-R×J+T×K

D_T＝2×T-R×K-T×J

before the electrical chip determines that the value of the iteration number parameter is not equal to the preset iteration number t, the electrical chip is further configured to repeatedly perform the following operations:

Determining the value of the real part iteration result obtained by the last time according to the first iteration formula as a new value of the first parameter matrix, and determining the value of the imaginary part iteration result obtained by the last time according to the second iteration formula as a new value of the second parameter matrix;

The new values of the third parameter matrix and the fourth parameter matrix are redetermined according to the new value first parameter matrix, the new value second parameter matrix and the real part and the imaginary part of the normalized channel correlation matrix;

determining a new value of the real part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the first iteration formula;

determining a new value of the imaginary part iteration result according to the first parameter matrix with the new value, the second parameter matrix with the new value, the third parameter matrix with the new value, the fourth parameter matrix with the new value and the second iteration formula;

adding 1 to the value of the iteration frequency parameter;

And the electric chip is used for determining the target inverse matrix of the channel correlation matrix according to the value of the real part iteration result and the value of the imaginary part iteration result obtained at the t time until the value of the iteration frequency parameter is equal to the preset iteration frequency t.

25. The channel estimation device of claim 18 wherein the channel correlation matrix and the first inverse matrix are real matrices, the first to-be-multiplied matrix is the channel correlation matrix, and the first parametric matrix takes on the first inverse matrix.

26. The channel estimation device of claim 25 wherein the electrical chip is configured to: determining a value of an inversion iteration result according to the first parameter matrix, the first product and a preset third iteration formula, wherein the third iteration formula comprises:

D＝R×(2I-A×R)

the electric chip is also used for adding 1 to the value of a preset iteration frequency parameter;

The electrical chip is further configured to repeatedly perform the following operations before determining that the value of the iteration number parameter is not equal to the preset iteration number t:

Determining the value of the inversion iteration result obtained by the last time according to the third iteration formula as a new value of the first parameter matrix;

determining a new product of the first to-be-multiplied matrix and the newly valued first parameter matrix;

Determining and obtaining a new value of the inversion iteration result according to the new value first parameter matrix, the new product and the third iteration formula;

adding 1 to the value of the iteration frequency parameter;

And the method is further specifically used for determining a target inverse matrix of the channel correlation matrix according to the value of the inversion iteration result obtained at the t time until the value of the iteration number parameter is equal to the preset iteration number t through the electrical chip.

27. The channel estimation device of any one of claims 18-26, wherein the electrical chip is configured to:

Decomposing any first column vector j of the m first column vectors into a first positive column vector j1 and a first negative column vector j2, wherein the sum of the first positive column vector j1 and the first negative column vector j2 is equal to the first column vector j, the value of any vector element in the first positive column vector j1 is a positive number or 0, and the value of any vector element in the first negative column vector j2 is a negative value or 0;

determining a first opposite column vector j3 according to the first negative column vector j2, wherein the sum of the first negative column vector j2 and the first opposite column vector j3 is 0;

The first positive column vector j1 and the first negative column vector j3 are transmitted to the photo chip.

28. The channel estimation device of claim 27 wherein the multiplication result of the first conversion matrix and the first column vector j comprises the multiplication result of the first conversion matrix and the first positive column vector j1 and the multiplication result of the first conversion matrix and the first opposite column vector j 3;

the optical chip is specifically used for:

Multiplying the first conversion matrix with the first positive column vector j1 to obtain a multiplication result of the first conversion matrix and the first positive column vector j 1;

and multiplying the first conversion matrix with the first opposite column vector j3 to obtain a multiplication result of the first conversion matrix and the first opposite column vector j3.

29. An electronic device, comprising:

the channel estimation device of any of claims 18-26, and a discrete component coupled to the channel estimation device.

30. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the method of any of the preceding claims 1-17.

31. An electronic device, comprising: a processor and a memory;

The memory is used for storing a computer program;

The processor configured to execute a computer program stored in the memory, to cause the electronic device to perform the method of any one of claims 1-17.