CN115411180A - Phase change memory - Google Patents

Abstract

Embodiments of the present disclosure relate to phase change memories. The memory cell is fabricated from: (a) Forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) Forming a mask over the stack covering only the memory cell locations; and (c) etching a portion of the stack not covered by the first mask. The forming of the mask covering only the memory cell locations includes defining a first mask extending in the row direction for each row of memory cell locations and then patterning the first mask in the column direction for each column of memory cell locations.

Description

Phase change memory

Cross Reference to Related Applications

The present application claims priority from french patent application No. 2105618, filed on 28/5/2021, the entire contents of which are incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic devices and, more particularly, to phase change memories and methods of manufacturing the same.

Background

Phase change materials are materials that can be switched between a crystalline phase and an amorphous phase under the action of heat. Since the resistance of amorphous material is significantly higher than the resistance of crystalline material, this phenomenon can be used to define two memory states, such as 0 and 1, distinguished by the resistance measured through the phase change material.

The memory cells are preferably arranged within the memory as an array comprising rows, e.g. associated with word lines, and columns, e.g. associated with bit lines.

Disclosure of Invention

One embodiment provides a method for fabricating a memory cell, comprising: a) Forming a stack comprising a first layer of phase change material and a second layer of conductive material; b) Forming a first mask over the stack covering only memory cell locations; and c) etching the portion of the stack not covered by the first mask.

According to one embodiment, step a) comprises forming at least a third layer of electrically insulating material between the second layer and the first mask.

According to one embodiment, step c) does not etch the first layer and the further layer of the further material simultaneously.

According to one embodiment, the method includes forming a resistive element in contact with the first layer.

According to one embodiment, step b) comprises: depositing a fourth layer of material of the first mask on the stack; forming a second mask extending in the first direction and covering the memory cell locations; etching a portion of the fourth layer not covered by the second mask; forming a third mask extending in a second direction and covering the memory cell locations; and etching a portion of the fourth layer not covered by the third mask.

According to one embodiment, the etching method for etching the fourth layer etches the material of the fourth layer at a rate of at least 20 times faster than the material of the layer located below the fourth layer.

According to one embodiment, the first mask is made of titanium nitride.

According to one embodiment, the first layer is made of an alloy of germanium, antimony and tellurium.

According to one embodiment, the method includes fabricating an array of memory cells, each cell fabricated by a method according to the above-described method.

According to one embodiment, a first mask is formed over the location of each memory cell, and wherein step c) is performed simultaneously for all cells.

According to one embodiment, each first mask is common to a row of cells in the array, and wherein each second mask is common to a column of cells in the array.

According to one embodiment, the method includes depositing at least one electrically insulating layer over the cells of the array.

According to one embodiment, the method includes depositing a conductive via through the insulating layer so as to reach the second layer.

According to one embodiment, the method includes forming a conductive strap extending over a second layer of cells in a row or column of the array.

Drawings

The foregoing features and advantages, as well as others, will be presented by way of illustration and not limitation in the following description of specific embodiments with reference to the accompanying drawings, in which:

FIGS. 1-8 illustrate steps, preferably sequential steps, of one embodiment of a method for fabricating a phase change memory;

FIG. 9 shows an alternative to the steps of FIG. 8; and

fig. 10 shows an alternative to the steps of fig. 8 and 9.

Detailed Description

Like features are denoted by like reference numerals throughout the various figures. In particular, structural and/or functional features that are common in the various embodiments may have the same reference numerals and may be provided with the same structural, dimensional and material properties.

For the sake of clarity, only the operations and elements useful for understanding the embodiments described herein have been illustrated and described in detail.

Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than conductors, and when two elements are referred to as being connected together, this means that the two elements may be connected or that they may be coupled via one or more other elements.

In the following disclosure, unless otherwise indicated, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or to relative positional qualifiers, such as the terms "upper", "lower", "higher", "lower", etc., or to orientation qualifiers, such as "horizontal", "vertical", etc., refer to the orientation shown in the figures.

Unless otherwise indicated, the expressions "about", "essentially" and "in" mean within 10%, preferably within 5%.

Fig. 1-8 illustrate steps, preferably consecutive steps, of one embodiment of a method for manufacturing a phase change memory.

FIG. 1 illustrates one step of an embodiment of a method for fabricating a phase change memory cell.

The manufacturing step includes forming conductive vias 10. This step includes fabricating a resistive element 12 disposed over the conductive via 10. The resistive element 12 is preferably L-shaped with a horizontal portion located over the through hole 10 and a vertical portion extending substantially perpendicular to the horizontal portion. The via 10 and the resistive element 12 are surrounded by an electrically insulating layer 14. The upper surface of the vertical portion of the resistive element 12 is flush with the upper surface of the layer 14. Layer 14 comprises a stack of a plurality of electrically insulating layers of, for example, different electrically insulating materials.

The layer 14 and the upper surface of the vertical part of the resistive element are covered by a stack comprising: a layer 16 made of a phase change material; a layer 18 made of an electrically conductive material; and a hard mask 20.

Layer 16 is a planar layer that covers the upper surface of the vertical portion of resistive element 12 and preferably completely covers layer 14. Thus, layer 16 is in contact with layer 14. Layer 16 is preferably made of a germanium-antimony-tellurium (GST) alloy. For example, layer 18 is titanium nitride.

Mask 20 is a layer that preferably extends through all layers 18. The mask 20 is made of a metal or metal alloy such as titanium nitride.

Mask 20 and layer 18 are separated by one or more layers (e.g., insulating layers) in the stack, such as forming an etch mask. In the example shown in fig. 1, mask 20 and layer 18 are separated by: a layer 22 made of an electrically insulating material such as silicon nitride; for example, a layer 24 made of an electrically insulating material such as amorphous carbon; and a layer 26 made of an antireflective material for lithography, such as an electrically insulating material comprising silicon oxide.

FIG. 2 illustrates another step in one embodiment of a method for fabricating a phase change memory cell.

During this step, a ribbon 28 is formed on the mask 20. For example, the strip 28 corresponds to a photolithographic mask.

The strip 28 covers the memory cell locations. For example, the stripes 28 extend in a first direction in the direction of the rows of the memory cell array. For example, the strip 28 covers a plurality of cell locations, such as all cells in a row (line) of the array (i.e., row). The strips 28 cover the location of only one memory cell in a direction orthogonal to the row direction, for example corresponding to the column direction of the array.

FIG. 3 illustrates another step in one embodiment of a method for fabricating a phase change memory cell.

In this step, the portions of mask 20 not covered by strip 28 are etched. The etch is preferably a selective etch of the material of mask 20 relative to the material of the layer below mask 20, such as the material of layer 26. Preferably, the etching process etches the layer material 20 at a rate 20 times faster than the material of the etch layer 26. Preferably, only mask 20 is etched in this step. Preferably, layers 18, 22, 24 and 26 are not etched during this step. Layer 16 is not etched during this step.

The tape 28 is then removed.

FIG. 4 illustrates another step in one embodiment of a method for fabricating a phase change memory cell.

In this step, the tape 30 is formed on the mask 20. For example, the ribbon 30 corresponds to a photolithographic mask.

The strip 30 covers the locations of the memory cells. The strips 30 extend in a second direction substantially orthogonal to the first direction, for example in the direction of the columns of the memory cell array. The band 30 overlaps the position of several cells, such as all cells in a column of the array, for example. The strip 30 covers the location of only one memory cell in a direction orthogonal to the column direction, for example corresponding to the row (row) direction of the array.

The strip 30 covers the mask portions 20 at the locations of the memory cells. Preferably, the strip 30 covers only the mask portions 20 at the locations of the memory cells. For example, the band 30 covers a portion of the layer 26.

FIG. 5 illustrates another step in one embodiment of a method for fabricating a phase change memory cell.

In this step, the portions of mask 20 not covered by ribbon 30 are etched. The etch is preferably a selective etch of the material of mask 20 relative to the material of the layer below mask 20, such as the material of layer 26. Preferably, only mask 20 is etched in this step. Preferably, layers 18, 22, 24, and 26 are not etched during this step. Layer 16 is not etched during this step.

The tape 30 is then removed.

The mask 20 obtained as a result of the step in fig. 5 is preferably a rectangular parallelepiped.

The steps in fig. 2 to 5 make it possible to form a mask 20 covering the memory cell locations. The mask 20 thus faces the memory cell locations, preferably only the memory cell locations.

In a variation, the steps in fig. 2-5 may be replaced by forming a mask that replaces masks 28 and 30 and covers only the memory cell locations and etching mask layer 20. The formation of mask 20 then includes only a single etch of mask layer 20.

FIG. 6 illustrates another step in one embodiment of a method for fabricating a phase change memory cell.

This step includes the etching of layers 26, 18 and 16 around mask 20, and the etching of layers separating layer 18 and mask 20, in this case layers 22, 24 and 26. This step may also include etching a portion of layer 14 around the memory cell.

The stacked layers (i.e., layers 16, 18, 22, 24, and 26) are planar layers that extend in a planar manner around the memory cells (e.g., throughout the memory cell array locations). Specifically, the layer 16 of phase change material extends continuously between individual memory cells of the array. Thus, during the stack etching step (i.e., the step in fig. 6), the material of the individual layers is not etched at the same time. In particular, the material of layer 16 is not etched at the same time as the material of the other layers in the stack.

At least some of the layers above layer 18 are also removed. In the example shown in fig. 6, layers 24, 26, and 20 are removed from the memory cell locations.

A method may be selected for forming a memory cell, comprising: performing a first etch on the stack including the phase change material layer 16 to separate the array rows from each other; depositing one or more electrically insulating layers, in particular between the rows of the array; and a second etch is performed on the stack including the phase change material layer 16 to separate the array columns from each other. The layer 16 will then be etched along with the electrically insulating material formed at the layer 16 between the rows. Etching the phase change material and another material (particularly an electrically insulating material) simultaneously can alter the phase change material and reduce the efficiency of the memory cell.

FIG. 7 illustrates another step in one embodiment of a method for fabricating a phase change memory.

This step includes a compliant (i.e., conformal) deposition of a passivation layer 31. Layer 31 is made of an electrically insulating material, such as silicon nitride, for example. Passivation layer 31 covers the walls of layers 14, 16, 18 and 22 exposed by the etch of step in fig. 6. A passivation layer 31 covers the upper surface of the memory cell, in this case the upper surface of layer 22.

This step also includes forming a layer 32, shown transparently by dashed lines. Layer 32 is made of an electrically insulating material such as silicon oxide.

Fig. 8 to 10 show three different embodiments of steps for manufacturing the upper contact or electrode of the cell.

FIG. 8 illustrates another step in one embodiment of a method for fabricating a phase change memory. In particular, fig. 8 illustrates the formation of conductive vias 34. This step is preferably performed after the step in fig. 7.

This step includes forming a cavity extending from the upper surface of layer 32 to layer 18 and filling the cavity with a conductive material such as a metal. The cavity is etched through layer 32, passivation layer 31 and layer 22 to reach conductive layer 18. The vias 34 of the cells in the same row or column of the array of cells are connected, for example, by a conductive strip (not shown) which is placed, for example, on the upper surface of the layer 32.

Fig. 9 shows an alternative to the steps of fig. 8. In other words, this step is performed after the step of fig. 7, rather than after the step of fig. 8. In particular, FIG. 9 illustrates the formation of conductive strips 36 connecting cells in the same row or column.

During this step, cavities are etched in layer 32 and in layers 31 and 22 of the cells connected by tape 36. The cavity thus extends from the upper surface of layer 32 to layer 18. Thus, the cavity extends through layers 22 and 31 in the memory cell. Between the memory cells, the cavities extend into the layer 31. The cavity is then filled with a conductive material such as a metal.

Fig. 10 shows an alternative to the steps in fig. 8 and 9. That is, after the step of fig. 7, this step is performed instead of the steps in fig. 8 or 9. In particular, FIG. 10 illustrates the formation of a conductive strap 38 connecting cells in the same row or column of the memory array.

In this step, layers 32, 31, 22 are etched in a planar fashion until the upper surface of layer 18 is exposed. A planar layer of conductive material, such as metal, is then formed on the structure obtained after etching. This layer thus covers the upper surface of layer 18 and the upper surfaces of layers 31 and 32 around the memory cell. The conductive layer is then etched so that a strip remains extending over the plurality of cells of layer 18 in the first direction. For example, in the second direction, strip 38 extends across the entire layer 18 and partially across the upper surface of layer 31.

Embodiments for fabricating a single memory cell are described. The method may be used to fabricate multiple cells, such as an array of memory cells, simultaneously. The method then includes forming a mask 20 covering each memory cell location and simultaneously etching the stack around the memory cell location, i.e., etching the portion of the stack not covered by the mask 20.

One advantage of the described embodiments is that the phase change material layer is not etched at the same time as the other material.

Another advantage of the described embodiments is that the described method comprises an etching step and a layer deposition step with respect to known methods.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of the embodiments may be combined, and that other variations will readily occur to those skilled in the art.

Finally, the actual implementation of the embodiments and variants described herein is within the abilities of one of ordinary skill in the art based on the functional description provided above.

Claims (22)

1. A method for fabricating a memory cell, comprising:

(a) Forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material;

(b) Forming a first mask over the stack, the first mask covering only locations of the memory cells; and

(c) Etching a portion of the stack not covered by the first mask.

2. The method of claim 1, wherein step a) comprises: a third layer of electrically insulating material formed at least between the second layer and the first mask.

3. The method of claim 1, wherein the etching in step c) does not simultaneously etch the phase change material of the first layer and the material of another layer in the stack.

4. The method of claim 1, further comprising: forming a resistive element in contact with the first layer.

5. The method of claim 1, wherein step b) comprises:

depositing a fourth layer made of the same material as the first mask on the stack;

forming a second mask extending in a first direction and covering a location of the memory cell;

etching a portion of the fourth layer not covered by the second mask;

forming a third mask extending in a second direction and covering a location of the memory cell; and

etching a portion of the fourth layer not covered by the third mask.

6. The method of claim 5, wherein etching portions of the fourth layer comprises: etching material of the fourth layer at a rate of at least twenty times as fast as etching material of a layer underlying the fourth layer.

7. The method of claim 1, wherein the first mask is made of titanium nitride.

8. The method of claim 1, wherein the first layer is made of a germanium, antimony, and tellurium alloy.

9. The method of claim 1, wherein the memory cell is one memory cell in an array of memory cells.

10. The method of claim 9, wherein a first mask is formed over the location of each memory cell in the array, and wherein step c) is performed simultaneously for all memory cells.

11. The method of claim 9, further comprising: depositing at least one electrically insulating layer over the memory cells of the array.

12. The method of claim 9, further comprising: depositing a conductive via through the electrically insulating layer to reach the second layer.

13. The method of claim 9, further comprising: forming a conductive strap extending over the second layer of memory cells in a row or column of the array.

14. A method for fabricating a memory array comprising a plurality of memory cells arranged in columns and rows, the method comprising:

(a) Forming a stack comprising a plurality of layers in the following order: a first layer made of a phase change material; a second layer made of an electrically conductive material; an electrically insulating layer; and a fourth layer made of a photolithographic material;

(b) Forming a first strip on the fourth layer, the first strip covering memory cell locations along each row;

(c) Lithographically patterning the fourth layer using the first tape to form a first mask covering memory cell locations along each row;

(d) Forming a second strip on the first mask, the second strip covering memory cell locations along each column;

(e) Lithographically patterning the first mask using the second tape to form a second mask that individually covers each memory cell location along the column and the row;

(f) Etching portions of the stack not covered by the second mask to define individual memory cells.

15. The method of claim 14, wherein the electrically insulating layer comprises: a first insulating layer made of a first electrically insulating material; and a second insulating layer made of a second electrically insulating material.

16. The method of claim 15, wherein the first electrically insulating material is silicon nitride and the second electrically insulating material is amorphous carbon.

17. The method of claim 14, wherein the photolithographic material is an antireflective material for photolithography.

18. The method of claim 17, wherein the antireflective material used for photolithography is titanium nitride.

19. The method of claim 14, wherein the first layer is made of a germanium, antimony, and tellurium alloy and the second layer is made of titanium nitride.

20. The method of claim 14, further comprising: at least one electrically insulating layer is deposited over the individual memory cells.

21. The method of claim 20, further comprising: depositing a conductive via through the electrically insulating layer to reach the second layer of each individual memory cell.

22. The method of claim 20, further comprising: forming a conductive strap extending into contact with a portion of the second layer in the individual memory cell in a row or column of the array.

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