CN115408980B - Regularization clock grid planning method based on dynamic planning - Google Patents

Regularization clock grid planning method based on dynamic planning Download PDF

Info

Publication number
CN115408980B
CN115408980B CN202211359161.0A CN202211359161A CN115408980B CN 115408980 B CN115408980 B CN 115408980B CN 202211359161 A CN202211359161 A CN 202211359161A CN 115408980 B CN115408980 B CN 115408980B
Authority
CN
China
Prior art keywords
clock
grid
window
clock grid
layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202211359161.0A
Other languages
Chinese (zh)
Other versions
CN115408980A (en
Inventor
刘檬
王芸飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing University of Technology
Original Assignee
Beijing University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing University of Technology filed Critical Beijing University of Technology
Priority to CN202211359161.0A priority Critical patent/CN115408980B/en
Publication of CN115408980A publication Critical patent/CN115408980A/en
Application granted granted Critical
Publication of CN115408980B publication Critical patent/CN115408980B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention discloses a regularized clock grid planning method based on dynamic planning. The method comprises the following steps: 1) Extracting physical information of the layout to obtain a clock grid wiring topology initial state diagram; 2) Defining a window merging rule, and collecting clock grid evaluation parameter information in a layout; 3) Merging the clock grids concurrently based on a dynamic programming algorithm to generate a clock grid topological state diagram and an evaluation calculation value; 4) Screening out a clock grid topological state diagram of an optimal evaluation calculation value, and performing clock grid disconnection aiming at a region without a clock anchor point; 5) Parasitic parameters are extracted to carry out Monte Carlo analysis, experimental results are evaluated, weights and strategies are corrected, the consistency of the results is verified, and a clock grid topological graph is output. The scheme can realize optimization of a design target, guarantee regularization of clock grid topology, perform off-line decision aiming at the design parameter target of the integrated circuit layout and improve the quality of clock network results.

Description

Regularization clock grid planning method based on dynamic planning
Technical Field
The invention relates to the technical field of integrated circuit layouts, in particular to a regularized clock grid planning method based on dynamic planning.
Background
The multiple process corners, clock domains, and low power consumption requirements make the design of Clock Distribution Networks (CDNs) a challenging problem. In addition to affecting the frequency of the SoC, the power consumption caused by the CDN can account for over 40% of the total power consumption of the chip. While key outcome parameters of the clock distribution network include performance and power consumption. Performance is expressed in terms of clock skew and clock transitions, requiring precise control by the designer. Clock skew refers to the delay difference between clock sinks from the same clock source. In addition, a slew constraint representing the slew rate of the clock signal from 0 to 1 may also be considered. Since the design frequency and voltage are usually not changed, the power consumption can be statistically calculated from the capacitance values. Considerable work has been done to calculate only the wire length of the clock distribution network without considering the wire width parameter. There have been H-tree based global and local clock tree structures that can precisely control delay, yet have not been seen in mesh design. In addition, the power consumption overhead of the grid needs to be further controlled.
The clock grid track details are shown in figure 1. Tvm denotes a wiring trace in the mth vertical space. Thn denotes a wiring trace in the nth horizontal space. Each grid window is formed by the intersection of the traces in different directions. In other words, each grid window affects the state of the associated trace.
The grid type clock network is an ideal topological structure resisting the process fluctuation constraint condition, and has obvious advantages in large-scale integrated circuit layouts with higher main frequency requirements and more advanced process nodes. The grid type clock structure can be used as the middle layer of the hierarchical clock network, and the time sequence result quality of the whole clock network is improved.
At present, the key parameters of clock grid planning need to be manually decided, the decision process depends on iterative simulation, and whether the design requirements are met needs to be judged according to EDA tool result feedback and engineering experience. Aiming at the clock grid planning decision problem, at the present stage, a clock grid design based on a clustering algorithm and a clock grid design based on a linear programming algorithm exist, and a method with higher automation degree is not provided.
Aiming at the clock grid planning problem, the balanced design of a uniform type and a non-uniform type is difficult to solve no matter the regular topology design based on simulation experience values or the solution based on 0-1 integer linear programming.
The clock grid planning process relates to a clock trunk line planning problem, and the clock grid planning method based on dynamic planning can automatically solve a manual planning decision process, effectively shorten a key parameter decision process, reduce manual intervention workload and improve the clock network design efficiency.
Disclosure of Invention
Based on the above background, the present invention provides a new method, which can greatly improve the delay-limited clock grid synthesis efficiency. Based on a dynamic planning algorithm, the grid topology design of a complex layout scene can be automatically completed after the layout stage.
In order to realize the purpose, the invention provides the following technical scheme:
the regularized clock grid planning method based on dynamic planning comprises the following steps:
s1, extracting physical information of the layout to obtain a layoutHeight and width information of the graph and clock grid wiring track information, and establishing an initial state graph of a clock grid wiring topological model; defining a regularization window size with a minimum routing trajectory, and then generating based on the regularization window
Figure 136710DEST_PATH_IMAGE001
An initial window of specifications;
s2, defining a window merging rule, and collecting clock grid evaluation parameter information in the layout, wherein the information comprises a maximum clock deviation value and time delay;
s3, performing concurrent merging on the clock grids based on a dynamic programming algorithm to generate a clock grid topological state diagram and an evaluation calculation value, wherein the specific formula of the evaluation calculation value is as follows:
Figure 274299DEST_PATH_IMAGE002
Figure 297750DEST_PATH_IMAGE003
Figure 604229DEST_PATH_IMAGE004
wherein,
Figure 812356DEST_PATH_IMAGE005
a variance representing the clock delay;
Figure 453553DEST_PATH_IMAGE006
a line area value representing a current window;
Figure 529962DEST_PATH_IMAGE007
a short-circuit wire length value representing the current window, which is the sum of Manhattan distances from all grid wires to a sink in the current window area;
Figure 674636DEST_PATH_IMAGE008
representing a variable factor weight;
Figure 319244DEST_PATH_IMAGE009
representing the value range of the strategy counting value of the clock grid window;
Figure 932890DEST_PATH_IMAGE010
representing a delay value for each grid window;
Figure 360460DEST_PATH_IMAGE011
to represent
Figure 77749DEST_PATH_IMAGE010
Average value of (d);
Figure 627679DEST_PATH_IMAGE012
is shown in
Figure 243469DEST_PATH_IMAGE013
And with
Figure 163145DEST_PATH_IMAGE014
The numerical ranges specified therein;
recording the current score value, reserving the merging strategy with the highest score of the current window, and iteratively calculating other windows until the clock deviation value overflows;
s4, screening out a clock grid topological state diagram of the optimal evaluation calculation value, performing clock grid disconnection aiming at a region without a clock anchor point, and finishing direct connection topology without the clock anchor point and clock grid wiring;
and S5, extracting parasitic parameters to carry out Monte Carlo rapid analysis, evaluating an experimental result, correcting weight and strategy, verifying result consistency and outputting a clock grid topological state diagram.
Preferably, the specific process of the step S2 is as follows: the initial concurrent node number is consistent with the initial grid number of the clock grid wiring topological model diagram; then traversing all window combinations to obtain the number and arrangement of the sub-graph combinations obtained under different windows, wherein the number of the sub-graph combinations is as follows:
Figure 547990DEST_PATH_IMAGE015
wherein,
Figure 3242DEST_PATH_IMAGE016
is an initial window specification;
Figure 558858DEST_PATH_IMAGE017
a sub-graph combination is represented that,
Figure 62651DEST_PATH_IMAGE018
；
and then carrying out Monte Carlo rapid analysis on the subgraph, and estimating a maximum clock deviation value and time delay by using an Elmore-based time delay model.
Preferably, during the merging of the grids in the step S3, the physical information input includes layout size information
Figure 895478DEST_PATH_IMAGE019
Wiring track
Figure 210047DEST_PATH_IMAGE020
The clock-free anchor point area S and the window time delay lookup table tablemsesh.
By adopting the clock grid planning method, the inconvenience that manual decision is needed in clock grid planning is avoided, the efficiency and the reliability of clock grid planning are improved, and the clock grid planning process is optimized.
Drawings
FIG. 1 is a detailed diagram of a clock grid track in the prior art;
FIG. 2 illustrates the technical route and key technology of the present invention;
FIG. 3 is a diagram of an analytic method grid window model;
fig. 4 is a schematic diagram of an initial grid planning state s 11;
fig. 5 is a schematic diagram of a grid planning state s 12;
fig. 6 is a schematic diagram of a grid planning state s 21;
FIG. 7 is a clock grid area removal schematic.
Detailed Description
The technical scheme of the invention is further explained by combining the drawings and the embodiment.
The regularized clock grid planning method based on dynamic planning shown in fig. 2 specifically includes the following processes.
S1, extracting physical information of the layout after layout to obtain height and width information of the layout and clock grid wiring track information, and establishing a clock grid wiring topology initial state diagram.
Performing window topology predefining, and defining a regularized window size by using a minimum wiring track, namely the regularized window size is
Figure 738111DEST_PATH_IMAGE021
. Then based on the regularized window to generate
Figure 560443DEST_PATH_IMAGE022
The initial window of the specification can be expanded to any specification, and a clock grid wiring topology initial state diagram is obtained. Each row of the initial window comprisesxEach column of the regularized windows includesyThe combination of all the windows is shown in table 1.
TABLE 1 Window combination List
Figure 982197DEST_PATH_IMAGE023
And S2, defining a window merging rule, and collecting clock grid evaluation parameter information in the layout, wherein the information comprises a maximum clock deviation value, time delay and the like.
And S3, performing concurrent merging on the clock grid based on a dynamic programming algorithm to generate a clock grid topological state diagram and an evaluation calculation value, wherein the specific formula of the evaluation calculation value is as follows:
Figure 716935DEST_PATH_IMAGE002
Figure 217448DEST_PATH_IMAGE003
Figure 594203DEST_PATH_IMAGE004
wherein,
Figure 870464DEST_PATH_IMAGE005
a variance representing the clock delay;
Figure 290949DEST_PATH_IMAGE006
a line area value representing a current window;
Figure 793606DEST_PATH_IMAGE007
a short wire length value representing the current window, which is the sum of the Manhattan distances from all grid wires to the sink in the current window area;
Figure 928046DEST_PATH_IMAGE008
representing a variable factor weight;
Figure 730917DEST_PATH_IMAGE009
representing the value range of the strategy counting value of the clock grid window;
Figure 56725DEST_PATH_IMAGE010
representing a delay value for each grid window;
Figure 577837DEST_PATH_IMAGE011
to represent
Figure 312706DEST_PATH_IMAGE010
Average value of (a);
Figure 891454DEST_PATH_IMAGE012
is shown in
Figure 873317DEST_PATH_IMAGE013
And with
Figure 429194DEST_PATH_IMAGE014
The numerical ranges specified in (a) and (b).
And recording the current score value, keeping the combination strategy with the highest score of the current window, and iteratively calculating other windows until the clock deviation value overflows.
And S4, screening out a clock grid topological state diagram with an optimal evaluation calculation value, performing clock grid disconnection aiming at a region without a clock anchor point (sink point), and finishing direct connection topology without the clock anchor point and clock grid wiring.
And S5, performing fast Monte Carlo analysis on the relevant window to determine whether necessary constraint conditions are met. In the clock mesh routing stage, detailed routing is performed according to the clock mesh topology. After the sink direct connection topology and the clock routing are completed, accurate monte carlo simulation can be performed to evaluate the experimental results, correct the weights and strategies, ensure the consistency of the results under specific process conditions, and output a clock grid topological graph.
Specifically, the S2 step process is as follows: counting initial concurrent nodesnInitial mesh number of topological model graph for wiring with clock meshNAnd (5) the consistency is achieved. Traversing all window combinations to obtain the number and arrangement of sub-graph combinations obtained under different windows, wherein the number of the sub-graph combinations is as follows:
Figure 623546DEST_PATH_IMAGE015
wherein,
Figure 650277DEST_PATH_IMAGE016
is an initial window specification;
Figure 68620DEST_PATH_IMAGE017
a sub-map combination is represented that,
Figure 846214DEST_PATH_IMAGE018
。
and then carrying out Monte Carlo rapid analysis on the subgraph, and estimating the maximum clock deviation value and the time delay by using an Elmore-based time delay model.
Specifically, in step S3, the track information of the entire layout is equivalent to the initial state of the grid as shown in fig. 4,
Figure 844257DEST_PATH_IMAGE024
indicating the grid row and column positions to be merged; in FIG. 5
Figure 69702DEST_PATH_IMAGE025
A state of merging in the horizontal direction, as shown in FIG. 6
Figure 908214DEST_PATH_IMAGE026
In another state of vertical merge, the dashed lines represent potential mesh lines that need to be deleted. During mesh merging, physical information input includes layout size information
Figure 360055DEST_PATH_IMAGE027
Wiring track
Figure 709259DEST_PATH_IMAGE028
The clock-free anchor point area S and the window time delay lookup table tablemsesh.
Specifically, the clock grid at step S4 is disconnected, as shown in fig. 7, and the dashed lines indicate the wires to be deleted. Insignificant mesh segments should be removed to minimize mesh line length without significantly affecting the variation tolerances.
In conclusion, the method avoids manual decision in the clock grid planning process, improves the efficiency and reliability of clock grid planning, and optimizes the clock grid planning process.
The above is a specific embodiment of the present invention, but the scope of the present invention should not be limited thereto. Any changes or substitutions which can be easily made by those skilled in the art within the technical scope of the present invention disclosed herein shall be covered by the protection scope of the present invention, and therefore the protection scope of the present invention shall be subject to the protection scope defined by the appended claims.

Claims (3)

1. The regularization clock grid planning method based on dynamic planning is characterized by comprising the following steps:
s1, extracting physical information of the layout after layout to obtain height and width information of the layout and clock grid wiring track information, and establishing an initial state diagram of a clock grid wiring topological model; defining a regularized window size with a minimum routing trajectory and then generating based on the regularized window
Figure 436622DEST_PATH_IMAGE001
An initial window of specifications;
s2, defining a window merging rule, and collecting clock grid evaluation parameter information in the layout, wherein the information comprises a maximum clock deviation value and time delay;
s3, merging the clock grids concurrently based on a dynamic programming algorithm to generate a clock grid topological state diagram and an evaluation calculation value, wherein the specific formula of the evaluation calculation value is as follows:
Figure 419622DEST_PATH_IMAGE002
wherein,
Figure 549252DEST_PATH_IMAGE003
a variance representing the clock delay;
Figure 832466DEST_PATH_IMAGE004
a line area value representing a current window;
Figure 389349DEST_PATH_IMAGE005
a short wire length value representing the current window, which is the sum of the Manhattan distances from all grid wires to the sink in the current window area;
Figure 125224DEST_PATH_IMAGE006
representing a variable factor weight;
Figure 792965DEST_PATH_IMAGE007
representing the value range of the strategy counting value of the clock grid window;
Figure DEST_PATH_IMAGE008
representing a delay value for each grid window;
Figure 399527DEST_PATH_IMAGE009
to represent
Figure DEST_PATH_IMAGE010
Average value of (d);
Figure 596153DEST_PATH_IMAGE011
is shown in
Figure DEST_PATH_IMAGE012
The numerical ranges specified below are,
Figure 288166DEST_PATH_IMAGE013
the number of layout longitudinal wiring tracks is represented,
Figure DEST_PATH_IMAGE014
representing the number of transverse wiring tracks of the layout;
recording the current score value, reserving the merging strategy with the highest score of the current window, and iteratively calculating other windows until the clock deviation value overflows;
s4, screening out a clock grid topological state diagram with an optimal evaluation calculation value, performing clock grid disconnection aiming at a region without a clock anchor point, and completing direct connection topology without the clock anchor point and clock grid wiring;
and S5, extracting parasitic parameters to carry out Monte Carlo rapid analysis, evaluating an experimental result, correcting weight and strategy, verifying result consistency and outputting a clock grid topological state diagram.
2. The method for planning a regulated clock grid according to claim 1, wherein the specific process of the step S2 is as follows: the initial concurrent node number is consistent with the initial grid number of the clock grid wiring topological model graph; traversing all window combinations to obtain the number and arrangement of sub-graph combinations obtained under different windows, wherein the number of the sub-graph combinations is as follows:
Figure 959931DEST_PATH_IMAGE015
wherein,
Figure DEST_PATH_IMAGE016
is an initial window specification;
Figure 686579DEST_PATH_IMAGE017
a sub-graph combination is represented that,
Figure DEST_PATH_IMAGE018
，
Figure 54106DEST_PATH_IMAGE019
；
and then carrying out Monte Carlo rapid analysis on the subgraph, and estimating the maximum clock deviation value and the time delay by using an Elmore-based time delay model.
3. The method of claim 1, wherein during the merging of the grids in step S3, the physical information input includes layout size information
Figure DEST_PATH_IMAGE020
Wiring track
Figure 498994DEST_PATH_IMAGE021
The clock-free anchor point area S and the window time delay lookup table tablemsesh.
CN202211359161.0A 2022-11-02 2022-11-02 Regularization clock grid planning method based on dynamic planning Active CN115408980B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211359161.0A CN115408980B (en) 2022-11-02 2022-11-02 Regularization clock grid planning method based on dynamic planning

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211359161.0A CN115408980B (en) 2022-11-02 2022-11-02 Regularization clock grid planning method based on dynamic planning

Publications (2)

Publication Number Publication Date
CN115408980A CN115408980A (en) 2022-11-29
CN115408980B true CN115408980B (en) 2023-01-24

Family

ID=84169405

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211359161.0A Active CN115408980B (en) 2022-11-02 2022-11-02 Regularization clock grid planning method based on dynamic planning

Country Status (1)

Country Link
CN (1) CN115408980B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101192608A (en) * 2006-12-01 2008-06-04 松下电器产业株式会社 Semiconductor integrated circuit and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6668365B2 (en) * 2001-12-18 2003-12-23 Cadence Design Systems, Inc. Quadratic programming method for eliminating cell overlap and routing congestion in an IC layout
US7802215B2 (en) * 2006-06-06 2010-09-21 Fujitsu Limited System and method for providing an improved sliding window scheme for clock mesh analysis
US9003344B2 (en) * 2012-06-20 2015-04-07 Synopsys, Inc. Generating pattern-based estimated RC data with analysis of route information

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101192608A (en) * 2006-12-01 2008-06-04 松下电器产业株式会社 Semiconductor integrated circuit and manufacturing method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
动态时钟拓扑引导下的布局算法;刘大为 等;《计算机辅助设计与图形学学报》;20130531;第25卷(第5期);全文 *
基于神经网络的时延驱动版图规划算法;胡卫明 等;《电子学报》;20000531;第28卷(第5期);全文 *

Also Published As

Publication number Publication date
CN115408980A (en) 2022-11-29

Similar Documents

Publication Publication Date Title
Viswanathan et al. FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control
CN100423012C (en) Techniqes for making sure of buffer insertion
CN101206686B (en) Latch placement for high performance and low power circuits
US6480991B1 (en) Timing-driven global placement based on geometry-aware timing budgets
US11093681B2 (en) Method and system for generating layout design of integrated circuit
JP5609364B2 (en) Integrated circuit design apparatus, integrated circuit design method, and integrated circuit design program
Liu et al. PSO-based power-driven X-routing algorithm in semiconductor design for predictive intelligence of IoT applications
Li et al. Automatic layout design of plastic injection mould cooling system
US9785740B2 (en) Computer implemented system and method for modifying a layout of standard cells defining a circuit component
Guerra et al. Artificial neural networks as an alternative for automatic analog IC placement
CN109684731A (en) A kind of efficient detailed routing driving track allocation algorithm
CN112560389B (en) Detailed wiring method based on track distribution
CN112100971A (en) Method for constructing hierarchical clock tree for integrated circuit
CN114386352A (en) Time sequence driving layout method and device, equipment and storage medium
CN116362194A (en) Wiring resource pre-allocation method, device, computing equipment and storage medium
Ahmadi et al. Analog layout placement for FinFET technology using reinforcement learning
CN115526140A (en) Global wiring method considering advanced process constraint and unit movement
US20070130094A1 (en) Apparatus for rapid model calculation for pattern-dependent variations in a routing system
CN115408980B (en) Regularization clock grid planning method based on dynamic planning
US11694016B2 (en) Fast topology bus router for interconnect planning
Korte et al. BonnTools: Mathematical innovation for layout and timing closure of systems on a chip
US8863066B1 (en) Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints
TWI623844B (en) Floorplanning approach for mixed-size modules
CN113673195B (en) Circuit gate size optimization method based on network topology sequence
US10289784B1 (en) Determination of clock path delays and implementation of a circuit design

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant