CN115408138A

CN115408138A - Memory page processing method and related equipment thereof

Info

Publication number: CN115408138A
Application number: CN202110577591.9A
Authority: CN
Inventors: 郭帆; 樊成阳; 王克锋
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2022-11-29
Also published as: WO2022247821A1

Abstract

The application provides a memory page processing method and related equipment thereof, which can reduce the cost of a CPU and improve the duplicate removal speed. The method comprises the following steps: if the target memory page during the ith scanning is different from the target memory page during the (i-1) th scanning, increasing the value of a counter corresponding to the target memory page during the ith scanning by a first value; if the target memory page during the ith scanning is determined to be the same as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is determined to be different from the target memory page during the i-2 th scanning, detecting the value of a counter corresponding to the target memory page during the ith scanning; if the value of the counter corresponding to the target memory page in the ith scanning is larger than the first value, merging the target memory page in the ith scanning and the repeated page in the ith scanning; the memory pages with different contents correspond to different counters, and the memory pages with the same contents correspond to the same counter.

Description

Memory page processing method and related equipment thereof

Technical Field

The present application relates to the field of computer technologies, and in particular, to a memory page processing method and a related device.

Background

The memory deduplication technology is that a Central Processing Unit (CPU) of a computer, when determining that contents of multiple physical memory pages pointed to by multiple virtual memory pages are the same, may point the multiple virtual memory pages to the same physical memory page, that is, merge the multiple physical memory pages with the same contents, thereby releasing redundant physical memory pages and achieving the purpose of memory deduplication.

In the related art, the CPU can effectively increase the available memory by circularly executing the memory deduplication operation. Specifically, when performing the current deduplication on a plurality of memory pages (i.e., the aforementioned physical memory pages), the CPU may scan a certain memory page to obtain the content of the memory page, generate a value based on the content of the memory page, compare the value with each value in the red-black tree (generated based on the content of the scanned remaining memory pages), determine that a memory page having the same content as the memory page (i.e., a duplicate page of the memory page) exists if there are other values that are the same as the value, merge the memory pages, and store the value into the red-black tree if there are no memory pages. After that, the operations may also be performed on the remaining memory pages that are not scanned until the current deduplication of all the memory pages is completed, and then the next deduplication of all the memory pages is performed.

During each deduplication, the CPU compares each memory page with the remaining memory pages to obtain duplicate pages for each memory page. If a certain memory page does not have a duplicate page, the duplicate removal operation of the CPU to the memory page is invalid. This is quite common in each deduplication, and too many invalid deduplication operations result in too much CPU overhead and reduce deduplication speed.

Disclosure of Invention

The embodiment of the application provides a memory page processing method and related equipment thereof, which can avoid a large amount of invalid deduplication operations so as to reduce the cost of a CPU (Central processing Unit) and improve the deduplication speed.

A first aspect of an embodiment of the present application provides a memory page processing method, where the method includes:

when the CPU performs the i-th deduplication on the target memory page, the CPU may first perform the i-th scanning on the target memory page. Then, the CPU may determine whether the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and determine whether the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning.

If the contents of the target memory page during the ith scanning are different from the contents of the target memory page during the i-1 th scanning, and the CPU can determine that the target memory page has just changed, the CPU increases the value of the counter corresponding to the target memory page during the ith scanning by a first value, and ends the processing of the target memory page during the ith scanning. The memory pages with different contents correspond to different counters, and the memory pages with the same contents correspond to the same counter. For example, if the contents of the memory page 1 at the time of the 3 rd scan and the memory page 1 at the time of the 2 nd scan are the same, the memory page 1 at the time of the 3 rd scan and the memory page 1 at the time of the 2 nd scan correspond to the same counter. For another example, if the contents of the memory page 1 at the 3 rd scanning and the memory page 2 at the 3 rd scanning are the same, the memory page 1 at the 3 rd scanning and the memory page 2 at the 3 rd scanning correspond to the same counter. For example, if the contents of the memory page 1 at the time of the 3 rd scan and the memory page 2 at the time of the 2 nd scan are the same, the memory page 1 at the time of the 3 rd scan and the memory page 2 at the time of the 2 nd scan correspond to the same counter. For example, if the contents of the memory page 1 at the 3 rd scanning and the memory page 1 at the 2 nd scanning are different, the memory page 1 at the 3 rd scanning and the memory page 1 at the 2 nd scanning correspond to two different counters. For another example, if the contents of the memory page 1 at the 3 rd scanning and the memory page 2 at the 3 rd scanning are different, the memory page 1 at the 3 rd scanning and the memory page 2 at the 3 rd scanning correspond to two different counters. For another example, if the contents of the memory page 1 at the 3 rd scanning and the memory page 2 at the 2 nd scanning are different, the memory page 1 at the 3 rd scanning and the memory page 2 at the 2 nd scanning correspond to two different counters.

If the target memory page during the ith scanning is determined to have the same content as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is determined to have different content from the target memory page during the i-2 th scanning, and the CPU determines that the target memory page has just remained unchanged, the value of the counter corresponding to the target memory page during the ith scanning is detected, so as to determine whether the remaining memory pages having the same content as the target memory page during the ith scanning exist based on the value of the counter. It should be noted that, in the process of performing, by the CPU, i-1 th deduplication on a target memory page, because contents of the target memory page during the i-1 st scanning are different from contents of the target memory page during the i-2 nd scanning, the CPU may determine a counter corresponding to the target memory page during the i-1 st scanning, and increase a value of the counter corresponding to the target memory page during the i-1 st scanning by a first value. Then, in the process that the CPU performs the i-th deduplication on the target memory page, since the target memory page during the i-th scanning is the same as the target memory page during the i-1-th scanning, the target memory page during the i-th scanning and the target memory page during the i-1-th scanning correspond to the same counter, and at this time, the value of the counter is at least the first value.

If it is determined that the value of the counter corresponding to the target memory page at the ith scanning is greater than the first value, the CPU may determine that there is a memory page (i.e., a duplicate page of the target memory page at the ith scanning) having the same content as the target memory page at the ith scanning, and merge the target memory page at the ith scanning and the duplicate page of the target memory page at the ith scanning.

From the above method, it can be seen that: after the target memory page is scanned for the ith time, when the CPU determines that the target memory page during the ith time is in a state of being changed (that is, the target memory page during the ith time is different from the target memory page during the i-1 st time), the CPU may increase the value of the counter corresponding to the target memory page during the ith time by a first value. When the CPU determines that the target memory page during the ith scanning is in a state of being just maintained (that is, the content of the target memory page during the ith scanning is the same as that of the target memory page during the i-1 st scanning, and the content of the target memory page during the i-1 st scanning is different from that during the i-2 nd scanning), and the value of the counter corresponding to the target memory page during the ith scanning is greater than the first value, it may accurately determine that a duplicate page exists in the target memory page during the ith scanning. Then, the CPU may obtain the duplicate page of the target memory page during the ith scanning, and merge the target memory page during the ith scanning and the duplicate page of the target memory page during the ith scanning. Therefore, the CPU can fully filter the memory pages without the duplicate pages and carry out effective deduplication operation on the memory pages with the duplicate pages in a targeted manner, so that a large amount of ineffective deduplication operation is avoided, the CPU overhead is reduced, and the deduplication speed is improved.

In one possible implementation, the method further includes: and if the value of the counter corresponding to the target memory page during the ith scanning is determined to be equal to the first value, ending the processing of the target memory page during the ith scanning. In the foregoing implementation manner, after the CPU detects the value of the counter corresponding to the target memory page during the ith scanning, if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is equal to the first value, the CPU considers that no duplicate page exists in the target memory page during the ith scanning. Therefore, the CPU may end the processing of the target memory page at the i-th scan, i.e., skip the target memory page at the i-th scan.

In one possible implementation, the method further includes: if the target memory page during the ith scanning is determined to be the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is determined to be the same as the target memory page during the i-2 nd scanning, the processing on the target memory page during the ith scanning is finished. In the foregoing implementation manner, after the CPU detects the value of the unmodified round of the target memory page, if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning, that is, between the ith scanning and the i-1 st scanning, and between the i-1 st scanning and the i-2 nd scanning, the content of the target memory page is not modified (it may also be understood that the target memory page is in a state of being kept unchanged for a long time), the CPU considers that no duplicate page exists in the target memory page during the ith scanning. Then, the CPU ends the processing of the target memory page at the time of the ith scanning, that is, skips the target memory page at the time of the ith scanning.

In a possible implementation manner, after the ith scanning is performed on the target memory page, the method further includes: the CPU may obtain a checksum of the target memory page during the ith scanning and a checksum of the target memory page during the i-1 th scanning, where the checksum of the target memory page during the ith scanning is generated based on the target memory page during the ith scanning, and the checksum of the target memory page during the i-1 th scanning is generated based on the target memory page during the i-1 th scanning. Then, the CPU may accurately detect whether the content of the target memory page during the ith scanning is the same as that of the target memory page during the i-1 st scanning, and whether the content of the target memory page during the i-1 st scanning is the same as that of the target memory page during the i-2 nd scanning, based on the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the i-1 st scanning.

In a possible implementation manner, detecting, based on a checksum of the target memory page during the ith scanning and a checksum of the target memory page during the i-1 th scanning, whether the content of the target memory page during the ith scanning is the same as that of the target memory page during the i-1 th scanning, and whether the content of the target memory page during the i-1 th scanning is the same as that of the target memory page during the i-2 th scanning includes: if the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the i-1 th scanning are determined to be different, the CPU sets the value of the unmodified round of the target memory page to be a second value. If the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the i-1 th scanning are determined to be the same, the CPU increases the value of the unmodified round of the target memory page by a third value. In this way, the CPU can accurately detect whether the target memory page at the ith scanning time is the same as the target memory page at the i-1 st scanning time, and whether the target memory page at the i-1 st scanning time is the same as the target memory page at the i-2 nd scanning time, based on the magnitude of the unmodified round of the target memory page.

In a possible implementation manner, if it is determined that the target memory page at the ith scanning time is different from the target memory page at the i-1 th scanning time, the method includes: if it is determined that the value of the unmodified round of the target memory page is equal to the second value, the CPU determines that the target memory page during the ith scanning is different from the target memory page during the (i-1) th scanning, that is, the content of the target memory page is modified (it can also be understood that the target memory page has just changed) between the ith scanning and the (i-1) th scanning.

In a possible implementation manner, if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is different from the target memory page during the i-2 nd scanning, the method includes: if it is determined that the value of the unmodified round of the target memory page is equal to the third value, the CPU determines that the content of the target memory page in the ith scanning is the same as the content of the target memory page in the i-1 th scanning, and the content of the target memory page in the i-1 th scanning is different from the content of the target memory page in the i-2 th scanning, that is, between the ith scanning and the i-1 st scanning, the content of the target memory page is unmodified, and between the i-1 th scanning and the i-2 th scanning, the content of the target memory page is modified (it can also be understood that the target memory page just remains unchanged).

In a possible implementation manner, if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning, the method includes: if the value of the unmodified round of the target memory page is determined to be greater than the third value, the CPU determines that the target memory page in the ith scanning is the same as the target memory page in the i-1 st scanning, and the target memory page in the i-1 st scanning is the same as the target memory page in the i-2 nd scanning, that is, the content of the target memory page is not modified between the ith scanning and the i-1 st scanning and between the i-1 st scanning and the i-2 nd scanning (it can also be understood that the target memory page remains unchanged for a long time).

In one possible implementation manner, merging the target memory page at the time of the ith scanning and the memory page having the same content as the target memory page at the time of the ith scanning includes: if the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to the same process and the target memory page during the ith scanning and the first memory page in the queue to be merged are located in a preset address range, adding the target memory page during the ith scanning into the queue to be merged until a new queue to be merged is constructed, and merging each memory page in the queue to be merged and the memory page with the same content as the memory page; if it is determined that the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to different processes, or the target memory page during the ith scanning and the first memory page are not located within a preset address range, merging each memory page in the queue to be merged and a memory page having the same content as the memory page, and constructing a new queue to be merged by taking the target memory page during the ith scanning as the first memory page. In the related art, after determining a memory page with a duplicate page, the CPU merges the memory page and the duplicate page of the memory page immediately, and during the merging process, the CPU needs to flush a Translation Lookaside Buffer (TLB). Therefore, in the related art, if the CPU determines N memory pages having duplicate pages, it needs to perform the TLB refresh operation N times. In the present application, after determining a plurality of memory pages with duplicate pages, the CPU may put the memory pages into a queue to be merged, and when a certain condition is satisfied, may merge each memory page in the queue to be merged together with the duplicate page of each memory page. Therefore, the method and the device have the advantages that the queue to be merged is taken as a unit, the batch merging of the repeated pages is realized, the CPU only needs to carry out the refreshing operation of the TLB once in the batch merging process, and the CPU overhead can be further reduced.

A second aspect of the embodiments of the present application provides a memory page processing apparatus, including: the scanning module is used for scanning the target memory page for the ith time; the first processing module is configured to, if it is determined that the target memory page during the ith scanning is different from the target memory page during the i-1 st scanning in content, increase a first numerical value of a counter corresponding to the target memory page during the ith scanning; a second processing module, configured to detect a value of a counter corresponding to a target memory page during an ith scanning if it is determined that the target memory page during the ith scanning is the same as the target memory page during an (i-1) th scanning, and the target memory page during the (i-1) th scanning is different from the target memory page during an (i-2) th scanning; a third processing module, configured to, if it is determined that a value of a counter corresponding to the target memory page during the ith scanning is greater than the first value, merge the target memory page during the ith scanning and the remaining memory pages having the same content as the target memory page during the ith scanning; the memory pages with different contents correspond to different counters, and the memory pages with the same contents correspond to the same counter.

From the above device it can be seen that: after the target memory page is scanned for the ith time, when the CPU determines that the target memory page during the ith time is in a state of being changed (that is, the target memory page during the ith time is different from the target memory page during the i-1 st time), the CPU may increase the value of the counter corresponding to the target memory page during the ith time by a first value. When the CPU determines that the target memory page during the ith scanning is in a state of being just unchanged (that is, the target memory page during the ith scanning is the same as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is different from the target memory page during the i-2 th scanning), and the value of the counter corresponding to the target memory page during the ith scanning is greater than the first value, it may be accurately determined that there is a duplicate page in the target memory page during the ith scanning. Then, the CPU may obtain the duplicate page of the target memory page during the ith scanning, and merge the target memory page during the ith scanning and the duplicate page of the target memory page during the ith scanning. Therefore, the CPU can fully filter the memory pages without the duplicate pages and carry out effective deduplication operation on the memory pages with the duplicate pages in a targeted manner, so that a large amount of ineffective deduplication operation is avoided, the CPU overhead is reduced, and the deduplication speed is improved.

In one possible implementation, the apparatus further includes: and a fourth processing module, configured to end processing of the target memory page during the ith scanning if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is equal to the first value.

In one possible implementation, the apparatus further includes: a fifth processing module, configured to, if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is the same as the target memory page during the i-2 th scanning, end the processing on the target memory page during the ith scanning.

In one possible implementation, the apparatus further includes: the detection module is configured to detect, based on a checksum of the target memory page during the ith scanning and a checksum of the target memory page during the i-1 th scanning, whether the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and whether the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning; the checksum of the target memory page during the ith scanning is generated based on the target memory page during the ith scanning, and the checksum of the target memory page during the i-1 th scanning is generated based on the target memory page during the i-1 th scanning.

In a possible implementation manner, the detection module is specifically configured to: if the checksum of the target memory page in the ith scanning and the checksum of the target memory page in the (i-1) th scanning are different, setting the numerical value of the unmodified round of the target memory page as a second numerical value; if the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the (i-1) th scanning are determined to be the same, increasing a third numerical value of the number of unmodified rounds of the target memory page; based on the numerical value of the unmodified round of the target memory page, whether the content of the target memory page during the ith scanning is the same as that of the target memory page during the (i-1) th scanning, and whether the content of the target memory page during the (i-1) th scanning is the same as that of the target memory page during the (i-2) th scanning are detected.

In a possible implementation manner, the first processing module is specifically configured to, if it is determined that the value of the unmodified round of the target memory page is equal to the second value, determine that the content of the target memory page during the ith scanning is different from the content of the target memory page during the i-1 st scanning, and increase the value of a counter corresponding to the target memory page during the ith scanning by the first value.

In a possible implementation manner, the second processing module is specifically configured to, if it is determined that the value of the unmodified round of the target memory page is equal to a third value, determine that the content of the target memory page during the ith scanning is the same as the content of the target memory page during the i-1 st scanning, and the content of the target memory page during the i-1 st scanning is different from the content of the target memory page during the i-2 nd scanning, and detect the size of the value of the counter corresponding to the target memory page during the ith scanning.

In a possible implementation manner, the fifth processing module is specifically configured to determine that, if it is determined that the value of the unmodified round of the target memory page is greater than the third value, the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning, and end the processing of the target memory page during the ith scanning.

In a possible implementation manner, the third processing module is specifically configured to: if the value of a counter corresponding to the target memory page during the ith scanning is larger than a first value, detecting whether the target memory page during the ith scanning and a first memory page in the queue to be merged correspond to the same process or not, and whether the target memory page during the ith scanning and the first memory page in the queue to be merged are located in a preset address range or not; if the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to the same process and the target memory page during the ith scanning and the first memory page in the queue to be merged are located in a preset address range, adding the target memory page during the ith scanning into the queue to be merged until a new queue to be merged is constructed, and merging each memory page in the queue to be merged and the memory page with the same content as the memory page; if it is determined that the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to different processes, or the target memory page during the ith scanning and the first memory page are not located within a preset address range, merging each memory page in the queue to be merged and a memory page having the same content as the memory page, and constructing a new queue to be merged by taking the target memory page during the ith scanning as the first memory page.

A third aspect of embodiments of the present application provides an electronic device, comprising a memory and a processor; the memory stores code and the processor is configured to execute the code, and when executed, the electronic device performs the method as described in the first aspect or any one of the possible implementations of the first aspect.

A fourth aspect of embodiments of the present application is a computer-readable storage medium comprising computer-readable instructions that, when executed on a computer, cause the computer to perform a method as set forth in the first aspect or any one of the possible implementations of the first aspect.

A fifth aspect of embodiments of the present application is a computer program product comprising computer readable instructions which, when run on a computer, cause the computer to perform a method as described in the first aspect or any one of the possible implementations of the first aspect.

In this embodiment, after the target memory page is scanned for the ith time, when the CPU determines that the target memory page during the ith time is in a state of being changed (that is, the target memory page during the ith time is different from the target memory page during the i-1 st time), the CPU may increase the value of the counter corresponding to the target memory page during the ith time by a first value. When the CPU determines that the target memory page during the ith scanning is in a state of being just maintained (that is, the content of the target memory page during the ith scanning is the same as that of the target memory page during the i-1 st scanning, and the content of the target memory page during the i-1 st scanning is different from that during the i-2 nd scanning), and the value of the counter corresponding to the target memory page during the ith scanning is greater than the first value, it may accurately determine that a duplicate page exists in the target memory page during the ith scanning. Then, the CPU may obtain the duplicate page of the target memory page during the ith scanning, and merge the target memory page during the ith scanning and the duplicate page of the target memory page during the ith scanning. Therefore, the CPU can fully filter the memory pages without the duplicate pages and carry out effective deduplication operation on the memory pages with the duplicate pages in a targeted manner, so that a large amount of ineffective deduplication operation is avoided, the CPU overhead is reduced, and the deduplication speed is improved.

Drawings

Fig. 1 is a schematic diagram of a cloud scenario provided in an embodiment of the present application;

fig. 2 is a schematic flow chart illustrating a memory page processing method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a counter provided in an embodiment of the present application;

FIG. 4 is a graph showing the comparison results provided in the examples of the present application;

FIG. 5 is another schematic diagram of the comparison results provided by the embodiments of the present application;

fig. 6 is a schematic structural diagram of a memory page processing apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely descriptive of the manner in which objects of the same nature are distinguished in the embodiments of the application. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the application can be applied to a cloud scene. In this scenario, the physical server serves as a host, and is usually deployed with multiple Virtual Machines (VMs) or multiple containers (containers), and for convenience of description, the virtual machines will be schematically described below as an example. As shown in fig. 1 (fig. 1 is a schematic view of a cloud scenario provided by an embodiment of the present application), a plurality of virtual machines on a physical server often run the same or similar operating systems and applications, so that a large amount of repeated data exists between the virtual machines, and the repeated data is stored in a physical memory, so that a large number of physical memory pages with the same content are generated. Thus, memory deduplication technology arose.

Generally, each virtual machine may be allocated a certain virtual memory page, and each virtual machine may access a corresponding physical memory page through the virtual memory page allocated to the virtual machine, so as to obtain data stored in the physical memory page. It can be seen that, when the CPU of the physical server determines that the contents of multiple physical memory pages pointed by multiple virtual memory pages (i.e., data stored in the physical memory pages) are the same, the multiple virtual memory pages can be pointed to the same physical memory page, that is, multiple physical memory pages with the same contents are merged, so that redundant physical memory pages are released, and the purpose of removing duplicate in the memory is achieved.

In the related art, the CPU can effectively increase the available memory by circularly executing the memory deduplication operation. For convenience of description, the physical memory page is hereinafter referred to as a memory page, and will not be described in detail later. Specifically, when performing the current deduplication on a plurality of memory pages, a certain memory page may be scanned to obtain the content of the memory page, a numerical value is generated based on the content of the memory page, the numerical value is compared with each numerical value in the red-black tree (generated based on the content of the scanned remaining memory pages), if there are other numerical values that are the same as the numerical value, it is determined that there are memory pages that are the same as the content of the memory page, and the memory pages are merged, and if there are no memory pages, the numerical value is stored in the red-black tree. After that, the operations can be performed on the remaining memory pages that are not scanned until the current deduplication of all the memory pages is completed, and then the next deduplication of all the memory pages is performed.

As can be seen, during each deduplication, the CPU compares each memory page with the rest of the memory pages to obtain duplicate pages of each memory page. If a certain memory page does not have a duplicate page, the duplicate removal operation of the CPU to the memory page is invalid. This is quite common in each deduplication, and too many invalid deduplication operations result in excessive CPU overhead and reduce deduplication speed. In order to solve the problem, an embodiment of the present application provides a memory page processing method. Fig. 2 is a schematic flow chart of a memory page processing method according to an embodiment of the present application, where the method includes:

201. and scanning the target memory page for the ith time.

In this embodiment, the CPU may perform multiple deduplication processes on multiple memory pages in a cycle. In all the memory pages, the CPU may sequentially perform the ith deduplication on each memory page until the ith deduplication of all the memory pages is completed. For convenience of description, in the ith deduplication of all the memory pages, the current memory page is referred to as a target memory page, where the target memory page may be a 1 st memory page of all the memory pages, may also be a 2 nd memory page of all the memory pages, may also be a last memory page of all the memory pages, and the like, and this is not limited herein.

In the process of performing the ith deduplication on the target memory page, the ith scanning may be performed on the target memory page first, so as to obtain the content of the target memory page during the ith scanning, that is, the data stored in the target memory page during the ith scanning.

202. Whether the content of the target memory page in the ith scanning is the same as that of the target memory page in the (i-1) th scanning and whether the content of the target memory page in the (i-1) th scanning is the same as that of the target memory page in the (i-2) th scanning are detected.

After obtaining the content of the target memory page at the ith scanning time, the CPU may compare whether the content of the target memory page at the ith scanning time is the same as the content of the target memory page at the i-1 st scanning time, and compare whether the content of the target memory page at the i-1 st scanning time is the same as the content of the target memory page at the i-2 nd scanning time. For convenience of description, in this embodiment, it may be understood that "whether the content of the target memory page during the ith scanning is the same as the content of the target memory page during the i-1 st scanning" is "whether the content of the target memory page during the ith scanning is the same as the content of the target memory page during the i-1 st scanning", and, for example, "whether the content of the target memory page during the i-1 st scanning is the same as the content of the target memory page during the i-2 nd scanning" is "that the content of the target memory page during the i-1 st scanning is the same as the content of the target memory page during the i-2 nd scanning", and so on, the rest of similar descriptions are also the same, and will not be described in detail later.

Specifically, the CPU may perform calculation based on the target memory page during the ith scanning, to obtain the checksum of the target memory page during the ith scanning. For example, after scanning the target memory page for the ith time, the CPU may obtain data stored in the target memory page during the ith time, and perform a hash calculation on the first 64 bytes (byte) of the data to obtain a checksum of the target memory page during the ith time.

After the checksum of the target memory page during the ith scanning is obtained through calculation, the CPU may further obtain the stored checksum of the target memory page during the (i-1) th scanning. The checksum of the target memory page at the i-1 th scanning is calculated by the CPU based on the target memory page at the i-1 th scanning.

It is to be appreciated that the checksum of the target memory page at the ith scan may be used to indicate the target memory page at the ith scan. Similarly, the checksum of the target memory page at the i-1 st scan may be used to indicate the target memory page at the i-1 st scan. Then, the CPU may determine whether the content of the target memory page at the ith scanning is the same as that of the target memory page at the i-1 st scanning, and whether the content of the target memory page at the i-1 st scanning is the same as that of the target memory page at the i-2 nd scanning, based on the checksum of the target memory page at the ith scanning and the checksum of the target memory page at the i-1 st scanning.

Further, in all the memory pages, each memory page is provided with an unmodified round (clean circles) for indicating the number of times that the content of the memory page is unmodified, and when values of the unmodified rounds of the memory pages are different, the number of times that the content of the memory page is unmodified is different. The CPU may compare the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the i-1 th scanning, and if it is determined that the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the i-1 th scanning are different, which indicates that the content of the target memory page has just been modified between the i-1 th scanning and the ith scanning, the CPU may set the value of the unmodified round of the target memory page to be a second value (for example, the second value may be 0). If it is determined that the checksum of the target memory page during the ith scanning is the same as the checksum of the target memory page during the i-1 th scanning, which indicates that the content of the target memory page is not modified between the i-1 th scanning and the ith scanning, the CPU increases the value of the unmodified round of the target memory page by a third value (for example, the third value may be 1).

After processing the numerical value of the unmodified round of the target memory page, the CPU may detect the numerical value of the unmodified round of the target memory page, and determine, according to the numerical value of the unmodified round of the target memory page, whether the content of the target memory page during the ith scanning is the same as that of the target memory page during the i-1 st scanning, and whether the content of the target memory page during the i-1 st scanning is the same as that of the target memory page during the i-2 nd scanning.

203. If the target memory page during the ith scanning is determined to be different from the target memory page during the i-1 th scanning, the value of the counter corresponding to the target memory page during the ith scanning is increased by a first value, and the processing of the target memory page during the i-1 th scanning is finished.

In this embodiment, a counter array with a certain length is provided, and the length of the counter array may be 2 bits (bit), or 4 bits, and the like, which is not limited herein. Specifically, the counter array includes a plurality of counters, the initial values of all the counters are the same preset value (for example, the preset value may be 0), different counters have different index values, and the index values may be calculated by the CPU for the memory pages. Since different index values can be obtained by calculating different memory pages, and the same index value can be obtained by calculating the same memory page, different memory pages can correspond to different counters, and the same memory page can correspond to the same counter. It should be noted that, the two memory pages used for comparing whether they are the same may include: (1) a certain memory page during two times of scanning; (2) Two memory pages in all the memory pages are scanned at the same time; (3) A certain memory page at a certain scan, and another memory page at another scan.

For example, if the contents of the memory page 1 at the time of the 3 rd scan and the memory page 1 at the time of the 2 nd scan are the same, the index value (hash value) obtained by performing the hash calculation based on the memory page 1 at the time of the 3 rd scan is the same as the index value obtained by performing the hash calculation based on the memory page 1 at the time of the 2 nd scan, and therefore, the memory page 1 at the time of the 3 rd scan and the memory page 1 at the time of the 2 nd scan correspond to the same counter.

For another example, if the content of the memory page 1 at the 3 rd scanning time is the same as that of the memory page 2 at the 3 rd scanning time, the index value obtained by performing the hash calculation on the memory page 1 at the 3 rd scanning time is the same as that obtained by performing the hash calculation on the memory page 2 at the 3 rd scanning time, and therefore the memory page 1 at the 3 rd scanning time and the memory page 2 at the 3 rd scanning time correspond to the same counter.

For example, if the content of the memory page 1 at the 3 rd scanning time is the same as that of the memory page 2 at the 2 nd scanning time, the index value obtained by performing the hash calculation on the memory page 1 at the 3 rd scanning time is the same as that obtained by performing the hash calculation on the memory page 2 at the 2 nd scanning time, and therefore the memory page 1 at the 3 rd scanning time and the memory page 2 at the 2 nd scanning time correspond to the same counter.

For example, if the contents of the memory page 1 at the time of the 3 rd scan and the memory page 1 at the time of the 2 nd scan are different, the index value obtained by performing the hash calculation on the memory page 1 at the time of the 3 rd scan is different from the index value obtained by performing the hash calculation on the memory page 1 at the time of the 2 nd scan, and therefore the memory page 1 at the time of the 3 rd scan and the memory page 1 at the time of the 2 nd scan correspond to two counters having different contents.

For example, if the contents of the memory page 1 at the time of the 3 rd scan and the memory page 2 at the time of the 3 rd scan are different, the index value obtained by performing the hash calculation on the memory page 1 at the time of the 3 rd scan is different from the index value obtained by performing the hash calculation on the memory page 2 at the time of the 3 rd scan, and therefore the memory page 1 at the time of the 3 rd scan and the memory page 2 at the time of the 3 rd scan correspond to two counters having different contents.

For example, if the contents of the memory page 1 at the 3 rd scanning time and the memory page 2 at the 2 nd scanning time are different, the index value obtained by performing the hash calculation on the memory page 1 at the 3 rd scanning time is different from the index value obtained by performing the hash calculation on the memory page 2 at the 2 nd scanning time, and therefore the memory page 1 at the 3 rd scanning time and the memory page 2 at the 2 nd scanning time correspond to two counters having different contents.

After the CPU detects the value of the unmodified round of the target memory page, if it is determined that the value of the unmodified round of the target memory page is equal to the second value, the CPU determines that the content of the target memory page during the ith scanning is different from the content of the target memory page during the (i-1) th scanning, that is, the content of the target memory page is modified (it can also be understood that the target memory page has just changed) between the ith scanning and the (i-1) th scanning. Then, the CPU may determine a counter corresponding to the target memory page during the ith scanning, increase the value of the counter corresponding to the target memory page during the ith scanning by a first value (for example, the first value may be 1), and end the processing on the target memory page during the ith scanning, that is, skip the target memory page during the ith scanning.

204. If it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is different from the target memory page during the i-2 th scanning, the value of the counter corresponding to the target memory page during the ith scanning is detected.

After the CPU detects the value of the unmodified round of the target memory page, if it is determined that the value of the unmodified round of the target memory page is equal to the third value, the CPU determines that the content of the target memory page during the ith scanning is the same as the content of the target memory page during the i-1 st scanning, and the content of the target memory page during the i-1 st scanning is different from the content of the target memory page during the i-2 nd scanning, that is, the content of the target memory page is not modified between the ith scanning and the i-1 st scanning, and the content of the target memory page is modified between the i-1 st scanning and the i-2 nd scanning (it can also be understood that the target memory page is just maintained). Then, the CPU may determine a counter corresponding to the target memory page at the ith scanning, and detect a value of the counter corresponding to the target memory page at the ith scanning.

It should be noted that, in the process of performing the i-1 th deduplication on the target memory page by the CPU, since the target memory page during the i-1 th scanning is different from the target memory page during the i-2 th scanning in content, the CPU may determine a counter corresponding to the target memory page during the i-1 th scanning, and increase a value of the counter corresponding to the target memory page during the i-1 th scanning by a first value. It can be seen that, in the process of performing the ith deduplication on the target memory page by the CPU, since the contents of the target memory page during the ith scanning are the same as those of the target memory page during the i-1 st scanning, the target memory page during the ith scanning and the target memory page during the i-1 st scanning correspond to the same counter, and at this time, the value of the counter is at least the first value.

Then, based on the value of the counter corresponding to the target memory page at the scanning of the ith time, the CPU may determine whether there is a memory page with the same content as the target memory page at the scanning of the ith time in all the memory pages, that is, whether there is a duplicate page in the target memory page at the scanning of the ith time

205. If it is determined that the value of the counter corresponding to the target memory page at the ith scanning is greater than the first value, merging the target memory page at the ith scanning and the memory page having the same content as the target memory page at the ith scanning.

After the CPU detects the value of the counter corresponding to the target memory page during the ith scanning, if the value of the counter corresponding to the target memory page during the ith scanning is determined to be larger than the first value, the CPU considers that the target memory page during the ith scanning has a repeated page. Therefore, the CPU may compare the target memory page at the time of the ith scanning with the remaining memory pages except the target memory page at the time of the ith scanning, so as to obtain a memory page having the same content as the target memory page at the time of the ith scanning.

Thereafter, the CPU may merge the target memory page at the i-th scanning and the memory page having the same content as the target memory page at the i-th scanning (i.e., the duplicate page of the target memory page at the i-th scanning).

Specifically, the CPU may implement merging of memory pages by:

(1) And the CPU performs write protection on the target memory page during the ith scanning and the repeated page of the target memory page during the ith scanning. If the content of the target memory page during the ith scanning and/or the content of the duplicate page of the target memory page during the ith scanning are modified, the protection may disappear, and the CPU does not merge the part of memory pages.

(2) The CPU obtains a queue to be merged, where the queue to be merged includes multiple memory pages to be merged, that is, memory pages to be merged determined when the CPU performs an i-th deduplication, where the memory pages are generally memory pages used by the same process, and a last memory page and a first memory page are located in a preset address range (for example, the address range may be 64 KB). Then, the CPU may determine whether the target memory page at the ith scanning satisfies the following condition:

whether the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to the same process or not, and whether the target memory page during the ith scanning and the first memory page in the queue to be merged are located in a preset address range or not.

If the target memory page during the ith scanning meets the condition, the target memory page during the ith scanning is placed into the queue to be merged as the last memory page of the queue to be merged, and the repeated page of the target memory page during the ith scanning is not placed into the queue to be merged (when the CPU performs the ith deduplication, the determined rest of the memory pages to be merged are the same, and are not repeated here) until the memory pages to be merged which do not meet the condition appear (the CPU can construct a new queue to be merged based on the memory pages), and then each memory page in the queue to be merged and the repeated page of the memory page are merged.

If the target memory page during the ith scanning does not meet the condition, merging each memory page in the queue to be merged and the repeated page of the memory page, and constructing a new queue to be merged by taking the target memory page during the ith scanning as the first memory page.

206. If the value of the counter corresponding to the target memory page at the ith scanning time is determined to be equal to the first value, the processing of the target memory page at the ith scanning time is finished.

After the CPU detects the value of the counter corresponding to the target memory page during the ith scanning, if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is equal to the first value, the CPU considers that no duplicate page exists in the target memory page during the ith scanning. Therefore, the CPU may end the processing of the target memory page at the i-th scanning, i.e., skip the target memory page at the i-th scanning.

207. If it is determined that the target memory page at the ith scanning time is the same as the target memory page at the i-1 th scanning time, and the target memory page at the i-1 th scanning time is the same as the target memory page at the i-2 th scanning time, the processing of the target memory page at the ith scanning time is finished.

After the CPU detects the value of the unmodified round of the target memory page, if it is determined that the value of the unmodified round of the target memory page is greater than the third value, the CPU determines that the content of the target memory page during the ith scanning is the same as the content of the target memory page during the (i-1) th scanning, and the content of the target memory page during the (i-1) th scanning is the same as the content of the target memory page during the (i-2) th scanning, that is, between the (i) th scanning and the (i-1) th scanning, and between the (i-1) th scanning and the (i-2) th scanning, the content of the target memory page is not modified (it can be understood that the target memory page remains unchanged for a long time), so the CPU considers that there is no duplicate page in the target memory page during the (i) th scanning). Then, the CPU ends the processing of the target memory page at the i-th scanning, that is, skips the target memory page at the i-th scanning.

After steps 201 to 207 are completed, which is equivalent to the i-th deduplication of the target memory page, the i-th deduplication of the next memory page may be performed until the i-th deduplication of all the memory pages is completed, and then the i + 1-th deduplication of all the memory pages is performed, so as to effectively increase the available memory.

To facilitate an understanding of the above process, the following is further described with reference to a specific application example. In this application, N memory pages, i.e., memory page 1, memory page 2, memory page 3, 8230, are provided, and the CPU can perform M times of deduplication processing on the N memory pages. The application example comprises the following steps:

(1) Let the CPU currently perform the 3 rd deduplication to memory page 1. In the 3 rd deduplication process of the memory page 1, the CPU may first perform the 3 rd scanning on the memory page 1 to obtain the content of the memory page 1 at the 3 rd scanning, and based on the content, may generate the checksum of the memory page 1 at the 3 rd scanning. Then, it is determined whether the checksum of the memory page 1 at the time of the 3 rd scan is identical in content to the checksum of the memory page at the time of the 2 nd scan, and the numerical value of the unmodified round of the memory page 1 is processed based on the result.

(1.1) if the CPU determines that the checksum of the memory page 1 at the time of the 3 rd scan is different from the checksum of the memory page at the time of the 2 nd scan, the CPU sets the value of the unmodified round of the memory page 1 to 0. It should be noted that, in the process of performing the 1 st deduplication on the memory page 1, the checksum of the memory page 1 at the 1 st scanning is necessarily different from the checksum (which may be considered to be 0) of the memory page at the 0 th scanning, so when performing the 1 st deduplication on the memory page 1, the value of the unmodified round of the memory page 1 is also set to 0.

(1.2) if the checksum of the memory page 1 at the 3 rd scanning time is determined to be the same as the checksum of the memory page at the 2 nd scanning time, increasing the number of the unmodified round of the memory page 1 by 1. Based on (1.1) and (1.2), in the process of performing the 3 rd deduplication on the memory page 1, if the value of the unmodified round of the memory page 1 is equal to 0, it indicates that the memory page 1 is modified between the 3 rd scan and the 2 nd scan. If the value of the unmodified round of the memory page 1 is equal to 1, it indicates that the memory page 1 is not modified between the 3 rd scan and the 2 nd scan, and is modified between the 2 nd scan and the 1 st scan. If the value of the unmodified round of the memory page 1 is equal to 2, it indicates that the memory page 1 is not modified between the 3 rd scan and the 2 nd scan, and between the 2 nd scan and the 1 st scan.

(2) After completing (1), the value of the unmodified round of the memory page 1 can be detected, and corresponding processing is performed.

(2.1) if it is determined that the value of the unmodified round of the memory page 1 is 0, the CPU determines that the content of the memory page 1 is modified between the 3 rd scan and the 2 nd scan, that is, the memory page 1 has just changed, so the CPU may determine a counter corresponding to the memory page 1 at the 3 rd scan, increase the value of the counter by 1, and skip the memory page 1 at the 3 rd scan.

(2.2) if the number of unmodified rounds of the memory page 1 is determined to be 1, the CPU may determine that the content of the memory page 1 is not modified between the 3 rd scan and the 2 nd scan, and that the content of the memory page 1 is modified between the 2 nd scan and the 1 st scan, that is, the memory page 1 just remains unchanged, so the CPU may determine the counter corresponding to the memory page 1 at the 3 rd scan, and detect the value of the counter. In this way, the CPU can determine whether there are remaining memory pages having the same content as the memory page 1 based on the value of the counter.

(2.2.1) if the CPU determines that the counter value is greater than 1, it indicates that the memory page 1 at the 3 rd scanning time has a duplicate page, so the CPU can merge the memory pages. To facilitate an understanding of this process, it is further described below in conjunction with FIG. 3. Fig. 3 is a schematic diagram of a counter provided in this embodiment of the present application, and as shown in fig. 3, if a similar situation (2.1) occurs in the memory page 2 during the 1 st deduplication process, and the memory page 2 at the 1 st scanning corresponds to the counter 1 and the counter 6, the CPU may increment the values of the counter 1 and the counter 6 by 1 (e.g., in fig. 3, modify the values of the counter 1 and the counter 6 from 0 to 1). Then, since the memory page 1 also occurs in the process of performing the 2 nd deduplication, similar to (2.1), and the memory page 1 at the 2 nd scanning time becomes the same as the memory page 2 at the 1 st scanning time, the CPU may increase the values of the counter 1 and the counter 6 by 1 again (as in fig. 3, the values of the counter 1 and the counter 6 are modified from 1 to 2). Then, in the process of performing the 3 rd deduplication on the memory page 1, the CPU may determine that the values of the counter 1 and the counter 6 are both greater than 1, which indicates that the memory page 1 in the 3 rd scanning has a duplicate page (i.e., the memory page 2 in the 1 st scanning is assumed to have not changed in the subsequent process, and thus the CPU may merge the two memory pages.

(2.2.2) if the CPU determines that the counter value is 1, it indicates that there is no duplicate page in the memory page 1 at the 3 rd scanning, so the CPU can skip the memory page 1 at the 3 rd scanning.

(2.3) if it is determined that the value of the unmodified round of the memory page 1 is greater than 1, the CPU may determine that the memory page 1 has not been modified between the 3 rd scan and the 2 nd scan, and the content of the memory page 1 has not been modified between the 2 nd scan and the 1 st scan, that is, the memory page 1 remains unchanged for a long time, which indicates that there is no duplicate page in the memory page 1 at the 3 rd scan, and thus the CPU may skip the memory page 1 at the 3 rd scan.

(3) After completing (2), the 3 rd deduplication of the memory pages 6 may be continued until the 3 rd deduplication of the N memory pages is completed, and then the 4 th deduplication of the N memory pages is performed.

In addition, the memory page processing method provided by the embodiment of the present application can be compared with two related technologies, and the comparison results are shown in fig. 4 and fig. 5 (fig. 4 is a schematic diagram of the comparison results provided by the embodiment of the present application, and fig. 5 is another schematic diagram of the comparison results provided by the embodiment of the present application). In fig. 4 and 5, the deduplication processing result provided by the embodiment of the present application is a curve 1, and the deduplication processing results of the three related technologies are a curve 2 and a curve 3, respectively. In fig. 4, the abscissa represents time, the ordinate represents the number of memory pages to be deduplicated, the abscissa represents time, and the ordinate represents the usage rate of the CPU. Therefore, under the condition of performing deduplication processing on the same number of memory pages, the embodiment of the application can be obviously realized more quickly, has better performance, and greatly reduces the cost of the CPU.

In this embodiment, after scanning the target memory page for the ith time, when determining that the target memory page during the ith time of scanning is in a state of just changing (that is, the target memory page during the ith time of scanning is different from the target memory page during the i-1 th time of scanning), the CPU may increase the value of the counter corresponding to the target memory page during the ith time of scanning by a first value. When the CPU determines that the target memory page during the ith scanning is in a state of being just unchanged (that is, the target memory page during the ith scanning is the same as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is different from the target memory page during the i-2 th scanning), and the value of the counter corresponding to the target memory page during the ith scanning is greater than the first value, it may be accurately determined that there is a duplicate page in the target memory page during the ith scanning. Then, the CPU may obtain the duplicate page of the target memory page during the ith scanning, and merge the target memory page during the ith scanning and the duplicate page of the target memory page during the ith scanning. Therefore, the CPU can fully filter the memory pages without the duplicate pages and carry out effective deduplication operation on the memory pages with the duplicate pages in a targeted manner, so that a large amount of ineffective deduplication operation is avoided, the CPU overhead is reduced, and the deduplication speed is improved.

Furthermore, in the related art, after determining a memory page with a duplicate page, the CPU merges the memory page and the duplicate page of the memory page immediately, and during the merging process, the CPU needs to flush a Translation Lookaside Buffer (TLB). Therefore, in the related art, if the CPU determines N memory pages having duplicate pages, it is necessary to perform the flushing operation of the TLB N times. In this embodiment, after determining a plurality of memory pages with duplicate pages, the CPU may put the memory pages into a queue to be merged, and when a certain condition is satisfied, may merge each memory page in the queue to be merged together with the duplicate page of each memory page. Therefore, the method and the device have the advantages that the queue to be merged is taken as a unit, the batch merging of the repeated pages is realized, the CPU only needs to carry out the refreshing operation of the TLB once in the batch merging process, and the CPU overhead can be further reduced.

The foregoing is a detailed description of the memory page processing method provided in the embodiments of the present application, and the memory page processing apparatus provided in the embodiments of the present application is described below. Fig. 6 is a schematic structural diagram of a memory page processing apparatus according to an embodiment of the present application, and as shown in fig. 6, the apparatus includes:

a scanning module 601, configured to perform an ith scanning on a target memory page;

a first processing module 602, configured to increase a value of a counter corresponding to a target memory page during an ith scanning by a first value if it is determined that the target memory page during the ith scanning is different from the target memory page during the i-1 th scanning;

a second processing module 603, configured to detect a value of a counter corresponding to a target memory page during an ith scanning if it is determined that the target memory page during the ith scanning is the same as the target memory page during an i-1 th scanning, and the target memory page during the i-1 th scanning is different from the target memory page during an i-2 th scanning;

a third processing module 604, configured to, if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is greater than the first value, merge the target memory page during the ith scanning and the remaining memory pages having the same content as the target memory page during the ith scanning; the memory pages with different contents correspond to different counters, and the memory pages with the same contents correspond to the same counter.

In one possible implementation, the apparatus further includes: a fifth processing module, configured to, if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning, end the processing of the target memory page during the ith scanning.

In one possible implementation, the apparatus further includes: a detection module, configured to detect, based on a checksum of a target memory page during an ith scanning and a checksum of a target memory page during an i-1 th scanning, whether a target memory page during the ith scanning is the same as a target memory page during the i-1 th scanning, and whether a target memory page during the i-1 th scanning is the same as a target memory page during the i-2 th scanning; the checksum of the target memory page during the ith scanning is generated based on the target memory page during the ith scanning, and the checksum of the target memory page during the i-1 th scanning is generated based on the target memory page during the i-1 th scanning.

In a possible implementation manner, the detection module is specifically configured to: if the checksum of the target memory page in the ith scanning and the checksum of the target memory page in the (i-1) th scanning are different, setting the numerical value of the unmodified round of the target memory page as a second numerical value; if the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the (i-1) th scanning are determined to be the same, increasing a third numerical value to the numerical value of the unmodified round of the target memory page; based on the numerical value of the unmodified round of the target memory page, whether the content of the target memory page in the ith scanning is the same as that of the target memory page in the (i-1) th scanning, and whether the content of the target memory page in the (i-1) th scanning is the same as that of the target memory page in the (i-2) th scanning are detected.

In a possible implementation manner, the first processing module 602 is specifically configured to determine that the content of the target memory page during the ith scanning is different from the content of the target memory page during the i-1 st scanning if it is determined that the value of the unmodified round of the target memory page is equal to the second value, and increase the value of the counter corresponding to the target memory page during the ith scanning by the first value.

In a possible implementation manner, the second processing module 603 is specifically configured to determine that, if it is determined that the value of the unmodified round of the target memory page is equal to the third value, the content of the target memory page in the ith scanning is the same as the content of the target memory page in the i-1 th scanning, and the content of the target memory page in the i-1 th scanning is different from the content of the target memory page in the i-2 th scanning, and detect the value of the counter corresponding to the target memory page in the ith scanning.

In a possible implementation manner, the third processing module 604 is specifically configured to: if the value of a counter corresponding to the target memory page during the ith scanning is larger than a first value, detecting whether the target memory page during the ith scanning and a first memory page in the queue to be merged correspond to the same process or not, and whether the target memory page during the ith scanning and the first memory page in the queue to be merged are located in a preset address range or not; if the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to the same process and the target memory page during the ith scanning and the first memory page in the queue to be merged are located in a preset address range, adding the target memory page during the ith scanning into the queue to be merged until a new queue to be merged is constructed, and merging each memory page in the queue to be merged and the memory page with the same content as the memory page; if it is determined that the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to different processes, or the target memory page during the ith scanning and the first memory page are not located within a preset address range, merging each memory page in the queue to be merged and a memory page having the same content as the memory page, and constructing a new queue to be merged by taking the target memory page during the ith scanning as the first memory page.

It should be noted that, because the contents of information interaction, execution process, and the like between the modules/units of the apparatus are based on the same concept as the method embodiment of the present application, the technical effect brought by the contents is the same as the method embodiment of the present application, and specific contents may refer to the description in the foregoing method embodiment of the present application, and are not repeated herein.

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 7, an embodiment of a network device in the present application may include one or more central processing units 701, a memory 702, an input/output interface 703, a wired or wireless network interface 704, and a power supply 705.

The memory 702 may be transient storage or persistent storage. Still further, the central processor 701 may be configured to communicate with the memory 702 to execute a series of instruction operations in the memory 702 on the electronic device.

In this embodiment, the central processing unit 701 may execute the operations executed by the CPU in the embodiment shown in fig. 2, which are not described herein again.

In this embodiment, the specific functional module division in the central processing unit 701 may be similar to the division manner of the scanning module, the first processing module, the second processing module, the third processing module, the fourth processing module, the fifth processing module, the detection module, and the like described in fig. 6, and details thereof are not repeated here.

The embodiment of the application also relates to a computer storage medium which comprises computer readable instructions, and when the computer readable instructions are executed, the method is realized as shown in the figure 2.

Embodiments of the present application also relate to a computer program product containing instructions which, when run on a computer, cause the computer to perform the method as described in fig. 2.

It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims

1. A method for processing memory pages, the method comprising:

scanning the target memory page for the ith time;

if the target memory page during the ith scanning is different from the target memory page during the (i-1) th scanning, increasing the value of a counter corresponding to the target memory page during the ith scanning by a first value;

if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 th scanning, and the target memory page during the i-1 th scanning is different from the target memory page during the i-2 th scanning, detecting the value of a counter corresponding to the target memory page during the ith scanning; if it is determined that the value of the counter corresponding to the target memory page at the ith scanning is greater than the first value, merging the target memory page at the ith scanning and the memory page having the same content as the target memory page at the ith scanning;

the memory pages with different contents correspond to different counters, and the memory pages with the same contents correspond to the same counter.

2. The method of claim 1, further comprising:

if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is equal to the first value, ending the processing of the target memory page during the ith scanning.

3. The method according to claim 1 or 2, characterized in that the method further comprises:

if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning, ending the processing of the target memory page during the ith scanning.

4. The method of claim 3, further comprising:

detecting whether the content of the target memory page during the ith scanning is the same as that of the target memory page during the i-1 th scanning and whether the content of the target memory page during the i-1 th scanning is the same as that of the target memory page during the i-2 th scanning based on the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the i-1 th scanning;

the checksum of the target memory page during the ith scanning is generated based on the target memory page during the ith scanning, and the checksum of the target memory page during the (i-1) th scanning is generated based on the target memory page during the (i-1) th scanning.

5. The method according to claim 4, wherein the detecting whether the content of the target memory page in the ith scanning is the same as the content of the target memory page in the i-1 st scanning, and whether the content of the target memory page in the i-1 st scanning is the same as the content of the target memory page in the i-2 nd scanning, based on the checksum of the target memory page in the ith scanning and the checksum of the target memory page in the i-1 st scanning, includes:

if the checksum of the target memory page during the ith scanning and the checksum of the target memory page during the (i-1) th scanning are different, setting the value of the unmodified round of the target memory page as a second value;

if it is determined that the checksum of the target memory page during the ith scanning is the same as the checksum of the target memory page during the i-1 th scanning, increasing a third value to the value of the unmodified round of the target memory page;

based on the value of the unmodified round of the target memory page, detecting whether the content of the target memory page during the ith scanning is the same as that of the target memory page during the (i-1) th scanning, and whether the content of the target memory page during the (i-1) th scanning is the same as that of the target memory page during the (i-2) th scanning.

6. The method according to claim 5, wherein determining that the contents of the target memory page at the ith scanning are different from the contents of the target memory page at the i-1 st scanning comprises:

if it is determined that the value of the unmodified round of the target memory page is equal to the second value, it is determined that the target memory page at the ith scanning time is different from the target memory page at the i-1 th scanning time.

7. The method according to claim 5 or 6, wherein the determining that the target memory page at the ith scanning time is the same as the target memory page content at the i-1 st scanning time, and that the target memory page at the i-1 st scanning time is different from the target memory page content at the i-2 nd scanning time includes:

if it is determined that the value of the unmodified round of the target memory page is equal to the third value, it is determined that the content of the target memory page during the ith scanning is the same as the content of the target memory page during the i-1 st scanning, and the content of the target memory page during the i-1 st scanning is different from the content of the target memory page during the i-2 nd scanning.

8. The method according to any one of claims 5 to 7, wherein the determining that the target memory page content at the ith scanning is the same as the target memory page content at the i-1 st scanning, and that the target memory page content at the i-1 st scanning is the same as the target memory page content at the i-2 nd scanning comprises:

if it is determined that the value of the unmodified round of the target memory page is greater than the third value, it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning.

9. The method according to any of the claims 1 to 8, wherein the merging the target memory page at the ith scanning and the memory page having the same content as the target memory page at the ith scanning comprises:

if it is determined that the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to the same process, and the target memory page during the ith scanning and the first memory page in the queue to be merged are located within a preset address range, adding the target memory page during the ith scanning into the queue to be merged until a new queue to be merged is constructed, and merging each memory page in the queue to be merged and the memory page with the same content as the memory page;

if it is determined that the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to different processes, or the target memory page during the ith scanning and the first memory page are not located within a preset address range, merging each memory page in the queue to be merged and the memory page having the same content as the memory page, and constructing a new queue to be merged by using the target memory page during the ith scanning as the first memory page.

10. A memory page processing apparatus, the apparatus comprising:

the scanning module is used for scanning the target memory page for the ith time;

the first processing module is configured to, if it is determined that a target memory page during an ith scanning is different from a target memory page during an i-1 th scanning, increase a value of a counter corresponding to the target memory page during the ith scanning by a first value;

a second processing module, configured to detect a size of a value of a counter corresponding to a target memory page during an ith scanning if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning and the target memory page during the i-1 st scanning is different from the target memory page during the i-2 nd scanning;

a third processing module, configured to, if it is determined that a value of a counter corresponding to the target memory page during the ith scanning is greater than the first value, merge the target memory page during the ith scanning and the remaining memory pages having the same content as the target memory page during the ith scanning;

11. The apparatus of claim 10, further comprising:

a fourth processing module, configured to end processing of the target memory page during the ith scanning if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is equal to the first value.

12. The apparatus of claim 10 or 11, further comprising:

a fifth processing module, configured to, if it is determined that the target memory page during the ith scanning is the same as the target memory page during the i-1 st scanning, and the target memory page during the i-1 st scanning is the same as the target memory page during the i-2 nd scanning, end the processing of the target memory page during the ith scanning.

13. The apparatus of claim 12, further comprising:

a detection module, configured to detect, based on a checksum of a target memory page during an ith scanning and a checksum of a target memory page during an i-1 th scanning, whether a target memory page during the ith scanning is the same as a target memory page during the i-1 th scanning, and whether a target memory page during the i-1 th scanning is the same as a target memory page during the i-2 th scanning;

the checksum of the target memory page during the ith scanning is generated based on the target memory page during the ith scanning, and the checksum of the target memory page during the i-1 st scanning is generated based on the target memory page during the i-1 st scanning.

14. The apparatus according to claim 13, wherein the detection module is specifically configured to:

if it is determined that the checksum of the target memory page during the ith scanning is the same as the checksum of the target memory page during the (i-1) th scanning, increasing a third value to the value of the unmodified round of the target memory page;

15. The apparatus according to claim 14, wherein the first processing module is specifically configured to, if it is determined that the value of the unmodified round of the target memory page is equal to the second value, determine that the target memory page in the ith scanning is different from the target memory page in the i-1 th scanning, and increase a value of a counter corresponding to the target memory page in the ith scanning by a first value.

16. The apparatus according to claim 14 or 15, wherein the second processing module is specifically configured to, if it is determined that the value of the unmodified round of the target memory page is equal to the third value, determine that the content of the target memory page in the ith scanning is the same as the content of the target memory page in the i-1 th scanning, and the content of the target memory page in the i-1 th scanning is different from the content of the target memory page in the i-2 th scanning, and detect a value size of a counter corresponding to the target memory page in the ith scanning.

17. The apparatus according to any one of claims 14 to 16, wherein the fifth processing module is specifically configured to, if it is determined that the value of the unmodified round of the target memory page is greater than the third value, determine that the target memory page in the ith scanning is the same as the target memory page in the i-1 th scanning, and the target memory page in the i-1 th scanning is the same as the target memory page in the i-2 th scanning, and end the processing of the target memory page in the ith scanning.

18. The apparatus according to any one of claims 10 to 17, wherein the third processing module is specifically configured to:

if it is determined that the value of the counter corresponding to the target memory page during the ith scanning is greater than the first value, detecting whether the target memory page during the ith scanning and the first memory page in the queue to be merged correspond to the same process, and whether the target memory page during the ith scanning and the first memory page in the queue to be merged are located within a preset address range;

if it is determined that the target memory page during the ith scanning corresponds to a different process from the first memory page in the queue to be merged, or the target memory page during the ith scanning and the first memory page are not located within a preset address range, merging each memory page in the queue to be merged and a memory page having the same content as the memory page, and constructing a new queue to be merged by using the target memory page during the ith scanning as the first memory page.

19. An electronic device comprising a memory and a processor; the memory stores code, the processor is configured to execute the code, and when executed, the electronic device performs the method of any of claims 1 to 9.

20. A computer readable storage medium comprising computer readable instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 9.

21. A computer program product comprising computer readable instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 9.