CN115398538A - Current driven magnetic domain wall logic - Google Patents

Abstract

Spin-based logic architectures provide non-volatile data retention, near-zero leakage, and scalability, extending the technical roadmap beyond Complementary Metal Oxide Semiconductor (CMOS) logic. Magnetic domain wall based architectures utilize fast domain wall motion, high density, non-volatility, and flexible designs to process and store information. However, this approach relies on domain wall manipulation and clocking using external magnetic fields, which limits their implementation in dense large-scale chips. The invention discloses the concept of performing all-electrical logic operations and cascading in domain wall racetracks. The present invention utilizes chiral coupling between adjacent magnetic domains caused by interface Dzyaloshinskii-Moriya interactions to implement a domain wall inverter, a fundamental building block in all implementations of boolean logic. Reconfigurable NAND and NOR logic gates are also disclosed and operate by current-induced domain wall motion. Finally, several NAND gates are cascaded to build XOR gates and full adder gates to demonstrate the electrical control of magnetic data and device interconnections in logic circuits. The invention provides a feasible platform for the extensible full-electromagnetic logic and paves the way for the application of the logic memory.

Description

Current driven domain wall logic

The present invention relates to a device for storing and/or processing data. Furthermore, the invention relates to a logic gate comprising a plurality of the above-mentioned devices.

Zhaochu Luo et al in Chirally coupled nano magnets, science 363, pages 1435 to 1439 (2019) disclose magnetically coupled nanomagnets with a variety of applications in non-volatile memories, logic gates and sensors. Strong coupling of laterally adjacent nanomagnets can be achieved using interfacial Dzyaloshinskii-Moriya interactions. This coupling is mediated by chiral domain walls between out-of-plane and in-plane magnetic regions and dominates the behavior of nanomagnets below the critical dimension. The concept is used to achieve lateral exchange biasing, field-free current-induced switching between multi-state magnetic configurations, and synthetic antiferromagnets, skynes, and artificial spin ice covering a wide range of length scales and topologies. This document provides a platform for designing relevant nanomagnet arrays and enabling full electrical control of planar logic gates and memory devices.

In general, spin-based logic architectures provide non-volatile data retention, near-zero leakage, and scalability, extending the technical roadmap beyond Complementary Metal Oxide Semiconductor (CMOS) logic. Magnetic domain wall based architectures utilize fast domain wall motion, high density, non-volatility, and flexible designs to process and store information. However, this approach relies on domain wall manipulation and clocking (clocking) using external magnetic fields, which limits their implementation in dense, large-scale chips.

It is therefore an object of the present invention to provide a device for storing and/or processing data that provides a feasible platform for scalable all-electromagnetic logic, paving the way for the application of logical-in-logic.

According to the present invention, this object is achieved by an apparatus for storing and/or processing data using the concept of magnetic domain wall motion induced by spin-orbit torques, said apparatus comprising:

a) A support layer made of a conductive material;

b) A ferromagnetic or ferrimagnetic layer disposed on the support layer, the ferromagnetic or ferrimagnetic layer capable of exhibiting tunable magnetic anisotropy and providing a magnetic racetrack;

c) A functional layer in tunable magnetic anisotropy disposed on the ferromagnetic or ferrimagnetic layer, the functional layer having a first functional portion and a second functional portion and a third functional portion between the first functional portion and the second functional portion, wherein the first portion and the second portion of the functional layer enable the ferromagnetic or ferrimagnetic layer to have an OOP (out-of-plane) magnetization perpendicular to a plane of the layer and the third portion of the functional layer enables the ferromagnetic or ferrimagnetic layer to have an IP (in-plane) magnetization parallel only to the plane of the layer; wherein:

d) An OOP magnetization oriented vertically and upward represents a logical "0" and a downward oriented represents a logical "1", or vice versa, or an IP magnetization in one direction represents a logical "0" and in the other direction represents a logical "1", or vice versa;

e) Said logical "1" or logical "0" can be encoded in the second region of the ferromagnetic or ferrimagnetic layer covered by the second portion, or in the third region of the ferromagnetic or ferrimagnetic layer covered by the third portion, and/or vice versa, in response to moving the domain walls in the first region of the ferromagnetic or ferrimagnetic layer covered by the first portion along the magnetic Racetrack (RT) towards the interface given at the transition of the first portion to the third portion; and

f) A supply of current to the support layer, wherein a controlled current pulse applied to the support layer causes the domain walls to deterministically move along the magnetic racetrack.

The invention thus discloses the concept of performing all-electrical logic operations and cascading in a magnetic domain wall racetrack. The invention utilizes chiral coupling between adjacent magnetic domains caused by interface Dzyaloshinskii-Moriya interactions to implement domain wall inverters, the basic building blocks in all implementations of boolean logic.

When the function of at least one of the first, second and third portions of the functional layer is realized by at least one of the following, preferred embodiments of the present invention may be realized with respect to the realization of a tunable magnetic anisotropy in a ferromagnetic or ferrimagnetic layer:

a) The functional layers of the first and second portions are metal oxide layers and the third portion is a metal layer; b) The third part is an insulating layer comprising an electrode enabling application of an electric field in the OOP direction on the ferromagnetic or ferrimagnetic layer;

c) The third part of the functional layer is a metal oxide layer which is penetrated by the solid-state proton pump and/or the ionizing radiation; and/or

d) The third part of the functional layer is a metal oxide layer which is penetrated by a focused ion beam of helium and/or gallium.

In a further preferred embodiment of the invention, the width of the first functional part and of the ferromagnetic or ferrimagnetic layer and of the support layer, both below the first functional part, as seen in a direction perpendicular to the direction of the magnetic racetrack, is greater than the width of the second functional part and of the ferromagnetic or ferrimagnetic layer and of the support layer, both below the second functional part, or vice versa. This asymmetry in racetrack shape on both sides of the third portion (the interface portion between the first and second portions) also results in a smaller cross-section than the cross-section of the racetrack shapeThe asymmetry in the small to large width direction that suppresses the likelihood of domain nucleation compared to the opposite direction. Therefore, it is difficult to nucleate (nucleate) a reverse domain (reverse domain) on the side of the IP region having a large width. When DWs reach the V-shaped IP region from a smaller side, they are pinned and cannot pass through the inverter. In contrast, since the nucleation center on the inside of the vertex of the "V" is not affected, DWs incident from a wider side may be transmitted toward a side having a smaller width. To is directed at

And

both DWs observed this behavior. Therefore, nucleation of the inverted domains (nucleation) is highly asymmetric for positive and negative currents, but independent of the DW polarity.

Preferably, in this example, the course (course) of the width seen along the magnetic track (RT) may have the shape of a step function. Thus, the width w of the side having the larger width ₁ Is larger than the width w of the other side of the IP part (third part) ₂ 。

Further preferred embodiments of the device are defined by the further dependent claims.

The object relating to the realization of a logic gate is achieved according to the invention by a logic gate comprising a plurality of devices according to any one of the preceding claims, wherein the two magnetic runways representing the logic inputs of the logic gate are arranged substantially radially, preferably in a V-shape or Y-shape, to share a common second region of the ferromagnetic or ferrimagnetic layer, which second region thereby represents the logic outputs of the logic gate, and to share a second functional part of the functional layer, wherein the first regions of the two magnetic runways are separated by a magnetic bias region of determinable magnetization, and wherein the third region of the functional layer is arranged in the form of a ring segment shape aligned with the radial arrangement (preferably the V-shape or Y-shape arrangement) of the two magnetic runways.

Thus, reconfigurable NAND and NOR logic gates are also disclosed and operate by current-induced domain wall motion. Thus, several NAND gates may be cascaded to construct XOR gates and full adder gates to demonstrate the electrical control of magnetic data and device interconnections in logic circuits. The invention provides a feasible platform for the extensible full-electromagnetic logic and paves the way for the application of the logic memory.

Preferred embodiments of the logic gate are given by the other dependent claims.

In the following, preferred embodiments of the invention will be described in more detail with reference to the accompanying drawings, which are depicted in the following figures:

FIG. 1 chiral coupling and current driven DW inversion between adjacent nanomagnets;

FIG. 2 schematically illustrates a current-driven DW inverter;

FIG. 3 schematically illustrates a reconfigurable NAND/NOR logic gate;

FIG. 4 schematically illustrates the electrical control of the DW logic circuit in cascade and data flow;

FIG. 5 schematically illustrates a simple model of DW inversion for current drive in an OOP-IP-OOP structure;

FIG. 6 micromagnetic simulation of DW inversion with a straight IP region;

FIG. 7 DMI-OOP anisotropy phase diagram for current-driven DW inversion in narrow lines (narrow windows);

FIG. 8 time series MOKE images of (a) NAND gates and (b) NOR gates for operational reliability measurements;

FIG. 9 schematically illustrates a proposal for a MTJ/racetrack hybrid structure;

FIG. 10 various cascaded DW logic circuits;

FIG. 11 schematically illustrates an example of a magnetic DW logic element;

FIG. 12 DW velocities in uniform OOP regions of the racetrack and effective DW velocities in NOT gates according to current density;

figure 13 time series MOKE images and corresponding schematic of NAND gates during operation;

FIG. 14 schematically illustrates the concept of propagation delay time for DW logic;

FIG. 15 Hall (Hall) measurements of logic operations in NAND gates;

FIG. 16 schematically illustrates an apparatus configuration and magnetic characterization;

FIG. 17 DW inversion in a DW inverter with a straight IP zone;

FIG. 18 schematically illustrates the non-reciprocal operation of an asymmetric DW inverter;

FIG. 19 micromagnetic simulation of current driven DW inversion in both symmetric and asymmetric DW inverters; and

figure 20 schematically shows a properly operating DW diode obtained by cascading an asymmetric DW inverter and a symmetric DW inverter.

The present invention of chiral Domain Wall (DW) logic for storing and/or processing data utilizes a spin-orbit torque (SOT) H _SOT Efficiency and speed of induced magnetic DW motion, and the use of chiral coupling between adjacent magnets with competing magnetic anisotropy and interfacial dzyaloshinski-Moriya interaction (DMI) (fig. 1 a). Based on this coupling, the DW can be reversed using current, i.e., up/down

DW conversion to down/up

DW or vice versa. Here in the runway

And the magnetization directions of & ' represent Boolean logic ' 1 ' and ' 0 ', respectively.

In fig. 1b, a DW inverter design is shown that includes in-plane (IP) magnetized regions embedded in a racetrack with out-of-plane (OOP) magnetization. Since the two OOP zones on either side of the IP zone are coupled by the DMI, the reversal of one OOP zone causes the reversal of the other OOP zone, resulting in the reversal of DWs traveling along the racetrack that behave as NOT gates.

Fig. 1c schematically shows a cross-sectional view of the device 2 as described for fig. 1a and 1 b. The device 2 comprises a support layer 4 made of an electrically conductive material such as Pt. A ferromagnetic or ferrimagnetic layer 6 (Co-layer) disposed on the support layer 4 is capable of exhibiting magnetic spin anisotropy and providing a magnetic racetrack RT. Furthermore, a functional layer 8 is provided on the ferromagnetic or ferrimagnetic layer 6, which functional layer 8 in this example has a first metal oxide part 10 and a second metal oxide part 12 and a metal part 14 between the first metal oxide part 10 and the second metal oxide part 12, wherein the material of the functional layer is such that in its metal oxide form the ferromagnetic or ferrimagnetic layer 6 can have an OOP magnetization perpendicular to the plane of the layers 4,6,8 (OOP = out-of-plane) and that in its metal form the ferromagnetic or ferrimagnetic layer 6 can have an IP magnetization parallel only to the plane of the layers (IP = in-plane).

Thus, a vertically and upwardly oriented OOP magnetization may represent a logical "0" while a downwardly oriented OOP magnetization may represent a logical "1", or vice versa. The boolean logic "1" or logic "0" can be encoded in the second region 16 of the ferromagnetic or ferrimagnetic layer 6 covered by the second metal oxide portion 12 in response to moving the domain wall DW in the first region 18 of the ferromagnetic or ferrimagnetic layer 6 covered by the first metal oxide portion 10 along the magnetic racetrack RT towards the interface 20 given at the transition of the first metal oxide portion 10 to the metal portion 14 of the functional layer 8. The current source 22, which provides a current density j to the support layer 4, can deterministically move the magnetic domain wall DW back and forth along the magnetic racetrack RT using a controlled current pulse applied to the support layer 4.

In this embodiment, the magnetic spin anisotropy is achieved by a metal oxide layer and a metal layer overlying a ferromagnetic or ferrimagnetic layer. Of course, there are other possibilities to control the magnetic spin anisotropy, such as:

a) According to Aik Jun Tan et al ion control anisotropy, "magnetic-ionic control of magnetic using a solid-state prop pump", nature Materials, vol.18, 1 month 2019, pages 35 to 41 and Fanny Ummelen et al, "centrifugal substrate on-plane-controlled domain-wall ping", scientific reports, 7;

b) Electrical control of ferromagnetic phase transitions in cobalt temperature according to d.chiba et al, "Electrical control of the ferromagnetic phase transitions in cobalt temperature", nature Materials, volume 10, year 2011, month 11, pages 853 to 856, and according to t.maruyama et al "Large volume-induced magnetic resonance in a magnetic layers of iron", nature Nanotechnology, volume 4, pages 158 to 161 (2009);

c) Franken et al, "precision control of domain wall injection and pinning using helium and gallium focused on beams", j.appl.phys.109, 07D504 (2011).

To illustrate the operation of the DW inverter, a set of Pt/Co/AlO with 50nm wide V-shaped IP regions was fabricated as shown in FIG. 2 _x Patterned using a selective oxidation process (fig. 2 a). In the OOP magnetic nanowires, pt represents a support layer, co represents a ferromagnetic layer/magnetic racetrack, and AlO _x Indicating functional layer (AlO) _x = metal oxide form).

The DW motion is driven by a current (fig. 2 b) and tracked using a polar-magneto-optical Kerr effect (MOKE) microscope. Initial lower-right-upper magnetization configuration from OOP-IP-OOP structure

Beginning with implantation from the left OOP region

DW (FIG. 2 c).

By applying a sequence of current pulses, the current is,

the DW moves in the direction of the current flow towards the IP region (the region covered by the metal portion of the functional layer), as expected for left-hand chiral neldw. When the temperature is higher than the set temperature

When a DW encounters an IP region, the IP magnetization switches from → to ← with the extinction of the DW on the left side of the IP region and the nucleation of a new DW with opposite polarity on the right side of the IP region. An understanding of the microscopic mechanism of DW inversion is provided by a combination of scanning transmission x-ray microscopy (STXM) and micromagnetic simulation (fig. 2 d). When incident

As the DW approaches the IP region, it is forced toward the IP region by the spin orbit torque SOT, which in turn increases the magnetostatic and exchange energies.

The resulting compact high energy spin structure can only be expanded by extinguishing the incident DW by means of SOT and switching the IP magnetization. When the IP magnetization is switched from → to ← due to chiral coupling,

the domains nucleate on the right side of the IP region. This process is facilitated at the tip of the V-shaped inverter due to the additional contribution from the chiral coupling on both sides of the V-shaped region. Thus, the optimized design of the narrow V-shaped IP region (V-shaped metal region 14) facilitates the switching of the IP magnetization and the nucleation of new domains. As a result of which,

DWs are efficiently transported through the IP region and converted into

DW。

For incident

The DW undergoes a similar inversion process such that the inverter effectively inverts the magnetization of the domains traveling across the IP region, as shown in fig. 2 e. Not only a single DW may be inverted using current, but the sequence of DWs and thus the sequence of magnetic domains propagating along the magnetic racetrack RT may be inverted. This is a unique feature of chirally coupled nanomagnetic structures.

On the basis of the principle for constructing NOT gates, it is explained how reconfigurable NAND/NOR gates are implemented. This gate makes the concept of current driven DW logic functionally complete, as any boolean function can be implemented using a combination of NAND gates or NOR gates. The core structure of the gate (fig. 3 a) consists of four OOP regions in a ferromagnetic layer, which form two logic inputs (input a, input b), one Bias (Bias) and one logic Output (Output), which are connected via an IP region (region of the ferromagnetic or ferrimagnetic layer covered by the metal portion 14 of the functional layer 8). With reference to the notation used with respect to fig. 1c, a logic gate (NAND or NOR) comprises two magnetic runways RT representing the logic inputs of the logic gate. The magnetic runways RT are oriented substantially radially, preferably V-shaped or Y-shaped, so as to share a common second area 16 of the ferromagnetic or ferrimagnetic layer 6, said second area 16 thereby representing the logical output of the logic gate. In this region they also share the second metal oxide portion 12 of the functional layer 8 and the corresponding portion of the support layer 4, wherein the first regions 18 of the two magnetic racetracks RT are separated by a magnetic bias region of determinable OOP magnetization. Of course, the magnetic bias region may also be designed as a magnetic racetrack RT, allowing the OOP orientation of the magnetization to be switched up or down in the bias region. The metallic areas 14 of the functional layer 8 are arranged accordingly in the form of annular segment shapes (a ring segment shaped form) aligned with the radial arrangement (preferably V-or Y-shaped arrangement) of the two magnetic tracks (RT).

To illustrate the function of the NAND gate, four devices with the same core structure and different logic input configurations were fabricated. For each device, two DW reservoirs are connected to the input through a magnetic racetrack RT. The four logic input configurations "11", "10", "01" and "00" are implemented by placing inverters after some DW storage. Both DW reservoirs and the bias are set to logic "0" by applying an OOP magnetic field of 1 kOe. The application of a pulse of electric current,

("l") magnetic domains are propagated from the DW storage with (no) inverters, defining the logic input as "1" ("0"). The output magnetization being dependent on input and bias as a result of chiral couplingRelative alignment (fig. 3b and 3 c), which is similar to a majority gate (majority gate). Therefore, for an | bias, only if both input magnetizations are

While the output magnetization switches to &. Otherwise, the output magnetization is

As shown in the Magnetic Force Microscope (MFM) image (FIG. 3 d), the magnetization direction of the logic output is "" 0 "for logic input" 11", and" "10", "01", and "00" for logic inputs

("1"). This relationship between logic inputs and outputs corresponds to the logic operation required for the NAND gate (fig. 3 c). By changing the direction of the bias

As shown in fig. 3e, the NAND gate may be reconfigured as a NOR gate. In the latter case, only when both input magnetizations are-

Thus, the current logic gate can be reconfigured between NAND and NOR by switching the bias terminals, allowing for fast logic reconfiguration during runtime.

DW motion using current drive provides a series of different logic inputs to the same gate over time to demonstrate the operation of a single NAND gate (figure 3 f). In this apparatus, three DW inverters are placed in the left lane, and two DW inverters are placed in the right lane. This means that the sequence of current pulses will generate a sequence of logical inputs from "00" to "11" to "01" to "11" to "10". The corresponding logic outputs will vary over time from "1" to "0" to "1", respectively. For each operation, DWs giving these two inputs may not arrive at the gate at the same time. This is mitigated by introducing sufficient propagation delay time (see method). In a practical device this can be achieved by clocking the current. In addition, magnetic Tunnel Junctions (MTJs) fabricated on the magnetic racetrack may be used to control the logic input and bias terminals, which may also be used for electrical sensing of the output (see methods).

In addition to forming a complete logic set, the chiral DW racetrack meets three additional requirements for practical implementation in logic circuits, namely input selectivity, data interleaving, and cascading of different logic gates. The logic inputs can be electrically selected by the propagation of the current driven DW through the Y-shaped structure in FIG. 4 a. The simple crossover structure enables DWs to propagate in orthogonal runways (fig. 4 b), which simplifies the design of the crossover, avoiding the complexity of the metal bridges used in conventional charge-based circuits.

Furthermore, since the current logic inputs and outputs are based on the same physical phenomena, several logic gates can be cascaded directly without the need for additional converters between magnetic and electrical signals. As an example, a binary half adder created by cascading four NAND gates to form an XOR gate is shown in fig. 4c, and a full adder operation by cascading 15NAND gates is also shown in fig. 4 d. The circuit also illustrates the possibility of fanout of a single output that can be used to drive the input of the next logic gate.

It is even possible to create a magnetic logic circuit with a feedback loop. This is achieved by using external circuitry to read the output and write it back to the input using the MTJ, or by using an additional racetrack with reversed current direction to drive the DW from the output back to the input.

Scalability and efficiency of magnetic DW logic circuits can also be addressed for device applications. Since the chiral coupling caused by DMI is effective in the dimension of the magnetic moment, the size of the logic gate can be reduced to several nm using advanced photolithography techniques. The speed of the logic operation is related to the DW speed, which can reach several hundred m/s for chiral DWs driven by SOT. The operation time can be estimated from the time required for DW cross-gate propagation for scaling down to 10 × 10nm ² The reverse-rotating device of (1) is provided with a reversing valve,this time can be as fast as tens of ps (see method). At 0.8X 1nm ² The energy consumption of a single NOT operation in the runway is about 20pJ, which is at 10 × 10nm ² The footprint structure will be scaled down below 20aJ (see methods).

The non-volatility of the magnetic inputs and outputs further saves energy because the magnetic DW logic circuit does not consume power when idle and does not need to reload data after power is off. These features make full electromagnetic DW logic attractive for use in low-power, "instant-on" microelectronic processors prevalent in modern electronic devices.

The drawings are further described below:

figure 1 shows chiral coupling between adjacent nanomagnets and current-driven DW inversion. Fig. 1a schematically shows the magnetic chiral coupling caused by DMI. After selective oxidation, the magnetization of adjacent OOP (oxidized, shaded dark grey) and IP (unoxidized, shaded light grey) regions is correlated with Pt/Co/AlO _x Is in chiral alignment. FIG. 1b schematically shows current-driven DW inversion, which occurs as the DW propagates across the IP region. The white shaded area is the DW, and the direction of the effective field HSOT and the DW velocity VDW caused by SOT are indicated by arrows. In Pt/Co/AlO _x In the step (1), the first step,

and

both DWs move in the same direction as current J.

Fig. 2 shows a current-driven DW inverter. Figure 2a schematically depicts a NOT gate and a current-driven DW inverter. Dark and light gray shaded regions indicate regions with OOP and IP anisotropy, respectively. FIG. 2b shows SEM images of seven parallel DW inverters in a 3D perspective view of a DW measurement setup. The direction of the current pulse is indicated. FIG. 2c shows a device having

Configured for leftDW-inverted MOKE image sequences for edge-incident DWs. The edges of the magnetic racetrack are indicated by dark grey dashed lines and the position of the inverter is indicated by white lines. Light and dark contrast in the racetrack in the MOKE image correspond to [ ] and [ ] respectively

And (5) magnetizing.

FIG. 2d shows measured by STXM for a mobile station having

DW inverted XMCD image sequences of configured incident DWs. Each image is captured after one current pulse is applied. Light and dark contrast in XMCD images correspond to [ ] and [ ] respectively

And (6) magnetizing. Micromagnetic simulations of the inversion process are shown on the right side of each image, with the magnetization directions indicated by the color circles.

FIG. 2e depicts a MOKE image showing driving across the IP region using current pulses

Inversion of the domains. The current density and duration of the applied pulses in fig. 2c and 2e is 7.5 × 10 ¹¹ A/m ² And 50ns, while for FIG. 2d they are 1.1X 10 ¹² A/m ² And 1ns. The scale bar is 3 μm in the MOKE image and 500nm for the XMCD and the simulated image.

Fig. 3 schematically shows a reconfigurable NAND/NOR logic gate. FIG. 3a shows a color SEM image of a reconfigurable NAND/NOR logic gate and the corresponding logic circuit symbol. The different shades of gray represent the regions and Pt bars in the logic gates with OOP and IP magnetic anisotropy, respectively. FIG. 3b shows a schematic diagram for the relationship between magnetization, bias and logic output in two logic inputs of a NAND gate. Fig. 3c is a truth table for reconfigurable NAND and NOR logic operation. FIGS. 3d and 3e show the negations for inputs of "11", "10", "01" and "00" with offsets "0" (d) and "1" (e)MFM images that operate logically together, and their corresponding logical circuit symbols. The DW storage (circular disk at the top of each image) and bias are set to logic "0" by applying an OOP field of 1 kOe. Figure 3f shows a sequence of MOKE images and a corresponding schematic diagram showing the operation of a single NAND gate with a sequence of logic inputs driven by current. An OOP magnetic field of 1kOe was applied to set the initial magnetization to [ - ] U. Light gray and dark gray in the diagram correspond to &, respectively

And (6) magnetizing. The boundaries of the logic gates are indicated by dashed lines and the positions of the inverters are indicated by white lines. Indicating the direction and number of current pulses (current density 7.5 × 10) applied before each MOKE image ¹¹ A/m ² And pulse length 30 ns). Light and dark contrasts in the device areas in the MFM and MOKE images correspond to &, respectively

And (5) magnetizing. All scales were 1 μm.

Figure 4 schematically shows the data flow and electrical control of cascaded DW logic circuits. Fig. 4a shows the exchange of data streams through a wye structure. Left side: a color SEM image of the device and corresponding logic circuit symbols. Right side: MFM images of the magnetic configuration when current flows through the upper track (top) and the lower track (bottom). Fig. 4b shows a sequence of MOKE images showing the electrical control of the data flow through the crossbar. Indicating the direction and number of current pulses (current density 9X 10) ¹¹ A/m ² And pulse length 30 ns). At the top, SEM images of the cross-over structures and corresponding logic circuit symbols are shown. Figure 4c schematically shows an XOR gate manufactured by cascading four NAND gates. Left side: SEM image of XOR logic gate and corresponding logic circuit symbol. Right side: MEM image of XOR logic gates with different logic inputs "11", "10", "01" and "00". The DW reservoir and bias are set to a logic "0" by applying an OOP magnetic field of 1 kOe. The different shades of grey in the SEM image represent the areas with OOP and IP magnetization and the Pt bars, respectively. FIG. 4 d) schematically showsA full adder gate. Top: a logic circuit symbol with a full adder having input operands of "a =0", "b =1", and a carry bit of "cin = 1". Bottom: MFM image of full adder magnetic circuit. Light and dark contrast in the device area in MOKE and MFM images correspond to [ ] and [ ] respectively

And (6) magnetizing. All scales were 1 μm.

Method

A. Device manufacturing

Using dc magnetron sputtering at base pressure<2×10 ^-8 200nm thick SiN for magnetic film deposition on silicon substrate at Ar deposition pressure of 3 mTorr _x On the layer and patterned by electron beam lithography. A continuous film of Pt (5 nm)/Co (1.6 nm)/Al (2 nm) was striped through a negative resist (ma-N2401) mask using Ar ion milling. In these strips, the upper Co/Al bilayer was milled through a high resolution positive resist (PMMA) mask to create DW racetracks and logic devices. To define the IP region in these magnetic structures, a second PMMA mask was patterned over the Al layer by e-beam lithography. Using a low power (30W) oxygen plasma at an oxygen pressure of 10 mtorr, the unprotected Al layers ( regions 10 and 12 in fig. 1 c) were oxidized to induce perpendicular magnetic anisotropy in the Co layer. Finally, a Cr (5 nm)/Au (50 nm) electrode was fabricated using an electron beam lithography technique combining electron beam evaporation with lift-off processing. The main steps of the device fabrication are shown in fig. 16 a.

The different anisotropy of the OOP region (exposed to oxygen plasma) and the IP region (protected with PMMA mask) was confirmed using polar MOKE measurements (fig. 16 b). The effective OOP magnetic anisotropy field was 3.94kOe, which was obtained from an anomalous hall effect measurement with an IP magnetic field applied (fig. 16 c). By measuring the chiral coupling induced by DMI, the interfacial DMI constant D was estimated to be-0.9. + -. 0.1mJ/m ² 。

B. Electrical measurement arrangement

The magnetic DW motion and logic operation is driven by current pulses generated by the HP Agilent 8114A high voltage pulse generator and the AVTECH super speed pulse generator. The pulse generator may provide pulses of variable voltage and pulse width. The current density is calculated by dividing the nominal voltage by the device resistance and cross-sectional area and is indicated for each operation. The direction of the current pulse is depicted for each device and summarized in fig. 11.

MFM measurement

MFM measurements were made using a CoCr coated tip using a Bruker Dimension Icon scanning workstation mounted on a vibration and sound isolation stage. To minimize the effect of stray fields from the MFM tip during measurement, a thin PMMA layer (-20 nm) was spin coated on the sample to increase the distance between the tip and the magnetic film.

MOKE microscope measurements

MOKE images were recorded using a custom wide field MOKE microscope. The background image was captured after applying a large positive OOP magnetic field of 1 kOe. The background image is subtracted from the subsequent image to obtain a difference image with magnetic contrast. To prepare for the initial state of the DW shown in FIG. 2c, the racetrack is first saturated using the OOP magnetic field. The magnetic field is removed, leaving the OOP of racetrack magnetization with small inversion regions in the V-shaped IP region created by chiral coupling. Then, a current pulse is applied in the opposite direction to that shown in FIG. 2b, so that a single DW is generated on the left side of the DW inverter (FIG. 2 c).

STXM measurements

The magnetic configuration of the DW inverter was imaged using a scanning transmission x-ray microscope at the PolLux Beam line of the Swiss light source of the Paul Scherrer institute (5232 Villigen PSI, switzerland). Using x-ray magnetic circular dichroism (XMCD) for normal incidence on Co L ₃ The absorption edge detects the magnetization state. Apparatus using STXM measurements in x-ray transparent SiN _x And (3) manufacturing on the film.

F. Micromagnetic simulation

To understand the mechanism of DW inversion, a compute box containing 2048 × 1024 × 1 units is used, and MuMax is used ³ Code, 2X 1.6nm using the following magnetic parameters ³ Carrying out micromagnetic simulation by discretization: saturation magnetization M _S =0.9MA/m, effective OOP anisotropy field H _eff =150mT, exchange constant a =16pJ/m, spin hall angle Pt θ _sh =0.1, and an interfacial DMI constant D = -1.5mJ/m ² 。

G. Mechanism for DW inversion

To elucidate the basic mechanism of DW inversion in an OOP-IP-OOP structure, a simple model is considered. The DW inversion process can be explained in terms of the effective DMI field generated in the non-collinear magnet, where the DMI vector lies in the plane of the magnetic thin film. The effective DMI field is given by:

can then consider

The case where the DW is driven by the SOT toward the IP magnetization region (see FIG. 5 a). At equilibrium, IP domains form with the surrounding domains

Configuration by G _DMI The DMI field indicated by (IP) (pointing in + x) stabilizes. When a current is applied, the magnetization is subjected to an effective field H caused by the SOT _SOT Is given by:

wherein the content of the first and second substances,

θ _SH 、J、e、M _s t, m and σ are planck constant, spin hall angle, current density, electron charge, saturation magnetization, magnetic layer thickness, magnetization direction and spin polarization direction at the Pt/Co interface. Due to chiral coupling, in

The magnetization in the middle of the DW points along-x.

As shown in FIG. 5b, H _SOT (DW) edge+ z is directed such that

The DW will propagate in the direction of the current. Once the device is in use

The DW approaches the IP region where the magnetization experiences a dipole field H _dip (IP) of the dipole field

The IP magnetization of the DW pointing along-x is generated. The SOT also compresses the incident DW towards the IP region, which in turn increases the DW energy. This results in a compact high energy spin structure containing two closely spaced regions with tail-to-tail IP magnetization, as shown by the associated magnetic charges in fig. 5 b: an IP magnetized area in

In the middle of the DW, the magnetization points in the-x direction, and another IP magnetization region in the inverter, with the magnetization pointing in the + x direction.

At some point in time, the dipole field becomes strong enough to switch the magnetization in the IP region from + x to-x by means of the SOT (fig. 5b and 5 c). At the same time, the high energy spin structure on the left side of the IP region collapses, resulting in the gray color shown in FIG. 5b on the left side of the IP region

The domain is destroyed. After magnetization reversal in the IP region, due to H _DMI (OOP) pointing in the direction-z, reverse

The domains nucleate on the right side of the IP region (shown in grey in fig. 5 c). Magnetized in the presence of

DW middle points along + x and H _SOT (DW) points along-z, so that this new DW is then transported by the current towards + x (FIG. 5 c).

Despite this simplicityThe model of (a) provides an understanding of the DW inversion mechanism, but the detailed magnetization dynamics are more complex. Accordingly, micromagnetic simulation was performed accordingly. Here, the number of the first and second electrodes,

DW current density of 3 × 10 ¹² A/m ² Is driven in a narrow line containing a straight, 30nm wide IP region (fig. 6 a). The OOP anisotropy field is set to H in the OOP region _k =1.5kOe, set to zero in the IP area. All three components of the magnetization are recorded at three different positions along the line: at the center of the IP area, and 30nm from the center on each side (see points in fig. 6 a).

In fig. 6b to 6d, it is shown how the magnetization responds to a close DW. When in use

As the DW approaches the left side of the IP region, the magnetization on the left side of the IP region reverses from-z to + z (see FIG. 6 b). The magnetization in the IP region reverses from + x to-x along the path shown in fig. 6c to reduce the energy associated with the accumulated magnetostatic charge (shown schematically in fig. 6 c). The magnetization on the right side of the IP region is then forced to switch from + z to-z by chiral coupling (see fig. 6 d).

DMI is critical in the implementation of current-driven DW inversion, not only for achieving current-driven DW motion, but also due to its role in nucleation of the inversion domains. The effect of DMI during DW inversion is determined using micromagnetic simulations by varying the DMI values and OOP anisotropy in the IP region. In fig. 7 for a 3 × 10 narrow line containing a straight, 30nm wide IP region ¹² A/m ² Shows the current-driven DW inverted DMI-OOP anisotropy phase diagram. For zero OOP anisotropy in the IP region, when D<-1mJ/m ² When the DW is inverted, the DW may be inverted. If the DMI is reduced, it cannot provide sufficient chiral coupling to nucleate the inversion domains, so that the incident DW cannot be inverted.

By introducing the OOP anisotropy into the IP region expected from the Pt/Co interface, the energy for DW inversion decreases and the DMI operating window increases.

To verify the effect of the IP width on the DW inversion process, additional micromagnetic simulations have been performed on the magnetization dynamics in the inverters for various widths of the IP region. Current density of 3X 10 ¹² A/m ² And D = -1.5mJ/m ² The simulation results of (a) are given in table 1.

Table 1| for J =3 × 10 ¹² A/m ² And D = -1.5mJ/m ² Simulation results of the DW inverter of (1).

Anisotropy K _OOP (IP region) and K _OOP (OOP region) denotes uniaxial OOP anisotropy in the IP region and the OOP region, respectively. The pair (cross) indicates that the inverted DW may (may not) propagate from the IP region to the OOP region.

Here, the alignment indicates that the inverted DW is propagated from the IP region to the OOP region as needed. If the IP region is too narrow (< 25 nm), the OOP regions on either side of the inverter are strongly antiparallel coupled and the SOT induced by the current is not strong enough to overcome the chiral coupling.

If the width of the IP region is too large (> 35 nm), the chiral coupling becomes too weak to give an anti-parallel coupling of the OOP magnetization on the left and right side of the IP magnetization. The DW is then simply extinguished in the IP region without any further magnetization dynamics occurring on the other side of the inverter.

The results of the micromagnetic simulation were confirmed by experiments: for a straight DW inverter in an 800nm wide racetrack, DWs were successfully transmitted across a 50nm wide DW inverter, but not across a 100nm wide inverter. As shown in table 1, by including a small OOP anisotropy in the IP region, the operating window of the IP region may be increased.

Dw inverter's influence of shape of IP region

Here, starting from the measurement of a straight IP inverter, the performance of straight and V-shaped DW inverters was experimentally compared in the case of an IP region width of 50 nm. As shown in the STXM image in fig. 17aWhen is coming into contact with

When a DW encounters an IP region, the DW will die out on the left side of the IP region, and a new DW with the opposite polarity will nucleate on the right side of the IP region. Several inversion operations were performed in the same inverter with straight IP regions and the inverted domains were found to nucleate at different locations (fig. 17 b). This means that nucleation of the reverse magnetic domains is aided by random thermal fluctuations or local inhomogeneities.

To improve the reliability of DW inverters, V-shaped IP regions have been implemented, which have two main advantages: first, the tip of the chevron provides an easy nucleation site for the reverse magnetic domain. This is because, at the tip of the V, the output OOP region is surrounded by the input OOP region and experiences the strongest anti-parallel chiral coupling. In the STXM measurement, five nucleation of reverse domains were found to be located at the tip of the V-shape for five operations. Second, the V-shape of the IP region results in lower magnetostatic energy, thus lowering the energy barrier for DW inversion. As shown in fig. 17c, the effective DW velocity measured in a DW inverter with V-shaped and straight IP regions was measured (see the method outlined in the estimation of the logical operating velocity in the method). The DW travels across the IP region at a higher velocity in a chevron IP inverter than the DW travels across the IP region in a straight IP inverter, and the standard deviation of the velocities in the chevron IP inverter is less than the standard deviation of the velocities in the straight IP inverter. This demonstrates the higher efficiency and reliability of the chevron IP region as a DW inverter.

I. Estimation of logical operating speed

The speed of logical operations in NOT gates has been studied here. First, the DW velocity V in the uniform OOP region of the runway is measured _DM . Then, after N current pulses, from S across NOT gate ₁ To S ₂ Determination of the DW Displacement L _DW (see schematic in FIG. 12). Thus, the time t it takes for DW to propagate across NOT gate _NOT Has been expended so that when the DW is propagated across the NOT gate and inverted, the effective velocity v of the DW _NOT Comprises the following steps:

wherein t is _pulse And L _NOT The length of the current pulse and the length of the NOT gate, respectively. Using this method, we can determine V as a function of current density _DW And V _NOT (FIG. 12). For high current densities, the pulse length was reduced to 2ns to reduce heating, and the data is given in the inset of fig. 12. It has been found that for 1.65X 10 ¹² A/m ² The DW speed in the NOT gate can reach 160 +/-17 m/s. The value of the DW velocity is used to estimate the energy consumption.

Here, use is made of scaling down to 10X 10nm ² The dimensions indicated in fig. 11 of the figure to estimate the time of DW propagation across the DW inverter. With an experimentally determined effective inverter DW velocity of 160m/s, the time that the DW travels across the scaled-down inverter ≈ 60ps. For more accurate estimation, for dimensions of 10 × 10nm ² The scaled-down inverter of (a) performs a micromagnetic simulation. At such small scales, device design is limited by the size of features that can be nano-fabricated. Thus, considering a straight IP region rather than a V-shaped IP region, the width is 10nm. With a simulated effective inverter DW velocity of 118m/s, the time that the DW travels across the inverter is 85ps, similar to the rough estimate described above. Operating speed can be further improved by optimizing materials to increase DW speed, for example by using amorphous magnetic materials (e.g., coFeB instead of Co) and device design.

The speed of logic operation in the NAND gate was estimated from experiments using a similar approach to the DW inverter. To this end, the operation of a NAND gate with two DW inverters in the input memory is captured using MOKE imaging. After applying the current pulse, the DW propagates through the NAND gate and performs a logic operation (see MOKE image and corresponding schematic in FIG. 13). From these images, the current density was 7.5X 10 ¹¹ A/m ² The effective DW velocity is V _NAND In the case of =10.8m/s, the time at which DW is transmitted across the NAND gate is determined as t _NAND ＝74.1ns。

Synchronization and propagation delay times in DW circuits

The DW arrival times at the logic gates may be different due to the presence of defects that cause DW pinning (ping) and the inherently random nature of current driven DW motion. In electronic logic circuits, this is typically addressed by introducing a propagation delay time for each operation, i.e., the circuit cycles at a slower rate than the longest internal propagation delay time. The same concept of propagation delay time can be applied to current magnetic DW logic gates so that a stable output can be obtained independent of the arrival time of the input domain. In other words, with sufficient propagation delay time, all DWs will reach the logic gate, which will result in the correct output for a given logic operation.

To show how the introduction of propagation delay time can improve gate operation reliability, the simplest case of NAND gates has been considered, where the logic inputs change from "00" to "11" over time. As schematically shown in fig. 14a for logical inputs a and b

The DW arrival times are different. In this case, the change of input a from "0" to "1" is slower than that of input b, i.e., t _a ＞t _b Wherein t is _i (i = a, b) is the time of input change.

Once both DWs reach the gate, nucleation of the reverse magnetic domain will take some time, depending on the effective DW velocity in the NAND gate. The time after the correct domain has propagated to the output racetrack is defined as the required propagation delay time t _delay . NAND gates with "11" logic inputs are fabricated with different input racetrack lengths to give different arrival times of the two logic inputs. At the time of the application of the current pulse,

DWs propagate in both the left and right input runways. This is the most critical configuration for testing the propagation delay time reliability of logic gates. As shown in FIG. 14b, all devices give the correct output "0", indicating that the output of the magnetic DW logic gate is independent of the difference in arrival times of the input DW.

For all logical operations in a NAND gate, in general, the operations include (i) DW propagation in the input racetrack, (ii) DW transmission across the logical gates, and (iii) DW propagation in the output racetrack. The total operating time and hence the required propagation delay time can then be expressed as:

wherein L is _input 、L _out And L _NAND The lengths of the input runway, the output runway, and the NAND gate, respectively. v. of _DW And V _NAND DW speed in magnetic racetracks and NAND gates, respectively. The DW velocities in the magnetic racetrack and NAND gate are assumed to have normal distributions:

wherein

And σ _DW (σ _NAND ) Mean and standard deviation (NAND gate) of the velocity profile representing the DW motion in the magnetic racetrack. To obtain a 97.5% probability of success of a logical operation (see fig. 14 c), the required propagation delay time can be estimated as

To demonstrate that sufficient propagation delay time can improve reliability for a statistically significant number of operations in the NAND gate, the output of the NAND gate is placed on a Hall cross (Hall cross) (fig. 15 a) and 1172 measurements are performed. For each measurement, the NAND gates are saturated with OOP magnetic field to set the initial magnetization direction to [ [ lambda ] ] in all the reservoirs and a series of current pulses are applied. The output was measured by the anomalous Hall (Hall) effect when a DC current was applied. The pulsed source and the DC source are separated by a biaser.

As shown by the change in hall resistance in fig. 15b, the output changes from "0" to "1" and back to the state of "0". The electrical measurements are verified using the MOKE measurements performed on the NAND gates (see MOKE image in fig. 15 b). By using 14 current pulses (corresponding to a propagation delay time of 14 × 30 ns), the reliability of the NAND gate increases to >95% (fig. 15 c).

For cascaded logic circuits, the propagation delay time is determined by the longest DW propagation path in the circuit. To reduce the propagation delay time, several possible approaches may be taken, such as scaling of circuit size, increase in DW speed, and reduction in pinning.

K. Logic gate reliability

In order to achieve large scale implementation of logic gates, reliable operation is necessary. Here, the reliability of the two basic NOT gates and NAND gates is evaluated in terms of device-to-device reliability and operational reliability (table 2).

Table 2 includes the reliability of NOT gates and reconfigurable NAND gates.

* Device-to-device reliability is the number of functional devices/total number of devices that give the correct output.

* Operational reliability is the number of successful operations/total number of operations performed for a single device.

To demonstrate the high device-to-device reliability of NOT gates, 35 NOT gates were fabricated, of which 34 NOT gates (97%) were shown to operate successfully. In a single device with 100% operational reliability, also at 4 × 10 ¹¹ A/m ² To 1.65X 10 ¹² A/m ² The NOT operation is performed at various current densities within the range.

To test the device-to-device reliability of the NAND gates, 56 NAND gates with different logic inputs were fabricated and found to have an average success rate of 42/56 (75%). Failure of some devices may be related to pinning of the DWs due to defects in the material or irregular features resulting from nano-fabrication. The width of the magnetic racetrack in the NAND gate is 200nm, while the width of the magnetic racetrack in the NOT gate is 800nm, which means that edge roughness can cause more pinning. The operation is performed 20 times for each of the four selected devices (fig. 8), and they all give the correct output, showing high operational reliability.

The distribution of device-to-device reliability for different logical inputs is also considered. For 56 NAND gates, 14 NAND gates of each type are fabricated with logic inputs "00", "11", "01", and "10". The number of NAND gates giving correct outputs/total number of NAND gates are 13/14, 11/14, 10/14 and 8/14 for logic inputs "00", "11", "01" and "10", respectively. The device-to-device reliability for the "00" and "11" inputs is slightly higher than for the "01" and "10" inputs. This can be understood by considering the energy difference between the "1" and "0" outputs for the "00", "11", "01" and "10" inputs given below:

ΔE _1/0 ⁰⁰ ＝-(2E _input +E _bias )

ΔE _1/0 ¹¹ ＝2E _input -E _bias

ΔE _1/0 ⁰¹ ＝-E _bias

ΔE _1/0 ¹⁰ ＝-E _bias ，(8)

wherein, respectively,. DELTA.E _1/0 ^ij Is the energy difference, E, between the "1" and "0" outputs for an input "ij" ("ij" = "11", "00", "01", or "10") _input Is the coupling strength between output and input, E _bias Is the coupling strength between the output and the bias. From this set of equations, it follows that the stable output for the "11" input is "0" (Δ E) _1/0 > 0) and the stable output for the other inputs of "00", "01", and "10" is "1" (Δ E) _1/0 < 0) which satisfies a truth table of the NAND operation. For the NAND gate used in the experiment, the magnitude of the bias (bias) is a little smaller than the magnitude of the input. Since the coupling energy between two OOP magnetizations separated by an IP region is proportional to the length of their boundaries, the output and input magneticsThe coupling energy between the magnetizations is greater than the coupling energy between the output and bias magnetizations, i.e. E _input ＞E _bias . Thus, | Δ E for NAND operation ⁰⁰ |＞|ΔE ¹¹ |＞|ΔE ⁰¹ |＝|ΔE ¹⁰ L. The trend of the energy difference between correct and incorrect outputs of different logic inputs correlates well with the trend of device-to-device reliability of different logic inputs.

The operational reliability of the cascaded logic circuit (full adder) shown in fig. 4d was also tested. The number of successful operations/total number of operations performed was 28/30.

Therefore, in the present proof-of-concept experiment, the high reliability of the magnetic gate has been demonstrated. It must also be emphasized that there is a great deal of space to improve device-to-device reliability in terms of optimization of manufacturing processes, device design, and material properties.

L. detection of electrical control of logic inputs and logic outputs

For the proof-of-concept experiment shown in FIG. 3f, by placing inverters on the input racetrack, it is ensured that a particular DW reaches the input. After saturation with the OOP magnetic field, the magnetization direction in the racetrack is set to &. Upon application of a current, the magnetization of the propagating DWs is reversed as they propagate across each inverter. By placing different numbers of inverters at different locations in the input runway, a sequence of logical inputs is generated to obtain different inputs at the same gate over time, and in this way demonstrate its real-time operation. It is also shown that electrical switching of the DW propagation in a wye configuration can be used to inject DWs and define specific logic inputs (fig. 4 a).

For scaled down logic circuits, magnetic Tunnel Junctions (MTJs) fabricated on the logic input racetrack will provide a more compact method to control the logic inputs (fig. 9). Indeed, it has been shown that MTJs on the magnetic racetrack can be used to write magnetic domains via Spin Transfer Torque (STT). Therefore, the MTJ fabricated on the magnetic racetrack can be used to control logic inputs. To detect the logical output, MFM, MOKE microscope and hall measurements were used in our proof of concept experiments. For scaled down logic circuits, MTJs fabricated on the output racetrack may be used to electrically detect the logic output.

Furthermore, it is actually possible not only to read the output of a gate, but also to transmit it to the input of another gate using the MTJ device, in order to achieve information feedback. Feedback is critical for sequential logic operations such as those performed in flip-flop gates. Thus, the MTJ/racetrack hybrid structure may also provide a compact method of performing complex logic.

Energy consumption of small logic devices

To estimate the energy consumption of the inverter used in the experiment, a region containing a V-shaped IP region was considered, where the DW was inverted. The energy consumption per operation of the inverter is calculated from the power-delay product in the bottom Pt layer:

wherein J, ρ, W, L, h and V _NOT Current density, resistivity of Pt, inverter width, inverter length, thickness of Pt layer (5 nm) and effective DW velocity in the inverter are expressed respectively. W × L =0.8 × 1.0 μm ² ρ =30.0 μ Ω · cm, pt resistivity in a thin film, and J =1.65 × 10 ¹² A/m ² And V _NOT Experimentally measured current density and effective inverter DW speed of 160m/s, the energy consumption per operation of the inverter was calculated to be 20.4pJ according to equation 9.

For a rough estimate of the energy consumption of a scaled-down inverter, the size of the inverter has been scaled down while keeping the values of Pt layer thickness, pt resistivity, current density, and effective DW velocity across the inverter the same as measured in the experiment. Scaling down to 10X 10nm with the dimensions indicated in FIG. 11 ² The energy consumption per operation of the inverter of (1) is 25.5aJ. For more accurate estimation, 10 × 10nm for lateral dimensions ² The miniaturized inverter of (1) performs a micromagnetic simulation. At such small scales, device design is limited by the size of features that can be nano-fabricated. Thus, consider a straight IP region rather than a V-shaped region, where the width is 10nm. In formula 9, 1.2X 10 ¹² A/m ² And an effective inverter DW speed of 118m/s, the energy consumption per operation was found to be 18.4aJ, similar to the rough estimate above.

The energy consumption of the scaled inverter is comparable to the switching energy of ≈ 30aJ found in advanced CMOS devices. Further improvements in energy consumption can be achieved by optimizing material and device design to reduce the required current density and increase DW speed.

The above estimation only relates to the energy consumed in the logic gates, i.e., the energy consumed by the DW inversion. Additional energy is required to nucleate a DW in the racetrack of logic inputs to detect the logic outputs and move the DW along the interconnect. Therefore, the total energy consumption depends on the detailed design of the logic circuit.

The remaining figures are described in more detail below:

FIG. 5 schematically shows a simple model of DW inversion for current drive in an OOP-IP-OOP structure. Fig. 5a to 5c show side views of DW traveling across the inverter. Magnetization direction and effective field H in racetracks _DMI 、H _SOT And H _dip Is indicated by arrows in the different areas. The magnetic charge associated with the compact high energy spin structure is shown in b.

FIG. 6 shows a micromagnetic simulation of DW inversion with a straight IP region. Fig. 6 shows the device geometry used in the micromagnetic simulation. The position of the three components of the recording magnetization is indicated by dots. Fig. 6b to 6d show the temporal evolution of the magnetization at three points, indicated in fig. 6a, at the left side of the IP region (b), in the middle of the IP region (c) and at the right side of the IP region (d).

FIG. 7 shows that comprises having a 3 × 10 ¹² A/m ² For a direct, 30nm wide IP region of current density, for current-driven DW-inverted DMI-OOP anisotropic phase diagram (anisotropy phase diagram). Light gray circles and dark gray crosses indicate that DW is inverted or not inverted for a particular DMI and anisotropy in the simulation. The relevant areas in the phase diagram are highlighted with dark grey and light grey shading. Here, the anisotropic KOOP (IP area) and KOOP (OOP area) denote a single axis in the IP area and OOP area, respectivelyOOP anisotropy.

Fig. 8 shows time-series MOKE images of (a) NAND gates and (b) NOR gates for operational reliability measurements. On the left side a corresponding schematic of a different inverter configuration is shown. The DW storage and bias are set to (a) a "0" for NAND operation and (b) a "1" for NOR operation, respectively, using an applied OOP magnetic field. Light gray and dark gray in the diagram correspond to &, respectively

And (6) magnetizing. The V-shaped inverter at the DW reservoir is associated with a small inversion domain in the initial state (indicated as dark gray or light gray triangle) resulting from the chiral coupling. The boundaries of the NAND/NOR gates are indicated by dashed lines. Capturing a sequence of MOKE images in which the current density is 7.5 x 10 ¹¹ A/m ² And each image is acquired after two current pulses with a pulse length of 30ns. In the MOKE image, the light and dark contrasts in the gate structure correspond to &, respectively

And (6) magnetizing. All scales were 1 μm.

FIG. 9 schematically shows a proposal for MTJ/racetrack hybrid architecture for electrical control of logic inputs and detection of logic outputs in scaled magnetic DW logic devices. Dark and light grey shaded regions represent regions with OOP and IP magnetization, respectively. Three MTJs on the logic input and biased storage are used to control their magnetization, while one MTJ on the output race track is used to detect the output magnetization. The direction of the applied current is indicated by the arrows.

FIG. 10 shows various cascaded DW logic circuits. Fig. 10a shows an AND gate manufactured by cascading one NAND gate AND one NOT gate. FIG. 10b shows a cascaded DW logic circuit with NAND gates and NOR gates. Note that the inverter is placed in the bias reservoir of the NOR gate, highlighted using a green frame, giving a bias of "1" as shown in the inset, while the bias of the NAND gate is "0". FIG. 10c is a two-bit multiplexer fabricated by cascading three NAND gates and one NOT gate. FIG. 10d shows a circuit by cascading four NAND gates anda NOT gate made of a half-reducer. FIG. 10e shows a long cascaded DW logic circuit comprising 10 NAND gates and 11 NOT gates. Light and dark contrasts in the device area in the MFM image correspond to &, respectively

And (5) magnetizing. An MFM image is captured after saturation with an OOP magnetic field to set the initial magnetization direction to &' in all the reservoirs and then applying a current pulse to obtain the final state. All scales were 500nm.

FIG. 11 schematically illustrates an example of a magnetic DW logic element. The different gray shaded areas indicate areas with OOP and IP anisotropy, respectively. The direction of the current is indicated by the black arrows. The dimensions of the magnetic DW logic elements used in the experiments are shown.

FIG. 12 depicts DW velocities in a uniform OOP region of the racetrack and effective DW velocities in a NOT gate according to current density. Error bars represent the standard deviation of the DW velocities measured in 5 different devices.

FIG. 13 shows a time-series MOKE image of a NAND gate during operation and a corresponding schematic. The NAND gate contains two inverters in the DW memory and the offset is set to "0" and the boundaries of the NAND gate are indicated by dashed lines. Two V-inverters in the DW reservoir are associated with small inverted domains in the initial state (indicated as purple triangles) resulting from chiral coupling. Capturing a sequence of MOKE images in which the current density is 7.5 x 10 ¹¹ A/m ² And each image is acquired after two current pulses with a pulse length of 30ns. Light and dark contrast in the gate structure in the MOKE image correspond to &, respectively

And (5) magnetizing. Both DW reservoirs and bias are set to logic "0" by applying an OOP magnetic field of 1 kOe. All scales were 1 μm.

FIG. 14 schematically illustrates the concept of the propagation delay time of DW logic. FIG. 14a schematically illustrates the use of propagation delay times to improve the operational reliability of logic operations in NAND gates. Different shades of greyRespectively correspond to &

And (6) magnetizing. FIG. 14b shows an MFM image of NAND gates with different input runway lengths (top: 1) _a ＝1 _b And the middle: 1 _a ＞1 _b Bottom: 1 _a ＜1 _b In which 1 is _a And 1 _b The runway lengths of inputs a and b, respectively). Light and dark contrast correspond to &respectively

And (6) magnetizing. An MFM image is captured after saturation with an OOP magnetic field to set the initial magnetization directions in all the reservoirs to £ and then applying a current pulse to obtain the final state. Indicating the direction of the current. Fig. 14c schematically shows the dependence of the probability of giving a correct output in terms of propagation delay time. All scales in the MFM image were 500nm.

FIG. 15 shows Hall measurements of logical operations in a NAND gate. In fig. 15a, the different grey shades in the optical image of the device represent the areas with electrodes, pt crosses and NAND gates, respectively. Fig. 15b shows the hall resistance and the corresponding MOKE image according to the number of pulses. Left side: the typical hall resistance varies as the number of pulses increases. Right side: 1172 repeat the first 30 measurements and the last 30 measurements of the measurements. An as

The hall resistance level of the output magnetization is indicated by the dashed line. The OOP magnetic field is applied to set the initial state at the beginning of each measurement indicated with a red arrow. The bright and dark contrast in the gate structure in the MOKE image correspond to [ ] and [ ] respectively

And (5) magnetizing. The boundaries of the NAND gate are indicated by dashed lines. The current density and the pulse length of the applied current pulse were 7.5X 10, respectively ¹¹ A/m ² And 30ns. Fig. 15c shows the operational reliability of the logic NAND gate according to the number of current pulses. All scales were 2 μm.

Fig. 16 shows device fabrication and magnetic characterization. FIG. 16a shows a schematic of the main nano-fabrication process for magnetic DW logic circuits. (ii) ion milling the magnetic Pt/Co/Al multilayer to create a magnetic stripe, (ii) ion milling to create magnetic racetracks and logic gates, and (iii) oxidizing the Al layer in the OOP region. In the inset, an SEM image of a 50nm wide PMMA mask used to protect the IP region of the NAND gate shown in fig. 3a during oxygen plasma treatment is shown. The scale bar in the SEM image is 100nm. FIG. 16b shows polarity MOKE measurements of IP and OOP regions when OOP magnetic fields are applied. Finally, fig. 16c shows an anomalous hall measurement of the OOP region when an IP magnetic field is applied.

Fig. 17 shows DW inversion in a DW inverter with a straight IP zone. FIG. 17a shows a diagram for an incidence performed in a DW inverter with a straight IP region

DW inverted STXM image sequence of DWs. Each XMCD image is captured after application of two current pulses. The edges of the magnetic racetrack are indicated with red dashed lines and the position of the inverter is indicated with white solid lines. Light and dark contrast in XMCD images correspond to [ ] and [ ] respectively

And (6) magnetizing. The current density and duration of the pulse is 1.1X 10 ¹² A/m ² And 1ns. Fig. 17b shows STXM images of reverse domain nucleation in the same DW inverter with straight IP regions for four different operations. FIG. 17c shows the DW velocity in a DW inverter with V-shaped and straight IP regions according to the current density determined from experimental MOKE measurements. Error bars and color shading for each point represent the standard deviation of the 5 measured DW velocities. All scales are 500nm.

Asymmetric DW inverter

Now, referring to FIG. 18, it is shown that by modifying the shape of the DW inverter, nonreciprocity can be introduced in the DW inverter operation. Fig. 18 shows this non-reciprocal operation of an asymmetric DW inverter. Fig. 18 (a) schematically shows a top view of an asymmetric DW inverter for positive current (left diagram) and negative current (right diagram), where the fan angle of the inversion domains at different positions along "V" is shown. The energy ratio is defined by:

where N is the number of IP boundaries around the apex of the sector, σ _DMI Is the chiral coupling energy per unit length, σ _DW Is the DW energy per unit length. The energy ratio λ used to nucleate the inversion domains at each location along the IP region is indicated. Fig. 18 b) shows a differential MOKE image of an asymmetric DW inverter before and after the application of 30 current pulses. Light and dark contrasts in MOKE image correspond to &

And (6) magnetizing. The current density and duration of the current pulse are 4.2X 10, respectively ¹¹ A/m ² And 50ns. FIG. 18 c) is the speed of DWs delivered by asymmetric and symmetric DW inverters according to current density. Error bars represent the standard deviation of the DW velocities measured in 5 different devices.

As shown in fig. 18a, the width of the racetrack on the left side of the IP region is increased to suppress the possibility of domain nucleation of negative current. In this case, the OOP region at the intersection of "V" and the runway has a lower probability of nucleation than elsewhere along the IP region due to λ 1/(π/2+ α) < 2/π. Therefore, it is difficult to nucleate the inverted domains on the left side of the IP region. This has been experimentally demonstrated by propagating DWs from the right to the left side of the inverter using a negative current (fig. 18 b). When the DWs reach the V-shaped IP region from the right, they remain pinned and cannot pass through the inverter. In contrast, since the nucleation centers on the inside of the vertex of the "V" are not affected, DWs incident from the left side can be transmitted toward the right side with a positive current. For the purpose of

And

this behavior was observed for both DWs (fig. 18 b). Thus, nucleation of the inversion domains is highly asymmetric for positive and negative currents, but independent of the DW polarity. Furthermore, by measuring the DW displacement according to the current density, it was found that the DW propagates through the asymmetric inverter in the forward direction at a similar speed as the symmetric inverter, while being completely blocked in the backward propagation direction (fig. 18 c).

Micromagnetic simulation

To further understand the mechanism of DW inversion in symmetric and asymmetric DW inverters, micromagnetic simulations were performed using publicly available MuMax3 codes. The simulation involved the use of magnetic parameters having a size of 2X 1.6nm ³ Discretized, 2048 × 1024 × 1 cells: saturation magnetization M _s =0.9MA/m, effective OOP anisotropy field H _eff =200mT, exchange constant a =16pJ/m, effective spin hall angle Pt θ _sh =0.1, and an interfacial DMI constant D = -1.5mJ/m ² . The width of the runways in the symmetric DW inverter is 800nm, while the widths of the left and right runways in the asymmetric DW inverter are 1500nm and 800nm, respectively. The width of the IP region is 30nm and a =20 °.

Micromagnetic simulations of current driven DW inversion in both symmetric and asymmetric DW inverters are shown in FIG. 19. Fig. 19 (a) shows the speed of the DW transmitted through the inverter according to the current density. The crosses indicate the "breakdown" of the inversion process at high current densities, which corresponds to

And

continuous injection of DW. Fig. 18 (b) shows that j =4 × 10 ¹¹ A/m ² State (I) of (a), j =1.6 × 10 ¹² A/m ² State (II) and j =2.6 × 10 ¹² A/m ² A snapshot of the magnetic configurations of the symmetric (top two rows) and asymmetric inverters (bottom two rows) in state (III) of (a). The magnetization direction is indicated by the color circle.

Current density-The velocity profile shows three states of different DW behavior (fig. 19 a). At a low current density (j)<1.0×10 ¹² A/m ² ) In both symmetric and asymmetric DW inverters, the DW is pinned just before the IP region, regardless of the current direction (see snapshot I in FIG. 19 b). Pinning is due to the energy barrier that must be overcome to switch the chiral magnetic structure around the inverter region. For example, as shown in FIG. 19b, if the initial magnetic configuration of the inverter is

If DMI supports, the inverter must switch to other DMI supported configurations

So as to transmit the incident DW from the left side to the right side.

In state II, i.e. at medium current density (1.0X 10) ¹² <j<2.0×10 ¹² A/m ² ) Next, the SOT is strong enough to push the DW across the energy barrier and nucleate inversion domains on the other side of the IP region. In this state, the DW velocity through the inverter increases linearly with current density. The inversion domains in the symmetric DW inverter nucleate at the apex of the "V" for positive currents and at the intersection of the "V" with the runway edge for negative currents, consistent with the STXM measurements and arguments presented in section IV. In the simulation of a counter-propagating DW across a symmetric DW inverter, we found that the nucleation process is different at the upper and lower intersections of "V" with the runway edge (see snapshot II in FIG. 19 b), which is due to the combined effect of SOT and DMI causing the DW to tilt.

Furthermore, the threshold current density for DW reversals in the forward propagation direction is slightly lower than the threshold current density for the backward propagation direction, which means that nucleation at the "V" vertices is more favorable than nucleation at the racetrack edges, despite the same chiral coupling strength. In the simulation of asymmetric DW inverters, the behavior in the forward propagation direction is the same as that of symmetric DW inverters, and their DW velocities are nearly identical. In the backward propagation direction, there is no nucleation at the edges and the DW is completely blocked before the IP region. This non-reciprocal behavior is very consistent with the experimental results reported in fig. 18.

Finally, at high current density (j)>2.0×10 ¹² A/m ² ) State III at this point corresponds to the formation of complex magnetic structures around the IP region (see snapshot III in fig. 19 b) and to the saturation of the DW velocity. At even higher current densities (j)>2.6×10 ¹² A/m ² ) Next, a magnetic domain in the form of a bubble is continuously injected from the apex of "V", causing the DW transducer to break down in the backward propagation direction (indicated by crosses in fig. 19 a).

DW diode

In electronic circuits, a diode is a critical non-reciprocal element that rectifies the flow of electrons, i.e. it allows the passage of current in one direction (forward) and blocks the current in the opposite direction (backward). This rectification characteristic is commonly used to convert AC signals to DC signals in analog circuits. Thus, in one embodiment of the invention, such DW diodes are based on the non-reciprocal DW inverters described above.

The DW velocity-current density curves reported in FIG. 18c and FIG. 19a for the asymmetric DW inverter simulate the I/V characteristics of the diode. However, DWs propagating in the forward direction are inverted with respect to the initial DWs. This effect does not correspond in electronic circuits. Therefore, a properly functioning DW diode can be obtained by cascading an asymmetric DW inverter and a symmetric DW inverter.

Fig. 20 shows a schematic diagram of a diode in general. Fig. 20 (a) is a symbol and a schematic diagram of a DW diode. FIG. 20 (b) shows the difference MOKE image of the DW diode before and after the application of 30 current pulses. Light and dark contrasts in MOKE image correspond to &

And (5) magnetizing. The current pulse has a current density and duration of 4.2 × 10 ¹¹ A/m ² And 50ns.

As shown in fig. 20a, due to chiral coupling, the magnetizations of the left and right sides of the two cascaded DW inverters are the same in the equilibrium state. In the case of a positive current, DWs transmitted through asymmetric DW inverters with inverted polarity are inverted back at the symmetric inverters so that the final DW propagates in the racetrack without changing its polarity. Conversely, in the case of a negative current, the DW may pass through a symmetric DW inverter with inverted polarity, but it is blocked by an asymmetric DW inverter, as shown in fig. 20 b. This non-reciprocal operation is equivalent to a DW diode. Current-driven DW diodes are a new component that extends the operation of DW logic circuits to AC signal states.

Claims (11)

1. A device (2) for storing and/or processing data using the concept of magnetic domain wall motion induced by spin-orbit torque,

the apparatus comprises:

a) A support layer (4) made of electrically conductive material;

b) A ferromagnetic or ferrimagnetic layer (6) disposed on the support layer (4), the ferromagnetic or ferrimagnetic layer (6) being capable of exhibiting tunable magnetic anisotropy and providing a magnetic track (RT);

c) A functional layer (8) in terms of the tunable magnetic anisotropy disposed on the ferromagnetic or ferrimagnetic layer (6), the functional layer (8) having a first functional portion (10) and a second functional portion (12) and a third functional portion (14) between the first functional portion (10) and the second functional portion (12), wherein the first portion and the second portion of the functional layer (8) enable the ferromagnetic or ferrimagnetic layer (6) to have an OOP magnetization perpendicular to the plane of the layer (4, 6, 8) and the third portion of the functional layer enables the ferromagnetic or ferrimagnetic layer (6) to have an IP magnetization parallel only to the plane of the layer (4, 6, 8); wherein:

d) An OOP magnetization oriented vertically and upward represents a logical "0" and a downward orientation represents a logical "1", or vice versa, or an IP magnetization in one direction represents a logical "0" and in the other direction represents a logical "1", or vice versa;

e) -said logical "1" or logical "0" can be encoded in a second region (16) of the ferromagnetic or ferrimagnetic layer (6) covered by the second portion (12) or in the third region of the ferromagnetic or ferrimagnetic layer (6) and vice versa, in response to moving a Domain Wall (DW) in a first region (18) of the ferromagnetic or ferrimagnetic layer (6) covered by the first portion (10) along the magnetic Racetrack (RT) towards an interface (20) given at the transition of the first portion (10) to the third portion (14); and

f) A current supply (22) to the support layer (4), wherein controlled current pulses applied to the support layer (4) cause the magnetic Domain Walls (DW) to deterministically move along the magnetic Racetrack (RT).

2. The device (2) according to claim 1, wherein the functionality of the first and second portions of the functional layer is achieved by at least one of:

a) The functional layers of the first and second portions are metal oxide layers and the third portion is a metal layer;

b) The third portion is an insulating layer comprising electrodes enabling application of an electric field in an OOP direction on the ferromagnetic or ferrimagnetic layer;

c) The third portion of the functional layer is a metal oxide layer penetrated by a solid state proton pump; and/or

d) Said third portion of said functional layer is a metal oxide layer which is penetrated by a focused ion beam of helium and/or gallium.

3. The device (2) according to claim 1 or 2, wherein the electrically conductive material is selected from the group consisting of: platinum; w, ta, ir, pd, ru, WOx, WNx, taN, cuBi, ptxCUl-x, ptxAll-x, bi2Se3 and Bi2SbxTel-x.

4. A device (2) according to any of the preceding claims, wherein the ferromagnetic or ferrimagnetic layer (6) comprises a metal component selected from the group consisting of: iron, cobalt, nickel and their alloys, coFeB, co/Ni multilayers, gdFeCo, gdCo, gdFe, gdCoFe, tbCo.

5. The device (2) according to any one of the preceding claims, wherein the functional layer (8) comprises a metal component selected from the group consisting of: aluminum, tantalum, gadolinium, magnesium, ruthenium, hafnium.

6. Device (2) according to one of the preceding claims,

wherein the support layer (4) and/or the ferromagnetic or ferrimagnetic layer (6) and/or the functional layer (8) has a length in the range of 10nm to 100 μm and/or a width in the range of 10nm to 10 μm and/or a height in the range of 0.5nm to 10 μm.

7. Device (2) according to any one of the preceding claims, wherein the width of the first functional part (10) and of the ferromagnetic or ferrimagnetic layer (6) and of the support layer (4), both below the first functional part (10), seen in a direction perpendicular to the direction of the magnetic Racetrack (RT), is greater than the width of the second functional part (12) and of the ferromagnetic or ferrimagnetic layer (6) and of the support layer (4), both below the second functional part (12).

8. The device (2) according to claim 7, wherein the course of the width seen along the magnetic track (RT) has the shape of a step function.

9. A logic gate comprising a plurality of devices (2) according to any one of the preceding claims, wherein two magnetic Runways (RT) representing logical inputs of the logic gate are provided substantially radially, preferably V-shaped or Y-shaped, to share a common second region (16) of the ferromagnetic or ferrimagnetic layer, which second region thereby represents a logical output of the logic gate, and to share the second functional part of the functional layer (8), preferably the metal oxide part (12), wherein the first regions (18) of the two magnetic Runways (RT) are separated by a magnetic Bias region (Bias) of determinable magnetization, and wherein the third region (14) of the functional layer (8) is arranged in the form of a ring segment shape aligned with the radial arrangement, preferably V-shaped or Y-shaped arrangement, of the two magnetic Runways (RT).

10. Logic gate according to claim 9, wherein the two Runways (RT) have different input runway lengths to give different arrival times of the two logic inputs.

11. Logic gate according to claim 9 or 10, wherein the metallic area (14) of the functional layer (8) has a V-shape, such that the peaks of the V-shape are shown into the direction of the magnetic track (RT) and vice versa.

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