CN115394780A

CN115394780A - Fuse structure and forming method thereof

Info

Publication number: CN115394780A
Application number: CN202110551581.8A
Authority: CN
Inventors: 李雄; 杨彬
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2022-11-25

Abstract

The application provides a fuse structure and a forming method thereof. Wherein, the fuse structure includes: the substrate comprises an active region and is provided with a first surface and a second surface which are oppositely arranged, and a groove is formed on the first surface; the control grid is positioned in the groove and is electrically connected with the first power supply; and the gate dielectric layer is positioned between the control gate and the inner wall of the groove and surrounds the control gate, the gate dielectric layer is electrically connected with the second power supply, and the equivalent gate dielectric thickness of the gate dielectric layer is changed when the second power supply is switched on.

Description

Fuse structure and forming method thereof

Technical Field

The present disclosure relates to integrated circuit technologies, and more particularly, to a fuse structure and a method for forming the fuse structure.

Background

Fuse memory cells are widely used for repair work in integrated circuits, and the classic structure is a structure in which a control gate structure is separated from a fuse. But is limited by the design rule between two gate structures, and the fuse structure has the problem of overlarge area. As the integration degree of integrated circuits is increased, the disadvantage of too large area is also gradually revealed.

Disclosure of Invention

In view of the above, it is necessary to provide a fuse structure and a method for forming the same, which address the problem of the prior art that the area of the fuse structure is too large.

A fuse structure, comprising:

the substrate comprises an active region and is provided with a first surface and a second surface which are oppositely arranged, and a groove is formed on the first surface;

the control grid is positioned in the groove and electrically connected with a first power supply;

and the gate dielectric layer is positioned between the control gate and the inner wall of the groove and surrounds the control gate, the gate dielectric layer is electrically connected with a second power supply, and the equivalent gate dielectric thickness of the gate dielectric layer is changed when the second power supply is switched on.

In one embodiment, the active regions on both sides of the trench form a source region and a drain region.

In one embodiment, the gate dielectric layer includes an insulating dielectric layer and a fuse gate, the insulating dielectric layer is located between the control gate and the inner wall of the trench and wraps the fuse gate, and the fuse gate is electrically connected to the second power supply.

In one embodiment, the insulating dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located on the surface of the inner wall of the trench, and the second dielectric layer surrounds the control gate.

In one embodiment, the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

In one embodiment, the first power supply has a first voltage and the second power supply has a second voltage, the first voltage being less than the second voltage.

In one embodiment, the control gate and the first power supply have a first connection end, the fuse gate and the second power supply have a second connection end, and the first connection end and the second connection end are respectively located on two opposite sides of the active region.

A method for forming a fuse structure includes:

providing a substrate, wherein the substrate comprises an active region and is provided with a first surface and a second surface which are oppositely arranged, and a groove is formed on the first surface;

forming a gate dielectric layer on the surface of the inner wall of the groove, wherein the gate dielectric layer is electrically connected with a second power supply, and the equivalent gate dielectric thickness of the gate dielectric layer is changed when the second power supply is turned on;

and forming a control grid electrode on the surface of the gate dielectric layer, wherein the control grid electrode fills the groove and is electrically connected with a first power supply.

In one embodiment, after the forming the control gate on the surface of the gate dielectric layer, the method further includes:

and performing ion implantation on the active regions on two sides of the groove to form a source region and a drain region.

In one embodiment, the forming a gate dielectric layer on the surface of the inner wall of the trench includes:

a first dielectric layer is arranged on the surface of the inner wall of the groove;

forming a fuse grid on the bottom surface of the first dielectric layer;

forming a second dielectric layer on the surfaces of the exposed first dielectric layer and the fuse grid, wherein the second dielectric layer and the first dielectric layer form the insulating dielectric layer, and the insulating dielectric layer and the fuse grid form the grid dielectric layer;

forming a control grid electrode on the surface of the grid medium layer, comprising:

and forming a control grid on the surface of the second dielectric layer.

In one embodiment, the forming a fuse gate on the bottom surface of the first dielectric layer includes:

forming a fuse grid material layer on the surface of the first dielectric layer to fill the communication;

and removing part of the fuse gate material layer on the side wall of the first dielectric layer, wherein the rest fuse gate material layer forms the fuse gate.

In one embodiment, after forming the control gate on the surface of the second dielectric layer, the method further includes:

forming a first connection end connected with the control grid, wherein the first connection end is used for electrically connecting the first power supply;

forming a second connection terminal connected with the fuse grid, wherein the second connection terminal is used for being electrically connected with the second power supply; the first connection end and the second connection end are located on two opposite sides of the active region.

According to the fuse structure and the forming method thereof, the gate dielectric layer is electrically connected with the second power supply, so that the equivalent gate dielectric thicknesses of different gate dielectric layers are realized by switching on and switching off the second power supply, the gate control capacities of different control gates are further realized, and the discrimination between '0' and '1' is realized.

Meanwhile, the gate structure in the fuse structure is arranged in the groove, so that the area of the fuse unit can be effectively saved, and the integration level of the fuse circuit is greatly improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic cross-sectional view of a fuse structure provided in an embodiment;

FIG. 2 is a schematic cross-sectional view of a fuse structure provided in another embodiment;

FIG. 3 is another schematic cross-sectional view of a fuse structure provided in an embodiment;

FIG. 4 is a flow chart of a method of forming a fuse structure provided in one embodiment;

FIG. 5 is a flow chart of a method for forming a gate dielectric layer provided in one embodiment;

fig. 6 to 10 are schematic cross-sectional views illustrating a process of forming a fuse structure according to an embodiment.

Description of reference numerals:

100-a control gate; 200-a gate dielectric layer; 211-a first dielectric layer; 212-a second dielectric layer; 210-insulating dielectric layer; 220-a fuse gate; 310-an active region; 311-a source region; 312-a drain region; 400-a first connection end; 500-second connection end, 600-isolation structure.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

Referring to fig. 1, the present invention provides a fuse structure including a substrate, a control gate 100 and a gate dielectric layer 200.

The substrate includes an active region 310, which includes but is not limited to a silicon substrate. Specifically, an isolation region (not shown) may be further disposed in the substrate, and a shallow trench isolation structure is disposed in the isolation region. The shallow trench isolation structure isolates the substrate into a plurality of active regions 310 arranged at intervals.

Meanwhile, the substrate is provided with a first surface and a second surface which are oppositely arranged. The first surface is formed with a groove 300a.

Further, the active regions 310 at both sides of the trench 300a of the control gate 100 may form a source region 311 and a drain region 312.

The control gate 100 is located in the trench 300a, and may be made of polysilicon or the like. Also, the control gate 100 is electrically connected to a first power source. When the first power is turned on, the control gate 100 may receive a gate voltage control signal such that the active region 310 between the source region 311 and the drain region 312 forms a conductive channel. The active region 310 forming the conductive communication is a channel region surrounding the trench 300a.

The gate dielectric layer 200 is located between the control gate 100 and the inner wall of the trench 300a, and surrounds the control gate 100, so as to form a gate structure together with the control gate 100. The gate structure and the active region 310 together form a transistor structure.

Meanwhile, in the present embodiment, the gate dielectric layer 200 is electrically connected to a second power source. It is to be understood that the second power source is another power source than the first power source.

When the second power supply is turned on, the equivalent gate dielectric thickness of the gate dielectric layer 200 changes, thereby indirectly changing the gate control capability of the control gate 100. The "equivalent gate dielectric thickness" is the equivalent thickness of the gate dielectric layer 200 when the gate dielectric layer 200 is equivalent to an equivalent film with a predetermined dielectric constant.

The control gate 100 has different gate control capabilities, and the source-drain currents generated after the control gate 100 receives the gate voltage control signal are different. Thus, the discrimination between "0" and "1" can be realized by controlling the on and off of the second power supply.

Specifically, in the application process of the fuse structure, reading of different logic states can be realized by turning on and off the second power supply, and reading of "0" and "1" logic states can be realized by different source-drain currents.

In this embodiment, the gate dielectric layer 200 is electrically connected to a second power supply, so that the second power supply is turned on and off to realize different equivalent gate dielectric thicknesses of the gate dielectric layer 200, and further realize different gate control capabilities of the control gate 100, thereby realizing the discrimination between "0" and "1".

Meanwhile, since the gate structure in the fuse structure of the present embodiment is disposed in the trench 300a, the present embodiment can effectively save the area of the fuse unit, and greatly improve the integration level of the fuse circuit.

In one embodiment, with continued reference to fig. 1, the gate dielectric layer 200 includes an insulating dielectric layer 210 and a fuse gate 220. The insulating dielectric layer 210 is located between the control gate 100 and the inner wall of the trench 300a, and wraps the fuse gate 220.

The fuse gate 220 is a conductive film layer electrically connected to a second power source, thereby controlling the logic state of the fuse structure. Specifically, the material of the fuse gate 220 may be polysilicon.

Specifically, when the second power is turned off, the insulating medium layer 210 is in an insulating state as a whole. When the second power is turned on, a partial region of the insulating dielectric layer 210 is broken down by the voltage on the fuse gate 220 to become a conductive state, so that the equivalent gate dielectric thickness of the gate dielectric layer 200 is changed when the second power is turned on.

In one embodiment, the insulating dielectric layer 210 includes a first dielectric layer 211 and a second dielectric layer 212.

The material of the first dielectric layer 211 and the second dielectric layer 212 may be an insulating material such as oxide. Specifically, the materials of the first dielectric layer 211 and the second dielectric layer 212 may be the same or different, and the application is not limited thereto.

Specifically, the first dielectric layer 211 is located on the inner wall surface of the trench 300a. A second dielectric layer 212 surrounds the control gate 100.

In this embodiment, when the second power is turned off, the first dielectric layer 211 and the second dielectric layer 212 both serve as insulated gate dielectrics. Therefore, the equivalent gate dielectric thickness of the gate dielectric layer 200 at this time is about the sum of the equivalent thickness T1 of the first dielectric layer 211 and the equivalent thickness T2 of the second dielectric layer 212, that is, the equivalent gate dielectric thickness of the gate dielectric layer 200 at this time is about (T1 + T2).

As an example, when the second power is turned on, the fuse gate 220 may be configured to receive a voltage signal of the second power, so that the first dielectric layer 211 located on the inner wall surface of the trench 300a is broken down. At this time, the resistance of the first dielectric layer 211 becomes small. Therefore, the equivalent gate dielectric thickness of the gate dielectric layer 200 at this time is smaller than T1, that is, after the first dielectric layer 210 is broken down, the equivalent gate dielectric thickness of the gate dielectric layer 200 is smaller than (T1 + T2).

Therefore, in this embodiment, the equivalent gate dielectric thickness of the gate dielectric layer is effectively reduced when the second power is turned on, compared to when the second power is turned off. Therefore, different equivalent gate dielectric thicknesses of the gate dielectric layer 200 can be effectively realized by controlling the on and off of the second power supply, so that the discrimination between '0' and '1' can be effectively realized.

Of course, in this embodiment, a suitable second power source may be provided, so that when the second power source is turned on, a portion of the first dielectric layer 211 is broken down. For example, when the second power is turned on, a portion of the first dielectric layer 211 in contact with the fuse gate 220 may be broken down, and a portion of the first dielectric layer 211 far from the fuse gate 220 may not be broken down.

At this time, the equivalent gate dielectric thickness of the gate dielectric layer 200 is still reduced, so that the discrimination between "0" and "1" can be realized.

Alternatively, in other embodiments, the insulating dielectric layer 210 may be provided in other forms. For example, referring to fig. 2, the first dielectric layer 211 may be disposed at the bottom of the trench in contact with the fuse gate 220, and the top surface of the first dielectric layer 211 and the fuse gate 220 may be flush with each other, while the second dielectric layer 212 may be disposed in the trench above the first dielectric layer 21 and the fuse gate 220.

In one embodiment, referring to fig. 1, the thickness of the second dielectric layer 212 is greater than the thickness of the first dielectric layer 211.

Since the second dielectric layer 212 and the first dielectric layer 211 jointly wrap the fuse gate 220, the second dielectric layer 212 is inevitably affected when the fuse gate 220 receives a voltage signal of the second power source to break down the first dielectric layer 211.

In this embodiment, the thickness of the second dielectric layer 212 is greater than the thickness of the first dielectric layer 211, so that the influence on the second dielectric layer 212 when the first dielectric layer 211 is broken down can be effectively reduced.

As an example, the thickness of the first dielectric layer 211 may be set to be 1.5nm to 2.5nm, and the thickness of the second dielectric layer 212 may be set to be 4.5nm to 6nm, so as to ensure that the second dielectric layer 212 is not damaged during the breakdown fusing process of the first dielectric layer 211, thereby ensuring the reliability of the product.

Of course, in other embodiments, the second dielectric layer 212 may be protected in other ways. For example, the dielectric constant of the second dielectric layer 212 may be set to be greater than that of the first dielectric layer 211.

In one embodiment, the first power supply has a first voltage and the second power supply has a second voltage. And, the first voltage is less than the second voltage.

At this time, when the second power is turned on, it can be effectively ensured that the second voltage can break down the first dielectric layer 211.

Specifically, the magnitudes of the first voltage and the second voltage may be set in conjunction with the thicknesses, materials, and the like of the first dielectric layer 211 and the second dielectric layer.

As an example, when the first dielectric layer 211 and the second dielectric layer 212 are made of the same material (e.g., both oxide), and the thickness of the first dielectric layer 211 is 1.5nm to 2.5nm, and the thickness of the second dielectric layer 212 is 4.5nm to 6nm, the first voltage may be set to be in a range of 2V to 3V, and the second voltage may be set to be in a range of 5V to 6V.

In one embodiment, referring to fig. 3, the control gate 100 and the first power source have a first connection 400. The fuse gate 220 and the second power supply have a second connection 500. That is, the control gate 100 is electrically connected to the first power source through the first connection terminal 400. And the fuse gate 220 is electrically connected to a second power source through a second connection terminal 500.

Meanwhile, in the present embodiment, the first connection terminal 400 and the second connection terminal 500 are respectively disposed at two opposite sides of the active region 310, so that signal coupling interference between the first connection terminal 400 and the second connection terminal 500 can be effectively prevented.

Specifically, the extending direction of the active region 310 of the substrate is set to a first direction. In the first direction, the active regions at both sides of the trench 300a are used to form a source region 311 and a drain region 312.

Meanwhile, referring to fig. 3, in a second direction perpendicular to the first direction or at a certain inclination angle, the trench 300a may penetrate the active region 310 of the substrate and extend to the isolation region 320 on both sides of the active region 310.

Therefore, in the second direction, the fuse gate 220 and the control gate 100 in the trench 300a also extend to the isolation region 320 at both sides of the active region 310.

At this time, the first connection terminal 400 connected to the control gate 100 and the second connection terminal 500 connected to the fuse gate 220 are respectively disposed on the isolation regions 320 at both sides of the active region 310.

Specifically, the second connection terminal 500 may be located in a through hole penetrating the control gate 100 and the second dielectric layer 212, and an isolation structure 600 is formed between the through hole and a wall of the through hole, so as to be isolated from the control gate 100.

Of course, the grooves 300a, the first connection ends 400, and the second connection ends 500 may be arranged in other practicable manners, which is not limited in the present application.

In one embodiment, referring to fig. 4, a method for forming a fuse structure is provided, which includes:

step S100, providing a substrate including an active region 310 and having a first surface and a second surface opposite to the first surface, wherein the first surface is formed with a trench 300a, please refer to fig. 6;

step S200, forming a gate dielectric layer 200 on the inner wall surface of the trench 300a, wherein the gate dielectric layer 200 is electrically connected to a second power supply, and the equivalent gate dielectric thickness of the gate dielectric layer 200 changes when the second power supply is turned on, please refer to fig. 8;

in step S300, a control gate 100 is formed on the surface of the gate dielectric layer 200, and the control gate 100 fills the trench and is electrically connected to the first power source, as shown in fig. 9.

Meanwhile, the gate structure in the fuse structure formed in the embodiment is disposed in the trench 300a, so that the embodiment can effectively save the area of the fuse unit, and greatly improve the integration degree of the fuse circuit.

Further, after step S300, the method may further include:

in step S400, ion implantation is performed on the active regions 310 on both sides of the trench 300a to form a source region 311 and a drain region 312, please refer to fig. 10.

In one embodiment, the gate dielectric layer 200 includes an insulating dielectric layer 210 and a fuse gate 220. The insulating dielectric layer 210 is disposed between the control gate 100 and the inner wall of the trench 300a, and wraps the fuse gate 220, and the fuse gate 220 is electrically connected to the second power source.

At this time, further, step S200 may include:

step S210, forming a first dielectric layer 211 on the inner wall surface of the trench 300a, please refer to fig. 6;

step S220, forming a fuse gate 220 on the bottom surface of the first dielectric layer 211, please refer to fig. 7;

in step S230, a second dielectric layer 212 is formed on the exposed surfaces of the first dielectric layer 211 and the fuse gate 220, the second dielectric layer 212 and the first dielectric layer 211 form an insulating dielectric layer 210, and the insulating dielectric layer 210 and the fuse gate 220 form a gate dielectric layer 200, please refer to fig. 8.

Accordingly, step S300 may then include:

a control gate 100 is formed on the surface of the second dielectric layer 212, please refer to fig. 9.

For example, in step S210, the first dielectric layer 211 may be formed on the inner wall surface of the trench 300a by thermal oxidation or chemical vapor deposition.

Also, as an example, step S220 may include:

step S221, forming a fuse gate material layer on the surface of the first dielectric layer 211 to fill the trench 300a;

specifically, the trench 300a may be filled with polysilicon as a fuse gate material layer, which may or may not be filled with polysilicon, and this is not required in this application.

In step S222, a portion of the fuse gate material layer on the sidewall of the first dielectric layer 211 is removed, and the remaining fuse gate material layer forms the fuse gate 220.

Specifically, a portion of the polysilicon may be removed by etching, thereby forming the fuse gate 220.

In step S230, the second dielectric layer 212 may be formed by chemical vapor deposition or the like. The material may be the same as the first dielectric layer 211, or may be different from the first dielectric layer 211, which is not limited in this application.

Meanwhile, in step S300, specifically, a control gate material layer may be formed on the first surface of the substrate and in the trench, and then the control gate material layer is etched back, so as to form the control gate.

In one embodiment, the thickness of the second dielectric layer 212 is greater than the thickness of the first dielectric layer 211.

In one embodiment, after step S300, the method further includes:

step S500, forming a first connection terminal 400 connected to the control gate 100, wherein the first connection terminal 400 is used for electrically connecting a first power source, please refer to fig. 3;

step S600, forming a second connection terminal 500 connected to the fuse gate 220, the second connection terminal 500 being used for electrically connecting to a second power supply; the first connection terminal 400 and the second connection terminal 500 are located at two opposite sides of the active region 310, please refer to fig. 3.

In step S500, a first connection hole may be formed first, and then the first via hole is filled with a first conductive material to form the first connection terminal 400.

In step S600, a second connection hole may be formed first, then an isolation structure 600 is formed on a sidewall of the second via, and then a second conductive material is filled in the second via to form the second connection terminal 500.

For the specific limitations and technical effects of the fuse structure forming method, reference may be made to the above limitations on the fuse structure method, which is not described herein again.

It should be understood that, although the steps in the flowcharts of fig. 4 and 5 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in fig. 4 and 5 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternatively with other steps or at least a part of the steps or stages in other steps.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A fuse structure, comprising:

2. The fuse structure of claim 1, wherein the active regions on both sides of the trench form a source region and a drain region.

3. The fuse structure of claim 1, wherein the gate dielectric layer comprises an insulating dielectric layer and a fuse gate, the insulating dielectric layer is located between the control gate and the inner wall of the trench and wraps the fuse gate, and the fuse gate is electrically connected to the second power supply.

4. The fuse structure of claim 3, wherein the insulating dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is located on the surface of the inner wall of the trench, and the second dielectric layer surrounds the control gate.

5. The fuse structure of claim 4, wherein the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

6. The fuse structure of claim 4, wherein the first power supply has a first voltage and the second power supply has a second voltage, the first voltage being less than the second voltage.

7. The fuse structure of claim 3, wherein the control gate and the first power source have a first connection end, the fuse gate and the second power source have a second connection end, and the first connection end and the second connection end are respectively located on two opposite sides of the active region.

8. A method for forming a fuse structure, comprising:

forming a gate dielectric layer on the surface of the inner wall of the groove, wherein the gate dielectric layer is electrically connected with a second power supply, and the equivalent gate dielectric thickness of the gate dielectric layer is changed when the second power supply is switched on;

9. The method of claim 8, wherein after forming the control gate on the surface of the gate dielectric layer, the method further comprises:

10. The method as claimed in claim 8, wherein the gate dielectric layer includes an insulating dielectric layer and a fuse gate, the insulating dielectric layer is located between the control gate and the inner wall of the trench and wraps the fuse gate, and the fuse gate is electrically connected to the second power source.

11. The method of claim 10, wherein forming a gate dielectric layer on the surface of the inner wall of the trench comprises:

forming a fuse grid on the bottom surface of the first dielectric layer;

and forming a control grid on the surface of the second dielectric layer.

12. The method of claim 11, wherein forming a fuse gate on a bottom surface of the first dielectric layer comprises:

and removing part of the fuse grid material layer on the side wall of the first dielectric layer, wherein the residual fuse grid material layer forms the fuse grid.

13. The method of claim 11, wherein the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

14. The method of claim 11, wherein the first power supply has a first voltage and the second power supply has a second voltage, and wherein the first voltage is less than the second voltage.

15. The method of claim 10, wherein after forming the control gate on the surface of the second dielectric layer, the method further comprises: