CN115394268B

CN115394268B - Shifting register, grid driving circuit and driving method

Info

Publication number: CN115394268B
Application number: CN202211195460.5A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2023-12-12
Anticipated expiration: 2042-09-28
Also published as: CN115394268A

Abstract

The invention discloses a shift register, a grid driving circuit and a driving method, wherein the shift register comprises: a first control circuit and an output circuit; the first control circuit comprises N cascaded control sub-circuits, wherein N is a positive integer not less than 2; the output end of the first control circuit is connected to the pull-up node, and the control end of the output circuit is connected to the pull-up node; the first control circuit is configured to write a first working level to the pull-up node after the N control sub-circuits are conducted in the first stage; the output circuit is configured to output the first drive level in the second stage and the second drive level in the third stage after the pull-up node is written to the first operation level. Display driving and random compensation can be realized without a separate random compensation circuit, the number of TFT devices is reduced, and the circuit area and the manufacturing cost are reduced.

Description

Shifting register, grid driving circuit and driving method

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit and a driving method.

Background

The Scan driving circuit (Scan river IC) functions to sequentially output the switching voltage of the TFT (Thin Film Transistor ) devices row by row. The scan driving circuit output is connected to the Gate of the TFT, and is also called a Gate Driver IC. The scanning driving circuit belongs to a pure digital circuit, so that a TFT device of the grid driving circuit can be integrated on a TFT substrate, which is also called GIP (Gate in Panel) technology for short, and is also called GOA (Gate on Array) technology for short, thereby effectively reducing the cost. However, the current panel adopts a gate driving circuit to realize a random sensing (sense) function to eliminate the scanning lines, so that the gate driving circuit is too complex, a large number of TFT devices are required to be used, the manufacturing cost is high, and the circuit area is increased.

Disclosure of Invention

In view of the above problems, the present application provides a shift register, a gate driving circuit and a driving method, which can realize display driving and random compensation without a separate random compensation circuit, reduce the number of TFT devices, and reduce the circuit area and manufacturing cost.

In a first aspect, the present application provides, by way of an embodiment, the following technical solutions:

a shift register, comprising: a first control circuit and an output circuit; the first control circuit comprises N cascaded control sub-circuits, wherein N is a positive integer not less than 2; the output end of the first control circuit is connected to a pull-up node, and the control end of the output circuit is connected to the pull-up node; the N control sub-circuits are configured to be conducted after receiving preset N pull-up control levels in the first stage, and each control sub-circuit corresponds to one pull-up control level; the first control circuit is configured to write a first working level to the pull-up node after the N control sub-circuits are conducted in a first stage; the output circuit is configured to output a first drive level in a second stage and a second drive level in a third stage after the pull-up node is written to the first operating level.

Optionally, the N control sub-circuits include: a first control sub-circuit and/or a second control sub-circuit; the N pull-up control levels include: a first control level and/or a second control level; the first control level and the second control level are inverted; wherein the first control sub-circuit is configured to turn on after the control terminal of the first control sub-circuit receives the first control level, and the second control sub-circuit is configured to turn on after the control terminal of the second control sub-circuit receives the second control level.

Optionally, the first control sub-circuit includes a first transistor configured to turn on after a gate of the first transistor receives the first control level; the second control sub-circuit comprises an inverter and a second transistor, wherein an output end of the inverter is connected with a gate electrode of the second transistor, an input end of the inverter is configured to receive the second control level, and the second transistor is configured to be turned on after the inverter receives the second control level.

Optionally, the shift register further includes: the output end of the second control circuit is connected to the pull-down node; the second control circuit is configured to write a second operating level to the pull-down node to reset the pull-up node in a fourth stage.

Optionally, the N control sub-circuits further include: a third control sub-circuit; the N pull-up control levels further include: the third control level is the same as or opposite to the level accessed by the input end of the second control circuit; the third control sub-circuit is configured to be turned on after the control end of the third control sub-circuit receives a third control level.

Optionally, the level signal accessed by the input end of the third control sub-circuit is the same as that accessed by the input end of the second control circuit, and the third control sub-circuit comprises a third transistor; the third transistor is configured such that a gate of the third transistor is turned on after receiving the third control level.

Optionally, for driving the display panel, N satisfies the relation: h is less than or equal to 2 ^K And x M, wherein H is the number of gate lines for driving the sub-pixels in the display panel, M is the number of clock signal lines for driving the sub-pixels, and K is the sum of the numbers of the first control sub-circuit and the second control sub-circuit.

Optionally, the first control circuit further includes: the output ends of the input control sub-circuits are connected with the input ends of the N cascaded control sub-circuits; the input end and the control end of the input control sub-circuit are configured to access the first working level in the first stage; the input control sub-circuit is configured to be turned on after the control end of the input control sub-circuit receives the first operation level, and to output the first operation level to the input ends of the N cascaded control sub-circuits.

Optionally, the input control sub-circuit includes a fourth transistor, and an output end of the fourth transistor is connected with input ends of the N cascaded control sub-circuits; the input terminal and the grid electrode of the fourth transistor are configured to be connected to the first working level in the first stage; the fourth transistor is configured such that a gate of the fourth transistor is turned on upon receiving the first operation level, and outputs the first operation level to the N control sub-circuits.

Optionally, the first operating level, the second operating level, and the first driving level are high, and the second driving level is low.

According to the second aspect, based on the same inventive concept, the present application provides, through an embodiment, the following technical solutions:

a gate driving circuit for driving a display panel, the gate driving circuit comprising: h shift registers according to any one of the first aspect, wherein the pull-up control levels of the H shift registers are different, and H is the number of gate lines for driving the sub-pixels in the display panel.

In a third aspect, based on the same inventive concept, the present application provides, by an embodiment, the following technical solutions:

A display device comprising the gate driving circuit described in the foregoing second aspect.

According to the fourth aspect, based on the same inventive concept, the present application provides, through an embodiment, the following technical solutions:

a driving method for driving the shift register according to any one of the preceding first aspects, the driving method comprising:

in response to the N control sub-circuits receiving preset N pull-up control levels in a first stage, the N control sub-circuits are conducted, and each control sub-circuit corresponds to one pull-up control level; in response to the N control sub-circuits being turned on in a first stage, the first control circuit writes a first operating level to the pull-up node; the output circuit outputs a first driving level in a second stage and outputs a second driving level in a third stage in response to the pull-up node being written with a first operating level; the second control circuit writes a second operating level to the pull-down node at a fourth stage to reset the pull-up node.

The shift register, the grid driving circuit and the driving method provided by the embodiment of the application can drive the pixel rows of the display panel based on the shift register structure, and can realize the display driving and the random compensation of one frame of picture; in addition, the shift register controls the output control of the driving level through N control sub-circuits, an independent random compensation circuit is not needed, the number of TFT devices is reduced, and the circuit area is reduced; the scheme is based on N control sub-circuits for control, so that independent driving of each row of sub-pixels can be realized, cascading is not needed when a grid driving circuit is formed, driving logic is simplified, and driving efficiency is improved.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

fig. 1 is a schematic diagram of a first gate driving circuit according to an embodiment of the invention;

FIG. 2 is a schematic diagram illustrating a first shift register according to an embodiment of the present invention;

FIG. 3 is a timing diagram of driving the shift register of FIG. 2;

FIG. 4 is a schematic diagram illustrating a second shift register according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of N control sub-circuits according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a first control sub-circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a second control sub-circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a first implementation of 10 control sub-circuits in an embodiment of the present invention;

FIG. 9 is a schematic diagram of a second implementation of 10 control sub-circuits in an embodiment of the present invention;

FIG. 10 is a schematic diagram of a first implementation of a third control sub-circuit in an embodiment of the present invention;

FIG. 11 is a schematic diagram of a second implementation of a third control sub-circuit in an embodiment of the present invention;

FIG. 12 is a schematic diagram of a third implementation of 10 control sub-circuits in an embodiment of the invention;

FIG. 13 is a schematic diagram of an input control sub-circuit according to an embodiment of the present invention;

FIG. 14 is a schematic diagram showing a third shift register according to an embodiment of the present invention;

FIG. 15 is a schematic diagram illustrating a fourth shift register according to an embodiment of the present invention;

FIG. 16 is a timing diagram of driving the shift register of FIG. 15;

FIG. 17 is a schematic diagram showing a fifth shift register according to an embodiment of the present invention;

FIG. 18 is a timing diagram of driving the shift register of FIG. 17;

FIG. 19 is a schematic diagram showing a sixth shift register according to an embodiment of the present invention;

FIG. 20 is a timing diagram of driving the shift register of FIG. 19;

fig. 21 is a schematic diagram of a first gate driving circuit according to an embodiment of the present invention;

fig. 22 is a flowchart of a driving method according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Referring to fig. 1, in an embodiment of the present invention, a gate driving circuit 100 is provided, where the gate driving circuit 100 includes a plurality of cascaded shift registers, and fig. 1 only shows a shift register A1, a shift register A2, a shift register A3, a shift register A4, a shift register A5, and a shift register A6. Taking a 6CLK (6 clock signal line driving) driving as an example, the clock signal lines include a first clock signal line CLKE1, a second clock signal line CLKE2, a third clock signal line CLKE3, a fourth clock signal line CLKE4, a fifth clock signal line CLKE5, and a sixth clock signal line CLKE6; the 6 clock signal lines correspondingly transmit a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal and a sixth clock signal. The first 6 stages of the cascade relationship of the gate driving circuit 100 may be as follows:

The clock signal input end of the first-stage shift register A1 is connected with a first clock signal line CLKE1, and the shift signal output end of the first-stage shift register A1 is connected with the shift signal input end of the third-stage shift register A3 and the shift signal input end of the fourth-stage shift register A4; the clock signal input end of the second stage shift register A2 is connected with a second clock signal line CLKE2; the clock signal input end of the third-stage shift register A3 is connected with a third clock signal line CLKE3, and the shift signal output end of the third-stage shift register A3 is connected with the shift signal input end of the fifth-stage shift register A5 and the shift signal input end of the sixth stage; the clock signal input end of the fourth stage shift register A4 is connected with a fourth clock signal line CLKE4; the clock signal input end of the fifth stage shift register A5 is connected with a fifth clock signal line CLKE5; the clock signal input terminal of the sixth stage shift register is connected to the sixth clock signal line CLKE6.

In addition, referring to fig. 2, the shift register for any stage may include: the blanking circuit 11, the first control circuit 12, the second control circuit 13, the third control circuit 14, the fourth control circuit 15, the fifth control circuit 16, the first reset circuit 18, the second reset circuit 20, the third reset circuit 21, the fourth reset circuit 22, the fifth reset circuit 23, the first output circuit 25, the second output circuit 26, the third output circuit 27, the pull-up node Q, and the pull-down node QBA.

Wherein the output end of the blanking circuit 11, the output end of the first control circuit 12 are all connected to the pull-up node Q, the input ends of the first reset circuit 18 and the second reset circuit 20 are all connected to the pull-up node Q, the output end of the second control circuit 13 and the input end of the third control circuit 14 are all connected to the pull-down node QBA, the input ends of the third control circuit 14, the fourth control circuit 15 and the fifth control circuit 16 are all connected to the pull-down node QBA, the input end of the second reset circuit 20 is connected to the pull-up node Q, the control end of the second reset circuit 20 is connected to the pull-down node QBA, the control ends of the third reset circuit 21, the fourth reset circuit 22 and the fifth reset circuit 23 are all connected to the pull-down node QBA, the input end of the third reset circuit 21 is connected to the first output node of the first output circuit 25, the input end of the fourth reset circuit 22 is connected to the second output node of the second output circuit 26, the input end of the fifth reset circuit 23 is connected to the third output node of the third output circuit 27, and the control end of the first output circuit 25, the second output circuit 26 and the third output circuit 27 are all connected to the pull-up node Q.

The first, second and third output circuits 25, 26 and 27 output under the level control of the pull-up node Q and reset under the level control of the pull-down node QBA.

Further, with continued reference to fig. 2, in this implementation, the shift register includes first through twenty-second transistors M22. The blanking circuit 11 includes a first transistor M1, a sensing cascode node H, a second transistor M2, and a third transistor M3; the output end of the first transistor M1 is connected to the sensing cascade node H, the gate end of the first transistor M1 is configured to be connected to an output enable signal OE, the output end of the first transistor M1 is connected to the gate end of the second transistor M2, the input end of the first transistor M1 is configured to be connected to a corresponding shift signal, the input end of the second transistor M2 is configured to be connected to a corresponding clock signal, and the output end of the second transistor M2 is connected to a pull-up node Q through a third transistor M3; the control terminal of the third transistor M3 is configured to access the corresponding shift signal.

The first reset circuit 18 includes a fourth transistor M4, an input terminal of the fourth transistor M4 is connected to the pull-up node Q, an output terminal of the fourth transistor M4 is configured to be connected to the first low level signal (VGL 1), and a gate terminal of the fourth transistor M4 is configured to be connected to the global reset signal TRST.

The first control circuit 12 includes a fifth transistor M5, the gate terminal and the input terminal of the fifth transistor M5 are configured to be connected to corresponding shift signals, and the output terminal of the fifth transistor M5 is connected to the pull-up node Q.

The third control circuit 14 includes a sixth transistor M6, a gate terminal of the sixth transistor M6 is configured to be connected to a corresponding shift signal, an output terminal of the sixth transistor M6 is connected to the pull-up node Q, and an output terminal of the sixth transistor M6 is configured to be connected to the first low level signal (VGL 1).

The second control circuit 13 includes a seventh transistor M7 and an eighth transistor M8, the gate terminal and the input terminal of the seventh transistor M7 being configured to be connected to the reference voltage, the output terminal of the seventh transistor M7 being connected to the pull-down node QBA; the control terminal of the eighth transistor M8 is connected to the pull-up node Q, the input terminal of the eighth transistor M8 is connected to the pull-down node QBA, and the output terminal of the eighth transistor M8 is configured to be connected to the first low level signal (VGL 1).

The second reset circuit 20 includes a ninth transistor M9 and a tenth transistor M10, input terminals of the ninth transistor M9 and the tenth transistor M10 are each connected to the pull-up node Q, output terminals of the ninth transistor M9 and the tenth transistor M10 are each configured to be connected to the first low level signal (VGL 1), and a gate terminal of the tenth transistor M10 is connected to the pull-down node QBA.

The fourth control circuit 15 includes an eleventh transistor M11 and a twelfth transistor M12, an input terminal of the eleventh transistor M11 is connected to the pull-down node QBA, an output terminal of the eleventh transistor M11 is connected to the input terminal of the twelfth transistor M12, an output terminal of the twelfth transistor M12 is configured to be connected to the first low level signal (VGL 1), a gate terminal of the eleventh transistor M11 is configured to be connected to the corresponding clock signal, and a gate terminal of the twelfth transistor M12 is connected to the sensing cascode node H.

The fifth control circuit 16 includes a thirteenth transistor M13, an input terminal of the thirteenth transistor M13 is connected to the pull-down node QBA, an output terminal of the thirteenth transistor M13 is configured to be connected to the first low level signal (VGL 1), and a gate terminal of the thirteenth transistor M13 is configured to be connected to the corresponding shift signal.

The first output circuit 25 includes a fourteenth transistor M14, the gate terminal of the fourteenth transistor M14 is connected to the pull-up node Q, the input terminal of the fourteenth transistor M14 is configured to be connected to a corresponding clock signal, and the output terminal of the fourteenth transistor M14 is connected to the first output node. The third reset circuit 21 includes a fifteenth transistor M15 and a sixteenth transistor M16, input terminals of the fifteenth transistor M15 and the sixteenth transistor M16 are connected to the first output node, output terminals of the fifteenth transistor M15 and the sixteenth transistor M16 are configured to be connected to the first low level signal (VGL 1), and a gate terminal of the fifteenth transistor M15 is connected to the pull-down node QBA.

The second output circuit 26 includes a seventeenth transistor M17, a gate terminal of the seventeenth transistor M17 is connected to the pull-up node Q, an input terminal of the seventeenth transistor M17 is configured to be connected to a corresponding clock signal, and an output terminal of the seventeenth transistor M17 is connected to the second output node. The fourth reset circuit 22 includes an eighteenth transistor M18 and a nineteenth transistor M19, the input terminals of the eighteenth transistor M18 and the nineteenth transistor M19 are each connected to the second output node, the output terminals of the eighteenth transistor M18 and the nineteenth transistor M19 are each configured to be connected to the second low level signal (VGL 2), and the gate terminal of the eighteenth transistor M18 is connected to the pull-down node QBA.

The third output circuit 27 includes a twentieth transistor M20, the gate terminal of the twentieth transistor M20 being connected to the pull-up node Q, the input terminal of the twentieth transistor M20 being configured to be connected to a corresponding clock signal, and the output terminal of the twentieth transistor M20 being connected to the third output node. The fifth reset circuit 23 includes a twenty-first transistor M21 and a twenty-second transistor M22, the input terminals of the twenty-first transistor M21 and the twenty-second transistor M22 are each connected to the third output node, the output terminals of the twenty-first transistor M21 and the twenty-second transistor M22 are each configured to be connected to the low level signal (VGL 2), and the gate terminal of the twenty-first transistor M21 is connected to the pull-down node QBA. The gate terminal of the twenty-second transistor M22, the gate terminal of the ninth transistor M9, the gate terminal of the sixteenth transistor M16, and the gate terminal of the nineteenth transistor M19 are connected.

Referring to fig. 3, the operation principle of the shift register 10 is described with reference to the signal timings for displaying one frame of image shown in fig. 3, and the 5 th (n=5) example is described.

First, the output enable signal OE and the global reset signal TRST are both high level, and global reset can be performed on the sensing cascade node HH and the pull-up node Q of all rows. Next, in driving one frame (1F) of the screen:

During Display (pixel writing phase), the specific operation for line 5 is as follows:

in the first stage, the shift signal CR < N-2> (CR <3 >) is high to turn on the fifth transistor M5, and the pull-up node Q <5> is written with a high voltage and kept at a high level; at this time, the clock signal CLKD accessed by the first output circuit 25, the clock signal CLKE accessed by the second output circuit 26 and the clock signal CLKF accessed by the third output circuit 27 are all low-level so that the shift signal CR <5> outputted by the first output node, the driving signal G1<5> outputted by the second output node and the driving signal G2<5> outputted by the third output node are all low-level.

In the second stage, the clock signal CLKD accessed by the first output circuit 25, the clock signal CLKE accessed by the second output circuit 26 and the clock signal CLKF accessed by the third output circuit 27 are all at high level. At this time, the pull-up node Q <5> point can be kept at a high level due to the presence of the capacitor C2, the capacitor C3 and the capacitor C4; so that the shift signal CR <5> outputted from the first output node, the driving signal G1<5> outputted from the second output node, and the driving signal G2<5> outputted from the third output node are all high.

In the third stage, the clock signal CLKD accessed by the first output circuit 25, the clock signal CLKE accessed by the second output circuit 26, and the clock signal CLKF accessed by the third output circuit 27 all become high levels. So that the shift signal CR <5> outputted from the first output node, the driving signal G1<5> outputted from the second output node, and the driving signal G2<5> outputted from the third output node are all low. .

In the fourth stage, the shift signal CR < N+4> (CR <9 >) is high to turn on the sixth transistor M6M6, the pull-up node Q <5> is pulled low, and the pull-up node Q is reset.

The sequential shifting completes the Display of all rows during Display (pixel charging phase) and then enters Blank region (Blank phase), i.e., SENSE period. The method comprises the following steps:

during SENSE, the description is also given with the 5 th example.

During Display of the first frame, when the 5 th row outputs the shift signal CR <3>, the output enable signal OE is high level; at this time, the high level signal is written into the sensing cascade node HH <5>, and the high level signal written into the sensing cascade node HH <5> makes the pull-up node Q <5> pulled down by the clock signal CLKA to ensure the stability of the pull-up node Q <5 >.

In the first stage, the clock signal CLKA is high so that the pull-up node Q <5> point is written high, and the pull-up node Q <5> will remain high due to the presence of the capacitor C3 and the capacitor C4.

In the second stage, the clock signal CLKE5 and the clock signal CLKF5 are at high level, and the corresponding output circuits are turned on to bootstrap the pull-up node Q <5>, and the second output node G1<5> and the third output node G2<5> are output at high level.

In the third stage, the clock signal CLKE5 and the clock signal CLKF5 become low, and the second output node G1<5> and the third output node G2<5> become low.

In the fourth stage, the clock signal CLKA goes low, the output enable signal OE and the global reset signal TRST go high, and the sense cascade node HH and the pull-up node Q of all rows are reset to low.

Thus, the driving process during Display and during random SENSE is completed. Details of the implementation of the structure and the driving implementation principle in the foregoing embodiments are not described in detail, and may be understood with reference to the prior art, which are not described herein. Although the gate driving circuit 100 of the above embodiment can effectively perform the functions of gate driving and random compensation, the entire circuit structure is complex in composition, requires a large number of TFT devices, is costly to manufacture, and also requires a large circuit layout area; the design of narrow bezel displays is not favored. In addition, since the shift registers 10 in the gate driving circuit 100 in the above embodiment are in a cascade relationship, the driving step is complicated when driving and random compensation are implemented, and it is difficult to perform independent control for each row of pixels.

Referring to fig. 4 and fig. 5, in order to solve the technical problem in the above embodiment, in yet another embodiment of the present invention, there is further provided a shift register 200, where the shift register 200 includes a first control circuit 210, a second control circuit 220, and an output circuit 230; the first control circuit 210 includes N control sub-circuits 21 in cascade, N being a positive integer not less than 2; as shown in fig. 5, the N control sub-circuits 21 are a control sub-circuit (1), a control sub-circuit (2), a … …, a control sub-circuit (N-1), and a control sub-circuit (N), respectively. An output terminal of the first control circuit 210 is connected to the pull-up node Q, an output terminal of the second control circuit 220 is connected to the pull-down node QB, and a control terminal of the output circuit 230 is connected to the pull-up node Q.

The N control sub-circuits 21 are configured to be turned on after receiving preset N pull-up control levels in the first stage, and each control sub-circuit corresponds to a pull-up control level; the first control circuit 210 is configured to write the first operating level to the pull-up node Q after the first stage N of control sub-circuits 21 are turned on; the output circuit 230 is configured to output the first driving level in the second stage and the second driving level in the third stage after the pull-up node Q is written with the first operation level; the second control circuit 220 is configured to write the second operating level to the pull-down node QB in the fourth stage to reset the pull-up node Q. Thus, the display driving and the random compensation of one frame of picture can be realized by driving based on the structure of the shift register 200; in addition, the shift register 200 controls the output control of the driving level through N control sub-circuits 21, and a separate random compensation circuit is not needed, so that the number of TFT devices is reduced, and the circuit area is reduced; the scheme is based on the control of N control sub-circuits 21, so that independent driving of each row of sub-pixels can be realized, cascading is not needed when a grid driving circuit is formed, driving logic is simplified, and driving efficiency is improved. Next, implementation details of the shift register 200 in this embodiment will be described in detail.

It will be appreciated that the input of the first control circuit 210 is also configured to access a corresponding first operating level; after the first control sub-circuit is turned on, the first operating level is written to the pull-up node Q. The first operating level may be a level of a clock signal; for example, when the driving circuit is turned on at a high level, the first operating level may be at a high level; otherwise, the level may be low. The operating state of the output circuit 230 may be controlled by the level change of the pull-up node Q.

The input of the second control circuit 220 is further configured to access a corresponding second operating level; after the second control circuit 220 is turned on, the second operating level may be written to the pull-down node QB. The second operating level may be a level of a clock signal; for example, the second operation level may be a high level when the pull-up node Q is reset when the pull-down node QB is a high level; otherwise, the level may be low. Whether the pull-up node Q is reset or not can be controlled by a level change of the pull-down node QB.

The output circuit 230 may be configured to access the first driving level or the second driving level and output the corresponding driving level under the control of the pull-up node Q; resetting the output node OUT may also be accomplished under control of the pull-down node QB. The first and second drive levels may be provided by a clock signal, it being understood that the first and second drive levels are inverted. For example, when the gate line of the driven display panel is at a high level, the sub-pixel is charged, and the first driving level may be at a high level and the second driving level may be at a low level.

In some implementations, referring to fig. 6 and 7, the n control sub-circuits 21 include: a first control sub-circuit 211 and/or a second control sub-circuit 212; each pull-up control level includes: a first control level and/or a second control level; the first control level and the second control level are inverted. The first control sub-circuit 211 is configured to turn on after the control terminal of the first control sub-circuit 211 receives a first control level, and the second control sub-circuit 212 is configured to turn on after the control terminal of the second control sub-circuit 212 receives a second control level. It can be understood that the N control sub-circuits 21 can be divided into two conductive types, and if the first control level is a high level and the second control level is a low level, the N control sub-circuits can respectively correspond to the first control sub-circuit 211 that is conductive at the high level and the second control sub-circuit 212 that is conductive at the low level; conversely, if the first control level is low and the second control level is high, the second control sub-circuit 212 and the first control sub-circuit 211 may be turned on at the high level and the low level, respectively.

For example, if the N control sub-circuits 21 are all the first control sub-circuits 211, the number of the first control sub-circuits 211 is N, and the number of the corresponding first control levels is also N. If the N control sub-circuits 21 are all the second control sub-circuits 212, the number of the second control sub-circuits 212 is N, and the number of the corresponding second control levels is also N. If the N control sub-circuits 21 are composed of the first control sub-circuit 211 and the second control sub-circuit 212, the sum of the first control sub-circuit 211 and the second control sub-circuit 212 is N, and the sum of the numbers of the corresponding first control level and second control level is also N. If the N control sub-circuits 21 include the first control sub-circuit 211 and the second control sub-circuit 212, other switch sub-circuits are included; the sum of the numbers of the first control sub-circuit 211, the second control sub-circuit 212 and the other switching sub-circuits is N, and the sum of the numbers of the corresponding first control level, the second control level and the corresponding switching sub-circuits is N.

It should be noted that, whether the first control sub-circuit 211, the second control sub-circuit 212, or the other switch sub-circuits, it should be understood that one first control sub-circuit 211/second control sub-circuit 212/switch sub-circuit corresponds to one switch unit, and each switch unit corresponds to one control level; that is, N switching units are the switching units formed by the first control sub-circuit 211, the second control sub-circuit 212 and the switching sub-circuit, and the switching units are formed in cascade, so that the conduction under a single set of control levels is realized.

With continued reference to fig. 6 and fig. 7, in a specific implementation, the first control sub-circuit 211 may include a first transistor M1, as shown in fig. 6, where the first transistor M1 is configured to be turned on after the gate of the first transistor M1 receives the first control level. The second control sub-circuit 212 includes an inverter 01 and a second transistor M2, as shown in fig. 7, an output terminal of the inverter 01 is connected to a gate of the second transistor M2, an input terminal of the inverter 01 is configured to receive a second control level, and the second transistor M2 is configured to be turned on after the inverter 01 receives the second control level, so that the second transistor M2 can be turned on even when the second control level is inverted from the first control level. Of course, other circuit structures may be added to the above example to process signals, but the effect of conducting can be achieved finally, and the embodiment is not limited.

For example, when N is 10, if all of the 10 control sub-circuits are the first control sub-circuit 211, the first transistor M1 is cascaded as shown in fig. 8, and D0 to D9 are control levels; if the 10 control sub-circuits include 9 first control sub-circuits 211 and 1 second control sub-circuit 220, the cascade relationship is shown in fig. 9, where the cascade position of the second control sub-circuits 212 is not limited.

It should be further noted that the transistor devices mentioned in this embodiment may be all of the same type (including the transistor devices mentioned later), and for example, the transistor devices may be all of high-level conductive transistor devices. In addition, other on-type transistor devices are also possible, and those skilled in the art can use other device combinations to replace the transistors used in the present application based on the practical adaptation to achieve the same function. Therefore, these alternatives should also fall within the scope of coverage of this embodiment.

Referring to fig. 10, in some implementations, the N control sub-circuits 21 may further include: a third control subcircuit 213. The N pull-up control levels further include: and a third control level, which is the same as or opposite to the level at which the input of the second control circuit 220 is connected. The third control level may be a level provided by a clock signal, that is, a combination of N pull-up control levels may be added by different clock signals. In this case, the number of the first control sub-circuits 211 and/or the second control sub-circuits 212 can be reduced, and the same effect can be achieved. It will be appreciated that in such an implementation the third control level may be a clock signal and be the same or opposite to the clock signal that the second control circuit 220 is coupled to. This allows the first control circuit 210 to be turned on by adding the clock signal line. When the implementation mode is adopted, the high level of each clock signal can be partially overlapped (overlap), so that the display refresh rate can be improved; the requirement of high resolution can be satisfied.

Further, in a specific implementation, if the third control level is the same as the level accessed by the input terminal of the second control circuit 220, please continue to refer to fig. 10, the input terminal of the second control circuit 220 may be accessed by the third control level, and after the second control circuit 220 is turned on, the third control level may be written into the pull-down node QB. At this time, the third control sub-circuit 213 may include a third transistor M3, and the third transistor M3 is configured to turn on after receiving the third control level, and write the third control level to the pull-down node QB. If the third control level is opposite to the signal input to the input terminal of the second control circuit 220, referring to fig. 11, the third control sub-circuit 213 is connected to a fourth control level which is opposite to the third control level during the first stage operation, and the fourth control level needs to be inverted to be changed into the third control level. Thus, the third control sub-circuit 213 may comprise a third transistor M3 and an inverter D02, the input of which is configured to be connected to the fourth control level, the output of which is connected to the gate and input of the third transistor M3; the fourth control level may be converted to the third control level after the third transistor M3 is turned on, thereby writing the third control level to the pull-down node QB.

For example, when N is 10, if the 10 control sub-circuits include 9 first control sub-circuits 211 and 1 third control sub-circuit 213, the cascade relationship between the respective sub-circuits is as shown in fig. 12. The cascade position of the third control sub-circuit 213 is not limited.

Referring to fig. 13, in some implementations, the first control circuit 210 further includes: an input control sub-circuit 214, wherein the output end of the input control sub-circuit 214 is connected with the input ends of the N cascaded control sub-circuits 21; the input and control terminals of the input control subcircuit 214 are each configured to be switched on to a first operating level during a first phase. The input control sub-circuit 214 is configured to receive the first operation level from the control end of the input control sub-circuit 214, and then conduct the first operation level to the input end of the cascade connection of the N control sub-circuits 21; the first operating level is then written to the pull-up node Q through the N control sub-circuits 21, thereby adjusting the level of the pull-up node Q.

In some examples, the input control subcircuit 214 may include a fourth transistor M4, as shown in fig. 13. The output end of the fourth transistor M4 is connected with the input ends of the N cascaded control sub-circuits 21; the input and gate of the fourth transistor M4 are both configured to be switched in the first phase to the first operating level. The fourth transistor M4 is configured such that the gate of the fourth transistor M4 is turned on after receiving the first operation level, and outputs the first operation level to the input terminals of the N control sub-circuits 21 stages; the first operating level is then written to the pull-up node Q through the N control sub-circuits 21, thereby adjusting the level of the pull-up node Q.

Referring to fig. 14 and 15, the shift register 200 in the present embodiment may further include a first reset circuit 240, a second reset circuit 250, a third reset circuit 260, and a fourth reset circuit 270; in addition, regarding the second control circuit 220 and the output circuit 230, reference is also made to fig. 14 and 15 for understanding.

In some examples, the second control circuit 220 may include a fifth transistor M5, an output terminal of the fifth transistor M5 being connected to the pull-down node QB, and both a gate and an input terminal of the fifth transistor M5 may be configured to be connected to the second operation level. The fifth transistor M5 is configured such that the gate of the fifth transistor M5 is turned on after receiving the second operation level, and the second operation level is written to the pull-down node QB, thereby adjusting the level of the pull-down node QB.

In some implementations, the shift register 200 can further include a first reset circuit 240; an input terminal of the first reset circuit 240 is connected to the pull-up node Q, an output terminal of the first reset circuit 240 is configured to be connected to a reset level signal, for example, the reset level signal is a low level signal VGL, and a control terminal of the first reset circuit 240 is connected to the global reset signal TRST. In the gate driving circuit composed of the shift registers 200, global reset of each shift register 200 can be achieved at the end of one frame.

In some examples, the first reset circuit 240 may include a sixth transistor M6, an output of the sixth transistor M6 being connected to the pull-up node Q, an output of the sixth transistor M6 being configured to be coupled to the reset level signal, and a gate of the sixth transistor M6 being configured to be coupled to the global reset signal TRST.

The output circuit 230 may include an output sub-circuit 231 and a hold sub-circuit 232.

The input of the output sub-circuit 231 is configured to be switched in either the first drive level or the second drive level, in particular the first drive level may be switched in during the second phase and the second drive level may be switched in during the third phase. An output terminal of the output sub-circuit 231 is connected to the output node OUT, a control terminal of the output sub-circuit 231 is connected to the pull-up node Q, and the output sub-circuit 231 can be turned on or off by changing a level of the node. In some examples, the output subcircuit 231 may include a seventh transistor M7, the input of the seventh transistor M7 being configured to switch in the first drive level in the second phase and the second drive level in the third phase. The control terminal of the seventh transistor M7 is connected to the pull-up node Q, and the output terminal of the seventh transistor M7 is connected to the output node OUT.

A first terminal of the hold sub-circuit 232 is connected to the pull-up node Q, and a second terminal of the hold sub-circuit 232 is connected to the output node OUT. The holding sub-circuit 232 is configured to hold the level of the pull-up node Q unchanged, specifically, to keep the level of the pull-up node Q the same in the second stage and the third stage, so that the output sub-circuit 231 can be continuously turned on and output the corresponding driving level. In some examples, the holding subcircuit 232 may include a capacitor C1. The first terminal of the capacitor C1 is connected to the pull-up node Q, and the output terminal of the capacitor C1 is connected to the output node OUT. When the pull-up node Q writes the first operating level, the level across the capacitor C1 may be synchronized; when the first control circuit 210 is turned off, the pull-up node Q is maintained at the first operating level due to the capacitor C1, so that the on state of the output sub-circuit 231 is maintained.

In some implementations, the shift register 200 also includes a second reset circuit 250 and a third reset circuit 260. An input terminal of the second reset circuit 250 is connected to the pull-up node Q, a gate of the second reset circuit 250 is connected to the pull-down node QB, and an output terminal of the second reset circuit 250 is configured to be connected to a reset level signal; the gate terminal of the third reset circuit 260 is connected to the pull-up node Q, the input terminal of the third reset circuit 260 is connected to the pull-down node QB, and the output terminal of the third reset circuit 260 is configured to be connected to the reset level signal. The second reset circuit 250 is configured to reset the pull-up node Q when the pull-down node QB is written to the second operating level; the third reset circuit 260 is configured to reset the pull-down node QB when the pull-up node Q is written to the first operating level. For example, when the pull-down node QB is written to a high level, the pull-up node Q is reset; the third reset circuit 260 is configured to reset the pull-down node QB when the pull-up node Q is written to a high level.

In some examples, the second reset circuit 250 may include an eighth transistor M8 and the third reset circuit 260 may include a ninth transistor M9. The gate of the eighth transistor M8 and the input terminal of the ninth transistor M9 are both connected to the pull-down node QB, the gate of the eighth transistor M8 and the gate of the ninth transistor M9 are both connected to the pull-up node Q, and the output terminal of the eighth transistor M8 and the output terminal of the ninth transistor M9 are both configured to be connected to the reset level signal. Thereby enabling resetting of the pull-up node Q when the pull-down node QB is written to the second operating level; the pull-down node QB is reset when the pull-up node Q is written to the first operating level.

In some implementations, the shift register 200 may further include a fourth reset circuit 270, an input terminal of the fourth reset circuit 270 being connected to the output node OUT, an output terminal of the fourth reset circuit 270 being configured to be connected to the reset level signal, and a control terminal of the fourth reset circuit 270 being connected to the pull-down node QB. The fourth reset circuit 270 is configured to reset the output node OUT after the pull-down node QB is written to the second operating level.

In some examples, the fourth reset circuit 270 may include a tenth transistor M10, an input terminal of the tenth transistor M10 being connected to the output node OUT, a gate of the tenth transistor M10 being connected to the pull-down node QB, and an output terminal of the tenth transistor M10 being configured to be connected to the reset level signal. The tenth transistor M10 is configured to reset the output node OUT when the pull-down node QB is written to the second operation level.

In some embodiments, since the shift register 200 may be used to drive a display panel, the number of gate lines of the display panel to be driven is denoted as H herein. The number N of controllable control sub-circuits satisfies the following relation when the first control circuit 210 is set:

H≤2 ^K ×M

where H is the number of gate lines for driving the sub-pixels in the display panel, M is the number of clock signal lines for driving the sub-pixels, and K is the sum of the numbers of the first control sub-circuit 211 and the second control sub-circuit 212.

It will be appreciated that since the first control sub-circuit 211 and the second control sub-circuit 212 of the N control sub-circuits 21 are both conductiveAnd turning off two states that can be decoded by a processor, e.g., a Timing Controller (TCON), to implement any combination of pull-up control levels. Therefore, when the sum of the numbers of the first control sub-circuit 211 and the second control sub-circuit 212 is K, it can be corresponding to 2 ^K And (5) a conducting combination state. Further, each clock signal line for driving the sub-pixels may also represent a state, so that when M clock signal lines are provided, all the conduction modes of the first control circuit 210 are provided with 2 ^K X M species. At this time, when the number of gate lines for driving the sub-pixels in the display panel is less than 2 ^K In the case of the x M, it is possible to realize that the gate line of each driving sub-pixel of the display panel corresponds to the conductive combination of only one first control circuit 210. Thereby independently controlling the gate lines of all driving sub-pixels to realize random compensation.

The shift register 200 in this embodiment can be independently controlled by any implementation manner, so as to realize driving and random compensation of the sub-pixel rows of the display panel, without setting an independent random compensation circuit or performing gate driving according to a row-by-row sequence.

The circuit configuration implementation of the shift register 200 described above is only a partial implementation in the present embodiment. It will be appreciated that the functions implemented by the individual transistor devices may be replaced by other equivalent circuits, and will not be described in detail herein. In order to make the operation principle of the shift register circuit in this embodiment easier to understand, a description will be given below by way of specific examples.

In an example, the resolution of the display panel is 4k×2k, and there are 2160 rows of gate lines, each corresponding to a shift register 200, and the number of clock signal lines of the display panel is 4. For this, 10 cascaded control sub-circuits can be provided, so that 2 can be decoded ¹⁰ The display panel is driven in a combined state of x4=4096 pull-up control levels. The pull-up control levels respectively corresponding to the 10 control sub-circuits are recorded as follows: d0, D1, D2, D3, D4, D5, D6, D7, D8, D9. The pull-up control level of D0 to D9 is as follows: 1111111111, which illustrates a shift register 200The control sub-circuits in the bit register 200 may be the first control sub-circuit 211 turned on at a high level, and the first control sub-circuit 211 is implemented with the first transistor M1, the other portions are implemented with the fourth to tenth transistors M10 and the capacitor C1, and the transistor devices are turned on at a high level.

When operating with the circuit configuration of fig. 15 and the operation sequence of fig. 16, the operation procedure is as follows:

the first operating level is provided by the clock signal CLK3, the second operating level is provided by the clock signal CLK1, and the first and second drive levels are provided by the clock signal CLK 4.

In the first stage t1, the clock signal CLK3 turns on the high-level fourth transistor M4, and at this time, D0 to D9 are all at the first control level, i.e. the combination state is 1111111111, and 10 first transistors M1 are turned on. The entire first control circuit 210 is turned on. Accordingly, the pull-up node Q writes the first operation level of the high level supplied by the clock signal CLK3, the seventh transistor M7 is turned on, and the pull-down node QB is maintained at the low level. The clock signal CLK4 is low so that the output circuit 230 outputs the first driving level G <4N > of low level, i.e., G <4> in fig. 16, through the output node OUT.

In the second stage t2, the clock signal CLK4 is high, the pull-up node Q is kept high due to the capacitor C1, the pull-down node QB is kept low, the seventh transistor M7 is kept turned on, and the output circuit 230 outputs the second driving level G <4N > of the high level through the output node OUT.

In the third stage t3, the clock signal CLK4 goes low, the pull-up node Q remains high due to the capacitor C1, the pull-down node QB remains low, the seventh transistor M7 remains turned on, and the output circuit 230 outputs the first driving level G <4N > of the low level through the output node OUT.

In the fourth stage t4, the clock signal CLK1 becomes high so that the pull-down node QB is written high, the eighth transistor M8 and the tenth transistor M10 are turned on, the pull-up node Q is pulled down, and the pull-up node Q is reset; the seventh transistor M7 is turned off and the output node OUT is also reset.

Thus, independent driving and random compensation of each row can be realized as long as the decoded pull-up control level state combination corresponds to whether the display driving or the random compensation is performed, and the gate signal of the only row (gate line) can be obtained to be high. And compared with the first embodiment, the driving logic is greatly simplified, and the driving efficiency is effectively improved.

In an example, the resolution of the display panel is 4k×2k, and there are 2160 rows of gate lines, each corresponding to a shift register 200, and the number of clock signal lines of the display panel is 4. For this, 10 cascaded control sub-circuits can be provided, so that 2 can be decoded ¹⁰ The display panel is driven in a combined state of x4=4096 pull-up control levels. The pull-up control levels respectively corresponding to the 10 control sub-circuits are recorded as follows: d0, D1, D2, D3, D4, D5, D6, D7, D8, D9. The pull-up control level of D0 to D9 is as follows: 0111111111, the control sub-circuit corresponding to the pull-up control level D0 in the shift register 200 needs to be implemented by combining an inverter and a first transistor M1 with a high level being turned on, that is, an output end of the inverter is connected to a gate of the first transistor M1, and an input end of the inverter is connected to the pull-up control level D0 with the low level; the other 9 control sub-circuits may be the first control sub-circuit 211 that is turned on at a high level, and the first control sub-circuit 211 is implemented with the first transistor M1, and the other portions are implemented with the fourth to tenth transistors M10 and the capacitor C1, and the transistor devices are turned on at a high level.

When operating with the circuit configuration of fig. 17 and the operation sequence of fig. 18, the operation procedure is as follows:

In the first stage t1, the clock signal CLK3 turns on the high-level fourth transistor M4, and at this time, D0 to D9 are all at the first control level, i.e. the combination state is 0111111111, and 10 first transistors M1 are turned on. The entire first control circuit 210 is turned on. Accordingly, the pull-up node Q writes the first operation level of the high level supplied by the clock signal CLK3, the seventh transistor M7 is turned on, and the pull-down node QB is maintained at the low level. The clock signal CLK4 is low so that the output circuit 230 outputs the first driving level G <4N > of low level, i.e., G <4> in fig. 18, through the output node OUT.

Likewise, this implementation may also enable independent driving and random compensation for each row.

In an example, the resolution of the display panel is 4k×2k, and there are 2160 rows of gate lines, each corresponding to a shift register 200, and the number of clock signal lines of the display panel is 5. For this, 9 cascaded control sub-circuits can be provided, so that 2 can be decoded ⁹ The display panel is driven in a combination state of x 5=2560 pull-up control levels. The pull-up control levels respectively corresponding to the 10 control sub-circuits are recorded as follows: d0, D1, D2, D3, D4, D5, D6, D7, D8. The first control level of D0-D8 is: 111111111, the control sub-circuits in the shift register 200 may be a first control sub-circuit 211 and a third control sub-circuit 213 which are all turned on at high level, and the first control sub-circuit 211 is implemented by a first transistor M1, and the other parts are implemented by third to tenth transistors M10 and capacitor C1, and the transistor device is turned on at a high level.

When operating with the circuit configuration of fig. 19 and the operation sequence of fig. 20, the operation procedure is as follows:

the first operating level is provided by the clock signal CLK3, the second operating level is provided by the clock signal CLK2, and the third control level is provided by the clock signal CLK 2.

In the first stage t1, the clock signal CLK3 and the clock signal CLK2 are both at high level, so that the third transistor M3 and the fourth transistor M4 are turned on, and at this time, D0-D8 are both at the first control level, i.e. the combination state is 111111111,9 first transistors M1 are turned on. The entire first control circuit 210 is turned on, the pull-up node Q is written with the first operating level of the high level, and the seventh transistor M7 is turned on. The clock signal CLK4 is low so that the output node OUT of the output circuit 230 outputs the first driving level G <4N > of low level, i.e., G <4> in fig. 20.

Likewise, this implementation may also enable independent driving and random compensation for each row. Furthermore, the partial overlap (overlap) of the clock signals used to drive the sub-pixels in this implementation may better achieve high resolution as well as high refresh rates.

It can be seen that the shift register 200 provided in this embodiment adopts N control sub-circuits 21 to control the output control of the driving level, and no separate random compensation circuit is needed, so that the number of TFT devices is reduced, and the circuit area is reduced; the scheme is based on the control of N control sub-circuits 21, so that independent driving of each row of sub-pixels can be realized, cascading is not needed when a grid driving circuit is formed, driving logic is simplified, and driving efficiency is improved.

Note that the high level and the low level mentioned in this embodiment are only relative high or low, and do not represent absolute values. The input and output terminals of the transistor mentioned only represent the input and output terminals with reference to the current direction at a certain moment, and if the current direction changes, the input terminal of the transistor can also change to the output terminal; that is, the input and output of the transistor are not absolutely constant.

Referring to fig. 21, based on the same inventive concept as in the previous embodiment, there is also provided a gate driving circuit 300 for driving a display panel in a further embodiment of the present invention, the gate driving circuit 300 including: h shift registers 200 according to any of the above embodiments, H is the number of gate lines for driving the sub-pixels in the display panel. It is to be understood that only one exemplary partial implementation structure is shown in fig. 21, in which the gate driving circuit 300 is provided with 4 clock signal lines (clock signal line CLK1, clock signal line CLK2, clock signal line CLK3, clock signal line CLK 4), and 10 enable control lines (enable control line D0, enable control line D1, enable control line D2, enable control line D3, enable control line D4, enable control line D5, enable control line D6, enable control line D7, enable control line D8, enable control line D9).

Wherein the pull-up control levels of the H shift registers 200 are different. That is, for any one shift register 200, the N pull-up control levels that make N cascaded control sub-circuits conductive are different from the pull-up control levels corresponding to the other H-1 shift registers 200. In other words, when the N pull-up control levels output one combination, only the first control circuit 210 of one shift register 200 can be turned on.

Taking n=10 as an example, if N pull-up control levels are combined as follows: 1111111111, the shift register A1 is correspondingly turned on; the N pull-up control level combinations are: 0111111111, the shift register A2 is turned on correspondingly. Then, when the 10 pull-up control level outputs are 1111111111, the shift register A1 is conductive and the shift register A2 is non-conductive; when the output of the 10 pull-up control levels is 0111111111, the shift register A2 is conductive, and the shift register A1 is non-conductive; and so on.

The gate driving circuit 300 formed by the shift register 200 in the foregoing embodiment does not need to cascade the shift register 200, so as to reduce the number of TFT devices and the circuit area; driving logic is simplified, and driving efficiency is improved.

It should be noted that, the shift register 200 in the foregoing embodiment is adopted in the gate driving circuit 300 provided in this embodiment, and therefore, the implementation details and the beneficial effects of the gate driving circuit 300 in this embodiment can be specifically referred to the foregoing shift register 200 embodiment. In addition, the implementation details of the gate driving circuit 300 not described in the present embodiment can be implemented with reference to the prior art, and will not be described here again.

Based on the same inventive concept, there is also provided a display device including any of the gate driving circuits 300 of the foregoing embodiments in still another embodiment of the present invention. The display device can be any product or component with a display function, such as a mobile phone, a liquid crystal panel, an OLED panel, electronic paper, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

It should be noted that, in the display device provided in this embodiment, the gate driver in the foregoing embodiment is adopted, and therefore, implementation details and beneficial effects of the display device in this embodiment may be specifically referred to the foregoing gate driver embodiment. In addition, implementation details of the display device, which are not described in the embodiment, may also be implemented with reference to the prior art, and are not described herein.

Referring to fig. 22, based on the same inventive concept, in an embodiment of the present invention, there is further provided a driving method for driving the shift register according to any one of the foregoing embodiments, the driving method including:

step S10: in response to the N control sub-circuits receiving preset N pull-up control levels in a first stage, the N control sub-circuits are conducted, and each control sub-circuit corresponds to one pull-up control level;

step S20: after the N control sub-circuits are conducted in the first stage, the first control circuit is controlled to set the pull-up node to be high level;

step S30: and controlling the output circuit to maintain the high level of the pull-up node and output a first drive signal of the high level in the second stage, and outputting a second drive signal of the low level in the third stage.

In some implementations, the driving method may further include step S40: and controlling the second control circuit to set the pull-down node to be high in the fourth stage so as to reset the pull-up node.

The steps S10-S30 can realize the grid driving of the pixel rows of the display panel, the driving logic is simpler, and the driving efficiency is improved. It should be noted that, since the driving method described in the present embodiment is used to drive the shift register of the foregoing embodiment, the foregoing has been described; therefore, based on the driving method described in the present embodiment, a person skilled in the art can determine more implementation details of the driving method of the present embodiment based on the disclosure in the shift register and the prior art, so that the details are not repeated here.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

Claims

1. A shift register, comprising: a first control circuit and an output circuit; the first control circuit comprises N cascaded control sub-circuits, wherein N is a positive integer not less than 2; the output end of the first control circuit is connected to a pull-up node, and the control end of the output circuit is connected to the pull-up node;

the N control sub-circuits are configured to be conducted after receiving preset N pull-up control levels in the first stage, and each control sub-circuit corresponds to one pull-up control level; the first control circuit is configured to write a first working level to the pull-up node after the N control sub-circuits are conducted in a first stage;

the output circuit is configured to output a first driving level in a second stage and a second driving level in a third stage after the pull-up node is written into a first working level;

the N control sub-circuits include: a first control sub-circuit and/or a second control sub-circuit; the N pull-up control levels include: a first control level and/or a second control level; the first control level and the second control level are inverted;

wherein the first control sub-circuit is configured to turn on after the control terminal of the first control sub-circuit receives the first control level, and the second control sub-circuit is configured to turn on after the control terminal of the second control sub-circuit receives the second control level.

2. The shift register of claim 1, wherein the first control sub-circuit comprises a first transistor configured to turn on after a gate of the first transistor receives the first control level;

the second control sub-circuit comprises an inverter and a second transistor, wherein an output end of the inverter is connected with a gate electrode of the second transistor, an input end of the inverter is configured to receive the second control level, and the second transistor is configured to be turned on after the inverter receives the second control level.

3. The shift register of claim 1, further comprising: the output end of the second control circuit is connected to the pull-down node;

the second control circuit is configured to write a second operating level to the pull-down node to reset the pull-up node in a fourth stage.

4. A shift register as claimed in claim 3, in which the N control sub-circuits further comprise: a third control sub-circuit; the N pull-up control levels further include: the third control level is the same as or opposite to the level accessed by the input end of the second control circuit;

The third control sub-circuit is configured to be turned on after the control end of the third control sub-circuit receives a third control level.

5. The shift register of claim 4, wherein the third control sub-circuit is identical to the level signal coupled to the input of the second control circuit, the third control sub-circuit comprising a third transistor;

the third transistor is configured such that a gate of the third transistor is turned on after receiving the third control level.

6. The shift register of claim 1, wherein N satisfies a relationship for driving the display panel: h is less than or equal to 2 ^K And x M, wherein H is the number of gate lines for driving the sub-pixels in the display panel, M is the number of clock signal lines for driving the sub-pixels, and K is the sum of the numbers of the first control sub-circuit and the second control sub-circuit.

7. The shift register of claim 1, wherein the first control circuit further comprises: the output ends of the input control sub-circuits are connected with the input ends of the N cascaded control sub-circuits; the input end and the control end of the input control sub-circuit are configured to access the first working level in the first stage;

The input control sub-circuit is configured to be turned on after the control end of the input control sub-circuit receives the first operation level, and to output the first operation level to the input ends of the N cascaded control sub-circuits.

8. The shift register of claim 7, wherein the input control sub-circuit comprises a fourth transistor, an output of the fourth transistor being connected to an input of the cascaded N control sub-circuits; the input terminal and the grid electrode of the fourth transistor are configured to be connected to the first working level in the first stage;

the fourth transistor is configured such that a gate of the fourth transistor is turned on upon receiving the first operation level, and outputs the first operation level to the N control sub-circuits.

9. The shift register of claim 1, wherein the first operating level and the first driving level are high and the second driving level is low.

10. A gate driving circuit for driving a display panel, the gate driving circuit comprising: the shift registers according to any one of claims 1 to 9, wherein the pull-up control levels of the H shift registers are different, and H is the number of gate lines for driving the sub-pixels in the display panel.

11. A display device comprising the gate driving circuit as claimed in claim 10.

12. A driving method for driving the shift register according to any one of claims 1 to 9, comprising:

in response to the N control sub-circuits receiving preset N pull-up control levels in a first stage, the N control sub-circuits are conducted, and each control sub-circuit corresponds to one pull-up control level;

in response to the N control sub-circuits being turned on in a first stage, the first control circuit writes a first operating level to the pull-up node;

the output circuit outputs the first driving level in the second stage and outputs the second driving level in the third stage in response to the pull-up node being written to the first operating level.