CN115392158B - Three-dimensional integrated circuit partitioning method and system based on variable neighborhood search algorithm - Google Patents
Three-dimensional integrated circuit partitioning method and system based on variable neighborhood search algorithm Download PDFInfo
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Abstract
The invention relates to the field of integrated circuits, in particular to a three-dimensional integrated circuit partitioning method and system based on a variable neighborhood search algorithm, wherein the method comprises the following steps: defining a target layer number after the three-dimensional integrated circuit containing a plurality of circuit elements and a network is partitioned as m, and dividing the three-dimensional integrated circuit according to a preset graph dividing method to obtain n initial partitions; according to a preset linear sequencing method, carrying out linear sequencing on the initial subareas, and calculating the number of TSVs obtained by each linear sequencing to obtain an initial solution which is the least in number of TSVs and corresponds to the circuit elements and the initial subareas; optimizing the initial solution by using a variable neighborhood search algorithm to obtain a partition result for partitioning; and partitioning the three-dimensional integrated circuit according to the partitioning result. The method converts the three-dimensional partition problem into the minimum cutting problem of the interconnection lines between circuit elements, is more beneficial to implementation, and can obtain the optimal solution of the partition in a shorter time to obtain a more uniform partition area.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a three-dimensional integrated circuit partitioning method and system based on a variable neighborhood search algorithm.
Background
Three-dimensional (3D) integration is a popular technology in the integrated circuit field because it reduces the line length of the integrated circuit, thereby reducing delay, manufacturability and circuit power consumption, and improving the integration level of very large scale integrated circuits (Very Large Scale Integration, VLSI for short). However, as with any new technology, three-dimensional integration has its own problems in that in a three-dimensional circuit, partitions are stacked on top of each other, through-Silicon Vias (TSVs for short) are communication elements between layers, any connection between two non-adjacent partitions may result in the use of multiple TSVs, and the problems with a three-dimensional circuit include loss of TSVs between layers because TSVs are expensive and occupy chip area, thus, it is important to minimize the total number of TSVs in addition to other objects of the integrated circuit (integrated circuit, IC for short) design, such as wire length, routability, and temperature; in addition, minimizing TSVs in three-dimensional circuits can further improve the quality of layout and routing because TSVs are bulky and they occupy a large area of the chip. Therefore, TSVs act as an obstacle in the layout and routing process and may lead to routability congestion, with the size of transistors becoming smaller in recent years, minimizing the total number of TSVs has become one of the major issues in the physical design part of very large scale integrated circuit design.
One of the most effective methods for reducing the number of TSVs is to use an efficient partitioning technique in the physical design stage of an integrated circuit, wherein two-dimensional circuit partitioning is a well-developed field, usually accomplished by a multi-level algorithm, such as hMetis, and the two-dimensional partitioning technique is not suitable for three-dimensional circuit partitioning, but can be a good basis for three-dimensional partitioning. In a three-dimensional circuit, the partitions are stacked on top of each other, and any connection between two non-adjacent partitions results in the use of multiple TSVs. Taking a 5-layer 3D IC as an example, if one terminal of a net of interconnect lines of circuit elements is placed on the top layer and the other terminal is placed on the bottom layer, the net is effectively cut 4 times, and 4 TSVs are required to complete one connection. Thus, the goal of three-dimensional zoning is to minimize the number of webs cut by any horizontal lines drawn between any adjacent layers, there are generally two main optimization goals in designing a three-dimensional zoning: the number of nets between partitions is reduced and the optimal position of the layers is determined, and both optimizations cannot be performed in series, because it is not possible to verify the optimal partition before stacking.
The effect obtained by the existing VLSI three-dimensional partition technology on reducing the number of TSVs is not capable of meeting the industrial requirements in all aspects, and the main problem is that the time spent for reducing the TSVs is too long, the area of each partition is uneven, the waste of chip materials is necessarily caused, and the three-dimensional partition technology cannot be well applied in practical problems.
Disclosure of Invention
The invention provides a three-dimensional integrated circuit partitioning method and system based on a variable neighborhood search algorithm, and aims to solve the problems of long time consumption and uneven partitioning area of the existing three-dimensional partitioning technology.
In a first aspect, an embodiment of the present invention provides a three-dimensional integrated circuit partitioning method based on a variable neighborhood search algorithm, where the three-dimensional integrated circuit partitioning method includes the following steps:
s1, defining a target layer number of a three-dimensional integrated circuit partition comprising a plurality of circuit elements and a network as m, and dividing the three-dimensional integrated circuit according to a preset graph dividing method to obtain n initial partitions;
s2, linearly sequencing the initial subareas according to a preset linear sequencing method, and calculating the number of TSVs obtained by linearly sequencing the initial subareas each time to obtain an initial solution which is the least in number of TSVs after the initial subareas are stacked and corresponds to the initial subareas;
s3, optimizing the initial solution by using a variable neighborhood search algorithm to obtain the final TSV number for partitioning and a partitioning result corresponding to each circuit element;
and S4, partitioning the three-dimensional integrated circuit according to the partitioning result.
Further, the preset map dividing method is based on hmis.
Further, the step of linearly sorting the initial partitions according to a preset linear sorting method, and calculating the number of TSVs obtained by linearly sorting the initial partitions each time, to obtain an optimal value of the TSVs obtained by stacking the initial partitions and an initial solution corresponding to the initial partitions of the circuit element, includes the following sub-steps:
s21, defining a first partition of n initial partitions as a seed layer S, setting the optimal value of TSVs before linear sorting to infinity, and connecting two non-adjacent initial partitions a and b to obtain the number of TSVs as a-b, wherein the number of TSVs satisfies the following calculation formula:
wherein Φ is the set of the mesh, w e Preset weights for the network;
s22, taking the seed layer S as a bottom layer, repeatedly stacking the partitions with the largest TSV number required by connection with the seed layer in the rest initial partitions on the upper layer of the seed layer until all the initial partitions are stacked, and obtaining stacked partitions;
s23, merging every n/m continuous stacking partitions in the stacking partitions to obtain m initial layers;
s24, calculating the total TSV quantity required by m initial layer connections;
s25, comparing the total TSV quantity with the TSV optimal value, and if the value of the total TSV quantity is smaller, giving the value of the total TSV quantity to the TSV optimal value;
s26, in the step S25, if the value of the total TSV number is larger, further judging whether the seed layer S number is the same as the initial partition number n, if so, executing the step S27; if not, adding 1 to the seed layer S value, and iterating to the step S22;
and S27, outputting the result of the optimal value of the TSV, which corresponds to the initial partition, of the circuit element as the initial solution.
Further, the step of optimizing the initial solution by using a variable neighborhood search algorithm to obtain the final TSV number for partitioning and the partitioning result corresponding to each circuit element includes the following substeps:
s31, setting iteration times k, k= (1, …, k) according to the initial solution max )；
S32, taking k=1;
s33, performing kth disturbance on the three-dimensional integrated circuit;
s34, carrying out local search on the three-dimensional integrated circuit according to a variable neighborhood search algorithm to obtain a search solution containing a search TSV value, wherein if the search TSV value is better than the TSV optimal value in the initial solution, the initial solution is replaced by the search solution; if not, directly executing the step S35;
s35, judging whether k is equal to k max If yes, outputting the initial solution to obtain the solution for dividingThe final TSV number of the region and the partition result corresponding to each circuit element; if not, add 1 to k and iterate to step S33.
Further, in step S33, the step of performing the kth perturbation on the three-dimensional integrated circuit specifically includes:
and randomly exchanging the circuit elements at different initial layers, and updating the corresponding relation between the circuit elements and the initial layers and the stress relation of the circuit elements, wherein the stress relation satisfies the following relation:
f ab ＝c a，b (z b -z b ) 0＜a，b＜n；
wherein c a，b Z is the weight between any two of said circuit elements a and b b 、z a The initial layers of the circuit elements b, a, respectively.
Further, in step S34, the step of performing local search on the three-dimensional integrated circuit according to the variable neighborhood search algorithm to obtain a search solution including a search TSV value, where if the search TSV value is better than the TSV optimal value in the initial solution, the step of replacing the initial solution with the search solution includes the following sub-steps:
s341, randomly selecting one circuit element in the three-dimensional integrated circuit, and starting search traversal;
s342, calculating the stress relation of the circuit element, moving the initial layer of the circuit element with the stress relation larger than 0 upwards by one layer, and moving the initial layer of the circuit element with the stress relation smaller than 0 downwards by one layer;
s343, calculating the current TSV searching value to obtain the searching solution;
s344, if the searched TSV value is better than the TSV optimal value in the initial solution, replacing the initial solution with the searched solution;
and S345, replacing the circuit elements to calculate the stress relation until all the circuit elements are traversed.
In a second aspect, an embodiment of the present invention further provides a three-dimensional integrated circuit partitioning system based on a variable neighborhood search algorithm, including:
the diagram dividing module is used for defining the number of target layers after the three-dimensional integrated circuit containing a plurality of circuit elements and the network is partitioned as m, and dividing the three-dimensional integrated circuit according to a preset diagram dividing method to obtain n initial partitions;
the linear sequencing module is used for carrying out linear sequencing on the initial subareas according to a preset linear sequencing method, and calculating the number of TSVs obtained by carrying out linear sequencing on the initial subareas each time to obtain an initial solution which is the least in number of TSVs after the initial subareas are stacked and corresponds to the initial subareas;
the variable domain searching module is used for optimizing the initial solution by using a variable neighborhood searching algorithm to obtain the final TSV number for partitioning and the partitioning result corresponding to each circuit element;
and the partitioning module is used for partitioning the three-dimensional integrated circuit according to the partitioning result.
The invention has the beneficial effects that the mathematical model based on the circuit elements is used as the guidance of the variable neighborhood search, and the circuit elements are directionally moved according to the force, so that the efficiency of the variable neighborhood search is greatly improved while the solving quality is ensured.
Drawings
FIG. 1 is a flow chart of a three-dimensional integrated circuit partitioning method based on a variable neighborhood search algorithm provided by an embodiment of the present invention;
fig. 2 is a schematic diagram of a three-dimensional integrated circuit partitioning system 200 based on a variable neighborhood search algorithm according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a flow chart of a three-dimensional integrated circuit partitioning method based on a variable neighborhood search algorithm according to an embodiment of the present invention, where the three-dimensional integrated circuit partitioning method includes the following steps:
s1, defining a target layer number of the three-dimensional integrated circuit after partitioning, wherein the target layer number is m, and partitioning the three-dimensional integrated circuit according to a preset graph partitioning method to obtain n initial partitions.
Specifically, in the embodiment of the present invention, the three-dimensional partition design in the VLSI very large scale integrated circuit chip is used as an optimization target, where m is known as the target layer number after the three-dimensional integrated circuit partition, and the interconnect lines between the network circuit elements consisting of the interconnect lines between n circuit elements and k circuit elements are used for determining the layer where each circuit element is located, and minimizing the total number of TSVs. Exemplary, the embodiments of the present invention select the standard reference circuit of ISPD 2004 as the three-dimensional integrated circuit optimized by the partitioning method.
Further, the preset map dividing method is based on hmis. The hMetis is used for executing graph partitioning tasks, can calculate 2D partitions through an efficient algorithm and present efficient algorithm running time, and arranges the partitions generated before in a single row by utilizing linear sequencing to minimize the length of connection, so that the number of interconnection lines between any layers is reduced. This therefore reduces the length of the connection and the number of long connections and gives a semi-optimal combination of the partitions that make up the layer, i.e. the initial partition.
S2, linearly sequencing the initial subareas according to a preset linear sequencing method, and calculating the number of TSVs obtained by linearly sequencing the initial subareas each time to obtain an initial solution which is the smallest in number of TSVs after the initial subareas are stacked and corresponds to the initial subareas.
Further, the step of linearly sorting the initial partitions according to a preset linear sorting method, and calculating the number of TSVs obtained by linearly sorting the initial partitions each time, to obtain an optimal value of the TSVs obtained by stacking the initial partitions and an initial solution corresponding to the initial partitions of the circuit element, includes the following sub-steps:
s21, defining a first partition of n initial partitions as a seed layer S, setting the optimal value of TSVs before linear sorting to infinity, and connecting two non-adjacent initial partitions a and b to obtain the number of TSVs as a-b, wherein the number of TSVs satisfies the following calculation formula:
wherein Φ is the set of the mesh, w e Preset weights for the network;
s22, taking the seed layer S as a bottom layer, repeatedly stacking the partitions with the largest TSV number required by connection with the seed layer in the rest initial partitions on the upper layer of the seed layer until all the initial partitions are stacked, and obtaining stacked partitions;
s23, merging every n/m continuous stacking partitions in the stacking partitions to obtain m initial layers;
s24, calculating the total TSV quantity required by m initial layer connections;
s25, comparing the total TSV quantity with the TSV optimal value, and if the value of the total TSV quantity is smaller, giving the value of the total TSV quantity to the TSV optimal value;
s26, in the step S25, if the value of the total TSV number is larger, further judging whether the seed layer S number is the same as the initial partition number n, if so, executing the step S27; if not, adding 1 to the seed layer S value, and iterating to the step S22;
and S27, outputting the result of the optimal value of the TSV, which corresponds to the initial partition, of the circuit element as the initial solution.
And S3, optimizing the initial solution by using a variable neighborhood search algorithm to obtain the final TSV number for partitioning and a partitioning result corresponding to each circuit element.
Further, the step of optimizing the initial solution by using a variable neighborhood search algorithm to obtain the final TSV number for partitioning and the partitioning result corresponding to each circuit element includes the following substeps:
s31, setting iteration times k, k= (1, …, k) according to the initial solution max )；
S32, taking k=1;
s33, performing kth disturbance on the three-dimensional integrated circuit;
s34, carrying out local search on the three-dimensional integrated circuit according to a variable neighborhood search algorithm to obtain a search solution containing a search TSV value, wherein if the search TSV value is better than the TSV optimal value in the initial solution, the initial solution is replaced by the search solution; if not, directly executing the step S35;
s35, judging whether k is equal to k max If yes, outputting the initial solution to obtain the final TSV number for partitioning and a partitioning result corresponding to each circuit element; if not, add 1 to k and iterate to step S33.
Further, in step S33, the step of performing the kth perturbation on the three-dimensional integrated circuit specifically includes:
and randomly exchanging the circuit elements at different initial layers, and updating the corresponding relation between the circuit elements and the initial layers and the stress relation of the circuit elements, wherein the stress relation satisfies the following relation:
f ab ＝c a，b (z b -z b ) 0＜a，b＜n；
wherein c a，b For weighting between any two of said circuit elements a and b，z b 、z a The initial layers of the circuit elements b, a, respectively.
For the force bearing relation, assuming that all the circuit elements belonging to the same initial layer are located at the center of the layer, a one-dimensional placement can be used to assign the position of each circuit element, so that no forces are exerted on each other between the circuit elements belonging to the same layer, and only the connections between the circuit elements belonging to different layers can generate forces. Connection weight c between any two of the circuit elements a，b Equal to the number of connections between the circuit elements, so that the force exerted on one of the circuit elements is equal to the sum of the forces exerted by all the other elements:
f i ＝∑ j f i，j 。
illustratively, in one possible implementation, the pseudo code implementation of the perturbation action in step S33 is as follows:
input: the tier (n) at which each circuit element resides;
aggregate net (N1, N2, N3 … Nm);
and (3) outputting: the tier (n) at which each circuit element resides;
force (n) experienced by each circuit element
Begin；
For k＝1to 30Do；
Randomly selecting two different layers; randomly selecting two circuit elements from the selected layers for switching; updating the force according to the net;
k＝k+1；
End。
the variable neighborhood search algorithm (Variable Neighborhood Search, VNS) used in the embodiment of the invention is a meta-heuristic algorithm and is mainly used for solving the optimization problem, especially for large-scale combination optimization.
Further, in step S34, the step of performing local search on the three-dimensional integrated circuit according to the variable neighborhood search algorithm to obtain a search solution including a search TSV value, where if the search TSV value is better than the TSV optimal value in the initial solution, the step of replacing the initial solution with the search solution includes the following sub-steps:
s341, randomly selecting one circuit element in the three-dimensional integrated circuit, and starting search traversal;
s342, calculating the stress relation of the circuit element, moving the initial layer of the circuit element with the stress relation larger than 0 upwards by one layer, and moving the initial layer of the circuit element with the stress relation smaller than 0 downwards by one layer;
s343, calculating the current TSV searching value to obtain the searching solution;
s344, if the searched TSV value is better than the TSV optimal value in the initial solution, replacing the initial solution with the searched solution;
and S345, replacing the circuit elements to calculate the stress relation until all the circuit elements are traversed.
Illustratively, in one possible implementation, the pseudo code implementation of the local search in step S34 is as follows:
input: the tier (n) at which each circuit element resides;
force (n) experienced by each circuit element;
a set net (N1, N2, N3 … Nm) of nets (interconnections between circuit elements);
and (3) outputting: the tier (n) at which each circuit element resides;
number of TSVs S;
Begin；
S＝Sinit；
For i＝1to n Do；
cell(i,tier(i),force(i))；
If force(i)！＝0；
If force(i)>0；
tier(i)＝tier(i)+1；
Else；
tier(i)＝tier(i)-1；
calculating the number of TSVs after the layers of the circuit element i are replaced, namely S1;
if S1< S; updating the force according to the net set; s=s1; i=1; else;
i＝i+1；
end If；
end If；
end If；
End。
and S4, partitioning the three-dimensional integrated circuit according to the partitioning result.
The invention has the beneficial effects that the mathematical model based on the circuit elements is used as the guidance of the variable neighborhood search, and the circuit elements are directionally moved according to the force, so that the efficiency of the variable neighborhood search is greatly improved while the solving quality is ensured.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a three-dimensional integrated circuit partitioning system 200 based on a variable neighborhood search algorithm according to an embodiment of the present invention, including:
the diagram dividing module 201 is configured to define a target layer number m after a three-dimensional integrated circuit including a plurality of circuit elements and a network is partitioned, and divide the three-dimensional integrated circuit according to a preset diagram dividing method to obtain n initial partitions;
the linear sorting module 202 is configured to perform linear sorting on the initial partitions according to a preset linear sorting method, and calculate the number of TSVs obtained by linear sorting on the initial partitions each time, so as to obtain an initial solution corresponding to the initial partitions and having the minimum number of TSVs after stacking the initial partitions;
the variable domain searching module 203 is configured to optimize the initial solution by using a variable neighborhood searching algorithm to obtain a final TSV number for partitioning, and a partitioning result corresponding to each circuit element;
and the partitioning module 204 is configured to partition the three-dimensional integrated circuit according to the partitioning result.
The three-dimensional integrated circuit partitioning system 200 based on the variable neighborhood search algorithm can implement the steps in the three-dimensional integrated circuit partitioning method based on the variable neighborhood search algorithm in the above embodiment, and can implement the same technical effects, and is not described herein again with reference to the description in the above embodiment.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM) or the like.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
While the embodiments of the present invention have been illustrated and described in connection with the drawings, what is presently considered to be the most practical and preferred embodiments of the invention, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various equivalent modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (6)
1. The three-dimensional integrated circuit partitioning method based on the variable neighborhood search algorithm is characterized by comprising the following steps of:
s1, defining a target layer number of a three-dimensional integrated circuit partition comprising a plurality of circuit elements and a network as m, and dividing the three-dimensional integrated circuit according to a preset graph dividing method to obtain n initial partitions;
s2, linearly sequencing the initial subareas according to a preset linear sequencing method, and calculating the number of TSVs obtained by linearly sequencing the initial subareas each time to obtain an initial solution which is the least in number of TSVs and corresponds to the initial subareas by the circuit elements after the initial subareas are stacked, wherein the step S2 comprises the following substeps:
s21, defining a first partition of n initial partitions as a seed layer S, setting the optimal value of TSVs before linear sorting to infinity, and connecting two non-adjacent initial partitions a and b to obtain the number of TSVs as a-b, wherein the number of TSVs satisfies the following calculation formula:
wherein Φ is the set of the mesh, w e Preset weights for the network;
s22, taking the seed layer S as a bottom layer, repeatedly stacking the partitions with the largest TSV number required by connection with the seed layer in the rest initial partitions on the upper layer of the seed layer until all the initial partitions are stacked, and obtaining stacked partitions;
s23, merging every n/m continuous stacking partitions in the stacking partitions to obtain m initial layers;
s24, calculating the total TSV quantity required by m initial layer connections;
s25, comparing the total TSV quantity with the TSV optimal value, and if the value of the total TSV quantity is smaller, giving the value of the total TSV quantity to the TSV optimal value;
s26, in the step S25, if the value of the total TSV number is larger, further judging whether the seed layer S number is the same as the initial partition number n, if so, executing the step S27; if not, adding 1 to the seed layer S value, and iterating to the step S22;
s27, outputting the optimal value of the TSV and the result corresponding to the initial partition of the circuit element as the initial solution;
s3, optimizing the initial solution by using a variable neighborhood search algorithm to obtain the final TSV number for partitioning and a partitioning result corresponding to each circuit element;
and S4, partitioning the three-dimensional integrated circuit according to the partitioning result.
2. The three-dimensional integrated circuit partitioning method based on a variable neighborhood search algorithm as set forth in claim 1, wherein said preset map partitioning method is based on hmis.
3. The method for partitioning a three-dimensional integrated circuit based on a variable neighborhood search algorithm according to claim 2, wherein the step of optimizing the initial solution using the variable neighborhood search algorithm to obtain a final number of TSVs for partitioning and a partitioning result corresponding to each of the circuit elements comprises the sub-steps of:
s31, setting iteration times k, k= (1, …, k) according to the initial solution max )；
S32, taking k=1;
s33, performing kth disturbance on the three-dimensional integrated circuit;
s34, carrying out local search on the three-dimensional integrated circuit according to a variable neighborhood search algorithm to obtain a search solution containing a search TSV value, wherein if the search TSV value is better than the TSV optimal value in the initial solution, the initial solution is replaced by the search solution; if not, directly executing the step S35;
s35, judging whether k is equal to k max If yes, outputting the initial solution to obtain the final TSV number for partitioning and a partitioning result corresponding to each circuit element; if not, add 1 to k and iterate to step S33.
4. The method for partitioning a three-dimensional integrated circuit based on a variable neighborhood search algorithm according to claim 3, wherein in step S33, the step of performing the kth perturbation on the three-dimensional integrated circuit is specifically:
and randomly exchanging the circuit elements at different initial layers, and updating the corresponding relation between the circuit elements and the initial layers and the stress relation of the circuit elements, wherein the stress relation satisfies the following relation:
f ab ＝c a，b (z b -z a )0＜a，b＜n；
wherein c a，b Z is the weight between any two of said circuit elements a and b b 、z a The initial layers of the circuit elements b, a, respectively.
5. The method for partitioning a three-dimensional integrated circuit based on a variable neighborhood search algorithm according to claim 4, wherein in step S34, the step of performing a local search on the three-dimensional integrated circuit according to the variable neighborhood search algorithm to obtain a search solution including a search TSV value, and wherein if the search TSV value is better than the TSV optimal value in the initial solution, the step of replacing the initial solution with the search solution includes the sub-steps of:
s341, randomly selecting one circuit element in the three-dimensional integrated circuit, and starting search traversal;
s342, calculating the stress relation of the circuit element, moving the initial layer of the circuit element with the stress relation larger than 0 upwards by one layer, and moving the initial layer of the circuit element with the stress relation smaller than 0 downwards by one layer;
s343, calculating the current TSV searching value to obtain the searching solution;
s344, if the searched TSV value is better than the TSV optimal value in the initial solution, replacing the initial solution with the searched solution;
and S345, replacing the circuit elements to calculate the stress relation until all the circuit elements are traversed.
6. A three-dimensional integrated circuit partitioning system based on a variable neighborhood search algorithm, comprising:
the diagram dividing module is used for defining the number of target layers after the three-dimensional integrated circuit containing a plurality of circuit elements and the network is partitioned as m, and dividing the three-dimensional integrated circuit according to a preset diagram dividing method to obtain n initial partitions;
the linear sorting module is used for carrying out linear sorting on the initial partitions according to a preset linear sorting method, calculating the number of TSVs obtained by carrying out linear sorting on the initial partitions each time, and obtaining an initial solution which is related to the minimum number of TSVs after the initial partitions are stacked and corresponds to the circuit elements and the initial partitions, and the linear sorting module is specifically used for executing:
s21, defining a first partition of n initial partitions as a seed layer S, setting the optimal value of TSVs before linear sorting to infinity, and connecting two non-adjacent initial partitions a and b to obtain the number of TSVs as a-b, wherein the number of TSVs satisfies the following calculation formula:
wherein Φ is the set of the mesh, w e Preset weights for the network;
s22, taking the seed layer S as a bottom layer, repeatedly stacking the partitions with the largest TSV number required by connection with the seed layer in the rest initial partitions on the upper layer of the seed layer until all the initial partitions are stacked, and obtaining stacked partitions;
s23, merging every n/m continuous stacking partitions in the stacking partitions to obtain m initial layers;
s24, calculating the total TSV quantity required by m initial layer connections;
s25, comparing the total TSV quantity with the TSV optimal value, and if the value of the total TSV quantity is smaller, giving the value of the total TSV quantity to the TSV optimal value;
s26, in the step S25, if the value of the total TSV number is larger, further judging whether the seed layer S number is the same as the initial partition number n, if so, executing the step S27; if not, adding 1 to the seed layer S value, and iterating to the step S22;
s27, outputting the optimal value of the TSV and the result corresponding to the initial partition of the circuit element as the initial solution;
the variable domain searching module is used for optimizing the initial solution by using a variable neighborhood searching algorithm to obtain the final TSV number for partitioning and the partitioning result corresponding to each circuit element;
and the partitioning module is used for partitioning the three-dimensional integrated circuit according to the partitioning result.
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