CN115391845B

CN115391845B - Key management apparatus and method

Info

Publication number: CN115391845B
Application number: CN202211331430.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2023-01-06
Anticipated expiration: 2042-10-28
Also published as: CN115391845A

Abstract

The application relates to the technical field of key security, and discloses a key management device and a method, wherein the device comprises: a key storage unit for storing a key; isolation circuitry to receive an operation request from a processor: the isolation circuitry denies access to an encryption range address of a key storage unit if the operation request is a read operation for a key, and passes the write operation to the key storage unit if the operation request is a write operation for a key. The embodiment of the application can realize safe and reliable key management in a simple mode.

Description

Key management apparatus and method

Technical Field

The present application relates to the field of key security technologies, and in particular, to a key management device and method.

Background

The key has a wide application in information security, for example, a chip or various electronic devices can encrypt information by using the key to ensure the security of the information.

In some existing solutions, the key is managed by a third-party trusted platform, that is, the key is stored in the third-party trusted platform, and both negotiation and distribution of the key depend on the third-party trusted platform, and when the device needs to use the key, a related request needs to be sent to the third-party trusted platform.

In other existing solutions, the management of the keys is implemented by a local software/hardware solution.

For example, in the solutions such as ARM ATZ or Intel SGX, the operating environment of the processor is divided into a secure environment and an insecure environment, the secret key is stored in the secure environment, the insecure environment cannot directly access the secure environment, and when the secret key needs to be used, a relevant request needs to be initiated by the insecure environment.

For example, there is also a solution of managing keys using a local storage medium, encrypting a key to be stored by an encryption key (e.g., a private key) and storing the generated encrypted information in a storage medium of a device, reading out a decryption key (e.g., a public key) corresponding to the encryption key from a one-time storage unit (e.g., OTP/Efuse) of the device when the key needs to be used, and decrypting the encrypted information using the decryption key to obtain the key for use.

It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.

Disclosure of Invention

The applicant has found that in the above-mentioned prior art solutions for key management, the following problems exist:

for the scheme managed by the third-party trusted platform, key-related communication needs to be performed between the device and the third-party trusted platform, including key request and distribution, which is easily sniffed by hackers, and there is a risk that the information of the communication is intercepted, and even if encrypted communication is performed between the device and the third-party trusted platform, replay attack is easily performed on personnel who know the key solution, and the information security is threatened; in addition, the management rules of the third-party trusted platform are often complicated, the communication setting of the third-party trusted platform is not universal, and the key management scheme cannot be realized by completely meeting the requirement of client privatization.

For such solutions as ARM ATZ or Intel SGX, although dividing the secure environment and the insecure environment to ensure the key security, on one hand, ATZ and SGX require complex software stack assistance, on the other hand, the device is in the secure environment at the first stage of the boot process, if the attacker suspends the boot of the device at this time, the attacker can violently scan all secure areas through external Jtag or other memory scanning tools, and the key storage is no longer secure.

For a solution using a local storage medium to manage keys, an attacker can read the disposable storage unit and the storage medium, whereby the attacker may analyze the encryption key through exhaustive attacks.

In view of at least one of the above problems or similar problems, embodiments of the present application provide a key management apparatus and method that prevent an illegal access to a key in a simple manner and improve the security and reliability of key management.

An embodiment of a first aspect of the present application provides a key management device, including:

a key storage unit for storing a key;

isolation circuitry to receive an operation request from a processor:

in the event that the operation request is a read operation for a key, the isolation circuitry denies access to an encryption bin address of a key storage unit;

in the event that the operation request is a write operation to a key, the isolation circuitry passes the write operation to the key storage unit.

In one or more embodiments of the present invention,

the key storage unit further comprises a verification circuit, the verification circuit verifies the received write operation, and if the verification is passed, the key in the write operation is written into the key storage unit.

In one or more embodiments of the present invention,

the key management device further includes an encryption/decryption circuit that is connected to the key storage unit and performs encryption or decryption using the key stored in the key storage unit.

In one or more embodiments of the present invention,

the isolation circuit includes:

the safety identification module identifies whether the operation address in the operation request is an encryption interval address; and

and the request identification module identifies whether the operation request is a read operation or a write operation when the security identification module identifies that the operation address is an encryption interval address, transfers the write operation to the key storage unit when the identification result is the write operation, and does not transfer the read operation to the key storage unit when the identification result is the read operation.

In one or more embodiments of the present invention,

the isolation circuit further comprises a filtering module, wherein the filtering module receives the operation request when the safety identification module identifies that the operation address is a non-encryption interval address, and receives the reading operation identified by the request identification module when the identification result of the request identification module is the reading operation.

In one or more of the embodiments described herein,

the filtering module returns a failure response message.

In one or more of the embodiments described herein,

the isolation circuit further comprises an acquisition module which acquires operation requests of the bus and inputs the acquired operation requests into the safety identification module.

In one or more of the embodiments described herein,

the key storage unit comprises a static random access register and a one-time storage unit, wherein the static random access register stores a symmetric encryption algorithm key and a certificate, and the one-time storage unit stores an asymmetric encryption algorithm public key.

In one or more embodiments, the apparatus further comprises:

the verification circuit does not perform the verification in a case where the one-time memory cell performs a first write operation.

In one or more embodiments of the present invention,

the symmetric encryption algorithm key and/or the certificate are periodically updated.

In one or more embodiments of the present invention,

and the verification circuit triggers the encryption and decryption circuit to verify the signature in the write operation when receiving the write operation, and writes the key corresponding to the signature in the write operation into the key storage unit when the signature verification passes.

In one or more embodiments of the present invention,

and the processor allocates a memory for the write operation or the read operation, and releases the memory when the check result of the check circuit is check failure or the isolation circuit rejects the read operation or the allocation time of the memory exceeds a preset time.

In one or more embodiments, the key management device further includes:

a memory unit for temporarily storing processing data of the processor;

a direct memory access unit for performing data transmission between different regions of the memory unit or between the memory unit and the encryption and decryption circuit; and

the processor, the encryption and decryption circuit, the memory unit and the direct memory access unit are hung on the bus.

An embodiment of the second aspect of the present application provides a key management method, which is applied to a key management device including a storage unit for storing a key, and includes:

in the case where the operation request from the processor is a read operation for the key, the isolation circuit denies access to the encryption bin address of the key storage unit;

Embodiments of the third aspect of the present application provide a chip, where the chip includes the key management device described in embodiments of the first aspect.

An embodiment of a fourth aspect of the present application provides an electronic device, which includes the key management apparatus described in the embodiment of the first aspect.

One of the beneficial effects of the embodiment of the application lies in: the isolation circuitry denies access to the encryption interval address of the key store by an operation request from the processor. Thus, it is possible to prevent unauthorized access to the key in a simple manner and to improve the security and reliability of key management.

Specific embodiments of the present application are disclosed in detail with reference to the following description and drawings, indicating the manner in which the principles of the application may be employed. It should be understood that the embodiments of the present application are not so limited in scope. The embodiments of the application include many variations, modifications and equivalents within the spirit and scope of the appended claims. Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for assisting understanding of the present application, and do not specifically limit the shapes, the proportional sizes, and the like of the respective members in the present application. The application can be carried out by a person skilled in the art, in the light of the teaching of the application, selecting from a variety of possible shapes and proportional dimensions according to the specific case.

FIG. 1 is a schematic diagram of a key management device according to an embodiment of the present application;

FIG. 2 is another schematic diagram of a key management device of an embodiment of the present application;

FIG. 3 is a schematic diagram of an isolation circuit of an embodiment of the present application;

FIG. 4 is a schematic diagram of a request data format according to an embodiment of the present application;

FIG. 5 is another schematic diagram of a key management device of an embodiment of the present application;

FIG. 6 is a process flow diagram of a write operation according to an embodiment of the present application;

FIG. 7 is a process flow diagram of a read operation in accordance with an embodiment of the present application;

fig. 8 is a schematic diagram of a key management method according to an embodiment of the present application.

Detailed Description

While the present application will be described in detail with reference to the drawings and specific embodiments, it is to be understood that these embodiments are merely illustrative of and not restrictive on the broad invention, and that various equivalent modifications may occur to those skilled in the art upon reading this disclosure and fall within the scope of the appended claims.

In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing different elements by reference, but do not indicate a spatial arrangement or a temporal order of the elements, and the elements should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprising," "including," "having," and the like, refer to the presence of stated features, elements, components, and do not preclude the presence or addition of one or more other features, elements, components, and elements.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Embodiments of the first aspect

An embodiment of a first aspect of the present application provides a key management device, and fig. 1 is a schematic diagram of the key management device according to the embodiment of the present application.

As shown in fig. 1, the key management apparatus 100 includes a key storage unit 101 and an isolation circuit 102.

In this embodiment, the key storage unit 101 is configured to store a key, the isolation circuit 102 is configured to receive an operation request from the processor 200, in a case where the operation request is a read operation for the key, the isolation circuit 102 denies an access to an encryption partition address of the key storage unit 101, and in a case where the operation request is a write operation for the key, the isolation circuit 102 passes the write operation to the key storage unit 101.

As can be seen from the above embodiments, the key storage unit in the key management apparatus 100 is connected to the isolation circuit, the operation request from the processor to the key storage unit is determined by the isolation circuit to be passed to the key storage unit, and the key management apparatus 100 rejects the read operation from the processor 200 to the encryption partition address of the key storage unit through the isolation circuit 102. Thus, it is possible to prevent unauthorized access to the key in a simple manner and to improve the security and reliability of key management.

For example, compared with the existing scheme of performing key management through a third-party trusted platform, the embodiment of the application performs key management by using a local software and hardware management mode, can avoid some defects existing when performing key-related communication with the third-party trusted platform, such as the possibility of being sniffed or attacked by a hacker, and can also omit the complicated communication limitation with the third-party trusted platform.

In addition, compared with the existing software/hardware management scheme, the embodiment of the application also has the advantage of realizing safe and reliable key management in a simple mode.

For example, compared with solutions such as ARM ATZ or Intel SGX, the embodiments of the present application do not need to partition a secure environment and a non-secure environment, and therefore do not need complex software stack assistance, and in addition, solutions such as ARM ATZ or Intel SGX have a risk of key leakage caused by violent scanning by an attacker during startup.

As another example, compared with the existing solution that uses a local storage medium to manage the key, in the embodiment of the present application, the isolation circuit of the hardware rejects the reading operation of the encryption interval address of the key storage unit from the processor, in other words, at least the encryption address space in the key storage unit where the key is stored is invisible to external software or devices, and an attacker cannot acquire the key in the key storage unit through brute force scanning.

In the embodiment of the present application, as shown in fig. 1, the isolation circuit 102 is provided between the key storage unit 101 and the processor 200, and thus, in the case where the processor 200 performs a read/write operation on the key storage unit 101, it is possible to judge the kind of the operation by the isolation circuit 102 and to reject the reading of the encryption section address of the key storage unit 101, whereby it is possible to prevent an illegal access to the key in the key storage unit 101 and to realize secure and reliable key management in a simple manner.

In the embodiment of the present application, the encryption block address is a storage unit in the key storage unit 101 for storing information that cannot be read by an external environment, where the external environment includes external software and hardware, such as a processor. In addition, the key storage unit may further include a non-encrypted section address storage unit, and the storage unit may store various information, for example, information such as another key and a certificate that allow an external environment to access, which is different from the key stored in the encrypted section address, and the present application is not limited thereto.

Fig. 2 is another schematic diagram of a key management device according to an embodiment of the present application.

As shown in fig. 2, the key storage unit 101 may include a verification circuit 103, where the verification circuit 103 verifies the received write operation, and in case of passing the verification, writes the key in the write operation into the key storage unit 101.

Thus, by verifying the write operation by the verification circuit 103, illegal tampering with the key storage unit can be prevented, and the security and reliability of key management can be further improved. The verification circuit 103 may also be a verification unit, and the verification function is realized by software or a combination of software and hardware.

For example, compared with the existing solution that uses a local storage medium to manage a key, in the embodiment of the present application, a key write operation can be verified through a verification circuit, and an attacker cannot maliciously tamper with the storage medium, so that the key can be prevented from being damaged, and the security performance can be improved.

As shown in fig. 2, in one or more embodiments, the key management device 100 further includes an encryption/decryption circuit 104, and the encryption/decryption circuit 104 is connected to the key storage unit 101 and performs encryption or decryption using a key stored in the key storage unit 101. Therefore, hardware encryption and decryption are realized through the encryption and decryption circuit 104, and only the encryption and decryption circuit 104 reads the secret key in the encryption or decryption process, that is, in the encryption or decryption process, the secret key storage unit is invisible to an external software/hardware module, an attacker cannot see secret information on the secret key storage device completely, the possibility of attack through software intervention is avoided, and the safety performance can be further improved. In one or more embodiments, the processor 200 may be a micro control unit MCU or a central processing unit CPU, etc., which is not limited in this application, and the processor executes software to implement corresponding functions, for example, the processor executes key management software to implement key management, the key management software includes, but is not limited to, commands of a key reading operation, a key writing operation, an encryption operation, a decryption operation, etc., and when executing the key management software, the processor executes related commands to control related components to perform corresponding operations. The key management software will be exemplified later.

The respective modules of the key management device 100 and the processor 200 are exemplarily explained below.

In one or more embodiments, the key stored in the key storage unit may be understood as any information that needs to be kept secret, and may be a key of the chip or the device itself, such as a public key, a private key, a key in a symmetric encryption algorithm, a digital certificate (for example, an x.509 certificate generated according to the public key), and the like, and may also be a key of an opposite-end chip or device, where the opposite-end chip or device indicates that information interaction may be performed with a chip or device to which the key storage unit belongs, and may also be a key of a third-party chip or device, which is not limited in this application.

In One or more embodiments, the key storage unit 101 may include a static random access register SRAM and a One-Time storage unit, for example, a One Time Programmable (OTP) memory or an Efuse memory, which is not limited in this application.

In one or more embodiments, the static random access register SRAM stores modifiable keys or key-related information, e.g., the SRAM may store keys, digital certificates, etc. of a symmetric encryption algorithm, both of which may be periodically or aperiodically updated to improve security performance.

In one or more embodiments, the one-time storage unit may be configured to store a fixed key or key information, so that the key can be further prevented from being tampered, and security performance can be improved. For example, the one-time storage unit may be configured to store a public key of the asymmetric cryptographic algorithm, which may also be referred to as a root-of-trust key, and the key information may be a digital certificate generated according to the root-of-trust key.

In one or more embodiments, the write operation of the disposable memory cell may be performed before the disposable memory cell is shipped, and the verification is not performed by the verification circuit if the disposable memory cell performs the first write operation or the disposable memory cell is empty. After the write operation is completed in the one-time memory cell, the write operation may be verified by the verification circuit, for example, when the verification result of the verification circuit is that the write operation target is the one-time memory cell, the verification circuit may reject the write operation to the one-time memory cell, and may return a write failure response signal.

In one or more embodiments, for the SRAM storing the modifiable key or key information, when a write operation is performed on the SRAM, the check circuit may perform a check, and if the check passes, the corresponding write operation is allowed to be performed.

For example, in one or more embodiments, for a key or key information that needs to be written, a digital signature of a sender of the key or key information needs to be carried by a write operation, the verification circuit first determines whether the digital signature is carried, if the determination result is that the digital signature is not carried, the write operation is rejected, a write failure response signal is returned, if the determination result is that the digital signature is carried, the verification circuit verifies the digital signature, and if the verification is passed, the corresponding key or key information is written into the SRAM.

In the embodiment of the present application, the digital signature includes hash digest encryption of a key or key information and encryption by using a private key of a sender, and the verification of the digital signature requires asymmetric decryption and hash digest encryption, and reference may be made to related technologies regarding the digital signature.

In one or more embodiments, the verification circuit may send a trigger signal to the encryption and decryption circuit to control the encryption and decryption circuit to verify the digital signature, and in the case of successful verification, write the corresponding key or key information into the SRAM, otherwise, refuse the write operation, and return a write failure response signal.

In one or more embodiments, the key storage unit itself includes a verification circuit to implement the verification function, that is, the verification circuit may be integrated in the key storage unit, which may improve the integration level and reduce the chip area. However, the present application is not limited thereto, and the verification circuit may be integrated with the isolation circuit, for example.

In one or more embodiments, when the processor performs a corresponding operation, for example, a write operation or a read operation, the processor may allocate a memory for the corresponding operation to construct a corresponding requested data format, where the requested data format may include secret information such as a secret key and a digital signature, and in a case where a verification result of the verification circuit is a verification failure or the isolation circuit rejects the read operation or an allocation time of the memory exceeds a predetermined time, the processor releases the memory, so that, by releasing the secret key, the digital signature, and the like stored in the memory in time, leakage of the secret information can be prevented, and security is improved. In one or more embodiments, the verification circuit verifies the write operation, including verifying whether the write operation carries a digital certificate and verifying a signature of the digital certificate, the verification circuit may be connected to the encryption/decryption circuit, or the verification circuit may send a signal to trigger the encryption/decryption circuit to perform the signature verification of the digital certificate, further, the verification circuit may store a key or key information in the write operation, that is, the verification circuit may include a storage unit to store information, and further, the verification circuit may be connected to the SRAM and the OTP/Efuse in the key storage unit, thereby implementing the write of the key or key information.

In one or more embodiments, the check circuit itself may perform only the check operation, and thus the check circuit may be connected to the isolation circuit, that is, the isolation circuit may check the address of the write operation, and the isolation circuit may transfer the write operation to the check circuit only when the write address of the write operation is the address of the memory cell capable of performing the write operation in the key memory cell, for example, the write address is the address of the SRAM memory, and thus the check circuit does not need an address check function in advance, and the check circuit can be simplified.

In one or more embodiments, the isolation circuit checks the read operation, for example, checks the address of the key storage unit to be read by the read operation, so that the read of the key storage unit which is prohibited from being accessed can be prevented, a shielding function is realized from hardware, and the reliability of preventing password sniffing and preventing attacks can be improved.

In one or more embodiments, the isolation circuit may allow reading of the digital certificate stored in the SRAM and the root-of-trust key in the OTP/Efuse, that is, allow reading of the address space of the storage unit storing the digital certificate and the root-of-trust key, and reject reading requests of other address spaces of the storage unit, but the present application is not limited thereto, for example, the isolation circuit may reject reading requests of all address spaces of the key storage unit, and the isolation circuit may be provided as needed.

In one or more embodiments, the isolation circuit may also check the write operation, for example, check a write address of the write operation, in which case, data carried in the write operation, including a key or key information, may be temporarily stored in the check circuit, and in a case that a check result of the isolation circuit on the write address is passed, for example, the write address is in an address space of the SRAM memory, the check circuit is triggered to perform the check operation, otherwise, a write operation failure response is returned.

That is, both write and read operations of the processor to the key storage unit may be checked by the isolation circuit.

Fig. 3 is a schematic diagram of an isolation circuit according to an embodiment of the first aspect of the present application.

As shown in fig. 3, in one or more embodiments, the isolation circuit 102 may include a security identification module 302 and a request identification module 303.

The security identification module 302 identifies whether the operation address in the operation request is an encryption interval address;

the request identification module 303, when the secure identification module 302 identifies that the operation address is the encrypted extent address, identifies whether the operation request is a read operation or a write operation, passes the write operation to the key storage unit 101 when the identification result is the write operation, and does not pass the read operation to the key storage unit 101 when the identification result is the read operation.

Thus, the isolation circuit 102 can prevent the processor from reading the encryption section address of the key storage unit 101, and improve the security performance of the key management device.

However, the present application is not limited to this, and for example, in the isolation circuit, the request identification module may first identify the type of the read operation, and then the security identification module may identify whether the operation is an operation for the encrypted range address, which is not limited by the present application.

As shown in fig. 3, in one or more embodiments, the isolation circuit 102 further includes a filtering module 304, where the filtering module 304 receives the operation request when the security identification module 302 identifies that the operation address is the non-encrypted section address, and the filtering module 304 receives the read operation identified by the request identification module 303 when the identification result of the request identification module 303 is the read operation, that is, the filtering module 304 is configured to process the operation request of the non-encrypted section address and the read operation of the encrypted section address, so as to improve the processing efficiency of the operation request in a modular processing manner.

In one or more embodiments, the filtering module 304 returns a failure reply message, that is, the filtering module 304 returns a failure reply message if any message is received. For example, when the filtering module 304 receives a read operation of a general address, and the general address is an address storing information such as an accessible key, certificate, etc. in the key storage unit, the filtering module may also read corresponding information according to the read operation and return the corresponding information to the processor. The present application does not limit this, and may be set according to actual needs.

As shown in fig. 3, in one or more embodiments, the isolation circuit 102 may further include an acquisition module 301, where the acquisition module 301 acquires an operation request of the bus, and inputs the acquired operation request into the security identification module 302, and the operation request of the bus may include a data request and address information.

In this embodiment of the application, the acquisition module 301 may receive a request, for example, the acquisition module 301 may receive a request from a bus, that is, the isolation circuit 104 may be connected to the bus, but the application is not limited thereto, and the acquisition module 301 may also receive a request from a processor. In the embodiment of the present application, the request may be a read request or a write request, and the request may include related data and/or address. The following is an exemplary description of the request.

Fig. 4 shows a requested data format according to an embodiment of the first aspect of the present application.

As shown in fig. 4, the request data format may include a request type field, a request service field, a data length field, and a content field, where the request type field may have a length of 1 byte, the request service field may have a length of 1 byte, the data length field may have a length of 2 bytes, and the content field may have a length of any number in a range of 0 to 64 kbytes, but the present application is not limited thereto, and the length of each field may also be set according to actual needs, and the present application is not limited thereto.

In the embodiment of the present application, the request type field indicates the type of the request, for example, 0x80 indicates a write request, i.e., a write operation, and 0x81 indicates a read request, i.e., a read operation, and it is noted that the write request and the read request may also be indicated by other values, which are only exemplarily described herein.

In the embodiment of the present application, the request service field indicates the requested service, for example, 0x70 indicates a key of a symmetric encryption algorithm, 0x71 indicates a digital certificate, such as an x.509 certificate, and 0x72 indicates an asymmetric root key (public key), it should be noted that each service may also be indicated by other values, which are only exemplified herein.

In the embodiment of the present application, the data length field indicates the length of data in the content field in bytes.

In the embodiment of the present application, the content field indicates data or an address carried by the request, for example, when the request type is a write request, the content field may store a key and a digital signature of a symmetric encryption algorithm, or store a digital certificate and a digital signature, or store other types of information that needs to be kept secret, and when the request type is a read request, the content field stores a memory address, and in a case that the key storage unit is successfully read, the memory address is used for storing the read content. In addition, the content field may also carry an address of a key storage unit corresponding to a write operation or a read operation.

In the embodiment of the present application, the security identification module 302 identifies the address space corresponding to the request, in one or more embodiments, the address space of the SRAM and the OTP/Efuse storing the key is an encryption section, and the other address space is a general address space, but the present application is not limited thereto, and the section storing the secret information such as the key prohibited from being read may also be referred to as an encryption section, for example, the address of the key storing the symmetric encryption algorithm in the SRAM is set as the encryption section, and the address storing the public key in the SRAM and the address of the OTP/Efuse may belong to the general address space.

In the embodiment of the present application, when the identification result of the security identification module 302 is the encrypted inter-zone address, the request identification module 303 may perform the next processing, and when the identification result of the security identification module 302 is the general inter-zone address, the filtering module 304 may perform the next processing. Therefore, whether a read operation or a write operation is performed, whether the operation is performed on the key storage unit or not can be firstly identified by the security identification module 302, and the next processing is performed by different modules according to the identification result, so that random access to the key storage unit, especially an encryption interval of the key storage unit, by other uncontrollable hardware can be avoided, in addition, in the case that an address of the key storage unit carrying an error in a request data format or an address written into an address register in the request processing process is wrong, an exception or a security risk caused by writing a key or key information into the wrong address by the write operation can be avoided, and the security risk caused by reading information from an inaccessible encryption interval, especially an address space storing an asymmetric encrypted key for example, can also be avoided.

In this embodiment of the application, when the identification result of the security identification module 302 is the encrypted inter-zone address, the request identification module 303 identifies the type of the request for the encrypted inter-zone address, that is, whether to read or write, when the identification result is write, the request identification module forwards the request, for example, forwards the request to the verification circuit or sends a trigger signal to the verification circuit to perform a verification operation, and when the identification result is read, the request identification module forwards the read request to the filtering module for processing.

In this embodiment, the filtering module 304 filters the general address access and the encryption block read data request, for example, for the general address, the filtering module 304 may output a failure response to avoid an exception caused by an illegal address access, and for the encryption block read data request, the filtering module 304 may also output a failure response to prevent the encryption block read data request, but the present application is not limited thereto, for example, for the encryption block read data request, the filtering module 304 may further identify whether the encryption block address is an address storing readable information (such as a key or a certificate) in the key storage unit, and if so, the filtering module 304 may read corresponding information from the key storage unit and return the read information to a memory address specified in the read request data format, or the filtering module 304 may send a read instruction to the verification circuit to read corresponding information and finally return the read information to a memory address specified in the read request data format, or the encryption and decryption circuit may read corresponding information from the key storage unit and store the read information in a memory address specified in the read request data format, and if not, the filtering module 304 may output a failure response signal to prevent the read request from failing.

In one or more embodiments, the encryption and decryption circuit 104 implements hardware encryption and decryption, and through hardware encryption and decryption, in the encryption or decryption process, only the encryption and decryption circuit 104 reads the secret key, that is, in the encryption or decryption process, the secret key storage unit is invisible to external software/hardware modules, so that an attacker cannot see secret information on the secret key storage device, the possibility of attack through software intervention is eliminated, and the security performance is improved.

In one or more embodiments, the encryption/decryption circuit 104 may perform various encryption/decryption operations, including but not limited to encryption and decryption with a symmetric encryption algorithm (such as AES, SM4, etc.), encryption and decryption with an asymmetric encryption algorithm, and encryption with a hash digest algorithm, which is not limited in this application and may be set according to actual needs.

In the embodiment of the present application, the key management apparatus 100 may be applied to various chips and electronic apparatuses, and in one or more embodiments, the key management apparatus 100 may include other components in addition to the key storage unit 101, the verification circuit 103, the isolation circuit 102, and the encryption and decryption circuit 104 described above.

Fig. 5 is another schematic diagram of a key management device according to an embodiment of the present application.

As shown in fig. 5, the key management device 100 further includes a memory unit 105, a direct memory access unit 106, and a bus 107.

In the embodiment of the present application, the memory unit 105 is used to temporarily store processing data of the processor, including various generated request data, information read from the key storage unit, and the like. The memory unit may be a double data rate synchronous dynamic random access memory DDR, but the application is not limited thereto, and the memory unit may also be other types of memories.

In this embodiment, the DMA unit 106 may be configured to move data in the memory unit 105, and the DMA data channel may include data movement between different memory areas, for example, data movement between the memory area 1 and the memory area 2, and the DMA data channel may also include data movement between the memory area and the encryption/decryption circuit, for example, between the memory area 1 and the encryption/decryption circuit, and between the memory area 2 and the encryption/decryption circuit, for example, data to be encrypted or decrypted in the memory area 1 may be moved to the encryption/decryption circuit first, and after the encryption/decryption circuit completes encryption or decryption, encrypted data or decrypted data may be moved to the memory area 2.

In the present embodiment, a bus 107 is used for communication between different components and data transmission, and for example, as shown in fig. 5, a processor, a cryptographic circuit, a memory unit, and a direct memory access unit may be attached to the bus 107. However, the present application is not limited thereto, and for example, the isolation circuit may be hung on the bus 107, that is, the processor performs communication and data transmission through the bus and the isolation circuit, and the present application is not limited thereto and may be set according to actual needs.

The above has been exemplarily described for each component of the key management apparatus 100, and the following is exemplarily described for a software process flow of each operation of the key management apparatus 100 for performing key management.

FIG. 6 is a process flow diagram of a write operation according to an embodiment of the present application.

As shown in fig. 6, the processing flow of the write operation includes the following steps:

step 601, receiving a certificate or a negotiated key sent by an opposite end, where the key is, for example, an asymmetric encrypted public key or a symmetric encrypted key, or other keys or secret information, which is not limited in this application.

Step 602, allocating a memory, and constructing a request command, where the request command is a write request command, a data format of the write request command is as shown in fig. 3, and specific content and length of each field of the write request command may be determined according to a setting.

Step 603 writes the constructed command to the corresponding register for execution by the processor.

In this step 603, the constructed command may be referred to as a write request data format, and in the case of writing the write request data format into the corresponding register, the execution flow of the processor may include that the corresponding register may write an address register according to the received data, that is, writing an address included in the write request data format into an address register, where the address indicates an address of a key storage unit to be written by a write operation corresponding to the write request data format, and then, the corresponding register may write a trigger register, thereby automatically triggering the request, and carrying the address of the key storage unit to the isolation circuit for further processing, including identification by the security identification module, which may be specifically referred to the above description about the security identification module and the isolation circuit.

At step 604, a status register is polled for a certain period of time, such as a timer may be set.

Step 605, determining whether the instruction execution is successful or whether the instruction execution is overtime through the status register, if the determination result is no, continuing to execute step 604 until the instruction execution is successful or overtime, and then executing step 606.

Step 606, the memory allocated for constructing the request command is released, and the key write request execution is finished.

It can be seen that, in the above writing operation process, the key management software is responsible for writing the request command into the register, and the key management software does not directly operate the key storage unit, and the embodiment of the present application rejects the read operation from the processor 200 for the encryption zone address of the key storage unit through the isolation circuit. Thus, it is possible to prevent unauthorized access to the key in a simple manner, and to improve the security and reliability of key management. In addition, in the case of having the verification circuit, the write operation can be verified by the verification circuit, so as to ensure that the source of the key written into the key storage unit is authentic and has not been tampered, and further improve the security performance.

In the embodiment of the present application, the above-mentioned process flow may be used for writing operation of various keys or key information, including a first write request of OTP/Efuse, a write request of a digital certificate, a write request of a symmetric key, and the like, wherein in the first write request of OTP/Efuse, the verification circuit does not perform the verification process.

FIG. 7 is a process flow diagram of a read operation according to an embodiment of the present application.

As shown in fig. 7, the processing flow of the read operation includes the following steps:

step 701, allocating a memory, and constructing a request command, where the request command is a read request command, a data format of the read request command is as shown in fig. 4, and specific content and length of each field of the read request command may be determined according to settings.

In this embodiment, the memory allocated in step 701 includes a storage space for constructing the read request command itself and a memory space pointed by the content field of the read request command, where the content field in the read request command is an address of the pointed memory for receiving the information read from the key storage unit.

At step 702, the constructed command is written to the corresponding register for execution by the processor. For an exemplary description of the execution flow of the processor in step 702, refer to the description above regarding step 603.

In step 703, a status register is polled for a certain period of time, such as a timer may be set.

Step 704, determining whether the instruction execution is successful or whether the instruction execution is overtime through the status register, and if the determination result is no, continuing to execute step 703 until the instruction execution is successful or overtime, and then executing step 705.

Step 705, releasing the memory allocated for constructing the request command, including constructing the memory space of the request command and the memory space for storing the read information, and ending the execution of the key read request, where the memory space for storing the read information should be released after the read information is sent to the opposite-end software or device.

Therefore, in the reading operation process, the key management software is responsible for writing the reading request command into the register, the key management software does not directly operate the key storage unit, and the reading operation can be checked through the isolation circuit, so that the access to the information stored in the encryption address space is prevented, and the safety performance is improved.

In the embodiment of the present application, the above-described process flow may be used for reading various keys or key information, including a read request of OTP/Efuse, a read request of a digital certificate, and the like.

In this embodiment of the present application, the key management software further includes an encryption/decryption function, and taking the encryption function as an example, the encryption process includes: distributing a memory, constructing an encryption request command, wherein the memory comprises a storage space of the encryption request command and a storage space of data to be encrypted, and can also comprise a space for storing encrypted data, writing the encryption request command into a corresponding register so that a processor executes a corresponding encryption processing instruction, then polling a status register by key software management software until encryption is successful or overtime, and extracting the encrypted data from the storage space of the encrypted data under the condition of successful encryption. The process flow of the decryption function of the key management software is similar and is not described herein.

Therefore, in the encryption and decryption operation process, the key management software is responsible for writing the encryption request command or the decryption request command into the register, in the embodiment of the application, the encryption and decryption circuit of the hardware reads the key from the key storage unit for encryption or decryption, and the key management software does not directly operate the key storage unit in the encryption or decryption processing flow, that is, the key storage unit is invisible to the key management software, so that the possibility of key leakage in the encryption or decryption process is eliminated, and the safety performance is improved.

As is apparent from the above-described embodiment, the key management apparatus 100 rejects a read operation for the encryption bin address of the key storage unit from the processor 200 through the isolation circuit 102. Thus, it is possible to prevent unauthorized access to the key in a simple manner and to improve the security and reliability of key management.

Embodiments of the second aspect

Embodiments of the second aspect of the present application provide a key management method, which is applied to a key management device that includes a storage unit for storing a key, and as the embodiments of the first aspect describe the key management device in detail, the content of the key management device is incorporated herein, and details are not repeated here.

As shown in fig. 8, in one or more embodiments, a key management method includes:

step 801, in the case that the operation request from the processor is a read operation for the key, the isolation circuit denies access to the encryption interval address of the key storage unit;

in step 802, in the event that the operation request is a write operation to a key, the isolation circuitry passes the write operation to the key store.

As can be seen from the above embodiments, a read operation from the processor for the encryption window address of the key store is denied through the isolation circuit. Thus, it is possible to prevent unauthorized access to the key in a simple manner and to improve the security and reliability of key management.

In one or more embodiments, the key management method may further include verifying the received write operation by using a verification circuit in the key storage unit, and in case the verification passes, writing the key in the write operation to the key storage unit. Thus, the verification circuit verifies the write operation, thereby preventing illegal tampering with the key storage unit and further improving the security and reliability of key management.

In one or more embodiments, the key management method may further include encrypting or decrypting, by an encryption/decryption circuit connected to the key storage unit, using the key stored in the key storage unit. Therefore, hardware encryption and decryption are achieved through the encryption and decryption circuit, and only the encryption and decryption circuit reads the secret key in the encryption or decryption process, namely, in the encryption or decryption process, the secret key storage unit is invisible to an external software/hardware module, an attacker cannot see secret information on the secret key storage device completely, the possibility of attack through software intervention is eliminated, and the safety performance can be further improved.

In one or more embodiments, step 802 includes,

step 8021, identifying whether the operation address in the operation request is an encryption interval address; and

step 8022, in a case that the identification result is that the operation address is the encryption zone address, identifying whether the operation request is a read operation or a write operation, in a case that the identification result is the write operation, transferring the write operation to the key storage unit, and in a case that the identification result is the read operation, not transferring the read operation to the key storage unit.

In one or more embodiments, step 802 further comprises,

in the case where the operation address is recognized as the non-encryption section address in step 8021, or in the case where the recognition result in step 8022 is the read operation, the key management apparatus returns a failure response message to the processor.

In one or more embodiments, step 802 further comprises,

an operation request of the bus is collected and the collected operation request is inputted to step 8021.

In one or more embodiments, the key management method further includes that the processor allocates a memory for a write operation or a read operation, and the processor releases the memory when the check result of the check circuit is a check failure or the isolation circuit rejects the read operation or the allocation time of the memory exceeds a predetermined time.

Embodiments of the third aspect

An embodiment of the third aspect of the present application provides a chip, where the chip includes the key management device described in the embodiment of the first aspect, and since the embodiment of the first aspect describes the key management device in detail, the content of the key management device is incorporated herein, and details are not repeated here.

In this embodiment, a chip may also be referred to as an integrated circuit (integrated circuit), a microcircuit (microcircuit), or a microchip (microchip), and the chip may be used in various scenarios or for various purposes, such as a chip for encrypting receiving processing of streaming media, a chip for graphics processing (e.g., a graphics processing chip, etc.), but the present application is not limited thereto and may be any chip with a security requirement, so that by making the chip include the key management device according to the embodiment of the present application, secure and reliable key management can be achieved, and the security of the chip is ensured.

Embodiments of the fourth aspect

An embodiment of a fourth aspect of the present application provides an electronic device, where the electronic device includes the key management device described in the embodiment of the first aspect, and since the embodiment of the first aspect performs detailed description on the key management device, the content of the key management device is incorporated herein, and details are not repeated here.

In the embodiment of the present application, the electronic device may be an electronic device used in various scenarios or implementing various usages, for example, the electronic device may be a computer, but the present application is not limited thereto, and may be any electronic device having a privacy requirement. Therefore, the electronic equipment comprises the key management equipment of the embodiment of the application, so that safe and reliable key management can be realized, and the safety of the electronic equipment is ensured. In one or more embodiments, the electronic device may comprise a chip, and the description of the embodiments of the third aspect can be seen with respect to this chip.

Although the present application provides method steps as described in an embodiment or flowchart, additional or fewer steps may be included based on routine or non-inventive labor. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or client product executes, it may execute sequentially or in parallel (e.g., in the context of parallel processors or multi-threaded processing) according to the embodiments or methods shown in the figures.

As will be appreciated by one of skill in the art, embodiments of the present application may be provided as a method, apparatus (system), or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage media known in the art) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any suitable combination thereof, to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present application in detail, and it should be understood that the above-mentioned embodiments are only examples of the present application and are not intended to limit the scope of the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A key management device, characterized in that the key management device comprises:

a key storage unit for storing a key;

isolation circuitry to receive an operation request from a processor:

2. The key management device according to claim 1,

the key storage unit comprises a verification circuit, the verification circuit verifies the received write operation, and if the verification is passed, the key in the write operation is written into the key storage unit.

3. The key management device according to claim 1 or 2,

4. The key management device according to claim 1,

the isolation circuit includes:

and the request identification module identifies whether the operation request is a read operation or a write operation when the operation address is identified as the encryption interval address by the security identification module, transmits the write operation to the key storage unit when the identification result is the write operation, and does not transmit the read operation to the key storage unit when the identification result is the read operation.

5. The key management device according to claim 4,

the isolation circuit further comprises a filtering module, wherein the filtering module receives the operation request when the security identification module identifies that the operation address is a non-encryption interval address, and receives the reading operation identified by the request identification module when the identification result of the request identification module is the reading operation.

6. The key management device according to claim 5,

the filtering module returns a failure response message.

7. The key management device according to any one of claims 4 to 6,

8. The key management device according to claim 2,

9. The key management device according to claim 8,

10. The key management device according to claim 8,

11. The key management device according to claim 2,

the verification circuit triggers the encryption and decryption circuit to verify a signature in the write operation when receiving the write operation, and writes a key corresponding to the signature in the write operation into the key storage unit when the signature verification passes.

12. The key management device according to claim 2,

13. The key management device according to claim 3, wherein the key management device further comprises:

a memory unit for temporarily storing processing data of the processor;

the direct memory access unit is used for carrying out data transmission between different areas of the memory unit or between the memory unit and the encryption and decryption circuit; and

the processor, the encryption and decryption circuit, the memory unit and the direct memory access unit are connected with the bus in a hanging mode.

14. A key management method applied to a key management apparatus including a storage unit for storing a key, the method comprising:

15. A chip characterized in that it comprises a key management device according to any one of claims 1 to 13.

16. An electronic device characterized in that it comprises a key management device according to any one of claims 1 to 13.