CN115391245A - Bus request arbitration method and chip - Google Patents

Abstract

The embodiment of the application provides a bus request arbitration method and a chip, and the scheme is suitable for various chips comprising ARM and RISC-V instruction set architectures, such as an Internet of things chip, an audio/video chip and the like. The bus request arbitration method comprises the following steps: acquiring a plurality of APB requests sent by a plurality of APB request initiating terminals to an APB request receiving terminal through an APB bus; according to the APB requests, carrying out effective bit setting on vector bits corresponding to the APB request initiating ends in preset vector signals to generate request vector signals; according to the rule of low vector bit and high priority, carrying out polling arbitration on a plurality of effective bits in the request vector signal, and selecting the least effective bit; and determining an APB request initiating end corresponding to the least significant bit, and processing the APB request of the determined APB request initiating end. The scheme can make the priority of the APB request initiating end dynamically variable, and the APB request can be processed relatively uniformly.

Description

Bus request arbitration method and chip

Technical Field

The embodiment of the application relates to the technical field of intelligent chips, in particular to a bus request arbitration method and a corresponding chip.

Background

An APB Bus (Advanced Peripheral Bus) is a Bus for low power consumption peripherals, suitable for peripherals with low bandwidth and without the need for high performance pipelines.

Generally, a master device master and a slave device slave are connected to the APB bus, and the devices exchange signals and data through the APB bus. With the development of the APB bus technology, some chips are now capable of supporting multiple master masters and multiple slave architectures, that is, multiple master masters and multiple slave slaves are connected through the APB bus. Thus, it is necessary to handle the requests from multiple masters master to slave in an arbitration manner, in this case, the master device master is also referred to as an APB request initiator, and the slave device slave is also referred to as an APB request receiver. However, in the conventional arbitration scheme of the master device master with the fixed priority, the request of the master device master with the higher priority is always processed preferentially, so that the requests of other master device masters need to wait for a longer time, thereby causing the problem of unbalanced waiting time of the requests of the master devices.

Disclosure of Invention

Embodiments of the present invention provide a bus request arbitration scheme to at least partially solve the above problems.

According to a first aspect of embodiments of the present application, there is provided a bus request arbitration method, including: acquiring a plurality of APB requests sent by a plurality of APB request initiating terminals to an APB request receiving terminal through an APB bus; according to the APB requests, carrying out effective bit setting on vector bits corresponding to the APB request initiating terminals in preset vector signals, generating request vector signals for indicating the APB request initiating terminals to initiate APB requests, and carrying out displacement processing on the vector signals according to a certain rule; performing polling arbitration on a plurality of effective bits in the request vector signal according to a rule of low vector bits and high priority, and selecting the least effective bit; and determining an APB request initiating end corresponding to the selected least significant bit, and processing the APB request of the determined APB request initiating end.

According to a second aspect of the embodiments of the present application, there is provided a chip, where an APB bus is disposed in the chip, and an arbitration unit is disposed in the APB bus, and the arbitration unit performs APB request arbitration according to the bus request arbitration method of the first aspect.

According to the bus request arbitration scheme provided by the embodiment of the application, different APB requests are processed in a priority polling mode. When a plurality of APB requests initiated by a plurality of APB request initiating terminals are received on the APB bus, the valid bit setting mode is carried out on the vector signal to indicate which APB request initiating terminal initiates the APB request at all. The vector signal comprises a plurality of bit positions, each bit position corresponds to one APB request initiating terminal, so that the effective indication of the APB request and the initiating terminal thereof can be realized, and a foundation is provided for arbitration in a priority polling mode in the scheme of the application. After the valid bits in the vector signal are set and the corresponding request vector signal is generated, the scheme of the embodiment of the application performs polling arbitration on a plurality of valid bits according to a rule of low vector bits and high priority, selects the least significant bit from the valid bits, and processes the APB request of the APB request initiating terminal corresponding to the least significant bit. Therefore, the priority of the APB request initiating terminal is dynamically variable, the APB requests initiated by the APB request initiating terminals can be processed relatively uniformly, and the waiting delay of each initiating terminal is relatively uniform when a plurality of APB request initiating terminals all initiate the APB requests.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a flow chart illustrating steps of a method for bus request arbitration according to an embodiment of the present application;

FIG. 2 is a diagram illustrating a chip using an APB bus in the embodiment shown in FIG. 1;

FIG. 3 is a process diagram of an example of arbitration in the embodiment shown in FIG. 1;

fig. 4 is a process diagram of another example of arbitration in the embodiment shown in fig. 1.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application shall fall within the scope of the protection of the embodiments in the present application.

The following further describes specific implementations of embodiments of the present application with reference to the drawings of the embodiments of the present application.

Referring to FIG. 1, a flow chart of steps of a method of bus request arbitration according to an embodiment of the present application is shown.

For convenience of description, in the embodiments of the present application, a chip structure of an APB bus required to be used in the scheme of the present application is first described. Illustratively, a PIC (Platform Interrupt Controller) chip is taken as a specific example, as shown in fig. 2. The PIC based on the APB bus in FIG. 2 supports a plurality of master devices and slave devices, wherein a plurality of APB request initiating terminals are shown as N, and are respectively cluster _0, … … cluster _ N-1, and an APB sync module, an APB matrix module and an APB request receiving terminal (schematically shown as PIC and clint in the figure) are arranged in the PIC. The APB sync module is responsible for a plurality of clusters, namely APB request initiating ends and PICs to synchronize APB and other signals; an APB _ arbiter module in the APB matrix module is responsible for arbitration of the synchronized multiple APBs; and an APB _ fsm module in the APB matrix module is responsible for sending two paths of APBs obtained after arbitration to the pic and clint respectively. Wherein, plic is a platform-level interrupt controller for processing external interrupts; clint is a processor core local interrupt controller used for processing timer interrupts and soft interrupts.

It should be noted that, in the example shown in fig. 2, the APB request receiving end only takes pic and clint as examples, but in practical applications, a person skilled in the art may set more number and more types (including types of non-interrupt signals that process interrupt signal types) of APB request receiving ends according to actual needs, and all of them may be applied to the scheme of the embodiment of the present application.

On this basis, the bus request arbitration method provided by the embodiment of the application comprises the following steps:

step S102: and acquiring a plurality of APB requests sent by a plurality of APB request initiating terminals to an APB request receiving terminal through an APB bus.

In this embodiment, a plurality of APB request initiating terminals are used to initiate a plurality of APB requests to one APB request receiving terminal, and when the number of APB request receiving terminals is multiple, each APB request receiving terminal has a set of arbitration mechanism described in this embodiment, and the bus request arbitration method of this embodiment is used to arbitrate the APB requests.

The APB request sent from the APB request initiator to the APB request receiver via the APB bus may be any request conforming to the APB protocol, including but not limited to an interrupt request, a data transmission or a read/write request, and the like.

In the embodiments of the present application, the numbers "plural" and "plural" relating to "plural" mean two or more unless otherwise specified.

Step S104: and according to the APB requests, carrying out effective bit setting on vector bits corresponding to the APB request initiating terminals in preset vector signals, and generating request vector signals for indicating the APB request initiating terminals to initiate the APB requests.

In the embodiment of the application, the vector signals are set for a plurality of APB request initiating terminals and are composed of a plurality of bit positions, the number of the bit positions can be the same as the number of the APB request initiating terminals, and can also be more than the number of the APB request initiating terminals, so that the APB request initiating terminals are reserved for the subsequent increase of the APB request initiating terminals. However, for convenience of processing, in the embodiment of the present application, the number of bits is kept consistent with the number of APB request initiating terminals, and one bit corresponds to one APB request initiating terminal.

Initially, the values of all bit bits in the vector signal may be set to 0, and when an APB request is initiated, the bit position 1 corresponding to the APB request initiating end that initiates the APB request is set, that is, the effective bit of the vector bit corresponding to the APB request initiating end is set. The vector signal after the valid position setting is the request vector signal.

For example, assuming that there are 5 APB request initiators and the vector signal includes 5 bits, from 0 to 4, initially, the vector signal may be:

0

0

0

0

0

assuming that after 1s, two of the 5 APB request initiators initiate APB requests, for example, the 1 st and the last ones, then at this time, the valid bit is set for the vector signal, and the generated request vector signal is:

1

0

0

0

1

it should be noted that, although bit position 1 is more consistent with the effective bit setting form in practical application, it should be understood by those skilled in the art that initially all bit positions 1, when there is an APB request, the manner of using bit position 0 corresponding to the APB request initiating end corresponding to the APB request is also applicable to the scheme of the embodiment of the present application. In the embodiment of the application, the bit position 1 is selected to realize the effective bit setting.

Step S106: according to the rule of low vector bit and high priority, a plurality of effective bits in the request vector signal are subjected to polling arbitration, and the least effective bit is selected.

Wherein, low vector bits and high priority means that the lower the vector bits (i.e. bit bits) in the vector signal, the higher its priority.

The request vector signal contains a valid bit indicating that an APB request is initiated, e.g., a bit of value 1 in the request vector signal. In the embodiment of the present application, since the arbitration process is performed on the plurality of APB requests initiated by the plurality of APB request initiators, there are a plurality of valid bits.

Based on this, in one possible approach, the round-robin arbitration of the plurality of valid bits in the request vector signal according to the low-vector-bit-high-priority rule may be implemented as: acquiring counting information in a preset counter, and performing shift operation on the request vector signal according to the counting information; and performing polling arbitration on a plurality of effective bits in the request vector signals after the shift operation according to the rule that the low vector bits have high priority. The counter is used for counting the arbitration times, the initial value is 0, and 1 is added every time arbitration is performed. By shifting the request vector signals based on the counting information, the dynamic change and polling of the priorities of a plurality of APB request initiating terminals are realized, and the APB requests of all the APB request initiating terminals can be effectively processed within a reasonable time.

Under the rule of low vector bit and high priority, the lowest bit is selected from a plurality of bits with 1 being set. Further, after the lowest bit is selected, all 0 setting operations can be performed on other bits, so that convenience is provided for subsequent processing.

In addition, as mentioned above, the counter is used to count the number of arbitrations, and each arbitration is incremented by 1, so that in a certain arbitration, it should be the value of the counter updated after the previous arbitration. That is, in acquiring the counting information in the preset counter, the shifting operation of the request vector signal according to the counting information may be implemented as: acquiring counting information which is updated and processed in a preset counter; and performing shift operation on the request vector signal according to the updated counting information to ensure the correctness of the shift operation and further ensure the fairness of processing the APB request.

In another possible way, according to the rule that the low vector bits are high priority, the polling arbitration for the plurality of valid bits in the request vector signal may be implemented as: acquiring a random code generated by a pseudo-random code generator; a plurality of valid bits in the request vector signal are round-robin arbitrated according to a random code, according to a rule that low vector bits are high priority. The number of random codes can be set according to the number of APB request initiators or the number of bit bits of a vector signal. Assuming that there are 5 APB request initiators, five random numbers may be set, for example, 0-4, if the random number is 0, it may be determined that the first APB request initiator is selected, if the random number is 2, it may be determined that the third APB request initiator is selected, and so on. By adopting a random code mode, one valid bit can be randomly selected from a plurality of valid bits, and the APB request initiated by the APB request initiating end corresponding to the valid bit is determined as the APB request to be processed.

However, in some cases, a bit pointed to by the random code may not be a valid bit, e.g. the bit is set to 0 instead of 1, so as to improve the arbitration efficiency and ensure that the valid bit in the request vector signal is selected, in a feasible manner, according to the random code, the polling arbitration for a plurality of valid bits in the request vector signal according to the rule of low vector bits and high priority can be implemented as: judging whether the vector bit corresponding to the random code is a valid bit; if so, determining the arbitration win of the vector bit corresponding to the random code; if not, shifting the request vector signal, and determining that the arbitration of the least significant bit in the request vector signal after the shifting operation wins.

Step S108: and determining the APB request initiating end corresponding to the selected least significant bit, and processing the APB request of the determined APB request initiating end.

Since the request vector signal is usually shifted when the least significant bit is determined, in this case, it cannot be directly determined which of the APB request initiators the APB request indicated by the selected least significant bit corresponds to. For this reason, after the least significant bit is selected, in one possible way, the request vector signal after the shift operation may be subjected to a reset process; determining a corresponding APB request initiating end according to the position of the selected least significant bit in the reset processed request vector signal; and processing the APB request of the determined APB request initiating end. The specific implementation of the reset process for the request vector signal may be implemented by those skilled in the art according to actual needs, and for example, a cyclic left shift or a cyclic right shift is performed. Through the reset processing, the position of each bit in the request vector signal is restored to the position of the original vector signal corresponding to each APB request initiating terminal, and therefore the APB request initiating terminal corresponding to the selected least significant bit can be determined efficiently and quickly. But is not limited thereto, other ways, such as determining the corresponding APB request originator according to the shift bit number, are also applicable.

After determining the APB request initiating terminal, the APB request initiated by the APB request initiating terminal may be processed, for example, the information of the determined APB request initiating terminal may be sent to the target APB request receiving terminal through the gating register; and receiving a response signal returned by the target APB request receiving end.

In addition, as described above, in the method using the counter, the count value in the counter is updated after each arbitration, and therefore, further alternatively, after receiving a reception response from the APB request receiving end that processes the APB request, the count information is updated by adding the count value. For example, a response signal returned by the target APB request receiving end may be returned to the corresponding APB request initiating end through the strobe register; further, the value of the strobe register may be cleared and the count value in the counter may be incremented by 1 for the next arbitration.

The bus request arbitration process in the case of the single APB request receiving side with multiple APB request initiating sides is described below by specific examples.

First, an arbiter (such as an APB _ arbiter module shown in fig. 2) detects psel signals (selecting APB request receiving end valid signals) and enable signals (enabling signals, acting in a transmission cycle) initiated by each APB request initiating end, and determines whether any APB request initiating end initiates an APB request. And if so, generating a request vector signal based on the request signal of a single bit of each APB request initiating end.

Based on the request vector signal, the following description of the arbitration process using two consecutive arbitration flows as an example is shown in fig. 3 and 4, respectively. In fig. 3 and 4, the APB request initiating end is schematically shown as a master, the APB request receiving end is schematically shown as a slave, and six masters are set, which are respectively master0, 1, 2, 3, 4 and 5.

Wherein fig. 3 shows a first arbitration process comprising:

1. this arbitration is the first arbitration, assuming that master0, master3, and master4 initiate APB requests, whose corresponding bit in the request vector signal is set to 1.

2. The request vector signal is circularly shifted to the left according to the count value in the counter, and at this time, the shift is not needed because the count value is 0.

3. And arbitrating a plurality of effective bits in the request vector signal by using a rule of low vector bits and high priority, selecting the least effective bit0 in the arbitration, and setting other bits to be 0.

4. The request vector signal obtained after setting 0 is subjected to a reset process such as a recycle left shift (N-counter value) bit, where N represents the number of masters. At this point, the loop is shifted left by 6 bits with the valid bit still at bit0.

5. And registering the request vector signal obtained after the reset processing into a gating register, wherein the gating register selects a bit, namely an APB request corresponding to the valid bit, and sends the APB request to a slave, and the gating register is equivalent to record a winner of the arbitration, namely a master0.

And 6.Slave replies a ready signal which is returned to the corresponding master through a gating register, namely the master0 arbitrated this time.

7. The strobe register is cleared and the counter +1 is counted and the next arbitration can begin.

FIG. 4 shows a second arbitration process, in FIG. 4, assuming that a new APB request comes after the first time a PSEL0 APB request is processed.

1. The current arbitration is the second arbitration after the first arbitration, and still has APB requests of master0, master3 and master4, wherein the master0 is a new APB request.

2. The count value in the counter is 1 after the last arbitration, and based on this, the request vector signal is circularly shifted left by 1bit.

3. And arbitrating a plurality of effective bits in the request vector signal by using a low vector bit high-priority rule, selecting a least effective bit2 in the arbitration, and setting other bits to be 0.

4. And resetting the request vector signal obtained after setting 0, wherein the request vector signal is effectively shifted to bit3 if the request vector signal is circularly shifted to the left (N-counter value) by bit, namely 5 bits.

5. And registering the request vector signal obtained after the reset processing into a gating register, selecting an APB request corresponding to a bit, namely an effective bit, by the gating register, sending the APB request to a slave, and recording a winner of the arbitration, namely a master3.

And 6.Slave reverts a ready signal which is returned to the corresponding master through the gating register, namely the gating register is returned to the corresponding master3.

7. The strobe register is cleared and the counter +1 is counted, and the next arbitration can begin.

Through the above two arbitration processes, it can be seen that the count value of the arbitration counter will be increased by 1 every time the arbitration is completed; the increment of the count value is matched with the shifting operation, the master priority is changed once every arbitration, so that the probability of winning each master in multiple arbitrations is relatively average, and the waiting time of each master is relatively balanced when a plurality of APB requests simultaneously appear.

As mentioned above, the above processes are all exemplified by a plurality of APB request initiators and a single APB request receiver, but in practical applications, there is also arbitration in the case of a plurality of APB request initiators and a plurality of APB request receivers. In this case, each APB request receiver has a base address and an address mask. The obtaining of the APB requests from the APB request initiators to the APB request receivers through the APB bus in step S102 may be implemented as: the method comprises the steps of obtaining a plurality of APB requests sent to an APB bus by a plurality of APB request initiating terminals, and determining a plurality of target APB request receiving terminals corresponding to the APB requests based on a base address and an address mask. Specifically, target address information carried by each APB request may be acquired for the APB request; determining a matched base address and address mask according to the target address information; and determining a corresponding target APB request receiving end for the APB request according to the matched base address and the address mask.

Each APB request receiving terminal is configured with the arbitration logic to ensure that different APB request sending terminals cannot block each other when accessing different APB request receiving terminals.

In a specific practical situation, each APB request receiving end, which is indicated as a base address and an address mask of the slave, may be configured in a manner of binding a chip input port, and the arbiter determines to which slave the APB request is to be sent, through the slave base address, the slave address mask, and the paddress in the APB request sent by the master.

For example:

slave0 base address: 6' b100000

slave0 address mask: 6' b111000

slave1 base address: 6' b110000

slave1 address mask: 6' b111000

Wherein 6' means 6 bits.

Suppose paddress in the APB request sent by the master is 6' b100110.

Then:

and (4) judging slave 0: 6'b100000 and 6' b111000= =6'b100110 and 6' b111000

slave1 judgment: 6'b110000 and 6' b111000=/=6'b100110 and 6' b111000

According to the above judgment result, the APB request should be sent to slave0.

Therefore, by the mode, the accuracy of target slave judgment can be effectively ensured under the condition of multiple masters and multiple slaves.

Further, in order to make the arbitration scheme of the present application have better portability so as to be migrated to a similar arbitration scenario, in a feasible manner, the APB bus request arbitration configuration information configured by different numbers of APB request initiators and APB request receivers may also be collected, where the configuration information includes at least one of the following: the number of APB request initiating ends, the number of APB request receiving ends, the bit width of an APB bus, the bit width of APB data and the number of APB interfaces for input and output; and generating the configuration information into a configuration file, wherein the configuration file is used for providing configuration parameters for the chip integration configured with the APB bus.

Therefore, the parameterizable configuration of the chip under the condition of multiple masters and multiple slave based on the APB bus is realized, and the parameterizable configuration can be realized, such as the APB master number, the APB slave number, the APB address bit width, the APB data bit width and the like. When the chip is manufactured based on the determined configuration, the number of input and output APB interfaces can be configured according to the master/slave number, chip integration is carried out after the number is configured, and slave base address and slave address mask are configured. Therefore, the scheme of the embodiment of the application has better adaptability and wide applicability, and can be conveniently transplanted to different scenes.

According to the embodiment of the application, different APB requests are processed in a priority polling mode. When a plurality of APB requests initiated by a plurality of APB request initiating terminals are received on the APB bus, the valid bit setting mode is carried out on the vector signal to indicate which APB request initiating terminal initiates the APB request at all. The vector signal comprises a plurality of bits, and each bit corresponds to an APB request initiating terminal, so that the effective indication of the APB request and the initiating terminal thereof can be realized, and a foundation is provided for arbitration in a priority polling mode in the scheme of the application. After the valid bits in the vector signal are set and corresponding request vector signals are generated, the scheme of the embodiment of the application performs polling arbitration on a plurality of valid bits according to a rule of low vector bits and high priority, selects the least significant bit from the valid bits, and processes an APB request at an APB request initiating terminal corresponding to the least significant bit. Therefore, the priority of the APB request initiating terminal is dynamically variable, the APB requests initiated by each APB request initiating terminal can be relatively and evenly processed, and the waiting delay of each initiating terminal is relatively and evenly balanced when a plurality of APB request initiating terminals initiate the APB requests.

The embodiment of the present application further provides a chip, where an APB bus is disposed in the chip, and an arbitration unit, for example, an APB _ arbiter module shown in fig. 2 is disposed in the APB bus. The arbitration unit can perform the APB request arbitration according to the bus request arbitration method described in the above embodiments.

Illustratively, the chip may be a PIC chip as shown in FIG. 2. The APB _ arbiter module in the PIC chip is responsible for selecting one APB request from the N APB requests according to the access plic and the access clint, and the two APB requests do not influence each other.

The arbitration logic for each APB request uses the round-robin arbitration priority described in the previous method embodiment, and the round-robin priority changes once each time arbitration is completed. For example, the APB request that arbitrates cluster0 for the first time has the highest priority, and the APB request that arbitrates cluster1 for the second time after the transfer is completed has the highest priority.

In conjunction with the example of fig. 3 and 4, psel _0-5 can be used as a vector signal, with the least significant bit first selected by round robin arbitration as a strobe signal. The psel used by each arbitration logic is generated using the synchronously derived psel and paddr, and a gating register is also used for the return of ready. The strobe register cannot be changed until one APB transfer between cluster and PIC is not completed.

After the ready signal of the PIC/clint is generated, the ready _ m of the corresponding client is returned through the strobe register, and the ready _ m _ pulse of the PIC clock domain is synchronized to obtain the ready _ s _ pulse of the cluster clock domain. The ready _ s _ pulse needs to be resynchronized back to the PIC clock domain, and the update of the gating register can be performed after trans _ cpmlt is obtained.

RISC-V is an open source instruction set architecture based on the principle of Reduced Instruction Set (RISC), can be applied to various aspects such as a single chip microcomputer and an FPGA chip, and can be particularly applied to the fields of safety of the Internet of things, industrial control, mobile phones, personal computers and the like, and because the design considers the practical conditions of small size, high speed and low power consumption, the RISC-V is particularly suitable for modern computing equipment such as warehouse-scale cloud computers, high-end mobile phones, micro embedded systems and the like. With the rise of the artificial intelligence internet of things AIoT, the RISC-V instruction set architecture is concerned and supported more and more, and is expected to become the CPU architecture widely applied in the next generation.

The computer operation instruction in the embodiment of the application can be a computer operation instruction based on a RISC-V instruction set architecture, and correspondingly, the arbitration unit can be designed based on the instruction set of the RISC-V. Specifically, the chip provided in the embodiment of the present application may be a chip designed by using a RISC-V instruction set, and the chip may execute an executable code based on a configured instruction, thereby implementing the bus request arbitration method in the above embodiment.

It should be noted that, according to the implementation requirement, each component/step described in the embodiment of the present application may be divided into more components/steps, and two or more components/steps or partial operations of the components/steps may also be combined into a new component/step to achieve the purpose of the embodiment of the present application.

The above-described methods according to embodiments of the present application may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD ROM, a RAM, a floppy disk, a hard disk, or a magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the methods described herein may be stored in such software processes on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware such as an ASIC or FPGA. It will be appreciated that a computer, processor, microprocessor controller, or programmable hardware includes memory components (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by a computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code for implementing the methods illustrated herein, execution of the code transforms the general-purpose computer into a special-purpose computer for performing the methods illustrated herein.

Those of ordinary skill in the art will appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

The above embodiments are only used for illustrating the embodiments of the present application, and not for limiting the embodiments of the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also belong to the scope of the embodiments of the present application, and the scope of the patent protection of the embodiments of the present application should be defined by the claims.

Claims (11)

1. A method of bus request arbitration, comprising:

acquiring a plurality of APB requests sent by a plurality of APB request initiating terminals to an APB request receiving terminal through an APB bus;

according to the APB requests, carrying out effective bit setting on vector bits corresponding to the APB request initiating terminals in preset vector signals, and generating request vector signals for indicating the APB request initiating terminals to initiate APB requests;

performing polling arbitration on a plurality of effective bits in the request vector signal according to a rule of low vector bits and high priority, and selecting the least effective bit from the effective bits;

and determining an APB request initiating end corresponding to the selected least significant bit, and processing the APB request of the determined APB request initiating end.

2. The method of claim 1, wherein performing round robin arbitration on a plurality of valid bits in the request vector signal according to a low vector bit high priority rule comprises:

acquiring counting information in a preset counter, and performing shifting operation on the request vector signal according to the counting information;

and performing polling arbitration on a plurality of effective bits in the request vector signals after the shifting operation according to the rule that low vector bits have high priority.

3. The method of claim 2,

the method further comprises the following steps: after receiving a receiving response of an APB request receiving end for processing the APB request, performing count value increasing updating processing on the counting information;

the obtaining counting information in a preset counter and performing a shift operation on the request vector signal according to the counting information includes: acquiring updated counting information in a preset counter; and carrying out shift operation on the request vector signal according to the updated counting information.

4. The method of claim 1, wherein performing round robin arbitration on a plurality of valid bits in the request vector signal according to a low vector bit high priority rule comprises:

acquiring a random code generated by a pseudo-random code generator;

and performing polling arbitration on a plurality of effective bits in the request vector signal according to the random code and the rule of low vector bits and high priority.

5. The method of claim 4, wherein performing round robin arbitration on a plurality of valid bits in the request vector signal according to the random code and a low vector bit high priority rule comprises:

judging whether the vector bit corresponding to the random code is a valid bit;

if so, determining the arbitration win of the vector bit corresponding to the random code;

if not, shifting the request vector signal, and determining that the least significant bit in the request vector signal after shifting wins arbitration.

6. The method according to claim 2, 3 or 5, wherein the determining the APB request initiator corresponding to the selected least significant bit, and processing the APB request of the determined APB request initiator comprises:

resetting the request vector signal after the shifting operation;

determining a corresponding APB request initiating end according to the position of the selected least significant bit in the reset processed request vector signal;

and processing the determined APB request of the APB request initiating end.

7. The method according to claim 6, wherein the processing the determined APB request of the APB request initiator includes:

sending the determined information of the APB request initiating terminal to a target APB request receiving terminal through a gating register;

and receiving a response signal returned by the target APB request receiving end.

8. The method of claim 1, wherein the APB request receiver comprises a plurality of APB request receivers, each APB request receiver having a base address and an address mask;

the acquiring of the multiple APB requests sent by the multiple APB request initiators to the multiple APB request receivers through the APB bus includes:

and acquiring a plurality of APB requests sent to an APB bus by a plurality of APB request initiating terminals, and determining a plurality of target APB request receiving terminals corresponding to the APB requests based on the base address and the address mask.

9. The method of claim 8, wherein determining a plurality of target APB request receivers to which the plurality of APB requests correspond based on the base address and the address mask comprises:

aiming at each APB request, acquiring target address information carried by the APB request;

determining a matched base address and address mask according to the target address information;

and determining a corresponding target APB request receiving end for the APB request according to the matched base address and the address mask.

10. The method of claim 1, further comprising:

acquiring APB bus request arbitration configuration information under the configuration of different APB request initiating terminal quantity and APB request receiving terminal quantity, wherein the configuration information comprises at least one of the following information: the number of APB request initiating ends, the number of APB request receiving ends, the bit width of an APB bus, the bit width of APB data and the number of APB interfaces for input and output;

and generating the configuration information into a configuration file, wherein the configuration file is used for providing configuration parameters for the chip integration configured with the APB bus.

11. A chip, wherein an APB bus is arranged in the chip, an arbitration unit is arranged in the APB bus, and the arbitration unit performs APB request arbitration according to the bus request arbitration method of any one of claims 1-10.

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