CN115391126A

CN115391126A - Hard disk interface test system, method, device, equipment and medium

Info

Publication number: CN115391126A
Application number: CN202210950147.1A
Authority: CN
Inventors: 黄赐昌; 杨建军; 尹春辉; 钱勇; 王淑瑶
Original assignee: Zhejiang Dahua Technology Co Ltd
Current assignee: Zhejiang Dahua Technology Co Ltd
Priority date: 2022-08-09
Filing date: 2022-08-09
Publication date: 2022-11-25

Abstract

The invention discloses a hard disk interface test system, a method, a device, equipment and a medium, wherein when a first power interface and a second power interface have normal functions, a test circuit supplies power to an SSD module, otherwise, the SSD module is not supplied with power. The test equipment identifies the electrification of the SSD module through the signal interface, determines that the interface of the hard disk to be tested has normal functions, and otherwise determines that the interface of the hard disk to be tested has abnormal functions. According to the scheme provided by the embodiment of the invention, any one of the first power interface and the second power interface has abnormal function, the test circuit does not supply power to the SSD module, and the test equipment determines that the interface of the hard disk to be tested has abnormal function. Therefore, the problem that the standard SSD hard disk cannot detect whether the function of each power interface is abnormal or not can be solved.

Description

Hard disk interface test system, method, device, equipment and medium

Technical Field

The present invention relates to the field of hard disk interface testing technologies, and in particular, to a hard disk interface testing system, method, apparatus, device, and medium.

Background

Monitoring equipment such as a hard disk video recorder, a server and the like all need to use a hard disk, the equipment protects a large number of hard disk interfaces, and the hard disk interfaces need to be tested in the production process. At present, a mechanical hard disk is usually used for verifying whether a hard disk interface of equipment is good, and because a power-on and power-off mode of directly plugging and unplugging a power line is adopted in a testing process, the hard disk is frequently powered on and powered off suddenly, so that the damage rate of the mechanical hard disk is extremely high, and the production cost is increased invisibly.

With the appearance of a Solid State Disk (SSD) and the gradual reduction of cost, a production test may also use the SSD to verify whether a hard Disk interface of the device to be tested is good. Theoretically, the SSD hard disk has relatively strong capacity of resisting sudden power-on and power-off frequently, relatively low damage rate and certain advantages compared with a mechanical hard disk. However, the standard SSD hard disk only needs 5V power supply, and the hard disk interface of the device to be tested includes two sets of power supplies, 12V and 5V, so that the 12V power supply function missing detection risk inevitably exists in the test using the standard SSD hard disk.

Disclosure of Invention

The embodiment of the invention provides a hard disk interface testing system, method, device, equipment and medium, which are used for solving the problem that a standard SSD (solid State disk) can not detect whether the function of each power interface of a hard disk to be tested is abnormal.

The embodiment of the invention provides a hard disk interface test system, which comprises: the device comprises a test device, a hard disk to be tested, a test circuit and a Solid State Disk (SSD) module; the hard disk to be tested comprises a first signal interface, a first power interface and a second power interface; the test equipment comprises a second signal interface; the SSD module comprises a third signal interface;

the test circuit is respectively connected with the first power interface and the second power interface; the first signal interface is respectively connected with the second signal interface and the third signal interface;

the test circuit is used for respectively testing whether the first power interface and the second power interface have normal functions, if the first power interface and the second power interface have normal functions, the test circuit supplies power to the SSD module, and otherwise, the test circuit does not supply power to the SSD module;

the test equipment is used for determining that the interface of the hard disk to be tested is normal when the SSD module is powered on through the first signal interface, the second signal interface and the third signal interface, and otherwise determining that the interface of the hard disk to be tested has abnormal functions.

Further, the test circuit includes: the device comprises a first interface test circuit, a second interface test circuit, a current limiting chip U1 and a voltage stabilizing chip U2;

the first interface test circuit is connected with the first power interface and used for testing whether the first power interface is normal in function;

the second interface test circuit is connected with the second power interface and used for testing whether the second power interface is normal or not;

when the first interface test circuit and the second interface test circuit test that the first power interface and the second power interface are normal in function, power is supplied to the SSD module through the current limiting chip U1 and the voltage stabilizing chip U2.

Further, the first interface test circuit and the second interface test circuit are respectively connected with the current limiting chip U1, the current limiting chip U1 is further respectively connected with the first power interface and the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected with the SSD module.

Further, the first interface test circuit includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the second interface test circuit includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second comparator U4, a voltage stabilizing diode D3 and a diode D5;

the first power interface is respectively connected with the input end of the current-limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the second power supply interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is respectively connected with the first end of a third resistor R3 and the anode of the first comparator U3; a second end of the fourth resistor R4 is connected to a cathode of the zener diode D2 and a cathode of the first comparator U3, respectively; the anode of the voltage stabilizing diode D2 is grounded; the second end of the third resistor R3 is grounded; the output end of the first comparator U3 is connected with the cathode of a diode D4; a second end of the ninth resistor R9 and an anode of the diode D4 are respectively connected with an EN pin of the current limiting chip U1;

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the anode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of a diode D5; and the anode of the diode D5 is connected with the EN pin of the current-limiting chip U1.

Further, the first interface test circuit is connected with the current limiting chip U1, the current limiting chip U1 is further connected with the first power interface and the voltage stabilizing chip U2, the voltage stabilizing chip U2 is further connected with the SSD module, and the second interface test circuit is connected with the SSD module.

the first power interface is respectively connected with the input end of the current-limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the input end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the second power interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is respectively connected with the first end of a third resistor R3 and the anode of the first comparator U3; a second end of the fourth resistor R4 is connected to a cathode of the zener diode D2 and a cathode of the first comparator U3, respectively; the anode of the voltage stabilizing diode D2 is grounded; the second end of the third resistor R3 is grounded; the output end of the first comparator U3 is connected with the cathode of a diode D4; a second end of the ninth resistor R9 and the anode of the diode D4 are respectively connected with the EN pin of the current limiting chip U1;

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the positive electrode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of the diode D5; the anode of the diode D5 is connected with an IO pin of the SSD module;

the SSD module comprises a control unit and a cache unit which are independently arranged, and the IO pin is the IO pin of the control unit.

Further, the first interface test circuit and the second interface test circuit are respectively connected with the current limiting chip U1, the current limiting chip U1 is further respectively connected with the second power interface and the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected with the SSD module.

Further, the second interface test circuit includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the first interface test circuit includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second comparator U4, a voltage stabilizing diode D3 and a diode D5;

the second power interface is respectively connected with the input end of the current limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the first power interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is respectively connected with the first end of a third resistor R3 and the anode of the first comparator U3; a second end of the fourth resistor R4 is connected to a cathode of the zener diode D2 and a cathode of the first comparator U3, respectively; the anode of the voltage stabilizing diode D2 is grounded; a second end of the third resistor R3 is grounded; the output end of the first comparator U3 is connected with the cathode of a diode D4; a second end of the ninth resistor R9 and an anode of the diode D4 are respectively connected with an EN pin of the current limiting chip U1;

Further, the second interface test circuit is connected with the current limiting chip U1, the current limiting chip U1 is further connected with the first power interface and the voltage stabilizing chip U2, the voltage stabilizing chip U2 is further connected with the SSD module, and the first interface test circuit is connected with the SSD module.

the second power interface is respectively connected with the input end of the current-limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the input end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the first power supply interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the anode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of the diode D5; the anode of the diode D5 is connected with an IO pin of the SSD module;

Further, the first interface test circuit and the second interface test circuit are respectively connected with the SSD module and the current limiting chip U1, the current limiting chip U1 is further connected with the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected with the SSD module.

the first power supply interface is respectively connected with the anode of the diode D6, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4 and the power supply end of the first comparator U3; the second power interface is respectively connected with the anode of the diode D7, the first end of the fifth resistor R5, the first end of the sixth resistor R6, the first end of the eighth resistor R8 and the power supply end of the second comparator U4; the cathode of the diode D6 and the cathode of the diode D7 are respectively connected with the input end of the current limiting chip U1; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module;

the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is respectively connected with the first end of a third resistor R3 and the anode of the first comparator U3; a second end of the fourth resistor R4 is connected to a cathode of the zener diode D2 and a cathode of the first comparator U3, respectively; the anode of the voltage stabilizing diode D2 is grounded; the second end of the third resistor R3 is grounded; the output end of the first comparator U3 is connected with the cathode of a diode D4; the anode of the diode D4 is connected with an IO pin of the SSD module;

In another aspect, an embodiment of the present invention provides a hard disk interface testing method, where the method includes:

the method comprises the steps that a test device identifies whether an SSD module is powered on or not through a first signal interface of a hard disk to be tested, a second signal interface of the test device and a third signal interface of the SSD module; the test circuit respectively tests whether the functions of a first power interface and a second power interface of the hard disk to be tested are normal, if the functions of the first power interface and the second power interface are both normal, power is supplied to the SSD module, otherwise, the SSD module is not supplied with power;

when the SSD module is identified to be powered on through the first signal interface, the second signal interface and the third signal interface, determining that the interface of the hard disk to be tested is normal in function, and otherwise determining that the interface of the hard disk to be tested is abnormal in function.

In another aspect, an embodiment of the present invention provides a hard disk interface testing apparatus, where the apparatus includes:

the identification module is used for identifying whether the SSD module is powered on or not through a first signal interface of the hard disk to be tested, a second signal interface of the test equipment and a third signal interface of the SSD module; the test circuit respectively tests whether the functions of a first power interface and a second power interface of the hard disk to be tested are normal, if the functions of the first power interface and the second power interface are tested to be normal, power is supplied to the SSD module, and otherwise, the SSD module is not supplied with power;

and the test module is used for determining that the interface of the hard disk to be tested has normal function when the SSD module is powered on through the first signal interface, the second signal interface and the third signal interface, and otherwise determining that the interface of the hard disk to be tested has abnormal function.

On the other hand, the embodiment of the invention provides a test device, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for completing mutual communication by the memory through the communication bus;

a memory for storing a computer program;

and the processor is used for realizing the steps of the method when executing the program stored in the memory.

In another aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the above method steps.

The embodiment of the invention provides a system, a method, a device, equipment and a medium for testing a hard disk interface, wherein the system comprises the following components: the device comprises a test device, a hard disk to be tested, a test circuit and a Solid State Disk (SSD) module; the hard disk to be tested comprises a first signal interface, a first power interface and a second power interface; the test equipment comprises a second signal interface; the SSD module comprises a third signal interface; the test circuit is respectively connected with the first power interface and the second power interface; the first signal interface is respectively connected with the second signal interface and the third signal interface; the test circuit is used for respectively testing whether the first power interface and the second power interface are normal in function, if the first power interface and the second power interface are tested to be normal in function, power is supplied to the SSD module, and otherwise, the SSD module is not supplied with power; the test equipment is used for determining that the interface of the hard disk to be tested is normal when the SSD module is powered on through the first signal interface, the second signal interface and the third signal interface, and otherwise determining that the interface of the hard disk to be tested has abnormal functions.

The technical scheme has the following advantages or beneficial effects:

the hard disk interface test system provided by the embodiment of the invention comprises test equipment, a hard disk to be tested, a test circuit and a Solid State Disk (SSD) module; the hard disk to be tested comprises a first signal interface, a first power interface and a second power interface; the test equipment comprises a second signal interface; the SSD module includes a third signal interface; the test circuit is respectively connected with the first power interface and the second power interface; the first signal interface is respectively connected with the second signal interface and the third signal interface. When the first power interface and the second power interface are normal in function, the test circuit supplies power to the SSD module, otherwise, the test circuit does not supply power to the SSD module. The test equipment identifies the electrification of the SSD module through the first signal interface, the second signal interface and the third signal interface, determines that the interface of the hard disk to be tested is normal in function, and otherwise determines that the interface of the hard disk to be tested is abnormal in function. According to the scheme provided by the embodiment of the invention, any one of the first power interface and the second power interface has abnormal function, the test circuit does not supply power to the SSD module, and the test equipment determines that the interface of the hard disk to be tested has abnormal function. Therefore, the problem that the standard SSD hard disk cannot detect whether the function of each power interface is abnormal or not can be solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a hard disk interface test system according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a test circuit structure provided in embodiment 1 of the present invention;

fig. 3 is a schematic diagram of a test circuit structure provided in embodiment 2 of the present invention;

fig. 4 is a schematic diagram of a test circuit structure provided in embodiment 3 of the present invention;

fig. 5 is a schematic diagram of a test circuit structure provided in embodiment 4 of the present invention;

FIG. 6 is a schematic diagram of a test circuit according to embodiment 5 of the present invention;

fig. 7 is a schematic diagram of a hard disk interface testing process provided in embodiment 6 of the present invention;

fig. 8 is a schematic structural diagram of a hard disk interface testing apparatus according to embodiment 7 of the present invention;

fig. 9 is a schematic structural diagram of a testing apparatus provided in embodiment 8 of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the attached drawings, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a hard disk interface testing system according to an embodiment of the present invention, including: the system comprises a test device 11, a hard disk to be tested 12, a test circuit 13 and a Solid State Disk (SSD) module 14; the hard disk 12 to be tested comprises a first signal interface 121, a first power interface 122 and a second power interface 123; the test equipment 11 comprises a second signal interface 111; the SSD module 14 includes a third signal interface 141;

the test circuit 13 is connected to the first power interface 122 and the second power interface 123 respectively; the first signal interface 121 is connected with the second signal interface 111 and the third signal interface 141 respectively;

the test circuit 13 is used for respectively testing whether the first power interface and the second power interface are normal, if the first power interface and the second power interface are both normal, power is supplied to the SSD module, and otherwise, power is not supplied to the SSD module;

and the test equipment 11 is used for determining that the interface of the hard disk to be tested has a normal function when the SSD module is powered on through the first signal interface, the second signal interface and the third signal interface, and otherwise determining that the interface of the hard disk to be tested has an abnormal function.

As shown in fig. 1, the hard disk interface test system includes: the system comprises a test device 11, a hard disk to be tested 12, a test circuit 13 and a Solid State Disk (SSD) module 14; the hard disk to be tested 12 comprises a first signal interface 121, a first power interface 122 and a second power interface 123; the test equipment 11 comprises a second signal interface 111; the SSD module 14 includes a third signal interface 141. The test circuit 13 is connected to the first power interface 122 and the second power interface 123 respectively; the first signal interface 121 is connected to the second signal interface 111 and the third signal interface 141, respectively.

In the embodiment of the present invention, the first power interface 122 included in the hard disk 12 to be tested is a 5V power interface, the second power interface 123 is a 12V power interface, and the first signal interface 121, the second signal interface 111, and the third signal interface 141 are SATA signal interfaces respectively.

The test circuit respectively tests whether the functions of a first power interface and a second power interface of the device to be tested, which are connected with the test circuit, are normal, only when the functions of the first power interface and the second power interface are normal, the power is supplied to the SSD module, and otherwise, the power is not supplied to the SSD module. The test equipment identifies the power-on state of the SSD module through the first signal interface, the second signal interface and the third signal interface, namely, whether each power interface of the hard disk to be tested is normal is determined according to whether the SSD module is powered on. And if the test equipment identifies that the SSD module is powered on, determining that the interface of the hard disk to be tested is normal in function, and otherwise, determining that the interface of the hard disk to be tested is abnormal in function.

In an embodiment of the present invention, a test circuit includes: the device comprises a first interface test circuit, a second interface test circuit, a current limiting chip U1 and a voltage stabilizing chip U2;

the second interface test circuit is connected with the second power interface and used for testing whether the second power interface is normal in function;

The following is a detailed description of the specific structure of the test circuit and the test procedure.

Example 1:

fig. 2 is a schematic diagram of a test circuit structure according to an embodiment of the present invention, in which a first interface test circuit and a second interface test circuit are respectively connected to a current limiting chip U1, the current limiting chip U1 is further connected to a first power interface and a voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected to the SSD module.

The first interface test circuit includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the first power interface is respectively connected with the input end of the current-limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the second power interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is respectively connected with the first end of a third resistor R3 and the anode of the first comparator U3; a second end of the fourth resistor R4 is connected to a cathode of the zener diode D2 and a cathode of the first comparator U3, respectively; the anode of the voltage stabilizing diode D2 is grounded; a second end of the third resistor R3 is grounded; the output end of the first comparator U3 is connected with the cathode of a diode D4; a second end of the ninth resistor R9 and the anode of the diode D4 are respectively connected with the EN pin of the current limiting chip U1;

As shown in fig. 2, the test circuit is powered by a 5V power interface, J1 is a standard SATA hard disk interface connector, and includes a pin related to a SATA signal, a pin related to a 5V power supply, and a pin related to a 12V power supply inside. SATA (Serial ATA) hard disk is also called Serial hard disk. M1 is an SSD module, which may be an SSD granular chip of an SATA interface, where the SATA control unit and the NAND FLASH cache unit are packaged in one chip, or may be a combination of an independent SATA control unit and an independent NAND FLASH cache unit. The SATA signal interface related signal of M1 is interconnected with J1, and is esd protected by using a transient suppression diode TVS tube D1. The SATA signal interfaces of J1 and M1 are respectively connected with the negative electrode of a transient suppression diode TVS tube D1, and the positive electrode of the transient suppression diode TVS tube D1 is grounded.

In fig. 2, U1 is a current limiting chip, which can play a role in limiting current to prevent a post-stage circuit from overcurrent or short circuit. On the other hand, the device can also be used as a power switch, and the EN pin of the device is used for controlling whether power is supplied to a post-stage circuit or not. U2 is DCDC voltage stabilization chip, and the 5V power that will await measuring hard disk such as the digital video recorder provides is stabilized to 3.3V or other voltage power supplies and is supplied power for SSD module and other circuit modules in the board, and the quantity is designed according to actual demand.

R1 and R5 are load resistors, usually resistors with high power are selected, such as cement resistors, and the aim is to provide a dummy load for 5V and 12V, so that abnormal problems of insufficient cold solder, insufficient power supply and the like of 5V and 12V power supply modules of the equipment to be tested are prevented.

U3 is a comparator, D2 is a voltage stabilizing diode, and the voltage stabilizing diode is matched with R2, R3, R4 and the like to monitor the input condition of a 5V power supply. If R4 is matched with the voltage stabilizing diode D2 to output a constant voltage V2 (such as 3.3V), the 5V input is divided into a voltage V1 by the R2 and the R3, and when the V1 is larger than the V2, the comparator outputs a high level to control the current limiting chip U1 to start and output. Similarly, when V1 is smaller than V2, the comparator outputs low level to control the current limiting chip U1 to close the output. By selecting appropriate resistors (e.g., R2=1.11K ohms, R3=10K ohms), it may be configured that comparator U3 outputs a high level when the 5V supply voltage is greater than a certain value (e.g., 4.5V), which may effectively monitor the 5V supply input condition. Similarly, by selecting appropriate resistors (e.g., R6=1.11K ohms, R7=10K ohms), it may be configured that the comparator U4 outputs a high level when the 12V power supply voltage is greater than a certain value (e.g., 10.8V), which may effectively monitor the 12V power supply input condition. If the 5V input or the 12V input is lower than the judgment threshold value (such as 4.5V and 10.8V), the current limiting chip closes the output, and the SSD module cannot supply power.

As shown in fig. 2, if the SATA signal interface of the hard disk to be tested is abnormal, the communication between the hard disk to be tested and the test circuit is abnormal, and the test fails. If the 5V power supply or the 12V power supply of the hard disk interface to be tested is abnormal, the SSD module in the test circuit cannot be powered on, and the test is also bound to fail. That is to say, no matter any function of the hard disk interface to be tested is abnormal (SATA signal, 5V power supply, 12V power supply), the test will fail (recognizing that the SSD module is not powered on), and a failed device interface can be intercepted effectively.

Example 2:

fig. 3 is a schematic structural diagram of a test circuit according to an embodiment of the present invention, where the first interface test circuit is connected to the current limiting chip U1, the current limiting chip U1 is further connected to the first power interface and the voltage stabilizing chip U2, the voltage stabilizing chip U2 is further connected to the SSD module, and the second interface test circuit is connected to the SSD module.

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the anode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of a diode D5; the anode of the diode D5 is connected with an IO pin of the SSD module;

In the embodiment of the invention, the test circuit is powered by a 5V power interface, and the SSD module comprises an independent SATA control unit and an independent NAND FLASH cache unit combination. The SATA control unit includes an IO pin.

U3 is a comparator, D2 is a voltage stabilizing diode, and the voltage stabilizing diode is matched with R2, R3, R4 and the like to monitor the input condition of a 5V power supply. For example, R4 cooperates with the zener diode D2 to output a constant voltage V2 (e.g., 3.3V), R2 and R3 divide the 5V input into a voltage V1, and when V1 is greater than V2, the comparator outputs a high level to control the current limiting chip U1 to turn on the output. Similarly, when V1 is smaller than V2, the comparator outputs low level to control the current limiting chip U1 to close the output. By selecting appropriate resistors (e.g., R2=1.11K ohms, R3=10K ohms), the comparator U3 can be configured to output a high when the 5V supply voltage is greater than a certain value (e.g., 4.5V), which can effectively monitor 5V supply input conditions.

For a 12V power interface, when V3 is greater than V4, the comparator outputs a high level to the IO pin of the control unit, and when V3 is less than V4, the comparator outputs a low level to the IO pin of the control unit. The test equipment effectively monitors the 12V power supply input condition by acquiring the level signal received by the IO pin of the control unit.

Example 3:

fig. 4 is a schematic structural diagram of a test circuit according to an embodiment of the present invention, where the first interface test circuit and the second interface test circuit are respectively connected to the current limiting chip U1, the current limiting chip U1 is further connected to the second power interface and the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected to the SSD module.

The second interface test circuit includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the second power interface is respectively connected with the input end of the current limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the first power supply interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the positive electrode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of a diode D5; and the anode of the diode D5 is connected with the EN pin of the current-limiting chip U1.

Compared with the test circuit shown in fig. 2, the test circuit provided by the embodiment of the invention is changed from the 5V power interface to the 12V power interface. When V1 is greater than V2, the comparator outputs high level to control the current limiting chip U1 to start output. Similarly, when V1 is smaller than V2, the comparator outputs low level to control the current limiting chip U1 to close the output. Likewise, the 5V power supply input condition can be effectively monitored.

Example 4:

fig. 5 is a schematic structural diagram of a test circuit according to an embodiment of the present invention, where the second interface test circuit is connected to the current limiting chip U1, the current limiting chip U1 is further connected to the first power interface and the voltage stabilizing chip U2, the voltage stabilizing chip U2 is further connected to the SSD module, and the first interface test circuit is connected to the SSD module.

the second power interface is respectively connected with the input end of the current-limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the input end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the first power interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

Compared with the test circuit shown in fig. 3, the test circuit provided by the embodiment of the invention is changed from the 5V power interface to the 12V power interface.

U3 is the comparator, and D2 is zener diode, and it cooperates with R2, R3, R4 etc. and monitors 12V power input condition. When V1 is greater than V2, the comparator outputs high level to control the current limiting chip U1 to start output. Similarly, when V1 is smaller than V2, the comparator outputs low level to control the current limiting chip U1 to close the output.

For a 5V power interface, when V3 is greater than V4, the comparator outputs a high level to the IO pin of the control unit, and when V3 is less than V4, the comparator outputs a low level to the IO pin of the control unit. The test equipment effectively monitors the 5V power supply input condition by acquiring the level signal received by the IO pin of the control unit.

Example 5:

fig. 6 is a schematic structural diagram of a test circuit according to an embodiment of the present invention, where the first interface test circuit and the second interface test circuit are respectively connected to the SSD module and the current limiting chip U1, the current limiting chip U1 is further connected to the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected to the SSD module.

the first power interface is respectively connected with the anode of the diode D6, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4 and the power supply end of the first comparator U3; the second power supply interface is respectively connected with the anode of the diode D7, the first end of the fifth resistor R5, the first end of the sixth resistor R6, the first end of the eighth resistor R8 and the power supply end of the second comparator U4; the cathode of the diode D6 and the cathode of the diode D7 are respectively connected with the input end of the current limiting chip U1; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module;

the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is respectively connected with the first end of a third resistor R3 and the anode of the first comparator U3; a second end of the fourth resistor R4 is connected to a cathode of the zener diode D2 and a cathode of the first comparator U3, respectively; the anode of the voltage stabilizing diode D2 is grounded; a second end of the third resistor R3 is grounded; the output end of the first comparator U3 is connected with the cathode of a diode D4; the anode of the diode D4 is connected with an IO pin of the SSD module;

In the embodiment of the invention, a 5V power interface and a 12V power interface jointly supply power to the test circuit, and the anode of the diode D4 and the anode of the diode D5 are respectively connected with different pins in the control unit of the SSD module.

For a 5V power interface, when V1 is greater than V2, the comparator outputs a high level to the IO pin of the control unit, and when V1 is less than V2, the comparator outputs a low level to the IO pin of the control unit. The test equipment effectively monitors the 5V power supply input condition by acquiring the level signal received by the IO pin of the control unit.

Example 6:

fig. 7 is a schematic diagram of a hard disk interface testing process provided in an embodiment of the present invention, where the process includes the following steps:

s101: identifying whether the SSD module is powered on or not through a first signal interface of a hard disk to be tested, a second signal interface of the testing equipment and a third signal interface of the SSD module; the test circuit respectively tests whether the first power interface and the second power interface of the hard disk to be tested are normal, if the first power interface and the second power interface are tested to be normal, power is supplied to the SSD module, and otherwise, power is not supplied to the SSD module.

S102: and when the SSD module is identified to be powered on through the first signal interface, the second signal interface and the third signal interface, determining that the interface of the hard disk to be tested is normal in function, and otherwise, determining that the interface of the hard disk to be tested is abnormal in function.

The hard disk interface test method provided by the embodiment of the invention is applied to test equipment in a hard disk interface test system, and the test equipment can be equipment such as a PC (personal computer), a tablet computer and a server.

Example 7:

fig. 8 is a schematic structural diagram of a hard disk interface testing apparatus according to an embodiment of the present invention, where the apparatus includes:

the identification module 81 is configured to identify whether the SSD module is powered on or not through the first signal interface of the hard disk to be tested, the second signal interface of the test device, and the third signal interface of the SSD module; the test circuit respectively tests whether the functions of a first power interface and a second power interface of the hard disk to be tested are normal, if the functions of the first power interface and the second power interface are tested to be normal, power is supplied to the SSD module, and otherwise, the SSD module is not supplied with power;

and the test module 82 is configured to determine that the interface of the hard disk to be tested is normal in function when the SSD module is powered on through the first signal interface, the second signal interface, and the third signal interface, and otherwise determine that the interface of the hard disk to be tested is abnormal in function.

Example 8:

on the basis of the foregoing embodiments, an embodiment of the present invention further provides a testing apparatus, as shown in fig. 9, including: the system comprises a processor 301, a communication interface 302, a memory 303 and a communication bus 304, wherein the processor 301, the communication interface 302 and the memory 303 are communicated with each other through the communication bus 304;

the memory 303 has stored therein a computer program which, when executed by the processor 301, causes the processor 301 to perform the above method steps.

Based on the same inventive concept, the embodiment of the present invention further provides a testing device, and since the principle of the testing device for solving the problem is similar to the hard disk interface testing method, the implementation of the testing device may refer to the implementation of the method, and repeated details are not repeated.

The testing equipment provided by the embodiment of the invention can be a desktop computer, a portable computer, a smart phone, a tablet computer, a Personal Digital Assistant (PDA), network side equipment and the like.

The communication bus mentioned in the above test device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface 302 is used for communication between the above-described test apparatus and other apparatuses.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Alternatively, the memory may be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, including a central processing unit, a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.

Example 9:

on the basis of the foregoing embodiments, the present invention further provides a computer storage readable storage medium, in which a computer program executable by a testing apparatus is stored, and when the program runs on the testing apparatus, the testing apparatus is caused to implement the above method steps when executed.

Based on the same inventive concept, embodiments of the present invention further provide a computer-readable storage medium, and since a principle of solving a problem when a processor executes a computer program stored on the computer-readable storage medium is similar to a hard disk interface testing method, implementation of the computer program stored on the computer-readable storage medium by the processor may refer to implementation of the method, and repeated parts are not described again.

The computer readable storage medium may be any available media or data storage device that can be accessed by a processor in a test device, including but not limited to magnetic memory such as floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc., optical memory such as CDs, DVDs, BDs, HVDs, etc., and semiconductor memory such as ROMs, EPROMs, EEPROMs, non-volatile memories (NAND FLASH), solid State Disks (SSDs), etc.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A hard disk interface test system, comprising: the device comprises a test device, a hard disk to be tested, a test circuit and a Solid State Disk (SSD) module; the hard disk to be tested comprises a first signal interface, a first power interface and a second power interface; the test equipment comprises a second signal interface; the SSD module comprises a third signal interface;

the test circuit is used for respectively testing whether the first power interface and the second power interface are normal in function, if the first power interface and the second power interface are tested to be normal in function, power is supplied to the SSD module, and otherwise, the SSD module is not supplied with power;

the test equipment is used for determining that the interface of the hard disk to be tested is in a normal function when the SSD module is powered on through the first signal interface, the second signal interface and the third signal interface, and otherwise determining that the interface of the hard disk to be tested is in an abnormal function.

2. The system of claim 1, wherein the test circuit comprises: the device comprises a first interface test circuit, a second interface test circuit, a current limiting chip U1 and a voltage stabilizing chip U2;

the first interface test circuit is connected with the first power interface and used for testing whether the first power interface is normal or not;

when the first interface test circuit and the second interface test circuit test that the first power interface and the second power interface are normal in function, the SSD module is supplied with power through the current limiting chip U1 and the voltage stabilizing chip U2.

3. The system of claim 2, wherein the first interface test circuit and the second interface test circuit are respectively connected to the current limiting chip U1, the current limiting chip U1 is further respectively connected to the first power interface and the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected to the SSD module.

4. The system of claim 3, wherein the first interface test circuit comprises: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

5. The system of claim 2, wherein the first interface test circuit is connected to the current limiting chip U1, the current limiting chip U1 is further connected to the first power interface and the voltage stabilizing chip U2, respectively, the voltage stabilizing chip U2 is further connected to the SSD module, and the second interface test circuit is connected to the SSD module.

6. The system of claim 5, wherein the first interface test circuit comprises: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the first power interface is respectively connected with the input end of the current limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the input end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the second power interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the positive electrode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of a diode D5; the anode of the diode D5 is connected with an IO pin of the SSD module;

7. The system of claim 2, wherein the first interface test circuit and the second interface test circuit are respectively connected to the current limiting chip U1, the current limiting chip U1 is further respectively connected to the second power interface and the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected to the SSD module.

8. The system of claim 7, wherein the second interface test circuit comprises: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the second power interface is respectively connected with the input end of the current-limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the first power interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

a second end of the fifth resistor R5 is grounded; a second end of the sixth resistor R6 is connected to a first end of a seventh resistor R7 and the positive electrode of the second comparator U4, respectively; a second end of the eighth resistor R8 is connected to a cathode of the zener diode D3 and a cathode of the second comparator U4, respectively; the anode of the voltage stabilizing diode D3 is grounded; a second end of the seventh resistor R7 is grounded; the output end of the second comparator U4 is connected with the cathode of the diode D5; and the anode of the diode D5 is connected with the EN pin of the current-limiting chip U1.

9. The system of claim 2, wherein the second interface test circuit is connected to the current limiting chip U1, the current limiting chip U1 is further connected to the first power interface and the voltage stabilizing chip U2, respectively, the voltage stabilizing chip U2 is further connected to the SSD module, and the first interface test circuit is connected to the SSD module.

10. The system of claim 9, wherein the second interface test circuit comprises: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the second power interface is respectively connected with the input end of the current limiting chip U1, the first end of the first resistor R1, the first end of the second resistor R2, the input end of the fourth resistor R4, the power supply end of the first comparator U3, the first end of the eighth resistor R8 and the first end of the ninth resistor R9; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module; the first power supply interface is respectively connected with a first end of a fifth resistor R5, a first end of a sixth resistor R6 and a power supply end of a second comparator U4;

11. The system of claim 2, wherein the first interface test circuit and the second interface test circuit are respectively connected to the SSD module and the current limiting chip U1, the current limiting chip U1 is further connected to the voltage stabilizing chip U2, and the voltage stabilizing chip U2 is further connected to the SSD module.

12. The system of claim 11, wherein the first interface test circuit comprises: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator U3, a voltage stabilizing diode D2, a diode D4 and a ninth resistor R9;

the first power interface is respectively connected with the anode of the diode D6, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the fourth resistor R4 and the power supply end of the first comparator U3; the second power interface is respectively connected with the anode of the diode D7, the first end of the fifth resistor R5, the first end of the sixth resistor R6, the first end of the eighth resistor R8 and the power supply end of the second comparator U4; the cathode of the diode D6 and the cathode of the diode D7 are respectively connected with the input end of the current limiting chip U1; the output end of the current limiting chip U1 is connected with the input end of the voltage stabilizing chip U2, and the output end of the voltage stabilizing chip U2 is connected with the power supply end of the SSD module;

13. A hard disk interface test method is characterized by comprising the following steps:

the method comprises the steps that a test device identifies whether an SSD module is powered on or not through a first signal interface of a hard disk to be tested, a second signal interface of the test device and a third signal interface of the SSD module; the test circuit respectively tests whether the functions of a first power interface and a second power interface of the hard disk to be tested are normal, if the functions of the first power interface and the second power interface are tested to be normal, power is supplied to the SSD module, and otherwise, the SSD module is not supplied with power;

and when the SSD module is identified to be powered on through the first signal interface, the second signal interface and the third signal interface, determining that the interface of the hard disk to be tested is normal in function, and otherwise, determining that the interface of the hard disk to be tested is abnormal in function.

14. A hard disk interface testing device, the device comprising:

the identification module is used for identifying whether the SSD module is powered on or not through a first signal interface of the hard disk to be tested, a second signal interface of the test equipment and a third signal interface of the SSD module; the test circuit respectively tests whether the functions of a first power interface and a second power interface of the hard disk to be tested are normal, if the functions of the first power interface and the second power interface are both normal, power is supplied to the SSD module, otherwise, the SSD module is not supplied with power;

and the test module is used for determining that the interface of the hard disk to be tested has a normal function when the SSD module is electrified through the first signal interface, the second signal interface and the third signal interface, and otherwise determining that the interface of the hard disk to be tested has an abnormal function.

15. The test equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;

a memory for storing a computer program;

a processor for implementing the method steps of claim 13 when executing a program stored in the memory.

16. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method steps of claim 13.