CN115390809A - Simulation scheduling method and system - Google Patents
Simulation scheduling method and system Download PDFInfo
- Publication number
- CN115390809A CN115390809A CN202210965061.6A CN202210965061A CN115390809A CN 115390809 A CN115390809 A CN 115390809A CN 202210965061 A CN202210965061 A CN 202210965061A CN 115390809 A CN115390809 A CN 115390809A
- Authority
- CN
- China
- Prior art keywords
- file
- model
- simulink
- resolving
- model file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/31—Programming languages or programming paradigms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/37—Compiler construction; Parser generation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/447—Target code generation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5022—Mechanisms to release resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/48—Indexing scheme relating to G06F9/48
- G06F2209/484—Precedence
Abstract
The invention provides a simulation scheduling method and a system, belonging to the technical field of control simulation, wherein the method comprises the following steps: constructing a Simulink mathematical model and generating an initial model file; converting the initial model file into an RTW file; calling a target language compiler to convert the RTW file into a model file to be called; calling a make tool to perform binding of automatically generated codes, and resolving a model file to be called to generate an execution model file; and executing closed-loop simulation in the Vxworks system according to the execution model file. The invention realizes the simulation scheduling distribution of the whole system in the form of auxiliary clock scheduling tasks, realizes the simulation scheduling between the Simulink simulation system and the VxWorks operating system, and improves the real-time performance of the Simulink simulation process.
Description
Technical Field
The invention belongs to the technical field of control simulation, relates to a control simulation scheduling technology, and particularly relates to a simulation scheduling method and a system.
Background
RTW is a Simulink-based code automatic generation environment, which can directly generate optimized and portable embedded real-time code from a Simulink model and can automatically generate an executable program suitable for the software and hardware environment of a target machine according to the configuration of the target machine. The VxWorks operating system is widely applied to the high-precision technical fields of communication, military, aviation, aerospace and the like and the fields with extremely high real-time requirements with good reliability and excellent real-time performance.
Because the real-time requirement of the prior art on the simulation system is gradually increased, the Windows operating system is adopted for the simulation under Simulink, and the simulation is often interfered by other tasks to delay the execution of the tasks, so that large errors are generated, and the real-time tasks cannot be accurately completed. The real-time performance of the VxWorks operating system is good, system public programs such as process scheduling, interprocess communication, interrupt processing and the like of the system are refined, and the delay caused by the system is short, but the difficulty in the technical field is how to realize simulation scheduling between the Simulink simulation system and the VxWorks operating system so as to realize the real-time performance of the Simulink simulation process.
Disclosure of Invention
The invention provides a simulation scheduling method and a simulation scheduling system, aiming at the problems that in the prior art, the Simulink simulation process has poor real-time performance, causes task delay, generates large errors and cannot accurately complete tasks.
When the system is used, a user only needs to construct a mathematical simulation model in Simulink, compile the mathematical simulation model through RTW and download the mathematical simulation model to a target machine running a VxWorks real-time operating system; the invention realizes the simulation scheduling distribution of the whole system by using the form of auxiliary clock scheduling tasks, and the VxWorks real-time operating system performs the whole control on the whole simulation by using the form of an auxiliary clock; the compiling amount of simulation codes is reduced, the real-time performance of system simulation is guaranteed, and the performance of the system simulation is improved; the specific technical scheme is as follows:
a simulation scheduling method comprises the following steps:
constructing a Simulink mathematical model and generating an initial model file;
converting the initial model file into an RTW file;
calling a target language compiler to convert the RTW file into a model file to be called;
calling a make tool to perform binding of automatically generated codes, and resolving the model file to be called to generate an execution model file;
and executing closed-loop simulation in the Vxworks system according to the execution model file.
Further defined, before the step of constructing the Simulink mathematical model and generating the model file, the method further comprises
Defining, constructing and/or packaging a hardware drive file based on a VxWorks kernel program;
and establishing communication between the driving module and the simulation board card.
Further limiting, the calling make tool performs binding for automatically generating a code, and the process of resolving the model file to be called to generate the execution model file specifically includes:
calling a make tool to perform binding for automatically generating codes, and identifying and checking the model file to be called through the codes;
setting the priority of a Simulink mathematical model resolving task;
initializing a memory space, a sampling step length, a semaphore and a resolving operation parameter of a Simulink mathematical model;
and establishing a resolving task of the Simulink mathematical model, controlling a resolving process through an auxiliary clock, finally generating an execution model file, ending the resolving task, deleting the task and releasing the memory.
Further, the process of creating a solving task of the Simulink mathematical model and controlling the solving through the auxiliary clock specifically includes:
creating a resolving task of the Simulink mathematical model;
judging the type of the resolving task;
if the Simulink mathematical model is single-task calculation, detecting the running state of the Simulink mathematical model, calling the model file to be called according to the running state to calculate the Simulink mathematical model, and releasing the semaphore of the single-task calculation;
if the multi-task calculation is carried out, the calculation task of the Simulink mathematical model is decomposed into a plurality of subtasks for calculation and detection respectively, the model file to be called is called according to the operation state of each subtask calculation to carry out Simulink mathematical model calculation, and the semaphore calculated by each subtask is released.
Further defined, the executing module, based on the execution model file, the process of executing closed-loop simulation in the Vxworks system specifically comprises the following steps:
calling an entry function in the execution model file, and initializing an interrupt function of the auxiliary clock;
resolving the model file to be executed through a clock function of an auxiliary clock, and detecting whether a sampling time point of a subtask is reached;
if the detection result is that the subtask does not reach the sampling time point, repeating the detection step;
if the detection result is that the subtask has reached the sampling time point, releasing the semaphore of the sampling time point;
judging the type of the semaphore at the sampling time point;
if the interruption resolving semaphore is the interruption resolving semaphore, suspending resolving of the model file to be executed through an interruption function of the auxiliary clock according to the interruption resolving semaphore;
if the stopping of the resolving semaphore is achieved, calling a termination function of model resolving according to the stopping of the resolving semaphore and releasing the memory to complete closed-loop simulation.
Further defined, the RTW file contains descriptions of the Simulink mathematical model, including data type, data input, data output, and internal logic.
A simulation scheduling system comprises
A model construction module: the Simulink model generation method comprises the steps of constructing a Simulink mathematical model and generating an initial model file;
an RTW file generation module: the initial model file is converted into an RTW file;
a conversion module: the system comprises a target language compiler, a model file to be called and a RTW file, wherein the target language compiler is used for calling the RTW file to be converted into the model file to be called;
code binding module: the binding machine is used for calling a make tool to automatically generate codes, and resolving the model file to be called to generate an execution model file;
and a simulation module: and the closed-loop simulation is executed in the Vxworks system according to the execution model file.
Further defined, the model building module further comprises a hardware driver file defined, built and/or packaged based on a VxWorks kernel program before being used for building the Simulink mathematical model and generating the initial model file; and establishing communication between the driving module and the simulation board card.
Further defined, the code binding module comprises:
a detection module: the binding machine is used for calling a make tool to automatically generate codes, and identifying and checking the model file to be called through the codes;
a priority design module: the method comprises the steps of setting the priority of a Simulink mathematical model resolving task;
an initialization module: the system comprises a memory space, a sampling step length, a semaphore and a resolving operation parameter, wherein the memory space, the sampling step length and the semaphore are used for initializing a Simulink mathematical model;
and a solution task creation module: the system is used for creating a resolving task of the Simulink mathematical model, controlling a resolving process through an auxiliary clock, finally generating an execution model file, ending the resolving task, deleting the task and releasing the memory.
A computer-readable storage medium storing a program file, the program file being executed to implement the above-described simulation scheduling method.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention relates to a simulation scheduling method, which is characterized in that the simulation scheduling method is compiled and downloaded to a target machine of a VxWorks real-time operating system through RTW; the code generated by the Simlink model is called by the model file to be called through the RTW automatic generation code, the model file to be called is modified, the simulation scheduling distribution of the whole system is realized through the form of the auxiliary clock scheduling task, the simulation scheduling is realized between the Simulink simulation system and the VxWorks operation system, and the real-time performance of the Simulink simulation process is improved.
2. The invention relates to a simulation scheduling method, which provides a new method, and the method is used for integrally controlling a simulation system by utilizing a scheduling auxiliary clock mode, thereby being beneficial to the control of peripheral equipment on model resolving operation; the performance of system simulation is improved.
3. The method modifies the entry function of the model file to be called, so that the model file to be called has 3 functions of program initialization, model operation calculation and program termination, is used for calling the VxWorks operating system, and generates the model file to be called by the method.
4. The invention checks the priority of the processing task by setting the Simulink mathematical model, processes the task in time and accelerates the resolving process of the model file.
5. The codes generated by the Simulink mathematical model are called by the model file to be called in a function mode to realize the scheduling and distribution of the whole simulation task. The invention realizes the task scheduling and distribution of the simulation system by modifying the model file to be called and combining the form of the auxiliary clock scheduling task.
Drawings
FIG. 1 is a schematic process diagram of a simulation scheduling method according to the present invention;
FIG. 2 is a schematic diagram illustrating a process of generating an execution model file by resolving a model file to be called;
FIG. 3 is a schematic process diagram of closed loop simulation;
FIG. 4 is a schematic diagram of a simulation scheduling system according to the present invention;
fig. 5 is a schematic diagram of a code binding module.
Detailed Description
The technical solutions of the present invention will be further explained below with reference to the drawings and examples, but the present invention is not limited to the embodiments explained below.
Example 1
Referring to fig. 1, the simulation scheduling method of the present embodiment includes the following steps:
s0: defining, constructing and/or packaging a hardware drive file based on a VxWorks kernel program; and establishing communication between the driving module and the simulation board card.
The method specifically comprises the following steps: defining, constructing and/or packaging a hardware drive file based on a VxWorks kernel program, and establishing communication between a VxWorks drive module and a VxWorks simulation board card; the driving module is an auxiliary calling hardware interface, a related driving module is constructed through an S function, and the communication of the system is ensured by calling a corresponding board card and a network calling function which are packaged in VxWorks;
s1: constructing a Simulink mathematical model and generating an initial model file;
specifically, the step of constructing the Simulink mathematical model and generating the initial model file comprises the following steps:
according to requirements, a Simulink mathematical model is built through a Simulink model library, an initialization model file is generated, the initialization model file can be operated under a Simulink platform firstly during initial debugging, corresponding modification and adjustment are carried out, and the step S2 can be carried out when a simulation result is consistent with the requirements; the method for constructing the Simulink mathematical model can be various, for example, a user can select the Simulink mathematical model through a Simulink model library according to actual requirements, and can also perform personalized construction in combination with simulation test requirements and the like;
s2: converting the initialization model file into an RTW file by using RTW; wherein, the RTW file contains the description content of the Simulink mathematical model, and the description content comprises data type, data input, data output and internal logic;
s3: calling a target language compiler to convert the RTW file into a model file to be called;
s4: calling a make tool to perform binding for automatically generating codes, identifying and checking an entry function of a model file to be called through the codes, calling the model file to be called to resolve, and generating an execution model file from the model file to be called; specifically, step S4 is: a target language compiler-TLC language is adopted, a tornado.tlc file is selected in the embodiment, and a model file to be called is converted into an execution model file;
referring to fig. 2, specifically, step S4 is:
s4.1: calling a make tool to perform binding for automatically generating codes, identifying an entry function of a model file to be called through the codes, checking the identified model file to be called, converting an unidentified model file to be called into an external mode to explain, and checking the model file to be called; specifically, the Simulink mathematical model is analyzed, and the analysis content comprises the stop time of the Simulink mathematical model and waiting information before simulation starts in an external mode; identifying an entry function of the model file to be called, converting the unidentified model file to be called into an external mode for interpretation, and checking the model file to be called; the external mode refers to communication between a host computer and a target computer, the host computer refers to a computer running MATLAB and Simulink environments, and the target computer refers to a computer running an execution model file generated by RTW;
s4.2: setting a Simulink mathematical model to check the priority of the processing task; the setting principle of the priority is as follows: the resolving process of the model file is prior to the calling process of the hardware board card;
s4.3: initializing a memory space, a sampling step length, a semaphore and a resolving operation parameter of a Simulink mathematical model;
s4.4: creating a resolving task of the Simulink mathematical model, and resolving by calling a model file to be called; the calculation tasks are divided into single-task calculation and multi-task calculation, and the single-task calculation and the multi-task calculation need to be judged; if the calculation task is judged to be single-task calculation, detecting the running state of the Simulink mathematical model, wherein the running state comprises a normal running state, an ending state or an error state, calling a model calculation running function according to the running state to calculate the Simulink mathematical model, and releasing the semaphore of the single-task calculation; judging that the calculation task is multi-task calculation, decomposing the calculation task of the Simulink mathematical model to form a plurality of subtasks for calculation, respectively detecting the operation states of the plurality of subtasks for calculation, calling a model calculation operation function according to the operation states of the subtasks for calculation of the Simulink mathematical model, and releasing the semaphore of the subtasks for calculation; and controlling the resolving process of the model file to be called through the auxiliary clock, generating an execution model file, ending the resolving task, deleting the task and releasing the memory. The auxiliary clock is a timer that utilizes another timer within the CPU of the target machine in addition to the system clock. Vxworks provides a series of operation interfaces which are the same as a system clock, accurate time delay can be achieved by hanging an interrupt service program, and when a timing period of an auxiliary clock is up, interrupt service is started.
S5: and downloading the generated execution model file to a Vxworks system to perform closed-loop system simulation.
Referring to fig. 3, specifically, step S5 is:
s5.1: calling an entry function of the generated execution model file, and initializing an interrupt function of the auxiliary clock;
s5.3: resolving the execution model file through a clock function of the auxiliary clock, detecting whether the sampling time point of the subtask is reached, and if the detection result is that the subtask does not reach the sampling time point, continuing to detect; if the detection result is that the subtask has reached the sampling time point, releasing the semaphore of the sampling time point; the sampling time points (including the start time, the end time, etc.) are set through the inside of the model, and the file generated by the RTW is set according to the start time and the end time of each subtask, and the corresponding start semaphore and end semaphore are released.
S5.4: receiving the semaphore of S5.3, judging the received semaphore at the sampling time point, and if the semaphore at the sampling time point is judged to be the interrupt resolving semaphore, suspending execution of resolving of the model file through an interrupt function of the auxiliary clock according to the interrupt resolving semaphore; and if the semaphore at the sampling time point is judged to be the stopping resolving semaphore, calling a termination function of model resolving according to the stopping resolving semaphore and releasing the memory to complete closed-loop simulation.
Example 2
Referring to fig. 4, a simulation scheduling system of this embodiment is formed based on the simulation scheduling method of embodiment 1, and includes a model building module, an RTW file generating module, a converting module, a code binding module and a simulation module,
defining, constructing and/or packaging a hardware drive file based on a VxWorks kernel program, and establishing communication between a VxWorks drive module and a VxWorks simulation board card; the driving module is an auxiliary calling hardware interface, a related driving module is constructed through an S function, and the communication of the system is ensured by calling a corresponding board card and a network calling function which are packaged in VxWorks;
a model construction module: the Simulink model generation method comprises the steps of constructing a Simulink mathematical model and generating an initial model file; specifically, a Simulink mathematical model is built through a Simulink model library, an initialization model file is generated, the initialization model file can be operated under a Simulink platform firstly during initial debugging, corresponding modification and adjustment are carried out, and an RTW file generation module can be operated when a simulation result is consistent with a requirement; the method for constructing the Simulink mathematical model can be various, for example, a user can select the Simulink mathematical model through a Simulink model library according to actual requirements, and can also perform personalized construction in combination with simulation test requirements and the like;
an RTW file generation module: the system comprises an initialization model file, an RTW file and a database, wherein the initialization model file is used for converting the initialization model file into the RTW file by applying the RTW; wherein, the RTW file contains the description content of the Simulink mathematical model, and the description content comprises data type, data input, data output and internal logic;
a conversion module: the system comprises a target language compiler, a model file to be called and a RTW file, wherein the target language compiler is used for calling the RTW file and converting the RTW file into the model file to be called;
code binding module: the system comprises a code generation module, a model file generation module, a code generation module, a model file analysis module and a model file database, wherein the code generation module is used for generating a code to be automatically generated by calling a make tool; specifically, a target language compiler-TLC language is used, in this embodiment, a tornado.
A simulation module: and the method is used for downloading the generated execution model file to a Vxworks system to carry out closed-loop system simulation.
Referring to fig. 5, the code binding module of the present embodiment includes a detection module, a priority design module, an initialization module and a calculation task creation module,
a detection module: used for calling a make tool to automatically generate the binding of codes, identifying the entry function of the model file to be called through the codes, checking the identified model file to be called, converting the unidentified model file to be called into an external mode for interpretation, and checking the model file to be called; specifically, the Simulink mathematical model is analyzed, and the analysis content comprises the stop time of the Simulink mathematical model and waiting information before simulation starts in an external mode; identifying an entry function of the model file to be called, converting the unidentified model file to be called into an external mode for interpretation, and checking the model file to be called; the external mode refers to communication between a host computer and a target computer, the host computer refers to a computer running MATLAB and Simulink environments, and the target computer refers to a computer running a model file to be called generated by RTW;
a priority design module: the priority level of the processing task is set by the Simulink mathematical model; the setting principle of the priority is as follows: the resolving process of the model file is prior to the calling process of the hardware board card;
an initialization module: the system comprises a memory space, a sampling step length, a semaphore and a resolving operation parameter, wherein the memory space, the sampling step length and the semaphore are used for initializing a Simulink mathematical model;
a calculation task creation module: the system comprises a calculation task used for creating a Simulink mathematical model and calculating by calling a model file to be called; the calculation tasks are divided into single-task calculation and multi-task calculation, and the single-task calculation and the multi-task calculation need to be judged; if the calculation task is judged to be single-task calculation, detecting the running state of the Simulink mathematical model, wherein the running state comprises a normal running state, an ending state or an error state, calling a model calculation running function according to the running state to calculate the Simulink mathematical model, and releasing the semaphore of the single-task calculation; judging that the calculation task is multi-task calculation, decomposing the calculation task of the Simulink mathematical model to form a plurality of subtasks for calculation, respectively detecting the operation states of the plurality of subtasks for calculation, calling a model calculation operation function according to the operation states of the subtasks for calculation of the Simulink mathematical model, and releasing the semaphore of the subtasks for calculation; and controlling the resolving process of the model file to be called by the auxiliary clock, generating an execution model file, ending the resolving task, deleting the task and releasing the memory. The auxiliary clock is a timer that utilizes another timer within the CPU of the target machine in addition to the system clock. Vxworks provides a series of operation interfaces which are the same as a system clock, accurate time delay can be achieved by hanging an interrupt service program, and when a timing period of an auxiliary clock is up, interrupt service is started.
Example 3
This embodiment is a computer-readable storage medium storing a program file executed to implement the simulation scheduling method of embodiment 1.
Claims (10)
1. A simulation scheduling method is characterized by comprising the following steps:
constructing a Simulink mathematical model and generating an initial model file;
converting the initial model file into an RTW file;
calling a target language compiler to convert the RTW file into a model file to be called;
calling a make tool to perform binding of automatically generated codes, and resolving the model file to be called to generate an execution model file;
and executing closed-loop simulation in the Vxworks system according to the execution model file.
2. The simulation scheduling method of claim 1 wherein prior to constructing the Simulink mathematical model and generating the model file further comprises
Defining, constructing and/or packaging a hardware drive file based on a VxWorks kernel program;
and establishing communication between the driving module and the simulation board card.
3. The simulation scheduling method according to claim 2, wherein the calling make tool performs binding of automatically generated codes, and the process of resolving the model file to be called to generate the execution model file specifically comprises:
calling a make tool to perform binding for automatically generating codes, and identifying and checking the model file to be called through the codes;
setting the priority of a Simulink mathematical model resolving task;
initializing a memory space, a sampling step length, a semaphore and a resolving operation parameter of a Simulink mathematical model;
and creating a resolving task of the Simulink mathematical model, controlling a resolving process through an auxiliary clock, finally generating an execution model file, ending the resolving task, deleting the task and releasing the memory.
4. The simulation scheduling method of claim 3, wherein the process of creating a solving task of the Simulink mathematical model and controlling the solving through the auxiliary clock specifically comprises:
creating a resolving task of the Simulink mathematical model;
judging the type of the resolving task;
if the single-task calculation is carried out, detecting the running state of the Simulink mathematical model, calling the model file to be called according to the running state to carry out Simulink mathematical model calculation, and releasing the semaphore of the single-task calculation;
if the multi-task calculation is carried out, the calculation task of the Simulink mathematical model is decomposed into a plurality of subtasks for calculation and detection respectively, the model file to be called is called according to the operation state of each subtask calculation to carry out Simulink mathematical model calculation, and the semaphore calculated by each subtask is released.
5. The simulation scheduling method of claim 4, wherein the process of executing closed-loop simulation in a Vxworks system according to the execution model file specifically comprises:
calling an entry function in the execution model file, and initializing an interrupt function of the auxiliary clock;
resolving the model file to be executed through a clock function of an auxiliary clock, and detecting whether a sampling time point of a subtask is reached;
if the detection result is that the subtask does not reach the sampling time point, repeating the detection step;
if the detection result is that the subtask has reached the sampling time point, releasing the semaphore of the sampling time point;
judging the type of the semaphore at the sampling time point;
if the interruption resolving semaphore is the interruption resolving semaphore, suspending resolving of the model file to be executed through an interruption function of the auxiliary clock according to the interruption resolving semaphore;
if the stopping of the resolving semaphore is achieved, calling a termination function of model resolving according to the stopping of the resolving semaphore and releasing the memory to complete closed-loop simulation.
6. The simulation scheduling method of claim 1 wherein the RTW file contains descriptions of Simulink mathematical models, including data type, data input, data output and internal logic.
7. A simulation scheduling system is characterized by comprising
A model construction module: the Simulink model generation method comprises the steps of constructing a Simulink mathematical model and generating an initial model file;
an RTW file generation module: the initial model file is converted into an RTW file;
a conversion module: the system comprises a target language compiler, a model file to be called and a RTW file, wherein the target language compiler is used for calling the RTW file to be converted into the model file to be called;
code binding module: the binding machine is used for calling a make tool to automatically generate codes, and resolving the model file to be called to generate an execution model file;
and a simulation module: and the closed-loop simulation is executed in the Vxworks system according to the execution model file.
8. The simulation scheduling system of claim 7 wherein the model building module further comprises defining, building and/or packaging hardware driver files based on a VxWorks kernel program prior to being used to build the Simulink mathematical model and generate the initial model file; and establishing communication between the driving module and the simulation board card.
9. The simulation scheduling system of claim 8 wherein the code binding module comprises:
a detection module: the link editing device is used for calling a make tool to automatically generate codes, and identifying and checking the model file to be called through the codes;
a priority design module: the method comprises the steps of setting the priority of a Simulink mathematical model resolving task;
an initialization module: the system comprises a memory space, a sampling step length, a semaphore and a resolving operation parameter, wherein the memory space, the sampling step length and the semaphore are used for initializing a Simulink mathematical model;
and a solution task creation module: the method is used for creating a solving task of the Simulink mathematical model, controlling a solving process through the auxiliary clock, finally generating an execution model file, ending the solving task, deleting the task and releasing the memory.
10. A computer-readable storage medium, characterized in that a program file is stored, which is executed to implement the simulation scheduling method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210965061.6A CN115390809A (en) | 2022-08-12 | 2022-08-12 | Simulation scheduling method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210965061.6A CN115390809A (en) | 2022-08-12 | 2022-08-12 | Simulation scheduling method and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115390809A true CN115390809A (en) | 2022-11-25 |
Family
ID=84118965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210965061.6A Pending CN115390809A (en) | 2022-08-12 | 2022-08-12 | Simulation scheduling method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115390809A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116431317A (en) * | 2023-06-12 | 2023-07-14 | 西安羚控电子科技有限公司 | Vxworks-based simulation interface scheduling method |
| CN116541131A (en) * | 2023-06-29 | 2023-08-04 | 西安羚控电子科技有限公司 | Multi-model operation method and system based on VxWorks real-time system |
-
2022
- 2022-08-12 CN CN202210965061.6A patent/CN115390809A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116431317A (en) * | 2023-06-12 | 2023-07-14 | 西安羚控电子科技有限公司 | Vxworks-based simulation interface scheduling method |
| CN116431317B (en) * | 2023-06-12 | 2023-09-01 | 西安羚控电子科技有限公司 | Vxworks-based simulation interface scheduling method |
| CN116541131A (en) * | 2023-06-29 | 2023-08-04 | 西安羚控电子科技有限公司 | Multi-model operation method and system based on VxWorks real-time system |
| CN116541131B (en) * | 2023-06-29 | 2023-09-22 | 西安羚控电子科技有限公司 | Multi-model operation method and system based on VxWorks real-time system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Sifakis et al. | Building models of real-time systems from application software | |
| CN115390809A (en) | Simulation scheduling method and system | |
| CN110674590A (en) | Programming method of real-time simulation program of aircraft based on simulation software Simulink real-time extended RTX | |
| Berry | SCADE: Synchronous design and validation of embedded control software | |
| CN109799971B (en) | File generation device and method | |
| Klotzbücher et al. | Orocos rtt-lua: an execution environment for building real-time robotic domain specific languages | |
| Yip et al. | The ForeC synchronous deterministic parallel programming language for multicores | |
| CN113076143A (en) | Artificial intelligence environment adaptation method and compatibility testing method for domestic platform | |
| Khan et al. | Model-driven development of real-time systems with UML 2.0 and C | |
| CN116431317B (en) | Vxworks-based simulation interface scheduling method | |
| Harmon et al. | Interactive back-annotation of worst-case execution time analysis for Java microprocessors | |
| CN111367579A (en) | V-REP plug-in and processor in-loop simulation method based on V-REP plug-in | |
| CN114281404B (en) | Method and device for transplanting algorithm codes of industrial personal computer | |
| Schulz-Rosengarten et al. | Polyglot modal models through Lingua Franca | |
| Gilles et al. | Applying WCET analysis at architectural level | |
| WO2004088508A2 (en) | A method of creating software that is portable across different operating systems | |
| Bøgholm et al. | Towards harnessing theories through tool support for hard real-time Java programming | |
| Haberl et al. | From COLA Models to Distributed Embedded Systems Code | |
| Mkaouar et al. | An ocarina extension for AADL formal semantics generation | |
| Ober et al. | Modeling and validation of a software architecture for the ariane-5 launcher | |
| CN111596923B (en) | Haxe static link library construction method and device and electronic equipment | |
| Zhou et al. | Development of a PLC virtual machine orienting IEC 61131-3 standard | |
| Thomsen et al. | Safety Critical Java for Robotics Programming | |
| CN108984164B (en) | IMCL model-based heterogeneous multi-platform code generation system | |
| Wang et al. | Automatic code generation for synchronous reactive communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |