CN115378837A

CN115378837A - Verification method and system based on BMC prototype, computer device and storage medium

Info

Publication number: CN115378837A
Application number: CN202211001608.7A
Authority: CN
Inventors: 唐云剑
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-11-22

Abstract

The invention relates to the technical field of chip testing, in particular to a verification method and a verification system based on a BMC prototype, computer equipment and a storage medium. The method analyzes the length and the protocol of the received Ethernet message, counts the number of the messages and checks CRC, and uploads the result to a statistical log record; checking the transmitted Ethernet message CRC, counting the number of the transmitted Ethernet messages CRC, and selecting the length and the protocol; and uploading the result to a statistical log record, and realizing more randomized and higher coverage rate test of the Ethernet link test by providing an Ethernet test case interface based on an application layer in an FPGA prototype verification stage of BMC chip development. The safety and the stability of the chip Ethernet interface in the later period are greatly improved.

Description

Verification method and system based on BMC prototype, computer device and storage medium

Technical Field

The invention relates to the technical field of chip testing, in particular to a verification method and a verification system based on a BMC prototype, computer equipment and a storage medium.

Background

The chip needs to be designed, verified and manufactured to achieve the final function. The BMC chip is a small operating system independent of the server system as a baseboard management controller, and is a chip integrated on a motherboard. The verification work runs through the whole chip design flow, and from chip requirement definition, functional design development to physical implementation manufacturing, a large amount of verification is required in each link. The Tape-out cost of tens of millions to hundreds of millions of dollars makes it extremely important to discover all design defects and errors through verification before Tape-out. The FPGA prototype verification work provides guarantee for some basic function verification of the chip and verification of upper-layer software. The chip works as the work with a long continuous period, and before the chip is returned, a verification platform meeting the functional requirements is quickly built.

The server cluster generally uses a BMC instruction to perform large-scale unattended operation, including remote management, monitoring, installation, restart, and the like of the server. While remote operations, block video images and some KVM operations need to be transmitted over the ethernet port. In the early stage, the verification of the Ethernet interface can be timely carried out on a built BMC prototype verification platform, which is very important. The good test case can also be applied to later chip verification to improve the test efficiency.

At present, in the FPGA prototype verification of the BMC chip, only a link checking means is used, some basic tftp file operations are carried out, and no formed test case exists, so that the realization of a complete Ethernet test by utilizing python is important.

Disclosure of Invention

In order to solve the technical problems in the prior art, the invention provides a verification method, a verification system, computer equipment and a storage medium based on a BMC prototype, and the verification method, the verification system, the computer equipment and the storage medium realize the test of receiving and sending Ethernet data by python. And randomly sending Ethernet messages with different lengths and messages with different protocols to an Ethernet interface of the BMC prototype verification platform, wherein the test case can also be applied to later chip test.

In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:

in a first aspect, in an embodiment provided by the present invention, a BMC prototype-based verification system is provided, the method including the following steps:

analyzing the length and the protocol of the received Ethernet message, counting the number of the messages, checking CRC, and uploading the result to a log record;

checking the transmitted Ethernet message CRC, counting the number of the transmitted Ethernet messages CRC, and selecting the length and the protocol; and uploading the results to a statistical log record.

As a further aspect of the present invention, the selecting a length and a protocol of the sent ethernet packet includes: the fixed length or random length of the sent Ethernet message, and the TCP/IP protocol Ethernet message or UDP message are selected.

As a further aspect of the present invention, the BMC prototype-based verification method further includes performing a buffering process on the received ethernet packet data when there is a burst in the received ethernet packet data.

As a further aspect of the present invention, the BMC prototype-based verification method further includes performing a caching process on the sent message data when there is a burst in the received ethernet message data.

In a second aspect, in another embodiment provided by the present invention, a BMC prototype-based verification system is provided, the system comprising:

distinguishing an Ethernet message module, a received message statistical module, a received message CRC check module, a transmitted message number statistical module, a transmitted message CRC field module and a transmitted message selection module;

the distinguishing Ethernet message module is used for analyzing the length of the received Ethernet message and the protocol of the message and distinguishing a TCP/IP message or a UDP Ethernet message;

the received message counting module is used for counting the number of the received Ethernet messages and uploading the counted Ethernet messages to a log record;

the received message CRC check module is used for checking the received Ethernet message CRC and uploading the check result to log record;

the number statistical module of the message sent, is used for counting the number of Ethernet message sent, and upload to the log record of statistics;

a message CRC field sending module used for selecting the length and protocol of the Ethernet message to be sent;

and the sending message selection module is used for checking the received Ethernet message CRC and uploading the checking result to log record.

As a further scheme of the present invention, the sending message CRC field module selects a length and a protocol of the sent ethernet message, including: the fixed length or the random length of the sent Ethernet message, the TCP/IP protocol Ethernet message or the UDP message are selected and uploaded to log records.

As a further scheme of the present invention, the verification system based on the BMC prototype further includes a buffer receiving module, which performs a buffering process on the received ethernet packet data when there is a burst in the received ethernet packet data.

As a further scheme of the present invention, the BMC prototype-based verification system further includes a buffer sending module, which performs buffer processing on the received message data when there is a burst in the sent ethernet message data.

In a third aspect, in a further embodiment provided by the present invention, there is provided a computer device comprising a memory storing a computer program and a processor implementing the steps of the BMC prototype-based verification system when the computer program is loaded and executed.

In a fourth aspect, in a further embodiment provided by the present invention, a storage medium is provided, which stores a computer program that, when loaded and executed by a processor, performs the steps of the BMC prototype-based verification system.

The technical scheme provided by the invention has the following beneficial effects:

the verification method, the verification system, the computer equipment and the storage medium based on the BMC prototype realize more randomized and higher coverage rate test of the Ethernet link test by providing the Ethernet test case interface based on the application layer in the FPGA prototype verification stage based on the development of the BMC chip. The safety and the stability of the chip Ethernet interface in the later period are greatly improved.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a BMC prototype-based verification method according to an embodiment of the present invention.

Fig. 2 is a block diagram of a first structure of a verification system based on a BMC prototype according to an embodiment of the present invention.

Fig. 3 is a block diagram of a second structure of the verification system based on the BMC prototype according to an embodiment of the present invention.

Fig. 4 is a location diagram of a verification system based on a BMC prototype according to an embodiment of the present invention.

In the figure: the system comprises a distinguishing Ethernet message module-100, a received message statistical module-200, a received message CRC check module-300, a transmitted message number statistical module-400, a transmitted message CRC field module-500, a transmitted message selection module-600, a received buffer module-700 and a transmitted buffer module-800.

Detailed Description

The following describes various embodiments and/or aspects with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. However, it will be understood by those skilled in the art that these aspects may be practiced without the specific details. Specific examples of one or more embodiments will be described in detail in the following description and the accompanying drawings. However, these aspects are merely illustrative, and some of the various methods in the principles that can utilize various aspects are possible, and the description set forth is intended to include all aspects and their equivalents. In particular, the terms "embodiment," "example," "modality," "exemplary" and the like used in this specification may be construed as any modality or design described may be better or have an advantage over other modalities or designs.

In addition, various aspects and features may be embodied in a system including one or more devices, terminals, servers, equipment, components, and/or modules. It is to be understood and appreciated that the various systems may include additional pluralities of devices, terminals, servers, equipment, components, and/or modules, and/or may not include all of the pluralities of devices, terminals, servers, equipment, components, modules, etc. shown in the figures.

As used in this specification, the terms "computer program," "component," "module," "system," and the like are used interchangeably and refer to a computer-related entity, either hardware, firmware, software, a combination of software and hardware, or software in execution. For example, a component may be, but is not limited to being, a process executing on a processor, an object, a thread of execution, a program, and/or a computer. For example, it may be an application program executed on the computing device and/or all components of the computing device. More than one component may be installed within a processor and/or thread of execution. A component may be localized in a computer. A component may also be distributed between more than two computers.

Also, these components can execute from various computer readable media having various data constructs stored therein. These components may communicate by way of local and/or remote processes such as in accordance with a signal having more than one data packet (e.g., data transmitted by one component interacting with another component in a local system, distributed system, and so forth over a network such as the internet with other systems by way of the signal).

Hereinafter, the same or similar components are denoted by the same reference numerals regardless of the reference numerals in the drawings, and redundant description thereof will be omitted. In describing the embodiments disclosed in the present specification, detailed descriptions of known techniques will be omitted if it is determined that the detailed descriptions thereof will obscure the gist of the present invention. The drawings are only for easier understanding of the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited to the drawings.

The terminology used in the description is for the purpose of describing the embodiments and is not intended to be limiting of the invention. Where not specifically mentioned, singular expressions in this specification include plural expressions. The use of "comprising" and/or "comprising" in the specification does not exclude the presence or addition of one or more other elements or components other than the stated elements.

The terms first, second, etc. may be used to describe various elements or components, but the elements or components are not limited by the terms. The term is used to distinguish one element or constituent element from another element or constituent element. Therefore, the first element or component mentioned below may be the 2 nd element or component within the technical idea of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in the same sense as commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, terms defined in a general dictionary should not be interpreted in an ideal or excessive manner unless they are explicitly defined.

In addition, the term "or" is not meant to be an exclusive "or" but rather an inclusive "or". That is, "X employs A or B" means one of the alternatives of natural connotations unless there is any other specificity or context is ambiguous. That is, X utilizes A or; when X uses B or X uses A and B, "X uses A or B" may be any of the above. Also, it should be understood that the term "and/or" as used in this specification refers to all possible combinations of more than one of the associated items included in the list.

In addition, the terms "information" and "data" used in this specification are generally used interchangeably.

The suffixes "module" and "section" used for the constituent elements in the following description are given or mixed for convenience of writing the description, and do not have mutually different meanings or functions.

In the BMC prototype verification stage, the Ethernet messages with different formats and different packet lengths are sent to the network ports, and the pressure test is carried out, so that the coverage rate of a verification scene can be improved, and the failure rate of the network ports in the later period is greatly reduced. Meanwhile, the complete test case can help the later chip tester to realize the chip test.

Specifically, the embodiments of the present invention will be further explained below with reference to the drawings.

Referring to fig. 1, fig. 1 is a flowchart illustrating a BMC prototype-based verification method according to an embodiment of the present invention, and as shown in fig. 1, the BMC prototype-based verification method includes steps S10 to S60.

S10, analyzing the length of the received Ethernet message and the protocol of the message, and distinguishing the TCP/IP message from the UDP Ethernet message.

And S20, counting the number of the received Ethernet messages, and uploading to a statistical log record. And the comparison is carried out by BMC verification personnel.

And S30, checking the received Ethernet message CRC, and uploading the checking result to a log record. And comparing the data with later-stage BMC verifiers.

S40, counting the number of the sent Ethernet messages, and uploading to a log record;

s50, selecting the length and the protocol of the sent Ethernet message.

Wherein, the selecting the length of the sent ethernet message and the protocol includes: the sent Ethernet message is selected to be of a fixed length or an instant length, and a TCP/IP protocol Ethernet message or a UDP message, and is uploaded to a log record for later-stage BMC verification personnel to refer and compare.

And S60, checking the CRC of the received Ethernet message, and uploading the checking result to a log record. And comparing the data with later-stage BMC verifiers.

In an embodiment of the present invention, the BMC prototype-based verification method further includes performing a buffering process on the received ethernet packet data when there is a burst in the received ethernet packet data. And normal operation is ensured.

In an embodiment of the present invention, the BMC prototype-based verification method further includes performing a buffering process on the data packet in a scenario where data congestion occurs in a bottom link (an ethernet packet occurs). And normal operation is ensured.

The invention acts on the FPGA prototype verification stage based on the development of the BMC chip, and realizes the test of more randomization and higher coverage rate of the Ethernet link test by providing the Ethernet test case interface based on the application layer. The safety and the stability of the Ethernet interface of the chip at the later stage are greatly improved.

It should be understood that although the steps are described above in a certain order, the steps are not necessarily performed in the order described. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, some steps of this embodiment may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.

In one embodiment, referring to fig. 2, in an embodiment of the present invention, a verification system based on a BMC prototype is further provided, where the system includes a differentiated ethernet message module 100, a received message counting module 200, a received message CRC check module 300, a sent message number counting module 400, a sent message CRC field module 500, and a sent message selection module 600.

The ethernet message distinguishing module 100 is configured to analyze the length of the received ethernet message and a protocol of the message, and distinguish whether the received ethernet message is a TCP/IP message or a UDP ethernet message.

The received message counting module 200 is configured to count the number of received ethernet messages and upload the counted number to a log record. And the comparison is carried out by BMC verification personnel.

The received message CRC check module 300 is configured to check the received ethernet message CRC and upload a check result to a log record. And comparing by later BMC verification personnel.

The number of sent messages counting module 400 is configured to count the number of sent ethernet messages, and upload the counted number to a statistical log record.

The message CRC field sending module 500 is configured to select a length and a protocol of the ethernet message to be sent.

In the embodiment of the present invention, the sending message CRC field module 500 selects the length and protocol of the sent ethernet message, including: the sent Ethernet message is selected to be of a fixed length or an instant length, and a TCP/IP protocol Ethernet message or a UDP message, and is uploaded to a log record for later-stage BMC verification personnel to refer and compare.

The sending message selection module 600 is configured to check the CRC of the received ethernet message, and upload a check result to a log record. And comparing the data with later-stage BMC verifiers.

In the embodiment of the present invention, the selecting the length and the protocol of the sent ethernet packet includes: the sent Ethernet message is selected to be of a fixed length or an instant length, and a TCP/IP protocol Ethernet message or a UDP message, and is uploaded to a log record for later-stage BMC verification personnel to refer and compare.

Referring to fig. 3, in the embodiment of the present invention, the BMC prototype-based verification system further includes a buffer receiving module 700, which performs a buffering process on received ethernet packet data when there is a burst in the received ethernet packet data. And normal operation is ensured.

Referring to fig. 3, in the embodiment of the present invention, the BMC prototype-based verification system further includes a buffer sending module 800, which performs buffering processing on received message data when there is a burst in the sent ethernet message data. And normal operation is ensured.

In an embodiment of the present invention, the BMC prototype-based verification system further includes a buffer processing unit configured to buffer the data packet in a scenario where data congestion occurs in the underlying link (e.g., an ethernet packet occurs). And normal operation is ensured.

In an embodiment of the present invention, the verification system based on the BMC prototype further includes a buffer processing unit configured to buffer the data packet in a scenario where data congestion occurs in the underlying link (e.g., an ethernet packet occurs). And normal operation is ensured.

The invention acts on the FPGA prototype verification stage based on BMC chip development, and realizes the test of more randomization and higher coverage rate of the Ethernet link test by providing the Ethernet test case interface based on the application layer. The safety and the stability of the Ethernet interface of the chip at the later stage are greatly improved.

In one embodiment, there is also provided a computer device in an embodiment of the present invention, including at least one processor, and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor, the instructions being executable by the at least one processor to cause the at least one processor to execute the prototype-based verification computer device, the processor implementing the steps of the method embodiments as described above when executing the instructions:

And S20, counting the number of the received Ethernet messages, and uploading to a log record. And the comparison is carried out by BMC verification personnel.

And S30, checking the CRC of the received Ethernet message, and uploading the checking result to a log record. And comparing the data with later-stage BMC verifiers.

s50, selecting the length and the protocol of the sent Ethernet message.

Wherein, the selecting the length and the protocol of the sent ethernet message includes: the transmitted Ethernet message is selected from a fixed length or a random length and a TCP/IP protocol Ethernet message or a UDP message, and is uploaded to a log record for later-stage BMC verifier to refer and compare.

In an embodiment of the present invention, the BMC prototype-based verification system further includes performing a buffering process on the received message data when there is a burst of the received ethernet message data. And normal operation is ensured.

The computer equipment comprises user equipment and network equipment. Wherein the user equipment includes but is not limited to computers, smart phones, PDAs, etc.; the network device includes, but is not limited to, a single network server, a server group consisting of a plurality of network servers, or a Cloud Computing (Cloud Computing) based Cloud consisting of a large number of computers or network servers, wherein Cloud Computing is one of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. Wherein, the computer equipment can be operated alone to realize the invention, and also can be accessed into the network and realize the invention through the interactive operation with other computer equipment in the network. The network in which the computer device is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a VPN network, and the like.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

In an embodiment of the present invention, there is also provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the above-described method embodiment:

s50, selecting the length and the protocol of the sent Ethernet message.

Wherein, the selecting the length and the protocol of the sent ethernet message includes: the sent Ethernet message is selected to be of a fixed length or an instant length, and a TCP/IP protocol Ethernet message or a UDP message, and is uploaded to a log record for later-stage BMC verification personnel to refer and compare.

It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory.

Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant only to be exemplary, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A verification method based on a BMC prototype is characterized by comprising the following steps:

analyzing the length and the protocol of the received Ethernet message, counting the number of the messages and checking CRC, and uploading the length and the analysis result of the protocol of the Ethernet message, the counting result of the number of the messages and the checking result of the CRC to a statistical log record;

checking the transmitted Ethernet message CRC, counting the number of the transmitted Ethernet messages CRC, and selecting the length and the protocol; and uploading the CRC check result, the number counting result, the length and the protocol selection result to a counting log record.

2. The BMC prototype-based verification method of claim 1, wherein the selecting a length and a protocol of the ethernet packet to be sent comprises: the fixed length or random length of the sent Ethernet message, and the TCP/IP protocol Ethernet message or UDP message are selected.

3. The BMC prototype-based verification method according to claim 1, further comprising buffering the received message data in the presence of a burst of accepted ethernet message data.

4. The BMC prototype-based verification method of claim 1, further comprising buffering the received message data in the presence of a burst of the transmitted ethernet message data.

5. A BMC prototype-based verification system, comprising: distinguishing an Ethernet message module, a received message statistical module, a received message CRC check module, a transmitted message number statistical module, a transmitted message CRC field module and a transmitted message selection module;

the message sending number counting module is used for counting the number of the sent Ethernet messages and uploading the counted number to a statistical log record;

and the sending message selection module is used for checking the received Ethernet message CRC and uploading the checking result to a log record.

6. The BMC prototype-based verification system of claim 5 wherein said transmit message CRC field module selects a length, protocol of the transmitted ethernet message, comprising: the fixed length or the random length of the sent Ethernet message, the TCP/IP protocol Ethernet message or the UDP message are selected and uploaded to log records.

7. The BMC prototype-based verification system according to claim 5, wherein the BMC prototype-based verification system further comprises a receive buffer module that buffers received ethernet message data in the event that there is a burst.

8. The BMC prototype-based verification system of claim 5, wherein the BMC prototype-based verification system further comprises a buffer module for buffering the received message data in case of a burst of the transmitted ethernet message data.

9. A computer device comprising a memory storing a computer program and a processor implementing the steps of the BMC prototype-based authentication method according to any one of claims 1 to 4 when the computer program is loaded and executed.

10. A storage medium storing a computer program which, when loaded and executed by a processor, carries out the steps of the BMC prototype-based authentication method according to any one of claims 1 to 4.