CN115374029A - Information transmission method, information transmission device, storage medium and electronic equipment - Google Patents

Information transmission method, information transmission device, storage medium and electronic equipment Download PDF

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Publication number
CN115374029A
CN115374029A CN202210954219.XA CN202210954219A CN115374029A CN 115374029 A CN115374029 A CN 115374029A CN 202210954219 A CN202210954219 A CN 202210954219A CN 115374029 A CN115374029 A CN 115374029A
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control chip
chip
information transmission
communication interface
memory
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陈帝亮
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Shenzhen Haiyi Zhixin Technology Co Ltd
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Shenzhen Haiyi Zhixin Technology Co Ltd
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Priority to CN202210954219.XA priority Critical patent/CN115374029A/en
Publication of CN115374029A publication Critical patent/CN115374029A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application discloses information transmission method is applied to information transmission system, information transmission system includes first control chip, second control chip and memory chip, first control chip with memory chip passes through first communication interface connection, the second control chip with memory chip passes through second communication interface connection, the method includes: when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the storage chip carry out information transmission; and when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip perform information transmission. By means of the method and the device, the communication effect between the first control chip and the second control chip is prevented from being influenced.

Description

Information transmission method, information transmission device, storage medium and electronic equipment
Technical Field
The present application relates to the field of computer technologies, and in particular, to an information transmission method and apparatus, a storage medium, and an electronic device.
Background
The main control chip and the micro-processing unit can communicate with each other through an Inter-Integrated Circuit (I2C) or a Universal Asynchronous Receiver/Transmitter (UART).
Disclosure of Invention
The embodiment of the application provides an information transmission method, an information transmission device, a storage medium and electronic equipment, information to be transmitted between a first control chip and a second control chip does not need to be transmitted through an I2C serial bus or a UART, information storage is carried out by taking the storage chip as a bridge between the first control chip and the second control chip, even if the transmitted information amount is large, instruction transmission cannot be influenced, congestion cannot be caused to a communication channel between the first control chip and the second control chip, and then the communication effect between the first control chip and the second control chip can be prevented from being influenced. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides an information transmission method, which is applied to an information transmission system, where the information transmission system includes a first control chip, a second control chip, and a memory chip, the first control chip is connected to the memory chip through a first communication interface, and the second control chip is connected to the memory chip through a second communication interface, where the method includes:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the storage chip carry out information transmission;
and when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip carry out information transmission.
In a second aspect, an embodiment of the present application provides an information transmission apparatus, which is applied to an information transmission system, where the information transmission system includes a first control chip, a second control chip, and a memory chip, the first control chip is connected to the memory chip through a first communication interface, the second control chip is connected to the memory chip through a second communication interface, and the apparatus includes:
the first information transmission module is used for carrying out information transmission between the first control chip and the storage chip when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state;
and the second information transmission module is used for carrying out information transmission between the second control chip and the storage chip when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state.
In a third aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of the first aspect described above.
The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:
by adopting the embodiment, by adding the memory chip in the information transmission system in which the first control chip and the second control chip cooperate, when the first control chip monitors that the target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the memory chip perform information transmission; and when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip carry out information transmission. The information that first control chip and second control chip need be transmitted need not transmit through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through the memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, can not cause the communication channel between first control chip and the second control chip to block up yet, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an information transmission system according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an information transmission system according to an embodiment of the present application;
fig. 3 is a schematic flowchart of an information transmission method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of an information transmission method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of an information transmission method according to an embodiment of the present application;
fig. 6 is a schematic flowchart of an information transmission method according to an embodiment of the present application;
fig. 7 is an exemplary schematic diagram of an information transmission system according to an embodiment of the present application;
fig. 8 is a flowchart illustrating an information transmission method according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of an information transmission apparatus according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of an information transmission apparatus according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of an information transmission apparatus according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.
In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art. In addition, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
The method may be implemented in dependence on a computer program, operable on an information transfer device based on the von neumann architecture. The computer program may be integrated into the application or may run as a separate tool-like application.
The information transmission system in the embodiment of the application can be a mobile terminal, a tablet computer, a handheld device, a wearable device, a computing device, an intelligent interactive tablet and other processing devices.
The present application will be described in detail with reference to specific examples.
The following description provides examples, and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements described without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For example, the described methods may be performed in an order different than the order described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.
The communication between the main control chip and the micro control unit mainly realizes the transmission of instructions such as control, alarm, active report and the like, if the communication is used for transmitting Log information, when the transmission quantity of the Log information between the main control chip and the micro control unit is large, the communication channel is blocked, and the communication effect between the main control chip and the micro processing unit is influenced.
Please refer to fig. 1, which is a schematic structural diagram of an information transmission system, where the information transmission system includes a first control chip, a second control chip, and a memory chip.
The first control chip may be a main control chip, the main control chip may be a core component of a motherboard or a hard disk, the second control chip may be a micro control Unit, the micro control Unit appropriately reduces the frequency and specification of a Central Processing Unit (CPU), and integrates peripheral interfaces such as a memory, a counter, a Universal Serial Bus (USB), and even a Liquid Crystal Display (LCD) driving circuit on a single chip.
The memory chip may be a memory chip implemented by Application Specific Integrated Circuit (ASIC) technology or a memory chip implemented by Field Programmable Gate Array (FPGA) technology. The storage chip can be a Flash chip, the Flash is one of the storage chips, and data in the Flash chip can be modified through a specific program. Flash often means Flash Memory in the field of electronics and semiconductors, namely 'Flash', which is called Flash EEPROM Memory, and is independent of a first control chip and a second control chip.
The first control chip may include a first communication Interface, the second control chip may include a second communication Interface, the first communication Interface may include at least one Interface, the number of specific interfaces included in the communication Interface is not limited, and the first communication Interface may be a Serial Peripheral Interface (SPI) communication Interface or a Secure Digital Input and Output (SDIO) Interface. Similarly, the number of interfaces included in the first communication interface may be the same as or different from the number of interfaces included in the second communication interface. The first communication interface is a communication interface corresponding to the first control chip, and the second communication interface is a communication interface corresponding to the second control chip. Correspondingly, a connection interface corresponding to the first communication interface and a connection interface corresponding to the second communication interface are included on the memory chip.
Specifically, as shown in fig. 2, for example, the first communication interface and the second communication interface use SPI communication interfaces, target pins corresponding to the first communication interface and the second communication interface may be Chip Select (CS) pins, other pins corresponding to the first communication interface and the second communication interface may be Clock Signal (CLK) pins, master Output Slave Input (MOSI) pins, and Master Input Slave Output (MISO) pins. Therefore, the first control chip is connected with the memory chip through the first communication interface, the second control chip is connected with the memory chip through the second communication interface, and each pin of the first communication interface can be connected with the corresponding pin of the second communication interface and then connected with the memory chip.
Any of the following embodiments is implemented based on the information transmission system described above.
Referring to fig. 3, a schematic flow chart of an information transmission method provided in an embodiment of the present application is shown, where the information transmission method is applied to an information transmission system, and the information transmission method may include the following steps:
s101, when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the storage chip carry out information transmission;
the target pin may be a chip select pin, and the chip select pin is a pin corresponding to a chip select signal, and is also referred to as an enable pin, and is used to indicate whether a chip where the target pin is located is selected or not, and whether data, address or command is independently transmitted with a certain chip or not. The target pin may have two level states, which may be an occupied state and a non-occupied state, and when the target pin is in the occupied state, it indicates that the current memory chip is performing an information transmission process, and when the target pin is in the non-occupied state, it indicates that the current memory chip is not performing the information transmission process, where the level state of the target pin may be a high level state, and when the target pin is in the non-occupied state, the level state of the target pin may be a low level state.
The first control chip can monitor the level state of a target pin corresponding to the first communication interface in real time, the monitored level state of the target pin can be a high level state or a low level state, and when the first control chip monitors that the target pin is in the high level state, the first control chip and the second control chip do not perform information transmission with the storage chip currently, that is, the first control chip can start to perform information transmission with the storage chip currently.
The information transmission between the first control chip and the memory chip can be performed to store information into the memory chip for the first control chip, or to read information stored in the memory chip for the first control chip.
And S102, when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip perform information transmission.
The second control chip may monitor a level state of a target pin corresponding to the second communication interface in real time, the monitored level state of the target pin may be a high level state or a low level state, and when the second control chip monitors that the target pin is brought into the high level state, it indicates that the current first control chip and the current second control chip do not perform information transmission with the memory chip, that is, the second control chip may start to perform information transmission with the memory chip at present.
The information transmission between the second control chip and the memory chip can be performed to store information into the memory chip for the second control chip, or to read information stored in the memory chip for the second control chip.
By adopting the embodiment, by adding the memory chip in the information transmission system in which the first control chip and the second control chip cooperate, when the first control chip monitors that the target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the memory chip perform information transmission; and when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip carry out information transmission. The information that first control chip and second control chip need to be transmitted does not need to be transmitted through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, also can not cause the communication channel between first control chip and the second control chip to block up, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
Referring to fig. 4, a flow chart of an information transmission method provided in an embodiment of the present application is schematically shown, where the information transmission method is applied to an information transmission system, and the information transmission method may include the following steps:
s201, when the first control chip monitors that a target pin corresponding to the first communication interface is in a high level state, the first control chip writes first information into the storage chip; or; when the first control chip monitors that a target pin corresponding to the first communication interface is in a high level state, the first control chip reads the first information and/or second information from the memory chip, wherein the second information is information written into the memory chip by the second control chip;
the first information is information that the first control chip needs to store to the memory chip, and the first information may be log information, where the log information is operation information for recording the system.
At present, a memory chip may store first information written into the memory chip by a first control chip before, or second information stored into the memory chip by a second control chip, and the first control chip may read both the first information and the second information, or may read only any one of the information according to a requirement.
The first control chip and the storage chip carry out information transmission, and simultaneously the first control chip sets a target pin corresponding to the first communication interface to be in a low level state;
according to the characteristic that the target pin is the chip selection pin, when the first control chip and the memory chip carry out information transmission, the level state needs to be set to be a low level state, and the current chip and the memory chip are informed to the outside that the information transmission is carried out.
S202, the first control chip sets a target pin corresponding to the first communication interface to be in a high level state.
After the first control chip and the memory chip perform information transmission, the control right of the memory chip is released, and the first control chip can set the level state of the target pin to be a high level state to inform that the information transmission between the external first control chip and the memory chip is finished.
By adding the memory chip in the information transmission system in which the first control chip and the second control chip cooperate, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high-level state, if the first control chip has information that needs to be written into the memory chip, the first control chip may select to write the first information into the memory chip, if the first control chip needs to read the information stored in the memory chip, the first information that was previously written into the memory chip by the first control chip or the second information that is written into the memory chip by the second control chip may also be read, after the information transmission between the first control chip and the memory chip is finished, the first control chip may set the target pin corresponding to the first communication interface to a high level, so as to inform that the information transmission process between the external first control chip and the memory chip is finished, and the other chips may start to perform information transmission with the memory chip. The information that first control chip and second control chip need be transmitted need not transmit through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through the memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, can not cause the communication channel between first control chip and the second control chip to block up yet, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
Referring to fig. 5, a flow chart of an information transmission method provided in an embodiment of the present application is schematically illustrated, where the information transmission method is applied to an information transmission system, and the information transmission method may include the following steps:
s301, when the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, the second control chip writes second information into the memory chip; or; when the second control chip monitors that a target pin corresponding to the second communication interface is in a high level state, the second control chip reads first information or second information from the memory chip, wherein the first information is information written into the memory chip by the first control chip;
currently, the memory chip may store first information that is written into the memory chip by the first control chip before, or second information that is stored into the memory chip by the second control chip, and the second control chip may read both the first information and the second information, or may read any one of the first information and the second information.
And the second control chip and the storage chip carry out information transmission, and simultaneously the second control chip sets a target pin corresponding to the second communication interface to be in a low level state.
According to the characteristic that the target pin is the chip selection pin, when the second control chip and the memory chip carry out information transmission, the level state needs to be set to be a low level state, and the current existing process of carrying out information transmission between the chip and the memory chip is informed to the outside.
And S302, the second control chip sets a target pin corresponding to the second communication interface to be in a high level state.
After the second control chip and the memory chip perform information transmission, the control right of the memory chip is released, and the second control chip can set the level state of the target pin to be a high level state to inform that the information transmission process between the external second control chip and the memory chip is finished.
It should be noted that, in practical applications, the method embodiment in the present application may perform only the process of information transmission between the first control chip and the memory chip, may perform only the process of information transmission between the second control chip and the memory chip, or may perform the processes of information transmission between the first control chip and the memory chip and the processes of information transmission between the second control chip and the memory chip and the processes of information transmission between the first control chip and the memory chip and the processes of information transmission between the second control chip and the memory chip are performed alternately.
By adding the memory chip in the information transmission system in which the first control chip and the second control chip cooperate, when the second control chip monitors that the target pin corresponding to the second communication interface is in a high-level state, if the second control chip has information that needs to be written into the memory chip, the second control chip can select to write the second information into the memory chip, if the second control chip needs to read the information stored in the memory chip, the second information that was previously written into the memory chip by the second control chip or the first information that was written into the memory chip by the first control chip can also be read, after the information transmission between the second control chip and the memory chip is finished, the second control chip can set the target pin corresponding to the second communication interface to be a high level, so as to inform that the information transmission process between the external second control chip and the memory chip is finished, and other chips can start to perform information transmission with the memory chip. The information that first control chip and second control chip need be transmitted need not transmit through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through the memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, can not cause the communication channel between first control chip and the second control chip to block up yet, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
Referring to fig. 6, which is a schematic flow chart of an information transmission method provided in an embodiment of the present application, the information transmission method is applied to an information transmission system, and the information transmission system may further include at least one fixed storage, for example, referring to fig. 7, a first control chip may be connected to one fixed storage, a second control chip may be connected to another fixed storage, and a connection manner adopted by the first control chip and the second control chip is not limited, and the information transmission method may include the following steps:
401, when the first control chip monitors that the target pin corresponding to the first communication interface is in a low level state and the second control chip performs information transmission with the memory chip, the first control chip stores corresponding information into a fixed memory and continuously monitors the level state of the target pin;
the first control chip and the second control chip use file systems with the same format.
The software mechanism in the operating system that is responsible for managing and storing file information is called a file management system, referred to as a file system for short. A file system is a method and data structure used by an operating system to specify files on a storage device or partition, i.e., a method of organizing files on a storage device.
The file system specifies rules for naming files. These rules include the maximum number of characters for a filename, which characters can be used, and in some systems how long the filename suffix can be. The file system also includes a format for finding a specified path for the file through the directory structure. Therefore, the file system with the same format is used, so that the files can be conveniently inquired in the storage chip, and the required files can be found out more quickly.
When the first control chip monitors that the target pin is in a low level state, two possibilities exist, the first is that the first control chip and the storage chip are in information transmission, the second is that the current second control chip and the storage chip are in information transmission, and when the second control chip and the storage chip are in information transmission, the first control chip cannot perform information transmission with the storage chip, so when the first control chip needs to store information to the storage chip, the first control chip can temporarily store the part of information to the fixed memory in advance. When the first control chip monitors that the target pin corresponding to the first communication interface is in a high level state, the part of information is taken out from the fixed memory and stored in the memory chip.
The fixed Memory may be any Memory capable of implementing a storage function, such as a Random Access Memory (RAM), a Read Only Memory (ROM), and the like.
402, when the first control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the first control chip reads corresponding information from the fixed memory and writes the information into the memory chip.
When the first control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the first control chip indicates that the memory chip does not currently perform information transmission with any chip, and therefore the first control chip can read corresponding information from the fixed memory and store the information into the memory chip.
By adopting the embodiment, when necessary, the information corresponding to the first control chip is stored in the fixed memory, and when the first control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the first control chip reads the corresponding information from the fixed memory and writes the information into the memory chip, so that the information transmission process is more flexible and convenient; the information that first control chip and second control chip need to be transmitted does not need to be transmitted through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, also can not cause the communication channel between first control chip and the second control chip to block up, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
Referring to fig. 8, which is a schematic flow chart of an information transmission method provided in an embodiment of the present application, the information transmission method is applied to an information transmission system, and the information transmission system may further include at least one fixed storage, for example, referring to fig. 7, a first control chip may be connected to one fixed storage, a second control chip may be connected to another fixed storage, and a connection manner adopted by the first control chip and the second control chip is not limited, and the information transmission method may include the following steps:
s501, when the second control chip monitors that a target pin corresponding to the second communication interface is in a low level state and the first control chip and the memory chip perform information transmission, the second control chip stores corresponding information into a fixed memory and continuously monitors the level state of the target pin;
when the second control chip monitors that the target pin is in a low level state, two possibilities exist, the first is that the second control chip and the storage chip are in information transmission, the second is that the first control chip and the storage chip are in information transmission at present, when the first control chip and the storage chip are in information transmission, the second control chip cannot perform information transmission with the storage chip, therefore, when the second control chip needs to store information to the storage chip, the second control chip can temporarily store the part of information to the fixed memory firstly. And when the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, the part of information is taken out from the fixed memory and stored in the memory chip.
It should be noted that, as shown in fig. 8, the information corresponding to the first control chip and the information corresponding to the second control chip may be stored in different memories, and of course, the information corresponding to the first control chip and the information corresponding to the second control chip may be stored in the same memory.
S502, when the second control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the second control chip reads corresponding information from the fixed memory and writes the information into the memory chip.
When the second control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the second control chip indicates that the memory chip does not currently perform information transmission with any chip, and therefore the second control chip can read corresponding information from the fixed memory and store the information into the memory chip.
By adopting the embodiment, the information corresponding to the first control chip is stored in the fixed memory, and when the second control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the second control chip reads the corresponding information from the fixed memory and writes the information into the memory chip, so that the information transmission process is more flexible and convenient; the information that first control chip and second control chip need to be transmitted does not need to be transmitted through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, also can not cause the communication channel between first control chip and the second control chip to block up, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.
Please refer to fig. 9, which shows a schematic structural diagram of an information transmission apparatus according to an exemplary embodiment of the present application. The information transmission means may be implemented as all or part of the terminal by software, hardware or a combination of both. The information transmission device is applied to an information transmission system, the information transmission system comprises a first control chip, a second control chip and a storage chip, the first control chip is connected with the storage chip through a first communication interface, the second control chip is connected with the storage chip through a second communication interface, and the information transmission device 1 comprises a first information transmission module 11 and a second information transmission module 12.
The first information transmission module 11 is configured to perform information transmission between the first control chip and the memory chip when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state;
and the second information transmission module 12 is configured to perform information transmission between the second control chip and the memory chip when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state.
Optionally, the unoccupied state includes that a target pin corresponding to the first communication interface is in a high level state.
Optionally, the first information transmission module 11 is specifically configured to:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a high level state, the first control chip writes first information into the memory chip;
or;
when the first control chip monitors that the target pin corresponding to the first communication interface is in a high level state, the first control chip reads the first information and/or second information from the memory chip, wherein the second information is information written into the memory chip by the second control chip.
Optionally, the second information transmission module 12 is specifically configured to:
when the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, the second control chip writes second information into the memory chip;
or;
when the second control chip monitors that a target pin corresponding to the second communication interface is in a high level state, the second control chip reads first information or second information from the memory chip, wherein the first information is information written into the memory chip by the first control chip.
Optionally, the first information transmission module 12 is further specifically configured to:
the first control chip and the storage chip carry out information transmission, and simultaneously the first control chip sets a target pin corresponding to the first communication interface to be in a low level state;
the second information transmission module 12 is further specifically configured to:
and the second control chip and the storage chip carry out information transmission, and simultaneously the second control chip sets a target pin corresponding to the second communication interface to be in a low level state.
Optionally, as shown in fig. 10, the apparatus 1 further includes:
a first state setting module 13, configured to set, by the first control chip, a target pin corresponding to the first communication interface to a high level state;
and a second state setting module 14, configured to set, by the second control chip, a target pin corresponding to the second communication interface to a high level state.
Optionally, as shown in fig. 11, the apparatus 1 further includes:
the first storage module 15 is configured to, when the first control chip monitors that a target pin corresponding to the first communication interface is in a low level state and the second control chip performs information transmission with the storage chip, store corresponding information in a fixed memory by the first control chip and continuously monitor a level state of the target pin;
the first information transmission module 11 is further configured to, when the first control chip monitors that the level state of the target pin is switched from the low level state to the high level state, read, by the first control chip, corresponding information from the fixed memory and write the information into the memory chip;
the second storage module 16 is configured to, when the second control chip monitors that a target pin corresponding to the second communication interface is in a low level state and the first control chip performs information transmission with the storage chip, store corresponding information in a fixed memory by the second control chip and continuously monitor a level state of the target pin;
the second information transmission module 12 is further configured to, when the second control chip monitors that the level state of the target pin is switched from the low level state to the high level state, read, by the second control chip, corresponding information from the fixed memory and write the information into the memory chip.
Optionally, in the device 1, the first control chip is connected to the memory chip through a first communication interface, and the second control chip is connected to the memory chip through a second communication interface;
the first control chip and the second control chip use file systems with the same format.
It should be noted that, when the information transmission apparatus provided in the foregoing embodiment executes the information transmission method, only the division of the functional modules is illustrated, and in practical applications, the above functions may be distributed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. In addition, the information transmission apparatus and the information transmission method provided by the above embodiments belong to the same concept, and details of implementation processes thereof are referred to as method embodiments, which are not described herein again.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
By adopting the embodiment, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high level state, if the first control chip has information to be written into the memory chip, the first control chip may select to write the first information into the memory chip, if the first control chip needs to read the information stored in the memory chip, the first information previously written into the memory chip by the first control chip or the second information written into the memory chip by the second control chip may also be read, after the information transmission between the first control chip and the memory chip is finished, the first control chip may set the target pin corresponding to the first communication interface to be a high level, so as to inform that the information transmission process between the external first control chip and the memory chip is finished, and other chips may start to perform information transmission with the memory chip. When the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, if the second control chip has information needing to be written into the memory chip, the second control chip can select to write the second information into the memory chip, if the second control chip needs to read the information stored in the memory chip, the second control chip can also read the second information previously written into the memory chip by the second control chip or the first information written into the memory chip by the first control chip, after the information transmission between the second control chip and the memory chip is finished, the second control chip can set the target pin corresponding to the second communication interface to be in a high level state so as to inform that the information transmission process between the external second control chip and the memory chip is finished, and other chips can start to perform information transmission with the memory chip. The first control chip and the second control chip use the file systems with the same format, so that the files can be conveniently inquired in the storage chip, and the required files can be found out more quickly. The information that first control chip and second control chip need be transmitted need not transmit through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through the memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, can not cause the communication channel between first control chip and the second control chip to block up yet, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the above-mentioned method. The computer-readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVD, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.
Please refer to fig. 12, which provides a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 12, the electronic device 1000 may include: at least one processor 1001, at least one network interface 1004, a user interface 1003, memory 1005, at least one communication bus 1002.
The communication bus 1002 is used to implement connection communication among these components.
The user interface 1003 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 1003 may further include a standard wired interface and a wireless interface.
The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.
Processor 1001 may include one or more processing cores, among other things. The processor 1001 interfaces various components throughout the electronic device 1000 using various interfaces and lines to perform various functions of the electronic device 1000 and to process data by executing or performing instructions, programs, code sets, or instruction sets stored in the memory 1005 and invoking data stored in the memory 1005. Alternatively, the processor 1001 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 1001 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 1001, but may be implemented by a single chip.
The Memory 1005 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 1005 includes a non-transitory computer-readable medium. The memory 1005 may be used to store an instruction, a program, code, a set of codes, or a set of instructions. The memory 1005 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 1005 may optionally be at least one memory device located remotely from the processor 1001. As shown in fig. 12, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and an information transmission method application program.
In the electronic device 1000 shown in fig. 12, the user interface 1003 is mainly used as an interface for providing input for a user, and acquiring data input by the user; the processor 1001 may be configured to call an application program for generating an information transmission method stored in the memory 1005, where the information transmission method is applied to an information transmission system, where the information transmission system includes a first control chip, a second control chip, and a memory chip, the first control chip is connected to the memory chip through a first communication interface, the second control chip is connected to the memory chip through a second communication interface, and specifically performs the following operations:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the storage chip carry out information transmission;
and when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip carry out information transmission.
In one embodiment, the unoccupied state includes a high state of a target pin corresponding to the first communication interface.
In an embodiment, when the first control chip monitors that the target pin corresponding to the first communication interface is in a non-occupied state, and the first control chip performs information transmission with the memory chip, the processor 1001 specifically performs the following operations:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a high level state, the first control chip writes first information into the memory chip;
or;
when the first control chip monitors that the target pin corresponding to the first communication interface is in a high level state, the first control chip reads the first information and/or second information from the memory chip, wherein the second information is information written into the memory chip by the second control chip.
In an embodiment, when the processor 1001 executes the following operation when the second control chip monitors that the target pin corresponding to the second communication interface is in the non-occupied state and the second control chip performs information transmission with the memory chip:
when the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, the second control chip writes second information into the memory chip;
or;
when the second control chip monitors that a target pin corresponding to the second communication interface is in a high level state, the second control chip reads first information or second information from the memory chip, wherein the first information is information written into the memory chip by the first control chip.
In one embodiment, when the processor 1001 performs information transmission between the first control chip and the memory chip, the following operations are specifically performed:
the first control chip and the storage chip carry out information transmission, and simultaneously the first control chip sets a target pin corresponding to the first communication interface to be in a low level state;
the information transmission between the second control chip and the storage chip comprises the following steps:
and the second control chip and the storage chip carry out information transmission, and simultaneously the second control chip sets a target pin corresponding to the second communication interface to be in a low level state.
In one embodiment, after the processor 1001 performs the information transmission between the first control chip and the memory chip, the following operations are specifically performed:
the first control chip sets a target pin corresponding to the first communication interface to be in a high level state;
after the second control chip and the memory chip perform information transmission, the method further comprises the following steps:
and the second control chip sets a target pin corresponding to the second communication interface to be in a high level state.
In one embodiment, the processor 1001 performs the following operations:
when the first control chip monitors that the target pin corresponding to the first communication interface is in a low level state and the second control chip and the storage chip carry out information transmission, the first control chip stores corresponding information into a fixed memory;
when the first control chip monitors that the target pin corresponding to the first communication interface is in a non-occupied state and the first control chip and the memory chip perform information transmission, specifically executing the following operations:
when the first control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the first control chip reads corresponding information from the fixed memory and writes the information into the storage chip;
or the processor 1001 performs the following operations:
when the second control chip monitors that a target pin corresponding to the second communication interface is in a low level state and the first control chip and the memory chip carry out information transmission, the second control chip stores corresponding information into a fixed memory and continuously monitors the level state of the target pin;
when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state and the second control chip and the memory chip perform information transmission, specifically executing the following operations:
and when the second control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the second control chip reads corresponding information from the fixed memory and writes the information into the storage chip.
And when the second control chip monitors that the target pin corresponding to the second communication interface is in a low level state and the first control chip and the memory chip carry out information transmission, the second control chip stores corresponding information into a fixed memory.
By adopting the embodiment, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high level state, if the first control chip has information to be written into the memory chip, the first control chip may select to write the first information into the memory chip, if the first control chip needs to read the information stored in the memory chip, the first information previously written into the memory chip by the first control chip or the second information written into the memory chip by the second control chip may also be read, after the information transmission between the first control chip and the memory chip is finished, the first control chip may set the target pin corresponding to the first communication interface to be a high level, so as to inform that the information transmission process between the external first control chip and the memory chip is finished, and other chips may start to perform information transmission with the memory chip. When the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, if the second control chip has information needing to be written into the memory chip, the second control chip can select to write the second information into the memory chip, if the second control chip needs to read the information stored in the memory chip, the second information previously written into the memory chip by the second control chip or the first information written into the memory chip by the first control chip can also be read, and after the information transmission between the second control chip and the memory chip is finished, the second control chip can set the target pin corresponding to the second communication interface to be in a high level state so as to inform that the information transmission process between the external second control chip and the memory chip is finished, and other chips can start to perform information transmission with the memory chip. The first control chip and the second control chip use file systems with the same format, so that files can be conveniently inquired in the storage chip, and the required files can be found out more quickly. The information that first control chip and second control chip need be transmitted need not transmit through I2C serial bus or UART, carry out information storage as the bridge of first control chip and second control chip through the memory chip, even the information quantity of transmission is great, can not influence the transmission of instruction yet, can not cause the communication channel between first control chip and the second control chip to block up yet, and then can avoid the communication effect between first control chip and the second control chip to receive the influence.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and should not be taken as limiting the scope of the present application, so that the present application will be covered by the appended claims.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art will recognize that the embodiments described in this specification are preferred embodiments and that acts or modules referred to are not necessarily required for this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some service ports, indirect coupling or communication connection of devices or units, and may be electrical or in other forms.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned memory comprises: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program, which is stored in a computer-readable memory, and the memory may include: flash disks, read-Only memories (ROMs), random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of the disclosure in any way. It is intended that all equivalent variations and modifications made in accordance with the teachings of the present disclosure be covered thereby. Embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (10)

1. An information transmission method is applied to an information transmission system, the information transmission system comprises a first control chip, a second control chip and a storage chip, the first control chip is connected with the storage chip through a first communication interface, the second control chip is connected with the storage chip through a second communication interface, and the method comprises the following steps:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip and the storage chip carry out information transmission;
and when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the second control chip and the storage chip carry out information transmission.
2. The method of claim 1, wherein the unoccupied state comprises a target pin corresponding to the first communication interface being in a high state.
3. The method according to claim 2, wherein when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip performs information transmission with the memory chip, including:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a high level state, the first control chip writes first information into the memory chip;
or;
when the first control chip monitors that the target pin corresponding to the first communication interface is in a high level state, the first control chip reads the first information and/or second information from the memory chip, wherein the second information is information written into the memory chip by the second control chip.
4. The method according to claim 2, wherein when the second control chip monitors that a target pin corresponding to the second communication interface is in a non-occupied state, the information transmission between the second control chip and the memory chip includes:
when the second control chip monitors that the target pin corresponding to the second communication interface is in a high level state, the second control chip writes second information into the memory chip;
or;
when the second control chip monitors that a target pin corresponding to the second communication interface is in a high level state, the second control chip reads first information or second information from the memory chip, wherein the first information is information written into the memory chip by the first control chip.
5. The method of claim 2, wherein the first control chip performs information transmission with the memory chip, and comprises:
the first control chip and the storage chip carry out information transmission, and simultaneously the first control chip sets a target pin corresponding to the first communication interface to be in a low level state;
the second control chip and the storage chip are used for information transmission, and the information transmission comprises the following steps:
and the second control chip and the storage chip carry out information transmission, and simultaneously the second control chip sets a target pin corresponding to the second communication interface to be in a low level state.
6. The method according to claim 2 or 5, wherein after the first control chip performs information transmission with the memory chip, the method further comprises:
the first control chip sets a target pin corresponding to the first communication interface to be in a high level state;
after the second control chip and the memory chip perform information transmission, the method further includes:
and the second control chip sets a target pin corresponding to the second communication interface to be in a high level state.
7. The method of claim 2, further comprising:
when the first control chip monitors that a target pin corresponding to the first communication interface is in a low level state and the second control chip and the storage chip carry out information transmission, the first control chip stores corresponding information into a fixed memory and continuously monitors the level state of the target pin;
when the first control chip monitors that the target pin corresponding to the first communication interface is in a non-occupied state, the information transmission between the first control chip and the storage chip is performed, including:
when the first control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the first control chip reads corresponding information from the fixed memory and writes the information into the storage chip;
or;
when the second control chip monitors that a target pin corresponding to the second communication interface is in a low level state and the first control chip and the memory chip carry out information transmission, the second control chip stores corresponding information into a fixed memory and continuously monitors the level state of the target pin;
when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state, the information transmission between the second control chip and the memory chip is performed, including:
and when the second control chip monitors that the level state of the target pin is switched from the low level state to the high level state, the second control chip reads corresponding information from the fixed memory and writes the information into the storage chip.
8. The method of claim 1, wherein the first control chip is connected to the memory chip through a first communication interface, and the second control chip is connected to the memory chip through a second communication interface, comprising:
the first control chip is connected with the storage chip through a first communication interface, and the second control chip is connected with the storage chip through a second communication interface;
the first control chip and the second control chip use file systems with the same format.
9. An information transmission device, characterized in that, is applied to information transmission system, information transmission system includes first control chip, second control chip and memory chip, first control chip with memory chip passes through first communication interface connection, the second control chip with memory chip passes through second communication interface connection, the device includes:
the first information transmission module is used for carrying out information transmission between the first control chip and the storage chip when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state;
and the second information transmission module is used for carrying out information transmission between the second control chip and the storage chip when the second control chip monitors that the target pin corresponding to the second communication interface is in a non-occupied state.
10. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 8.
CN202210954219.XA 2022-08-09 2022-08-09 Information transmission method, information transmission device, storage medium and electronic equipment Pending CN115374029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210954219.XA CN115374029A (en) 2022-08-09 2022-08-09 Information transmission method, information transmission device, storage medium and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210954219.XA CN115374029A (en) 2022-08-09 2022-08-09 Information transmission method, information transmission device, storage medium and electronic equipment

Publications (1)

Publication Number Publication Date
CN115374029A true CN115374029A (en) 2022-11-22

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Family Applications (1)

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Country Status (1)

Country Link
CN (1) CN115374029A (en)

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