CN115362658A

CN115362658A - Apparatus and method for flexible cell selection

Info

Publication number: CN115362658A
Application number: CN202180022551.6A
Authority: CN
Inventors: 侯平; 王燕鸣; 王原野
Original assignee: Zheku Technology Co ltd
Current assignee: Zeku Technology Shanghai Corp Ltd
Priority date: 2020-03-19
Filing date: 2021-03-16
Publication date: 2022-11-18
Anticipated expiration: 2041-03-16
Also published as: WO2021113883A3; CN115362658B; WO2021113883A2

Abstract

A baseband chip may include a frequency offset/decimation (FSD) circuit configured to receive Radio Frequency (RF) samples. The FSD circuit may rotate the RF samples by a fixed amount relative to a Synchronization Signal Block (SSB) center frequency to obtain a plurality of grating frequencies. The baseband chip may also include a Primary Synchronization Signal (PSS) processing circuit that may estimate a set of Integer Frequency Offsets (IFOs) for each of the plurality of grating frequencies, where each IFO may be estimated for a different SCS step size across the SCS range. The PSS processing circuitry may perform PSS correlation for each IFO. The PSS processing circuit may select a PSS candidate for each raster frequency based at least in part on the PSS correlation performed for each raster frequency.

Description

Apparatus and method for flexible cell selection

Cross Reference to Related Applications

This application is related to and claims priority from U.S. provisional patent application No.62/991,905, filed 3/19/2020, which is incorporated herein by reference in its entirety.

Technical Field

Embodiments of the present disclosure relate to apparatuses and methods for wireless communication.

Background

Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasting. In cellular communications such as 4 generation (4G) Long Term Evolution (LTE) and 5 generation (5G) New Radio (NR), the 3 rd generation partnership project (3 GPP) defines various mechanisms for cell selection.

Disclosure of Invention

Embodiments of an apparatus and method for harmonic interference cancellation are disclosed herein.

According to one aspect of the disclosure, a baseband chip is disclosed. The baseband chip may include: a frequency shifting/decimation circuit configured to receive Radio Frequency (RF) samples. The frequency offset/decimation circuit may be further configured to: the RF samples are rotated by a fixed amount relative to the synchronization signal block SSB center frequency to obtain a plurality of raster frequencies, where each raster frequency of the plurality of raster frequencies can be associated with a rotation of one of the fixed amounts. The baseband chip may further include: a Primary Synchronization Signal (PSS) processing circuit configured to estimate a set of Integer Frequency Offsets (IFOs) for each of a plurality of grating frequencies, wherein each integer frequency offset IFO of the set of IFOs is estimated for a different subcarrier spacing (SCS) step size across a SCS range. The PSS processing circuit may be further configured to: PSS correlation is performed for each IFO in a set of IFOs associated with each of a plurality of raster frequencies. The PSS processing circuit may be further configured to: selecting a PSS candidate for each raster frequency based at least in part on a PSS correlation performed for each of a plurality of raster frequencies, wherein the PSS candidate is selected for SSB detection.

In accordance with another aspect of the present disclosure, an apparatus is disclosed. The apparatus may include: a receiver configured to receive Radio Frequency (RF) samples. The apparatus may also include a baseband chip. The baseband chip may include frequency shifting/decimation circuitry configured to receive the RF samples. The frequency offset/decimation circuit may be further configured to: the RF sample is rotated by a fixed amount relative to the SSB center frequency to obtain a plurality of grating frequencies, where each grating frequency of the plurality of grating frequencies can be associated with a rotation of one of the fixed amounts. The baseband chip may further include: a PSS processing circuit configured to estimate a set of IFOs for each of a plurality of grating frequencies, wherein each IFO of the set of IFOs is estimated for a different SCS step size across a sub-SCS range. The PSS processing circuit may be further configured to: PSS correlation is performed for each IFO in a set of IFOs associated with each of a plurality of raster frequencies. The PSS processing circuit may be further configured to: selecting a PSS candidate for each raster frequency based at least in part on a PSS correlation performed for each of a plurality of raster frequencies, wherein the PSS candidate is selected for SSB detection.

In accordance with another aspect of the present disclosure, a method is disclosed. The method can comprise the following steps: the receiver receives the RF samples. The method may further comprise: the frequency shifting/decimation circuit rotates the RF samples by a fixed amount relative to the SSB center frequency to obtain a plurality of raster frequencies, each of which is associated with a rotation of one of the fixed amounts. The method may further comprise: the PSS processing circuit estimates a set of IFOs for each of the plurality of grating frequencies, wherein each IFO in the set of IFOs is estimated for a different SCS step size across the SCS range. The method may further comprise: the PSS processing circuitry performs PSS correlation for each IFO in a set of IFOs associated with each of a plurality of raster frequencies. The method may further comprise: the PSS processing circuit selects a PSS candidate for each raster frequency based at least in part on a PSS correlation performed for each of the plurality of raster frequencies, wherein the PSS candidate is selected for SSB detection.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates an example wireless network in accordance with some embodiments of the present disclosure.

Fig. 2 illustrates a block diagram of an apparatus including a baseband chip, a Radio Frequency (RF) chip, and a host chip, according to some embodiments of the disclosure.

Fig. 3A illustrates a block diagram of an extended view of the baseband chip of fig. 2, in accordance with some embodiments of the present disclosure.

Fig. 3B illustrates an expanded view of the PSS processing circuit depicted in fig. 3A, in accordance with some embodiments of the present disclosure.

Fig. 3C illustrates a block diagram of an SSB in accordance with some embodiments of the present disclosure.

Fig. 3E illustrates a graphical representation of the degradation of PSS correlation performance with respect TO, in accordance with some embodiments of the disclosure.

Figure 3F illustrates a graphical representation of PSS related degradation due to FO in accordance with some embodiments of the present disclosure.

Fig. 4A illustrates a flow diagram of a first exemplary method of wireless communication of a baseband chip, in accordance with some embodiments of the present disclosure.

Fig. 4B illustrates a flow diagram of a second exemplary method of wireless communication of a PSS processing circuit according to some embodiments of the disclosure.

Fig. 4C illustrates a flow diagram of a third example method of wireless communication of a Secondary Synchronization Signal (SSS) processing block, in accordance with some embodiments of the present disclosure.

Figure 4D illustrates a flow diagram of a third example method of wireless communication of a Physical Broadcast Channel (PBCH) processing block, in accordance with some embodiments of the present disclosure.

Fig. 5 illustrates a block diagram of an example node, in accordance with some embodiments of the present disclosure.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," or the like, indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used in a singular sense to describe any feature, structure, or characteristic, or may be used in a plural sense to describe a combination of features, structures, or characteristics, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the," depending at least in part on the context, may also be understood to convey a singular use or convey a plural use. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described.

Various aspects of a wireless communication system will now be described with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and are illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, procedures, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

The techniques described herein may be used for various wireless communication networks such as Code Division Multiple Access (CDMA) systems, time Division Multiple Access (TDMA) systems, frequency Division Multiple Access (FDMA) systems, orthogonal Frequency Division Multiple Access (OFDMA) systems, single carrier frequency division multiple access (SC-FDMA) systems, wireless Local Area Network (WLAN) systems, and other networks. The terms "network" and "system" are often used interchangeably. The CDMA network may implement a Radio Access Technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA2000, and so on. A TDMA network may implement a RAT, such as Global System for Mobile communications (GSM). The OFDMA network may implement a RAT, such as LTE or NR. The WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs described above, as well as other wireless networks and RATs.

In LTE system design, energy detection of CRS in RF samples may be used for initial cell selection and acquisition of User Equipment (UE) due to ubiquitous cell-specific reference signals (CRS). Cell selection using CRS energy detection may be performed using RF samples with a wide frequency bandwidth (also referred to as "wideband frequencies"), which is efficient in terms of time and computational simplicity compared to sampling narrowband RF samples. However, since data transmission may also be included in the wideband frequency searched by the UE, the RF samples may be corrupted. This means that the accuracy of energy detection may be limited when using wideband frequencies for initial cell selection. Furthermore, when communicating using a Time Division Duplex (TDD) frame structure in an LTE network, uplink and downlink transmissions may share the same frequency band, and thus, in some cases, a UE may not be able to separate and detect control signals (CRSs) transmitted by a base station from uplink data or control signals transmitted by other UEs located nearby. Thus, these conventional methods may only provide a rough indication of cell quality and may require the incorporation of time-consuming and complex measurements, which increase power consumption and computational delay in performing initial cell selection.

In some other conventional approaches, energy detection has been further extended to correlation detection, which uses the PSS reference to identify a PSS strength indicator, rather than the strength of the energy level of the received signal, when performing initial cell selection. Performing correlation (rather than pure energy detection) may increase the reliability of proper cell selection, since PSS is defined by orthogonality in the frequency domain and over a relatively narrow bandwidth (also referred to as "narrowband frequency"). Conventional PSS correlation techniques may be performed in the time domain by applying an Inverse Fast Fourier Transform (IFFT) to the PSS reference in the frequency domain. Since the reference defined in the frequency domain is based on an M-sequence and the IFFT is an orthogonal transform, the PSS reference can maintain its orthogonality in the time domain at the nyquist sampling rate. That is, when the PSS is shifted with reference to an integer sampling period defined at the nyquist rate in the time domain, orthogonality is almost achieved. Thus, PSS correlation may be performed in the frequency or time domain, depending on the target implementation delay, complexity, power consumption, shared hardware, etc. of the system.

However, while conventional PSS correlation has advantages over pure energy detection, there are still some drawbacks to this approach, which may limit its use in 5G NR applications. For example, conventional PSS correlation omits band-pass or band-select filters and therefore cannot remove wideband noise during correlation and other processing. Furthermore, in conventional PSS correlation, relatively accurate sampling times are ignored, which may lead TO inaccuracies in estimating the Timing Offset (TO) and/or the Frequency Offset (FO). For example, since the UE does not initially know the exact PSS timing to perform the detection, the sampling result may be different from the assumed ideal PSS waveform, which in turn reduces PSS correlation performance. Therefore, the conventional method using large TO and FO may degrade PSS correlation performance when performing initial cell selection, thereby degrading signal quality. Thus, this approach may not be compatible with 5G NR, which requires the UE to operate at lower signal-to-noise ratio (SNR) conditions than can be achieved using conventional PSS correlations.

To address these and other issues, the baseband chip of the present disclosure may perform PSS correlation using a set of IFOs estimated for each grating frequency (for each narrowband grating frequency obtained from wideband RF samples). More specifically, each IFO in a set of IFOs may be estimated for different SCS steps (e.g., 0.25SCS, 0.5SCS, etc.) across an SCS range (e.g., -3 to +3SCS, -4 to +4SCS, etc.). Each IFO may be used for PSS correlation and/or convolution of its associated grating frequency. Then, for each raster frequency, the PSS candidate with the largest correlation peak score may be selected for further processing. This and other information (determined for each raster frequency) may then be sent to a Physical (PHY) layer controller, which may use the information to determine which raster frequency/frequencies to acquire for initial cell selection. Therefore, by improving FO estimation using the present method, PSS correlation can be extended to cell selection for 5G NR by enabling the UE to operate at lower SNR conditions compared to the conventional method. Additional details are described below in connection with fig. 1-5.

Fig. 1 illustrates an example wireless network 100 in which certain aspects of the present disclosure may be implemented, in accordance with some embodiments of the present disclosure. As shown in fig. 1, wireless network 100 may include a network of nodes, such as User Equipment (UE) 102, access nodes 104, and core network elements 106. The user device 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle networking (V2X) network, a cluster network, a smart grid node, or an internet of things (IoT) node. It should be understood that the user device 102 is shown as a mobile telephone by way of illustration only and not limitation.

The access node 104 may be a device that communicates with the user equipment 102, such as a wireless access point, a Base Station (BS), a node B, an enhanced node B (eNodeB or eNB), a next generation node B (gdnodeb or gNB), a cluster master node, and so on. The access node 104 may have a wired connection to the user device 102, a wireless connection to the user device 102, or any combination thereof. The access node 104 may be connected to the user equipment 102 through multiple connections, and the user equipment 102 may be connected to other access nodes than the access node 104. The access node 104 may also be connected to other user equipment. It should be understood that the access node 104 is illustrated by a radio tower, by way of illustration and not limitation.

The core network element 106 may serve the access node 104 and the user equipment 102 to provide core network services. Examples of the core network element 106 may include a Home Subscriber Server (HSS), a Mobility Management Entity (MME), a Serving Gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an Evolved Packet Core (EPC) system, which is the core network of an LTE system. Other core network elements may be used in LTE and other communication systems. In some embodiments, the core network element 106 comprises an access and mobility management function (AMF) device, a Session Management Function (SMF) device, or a User Plane Function (UPF) device of a core network of the NR system. It is to be understood that the core network element 106 is shown as a set of rack-mounted servers, by way of illustration and not limitation.

The core network element 106 may be connected to a large network, such as the internet 108 or another Internet Protocol (IP) network, to transmit packet data over any distance. As such, data from user device 102 may be communicated to other user devices connected to other access points, including, for example, computer 110 connected to internet 108 (e.g., using a wired or wireless connection), or tablet 112 wirelessly connected to internet 108 via router 114. Thus, computer 110 and tablet 112 provide further examples of possible user devices, and router 114 provides an example of another possible access node.

A general example of a rack-mounted server is provided as an illustration of the core network element 106. However, there may be multiple elements in the core network, including database servers, such as database 116, and security and authentication servers, such as authentication server 118. For example, database 116 may manage data related to a user's subscription to a network service. A Home Location Register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and the like. In NR systems, an authentication server function (AUSF) device may be a specific entity that performs user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between the core network elements 106, the authentication server 118, and the database 116 may be local connections within the single rack.

Each element in fig. 1 may be considered a node of wireless network 100. More details on possible implementations of the node are provided as an example in the description of node 500 in fig. 5. The node 500 may be configured as the user equipment 102, the access node 104 or the core network element 106 in fig. 1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in fig. 1. As shown in fig. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown connected to each other by a bus, but other connection types are also permissible. When node 500 is user device 102, additional components may also be included, such as User Interfaces (UIs), sensors, and the like. Similarly, when node 500 is configured as a core network element 106, node 500 may be implemented as a blade in a server system. Other implementations are also possible.

Transceiver 506 may include any suitable device for transmitting and/or receiving data. The node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. Antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or antenna arrays may be used to receive multiple spatially multiplexed data streams. Further, examples of node 500 may communicate using wired technology instead of (or in addition to ) wireless technology. For example, the access node 104 may communicate wirelessly with the user equipment 102 and may communicate with the core network element 106 through a wired connection (e.g., through an optical or coaxial cable). Other communication hardware, such as a Network Interface Card (NIC), may also be included.

As shown in fig. 5, node 500 may include a processor 502. Although only one processor is shown, it will be appreciated that multiple processors may be included. The processor 502 may include a microprocessor, a micro-controller unit (MCU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a state machine, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. The processor 502 may be a hardware device having one or more processing cores. The processor 502 may execute software. Software is to be construed broadly as instructions, instruction sets, code segments, program code, programs, subprograms, software modules, applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software may include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also allowed under the broad category of software.

As shown in fig. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories may be included. The memory 504 may broadly include both memory and storage devices. For example, memory 504 may include Random Access Memory (RAM), read Only Memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically Erasable Programmable ROM (EEPROM), CD-ROM or other optical disk storage, a Hard Disk Drive (HDD) such as a magnetic disk storage or other magnetic storage device, a flash memory drive, a Solid State Drive (SSD), or any other medium that may be used to carry or store desired program code in the form of instructions that may be accessed and executed by processor 502. Broadly, the memory 504 can be implemented by any computer-readable medium, such as a non-transitory computer-readable medium.

The processor 502, memory 504 and transceiver 506 may be implemented in various forms in the node 500 for performing wireless communication functions. In some embodiments, the processor 502, the memory 504, and the transceiver 506 of the node 500 are implemented (e.g., integrated) on one or more systems on a chip (SoC). In one example, processor 502 and memory 504 may be integrated on an Application Processor (AP) SoC (sometimes referred to as a "host," herein referred to as a "host chip") that handles application processing in an Operating System (OS) environment, including generating raw data to be transmitted. In another example, the processor 502 and memory 504 may be integrated on a Baseband Processor (BP) SoC (sometimes referred to as a "modem," herein a "baseband chip") that converts raw data, e.g., from a host chip, into a signal that can be used to modulate a carrier frequency for transmission, or vice versa, which may run a real-time operating system (RTOS). In yet another example, processor 502 and transceiver 506 (and in some cases memory 504) may be integrated on an RF SoC (sometimes referred to as a "transceiver," herein "RF chip") that transmits and receives RF signals using antenna 508. It will be appreciated that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated into a single SoC. For example, the baseband chip and the RF chip may be integrated into a single SoC that manages all radio functions for cellular communication.

Referring back to fig. 1, in some embodiments, any suitable node of the wireless network 100 (e.g., user equipment 102 or access node 104) may perform PSS processing to determine a set of IFOs that span the SCS step size range when sending a signal to another node (e.g., via from user equipment 102 to access node 104, or vice versa) to improve the accuracy and delay associated with cell selection by selecting candidate PSS samples for further processing rather than processing all samples, as described in detail below. Thus, the accuracy of correctly selecting a cell for acquisition may be improved while reducing the time and power consumption associated with cell selection, as compared to known solutions in which SSB detection does not include determining an IFO to select a candidate raster frequency.

Fig. 2 illustrates a block diagram of an apparatus 200, the apparatus 200 including a baseband chip 202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. The apparatus 200 may be an example of any suitable node of the wireless network 100 in fig. 1, such as the user equipment 102 or the access node 104. As shown in fig. 2, apparatus 200 may include a baseband chip 202, an RF chip 204, a host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to fig. 5. In addition to on-chip memory (also referred to as "internal memory," such as registers, buffers, or caches) on each

chip

202, 204, or 206, the apparatus 200 may also include an external memory 208 (e.g., system memory or main memory) that each

chip

202, 204, or 206 may share through the system/main bus. Although baseband chip 202 is shown in fig. 2 as a separate SoC, it is understood that baseband chip 202 and RF chip 204 may be integrated into one SoC in one example; in another example, the baseband chip 202 and the host chip 206 may be integrated into one SoC; in yet another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated into one SoC, as described above.

In the uplink, the host chip 206 may generate and send raw data to the baseband chip 202 for encoding, modulation, and mapping. The baseband chip 202 may also access raw data generated by the host chip 206 and stored in the external memory 208, for example, using Direct Memory Access (DMA). Baseband chip 202 may first encode the raw data (e.g., by source coding and/or channel coding) and modulate the encoded data using any suitable modulation technique, such as Multiple Phase Shift Keying (MPSK) modulation or Quadrature Amplitude Modulation (QAM). The baseband chip 202 may perform any other function, such as symbol or layer mapping, to convert raw data into a signal that may be used to modulate a carrier frequency for transmission. In the uplink, baseband chip 202 may send modulated signals to RF chip 204.RF chip 204 may convert the modulated signal in digital form to an analog signal, i.e., an RF signal, via a transmitter and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, frequency up-conversion, or sample rate conversion. Antenna 210 (e.g., an antenna array) may transmit RF signals provided by a transmitter of RF chip 204.

In the downlink, antenna 210 may receive and transmit RF signals to a receiver (Rx) of RF chip 204.RF chip 204 may perform any suitable front-end RF functions such as filtering, IQ imbalance compensation, down conversion, or sample rate conversion to convert the RF signal to a low frequency digital signal (baseband signal) that may be processed by baseband chip 202. In the downlink, the baseband chip 202 may demodulate and decode the baseband signal to extract raw data that may be processed by the host chip 206. Baseband chip 202 may perform additional functions such as error checking, demapping, channel estimation, descrambling, and the like. The raw data provided by the baseband chip 202 may be sent to the host chip 206 or stored directly in the external memory 208.

In some implementations, the baseband chip 202 may perform PSS correlation using a set of IFOs estimated for each grating frequency (for each narrowband grating frequency obtained from the wideband RF samples). More specifically, each IFO in a set of IFOs may be estimated for different SCS steps (e.g., 0.25SCS, 0.5SCS, etc.) across an SCS range (e.g., -3 to +3SCS, -4 to +4 SCS). Each IFO may be used for PSS correlation and/or convolution of its associated grating frequency. Then, for each raster frequency, the PSS candidate with the largest correlation peak score may be selected for further processing. This and other information determined for each raster frequency may then be sent to the PHY layer controller, which may use the information in general to determine which raster frequency/frequencies to acquire for initial cell selection. Thus, by improving FO estimation using the present method implemented by baseband chip 202, PSS correlation can be extended to cell selection of 5G NR by enabling the UE to operate at lower SNR conditions compared to conventional methods. Additional details are described below in conjunction with fig. 3A-4.

Fig. 3A illustrates a detailed view of the baseband chip 202 of fig. 2, in accordance with some embodiments of the present disclosure. Fig. 3B illustrates a detailed view of the PSS processing circuit 304 depicted in fig. 3A according to some embodiments of the disclosure. Fig. 3C illustrates a block diagram of an SSB 350 in accordance with some embodiments of the present disclosure. Fig. 3E illustrates a graphical representation 360 of the degradation of PSS correlation performance with respect TO, in accordance with some embodiments of the disclosure. Fig. 3F illustrates a graphical representation 370 of PSS related degradation due to FO in accordance with some embodiments of the disclosure. Fig. 3A to 3E will be described together.

Referring to fig. 3A, the baseband chip 202 may include a plurality of functional blocks configured to perform PSS correlation compatible with initial cell selection for 5G NR communication. These functional blocks may include, for example, frequency offset/extraction circuitry 302 (hereinafter "FSD circuitry 302"), PSS processing circuitry 304, SSS processing circuitry 306, PBCH processing circuitry 308, and SSS/PBCH measurement circuitry 310 (hereinafter "measurement circuitry 310"). Each circuit in baseband chip 202 may be implemented as an Integrated Circuit (IC), such as an ASIC, dedicated to performing its functions disclosed herein. The operations may begin when the UE switches from a powered-off state to a powered-on state. In 5G NR, the baseband chip 202 of the UE may perform synchronization in an initial cell selection phase using the SSB 350 (an example of which is shown in fig. 3C). When the UE powers up, it may attempt to find a cell to acquire. Since NRs operate over a wide frequency range (e.g., wideband), the initial task of a UE is to identify the appropriate frequencies (e.g., RF samples) at which the NR cells are deployed and which can be detected by the UE.

To reduce the complexity of frequency selection, the SSBs 350 of the NR cells must be deployed on the synchronization raster frequency. That is, the synchronization raster indicates the frequency location of SSBs that may be used by the UE for system acquisition during initial cell selection. Each raster frequency may be associated with a cell (e.g., a base station), and the base station may transmit SSBs 350 at predetermined intervals (e.g., 20 ms) known a priori by the UE on its dedicated raster frequency. Thus, the RF sample 301 may include a plurality of different SSBs, each SSB being transmitted by a corresponding base station at a predetermined interval (e.g., 20 ms). As shown in the figure. As shown in fig. 3C, the SSB 350 may include one or more PSS symbols 330, one or more SSS symbols 332, and one or more PBCH symbols 334, as shown in fig. 3C. Thus, by rotating the RF sample 301 by a fixed amount relative to the SSB center frequency, multiple grating frequencies can be obtained from the RF sample 301. The receiver of the baseband chip 202 in fig. 2 may obtain wideband RF samples 301 (hereinafter "RF samples 301") that include multiple RF signals, each RF signal associated with a different narrowband frequency (also referred to as a "grating frequency"). The FSD circuit 302 may be configured to receive the RF samples 301 as input from a receiver (Rx) shown in fig. 2, which may initiate operations described below in association with initial cell selection.

More specifically, FSD circuit 302 may be configured to convert RF samples 301 to a lower sampling rate narrowband raster frequency (hereinafter "raster frequency") for subsequent PSS/SSS/PBCH processing. Each raster frequency may be associated with a potential cell for UE selection. To obtain multiple grating frequencies from the RF sample 301, the FSD circuit 302 may be configured to rotate the RF sample 301 by a fixed amount relative to the SSB center frequency. For example, the FSD circuit 302 may rotate the RF sample 301 to a desired grating frequency because the RF center frequency may be different from the SSB center frequency. By rotating the RF sample 301 by a fixed amount relative to the SSB center frequency, multiple grating frequencies may be obtained for processing by other circuitry of the baseband chip 202. For example, the RF band is typically very wide, e.g., 20MHz, 40MHz, 100MHz bandwidth for NR. In contrast, SSB bandwidth is narrow in comparison, occupying only 240 SCS. This means that if SCS =15KHz, the SSB bandwidth is 3.6MHz. Within a20 MHz RF bandwidth, there may be many SSBs, each with its own SSB center frequency. Typically, the RF center frequency is different from the single SSB center frequency. For purposes of illustration, assume that the difference between the RF center frequency and the SSB center frequency is Δ (in MHz), and that the RF samples must be rotated by an amount of Δ so that the RF samples can be shifted to the desired SSB center frequency to determine the SSB frequency using PSS and SSS detection.

However, because the sampling rate of wideband RF samples 301 is greater than the desired sampling rate for the narrowband grating frequencies, FSD circuit 302 may include a decimator to reduce the sampling rate for each grating frequency. For example, as shown in fig. 3C, the PSS/SSS symbol bandwidth in SSB 350 may be equal to 127SCS, and the sampling rate to recover the PSS/SSS bandwidth is at least 127SCS according to the nyquist sampling theorem. For a hardware implementation, the factor M may be chosen to be a power of "2", so M =128 is the smallest integer choice, since 128=2 ⁷ . Unfortunately, the minimum sampling rate of 128SCS is highThe quality of PSS-based detection is not large enough, especially in cases of practical impairments of low SNR, fading, FO, TO, doppler, etc. The next M that satisfies the power of 2 requirement (e.g., M = 2) ⁸ ) Is 256, which means 2 times oversampling (in the sense that 128 is the minimum value of M).

Therefore, to improve the accuracy of PSS detection, the grating frequency 303 may be oversampled by a factor of 2 to achieve a sampling rate of 256 SCS. The PBCH bandwidth of 240SCS and PSS/SSS symbol bandwidth of 127SCS will be covered using a sampling rate of 256 SCS. In addition, the sampling rate of 256SCS will cover the demodulation reference signals (DMRS) in the PBCH symbols 334, which may further improve the cell detection probability when used by the baseband chip 202 for initial cell selection. Further, since the timing of the PSS symbol 330 is unknown, oversampling can increase the number of samples tested in the same or smaller time period, thereby increasing the probability of estimating the TO of the PSS symbol 330 with high accuracy.

The graphical representation 370 of fig. 3E illustrates the degradation of PSS correlation performance relative TO without any other impairments (e.g., FO, doppler, etc.). The x-axis is the timing in nyquist sampling periods and the y-axis is the associated performance degradation in dB. It can be observed from the graphical representation 370 that as TO increases from 0 TO 0.5 cycles at the Nyquist sampling rate, the degradation increases from 0dB TO-1.95 dB, which is a significant degradation in performance. The graphical representation 370 further illustrates that the performance degradation increases TO-0.45 dB when TO is greater than or equal TO 0.25 cycles at the nyquist sampling rate, where at least 0.25 cycles of TO can be achieved with an oversampling rate of 2. In other words, when using twice the nyquist sampling rate, the worst case of TO is at most 0.25 cycles at the nyquist sampling rate, which may result in a performance loss of at most-0.45 dB. With an oversampling ratio of greater than 2, for example, oversampling ratio 4, when TO is equal TO or greater than 0.125 (= 0.5/4) period, the performance degradation may not exceed-0.2 dB, and thus a significant gain cannot be obtained. Thus, the over-sampling ratio 2 may be the best trade-off in terms of performance and complexity.

FSD circuit 302 may be configured to pass raster frequency 303 through a low pass filter before performing downsampling. Using a low pass filter, FSD circuit 302 may perform anti-aliasing and remove any unnecessary signals/noise from the specified raster frequency 303 before passing the raster frequency 303 to one or more of PSS processing circuit 304, SSS processing circuit 306, PBCH processing circuit 308, and/or measurement circuit 310 for further processing. SSB processing may begin with PSS processing circuitry 304 as shown in fig. 3A and 3B.

Fig. 3B illustrates two equivalent implementations that may be used for PSS correlation by the PSS processing circuit 304. The upper branch in fig. 3B, including convolution circuit 314 (e.g., a filter), shows a time domain implementation, and the lower branch, including fourier transform (FFT) 316, correlation circuit 318, and IFFT320, shows a frequency domain implementation, where output 1 313 and output 2315 produce the same result. Convolution circuit 314 in the time domain and correlation circuit 318 in the frequency domain may not have the same format, but the two circuits may be associated. For example, given the size of FFT 316, convolution circuit 314 (e.g., a filter) and correlation circuit 318 have a 1-to-1 mapping, and frequency domain multiplication is equivalent to time domain convolution. Since the FFT 316 and IFFT320 are orthogonal transforms, the time-domain correlation and frequency-domain correlation may be equivalent, i.e., a 1-to-1 mapping or a 1-to-1 correspondence. Correlation may be performed in either domain and the result obtained by applying a filter or correlator accordingly. The convolution circuit 314 may be a PSS reference filter defined in the time domain and convolved with the stream samples at the grating frequency 303. Thus, the convolution circuit 314 can obtain the equivalent PSS correlation result in the time domain and the sample index of the PSS position accordingly.

However, estimating IFO at different SCS steps across the SCS range may require multiplying each sample before performing convolution in the time domain. On the other hand, if the correlation is considered in the frequency domain with the subcarrier offset, no multiplication may be needed. The use of FFT 316 and IFFT320 further enhances the benefits of estimating multiple IFOs across the SCS range in the frequency domain, as compared to performing the calculations in the time domain, since these two transforms reduce or eliminate the multiplication, thereby reducing computational complexity and power consumption when estimating the FO hypothesis.

Still referring to fig. 3B, by converting the raster frequency 303 from the time domain to samples in the frequency domain, the PSS processing circuit 304 may exploit correlation because their normalized linear correlation coefficient may be relatively high if the PSS sequence in the time domain is similar to the PSS sequence in the frequency domain. Thus, the correlation result (obtained by correlation circuit 318) is mapped back to the time domain using IFFT320, and the correlation result in the frequency domain (e.g., output 2 315) may be defined by each of the three PSS references used to obtain the correlation peak in the time domain, which may correspond to the start timing of the PSS symbol. In addition to timing accuracy, FO is estimated to reduce and/or eliminate signal interference caused by FO, since otherwise PSS correlation performance would be degraded, as shown in fig. 3F.

Referring to fig. 3F, FO of multiple SCS would cause more than 20dB loss in PSS correlation performance. Therefore, it may be beneficial to estimate the IFO of different SCS's when estimating FO. The SCS range of the estimated IFO may be provided to the PSS processing circuit 304 by higher layer management, e.g., based on information from the most likely FO in SCS units. Taking 20ppm of 3GHz carrier frequency as an example, the maximum FO is 60kHz; if the current SCS =15kHz, 60kHz equals 4SCS, but if the current SCS =30kHz, 60kHz equals 2SCS. Then, using this example, for a smaller SCS =15kHz, the scan spans an SCS range of-4 to +4, the IFO is estimated for { -4, -3, -2, -1,0, +1, +2, +3, +4} with an SCS step size of 1. Conversely, for larger SCS =30khz, SCS range is-2 to +2, IFO is estimated at { -2, -1,0, +1, +2} with SCS step size of 1.

As shown in fig. 3F, when IFO =0, ideal correlation performance can be obtained. By rotating the grating frequency 303 with various IFOs, the curve will shift the offset of the IFOs to the left or right accordingly, and the peak fraction of the correlation can be measured at FO =0 (with the IFO rotating (or compensating) the grating frequency 303). By scanning a limited number of IFOs (up to the limit of RF crystal mismatch), the maximum PSS peak can be correlated to the PSS reference and correspondingly rotated IFO rotated samples, which gives the estimated IFO for that SCS step size. Since each FO hypothesis is tested with a given SCS step size, the resulting error of FO should not exceed half the step size.

Still referring to fig. 3F, if FO is further narrowed at fine resolution (also referred to herein as "fine FO") and the FO is estimated using an SCS step size of 0.5 instead of 1.0, the residual FO may not exceed 0.25SCS. FIG. 3F illustrates that the performance loss at 0.25SCS is about 0.4768dB. In other words, when the PSS processing circuit 304 estimates FO with an SCS step size of 0.5, the PSS-related performance degradation will be reduced from 2dB to 0.4768dB at worst, compared to using an SCS step size of 1.0. However, by selecting an SCS step size of 0.25, the performance loss is less than 0.5dB, as shown in fig. 3F. Furthermore, by performing additional FO estimation using a reduced SCS step size (e.g., 0.25), FO error may be reduced as compared to conventional techniques. Reducing FO errors enables more accurate PSS correlation.

Another way that the PSS processing circuit 304 may reduce the error associated with FO estimation is to perform correlation in the frequency domain at the resolution of 1.0 SCS. After determining the IFO, the relevant PSS samples are first compensated with the estimated IFO, and then the compensated and oversampled PSS samples can be used to estimate the residual FO. Simulations show that the estimation accuracy in statistical sense can also reach 0.25SCS in the case of multiple antennas. Using this solution, the number of IFFT iterations can be halved, since evaluating PSS correlations does not require a fine step size, thereby increasing processing speed and/or saving power, but may come at the expense of performance under weak signal and severe fading conditions.

Referring to fig. 3B and 3D, block-based processing may be used to perform convolution in the time domain before implementation in the frequency domain. For example, assuming convolution circuit 314 (also referred to herein as a "convolution filter") includes a time-domain filter of length L, then the convolution of any block of input samples of the filter for size M will generate M + L1 output samples (e.g., output 1 313) due to the filter tail effect. In principle, however, the M input samples may have M output samples by convolution with convolution circuit 314. Some of the output samples may then be discarded from output 1 313.

For example, assume that the convolution circuit 314 is defined as f = [ 11 ] and that g = [0.1,4.0,1.0, -2.0] is input. Here, the sequence g may pass through a filter f, output y (where y = g × h, where '×' denotes convolution), input g passing through a filter, and y may be y = [0.1,4.1,5.1,3.0, -1.0, -2.0]. In this illustrative example, when the 3-tap filter of convolution circuit 314 attempts to sum three adjacent samples up to the current sample timing index, the first (3-1) array of y (assuming g has two more 0 samples (assuming 0.1 before the first sample)) and the last (3-1) array of y may be found to be incorrect. This means that to perform block-based processing, some 0's need to be added to the first block before the actual data samples, while the last few output samples (all related to the size of the filter f) are incorrect and should be ignored, especially for this second order filter f with 3 coefficients, 2 ' 0's need to be added to the input g, and the last 2 output samples from y should be ignored.

To summarize the observation of the above example, considering a plurality of blocks processed sequentially, assuming that the convolution circuit 314 has L coefficients, the middle block for the input to the filter being processed is represented as a "new" block, with the first L samples from the last sample of the upper block (being the subsequent block). The last L samples in the middle block, shown as "overlapping", will be used by the lower block (the immediately next block). Since there is an "overlap" of L samples between two consecutive blocks, each block actually processes only the first M samples, whose output will be the last M samples of the output samples from the filter.

Note that as observed in the above example, 0 is added to the first block before the actual samples, and the first block will have L (the length of the PSS sequence) inserted "0" before the actual samples are sequentially padded into the block, which is the initial condition of the first block. Assuming that the sizes of L and FFT 316 are both known, then M is also known. Thus, M samples are appended to L samples to generate a new FFT block, where the L samples are obtained from the previous FFT block, and it generates an intermediate FFT block to run FFT 316. As described above, the convolution in the time domain and the correlation in the frequency domain are equivalent for the same input data, although the processing is not exactly the same. Thus, for either approach, the first block requires L "0" s, so that the first output will be a valid result.

As mentioned earlier, to operate in the frequency domain, the raster frequency processing in the time domain needs to be reconstructed as block-based processing in the frequency domain. To apply block-based processing in the frequency domain, for a filter length L (given by the system design), M is found such that (L + M) is the FFT size.

Referring to fig. 3B, which illustrates the equivalence between time-domain convolution and frequency-domain correlation, each sample block is transformed into the frequency domain, using a corresponding correlation circuit 318 (associated with convolution circuit 314 in the time domain) of size (L + M). Using the IFFT320, only the last M output samples from the IFFT320 will be reserved for each block in the time domain. More specifically, assume that convolution circuit 314 has 256 coefficients in the time domain, e.g., L =256. Thus, if the size of the FFT (hereinafter "NFFT") is selected to be 1024, then M = NFFT-256=768, which means that the current 768 samples and the last 256 samples will construct a new block, where L =256 samples are used twice in two consecutive blocks. Using FFT 316, the NFFT complex output is calculated; since the time-domain PSS filter has L =256 coefficients, its counterpart in the frequency domain can be defined as the PSS reference sequence plus an FFT of M zeros in the time domain. Next, correlation between NFFT pairs is done, where the correlation output will be mapped back to the time domain by IFFT. Since the IFFT size is 1024, and the last M output samples are the convolution result of the first M input samples with the filter.

For each block, the PSS processing circuitry 304 may perform PSS score processing and may save samples of the relevant PSS/SSS (SSS samples may be in the next block, in which case a "flag" will be used to imply that when the samples for the next block arrive, the SSS samples in that block relating to the PSS peak will be recorded first). These PSS/SSS samples may be used for subsequent frequency offset estimation/compensation and SSS cell detection and measurement.

The PSS processing circuit 304 may end the detection by selecting the final PSS candidate for detection based on the result of PSS correlation. The correlation performance loss can be significantly reduced by oversampling by a factor of 2 nyquist sampling rate (as described above) and searching for cells in the raster frequency with a step size of 0.25SCS (for low SNR and/or larger uncertain FO scenarios), and therefore the probability of finding the correct raster frequency and cell ID can be increased. Note that the PSS processing circuit 304 may keep a limited number of correlation peaks and associated SSB samples for additional measurements, which may increase the chances of correct cell selection and grating frequency. This limited number of winners will be updated by an efficient ranking scheme when new PSS peaks are found. The threshold may be adaptively defined, and many detected PSS scores may be filtered out, making the search more meaningful and power efficient. The PSS processing circuit 304 may be configured to determine information 305, the information 305 including a coarse FO estimate, symbol timing and sector ID for each PSS candidate. Additional details associated with the operations performed by the PSS processing circuit 304 are set forth below in connection with fig. 4B.

The PSS processing circuitry 304 may be configured to input information 305 including the coarse FO estimate, symbol timing, and sector ID into SSS processing circuitry 306. With the estimated FO and PSS symbol timing determined by the maximum correlation peak fraction and using the information 305, the SSS processing circuitry 306 can correspondingly determine the SSS symbol timing and can extract the SSS samples and, with appropriate FO compensation, can more accurately perform the SSS detection using the same correlation method as discussed above in connection with the PSS processing circuitry 304 of fig. 3B. SSS detection can be done using up to 336 SSS references, far exceeding 3 PSS references. There are many SSS sequences because SSS sequences are cell dependent. For capacity reasons, many users may be provided with hundreds of cells. However, a single PSS sequence may be shared by multiple users, and the PSS sequence is used for coarse estimation of FO and TO, as well as sector ID detection by SSS detection for cell detection.

The large number of SSS references not only provides more service capability but also reduces the chance of interference between cells or neighboring cells. Thus, in addition to carrying information associated with a cell ID, the SSS symbol 332 may be used for reliable measurement of signal quality and strength. Using the extracted SSS symbols 334 in the time domain, the SSS processing circuitry 306 may compensate the SSS samples using FO estimated in the time domain before demodulation in the frequency domain. SSS processing circuitry 306 may input information 307 associated with the cell ID and estimated FO into PBCH processing circuitry 308. Additional details of the operations performed by the SSS processing circuitry 306 are set forth below in connection with fig. 4C.

PBCH processing circuitry 308 may be configured to perform PBCH processing to assign a value to each raster frequency, where the value indicates a probability of correctness with respect to the estimated frequency offset, the sector ID, and the estimated symbol timing for each of the plurality of raster frequencies. Information 309 associated with the value for each of the plurality of grating frequencies may be input into the measurement circuit 310. Additional details associated with the operations performed by PBCH processing circuitry 308 are set forth below in conjunction with figure 4D.

Using the demodulated SSS reference, the measurement circuitry 310 may be configured TO measure one or more of the SSS or the PBCH for each of the plurality of raster frequencies TO estimate one or more of a Received Signal Strength Indicator (RSSI), a Reference Signal Received Power (RSRP), a Reference Signal Received Quality (RSRQ) signal TO interference and noise ratio (SINR), a fine Timing Offset (TO), or a fine FO. The measurement circuitry 310 may also be configured TO send information 311 associated with one or more of sector ID, symbol timing, cell ID, symbol index, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO TO the PHY layer controller 312 for cell selection. Using information 311, phy layer controller 312 may select a cell and associated raster frequency for acquisition. By increasing the number of signal indicators and including the raster frequency fraction, the PHY layer controller 312 may increase the probability of selecting a suitable cell for 5G NR communication.

Fig. 4A illustrates a flow chart of an example method 400 for wireless communication, in accordance with some embodiments of the present disclosure. Examples of an apparatus that may perform the operations of method 400 include, for example, apparatus 200, baseband chip 202 (see circuitry in fig. 3A), or node 500. It will be understood that the operations shown in method 400 are not exhaustive, and that other operations may be performed before, after, or in between any of the operations shown. Further, some operations may be performed concurrently, or in a different order than shown in FIG. 4A.

Referring to fig. 4, at 402, baseband chip 202 (e.g., FSD circuit 302) may be configured to receive RF samples. For example, referring to fig. 3A, a receiver of baseband chip 202 in fig. 2 may obtain wideband RF samples 301 (hereinafter "RF samples 301") that include a plurality of RF signals, each RF signal associated with a different narrowband frequency (also referred to as a "raster frequency"). The FSD circuit 302 may be configured to receive the RF samples 301 as input from the receiver (Rx) shown in fig. 2.

At 404, the baseband chip 202 (e.g., FSD circuit 302) may be configured to rotate the RF samples by a fixed amount relative to the SSB center frequency to obtain a plurality of grating frequencies, each of the plurality of grating frequencies associated with a rotation of one of the fixed amounts. For example, referring to fig. 3a, fsd circuit 302 may be configured to rotate an RF sample by a fixed amount relative to an SSB center frequency to obtain a plurality of raster frequencies, each raster frequency of the plurality of raster frequencies associated with a rotation of one of the fixed amounts. For example, the FSD circuit 302 may rotate the RF sample 301 to a desired grating frequency because the RF center frequency may be different from the SSB center frequency. By rotating the RF sample 301 by a fixed amount relative to the SSB center frequency, multiple grating frequencies can be obtained for processing by other circuitry of the baseband chip 202.

At 406, the baseband chip 202 (e.g., the PSS processing circuit 304) may be configured to estimate a set of IFOs for each of the plurality of grating frequencies, where each IFO in the set of IFOs may be estimated for a different SCS step size across an SCS range. For example, referring to fig. 3F, each IFO in the set of IFOs may be estimated for a different SCS step size (e.g., 0.25SCS, 0.5SCS, etc.) across an SCS range (e.g., -3 to +3SCS, -4 to +4SCS, etc.).

At 408, the baseband chip 202 (e.g., the PSS processing circuit 304) may be configured to perform PSS correlation for each IFO in a set of IFOs associated with each of the plurality of raster frequencies. For example, fig. 3B illustrates two equivalent implementations of PSS correlation. The upper branch, which includes convolution circuit 314 (e.g., a filter), illustrates a time domain implementation, and the lower branch, which includes FFT 316, correlation circuit 318, and IFFT320, illustrates a frequency domain implementation, where output 1 313 and output 2315 produce the same result. Convolution circuit 314 in the time domain and correlation circuit 318 in the frequency domain may not have the same format, but the two circuits may be associated. For example, given the size of FFT 316, convolution circuit 314 (e.g., a filter) and correlation circuit 318 have a 1-to-1 mapping. Thus, since frequency domain multiplication is equivalent to time domain convolution, the convolution circuit 314 may be a PSS reference filter defined in the time domain and convolved with the stream samples of the grating frequency 303. In this way, the convolution circuit 314 can obtain equivalent PSS correlation results and corresponding sample indices of PSS positions in the time domain. However, estimating IFO at different SCS steps across the SCS range may require multiplying each sample before performing the convolution in the time domain. On the other hand, if the correlation is considered in the frequency domain by means of subcarrier shifting, no multiplication may be needed. The use of FFT 316 and IFFT320 further enhances the benefits of estimating multiple IFOs across SCS ranges in the frequency domain, since these two transforms reduce or eliminate multiplication, thereby reducing computational complexity and power consumption when estimating FO hypotheses as compared to performing computations in the time domain. Still referring to fig. 3B, by converting the raster frequency 303 from the time domain to samples in the frequency domain, the PSS processing circuit 304 may exploit correlation because their normalized linear correlation coefficient may be relatively high if the PSS sequence in the time domain is similar to the PSS sequence in the frequency domain. Thus, the correlation result (obtained by correlation circuit 318) is mapped back to the time domain using IFFT320, and the correlation result in the frequency domain (e.g., output 2 315) may be defined by each of the three PSS references used to obtain the correlation peak in the time domain, which may correspond to the start timing of the PSS symbol.

At 410, the baseband chip 202 (e.g., PSS processing circuitry 304) may be configured to select a PSS candidate for each raster frequency based at least in part on the PSS correlation performed for each of the plurality of raster frequencies. For example, referring to fig. 3A, the baseband chip 202 may perform PSS correlation (for each narrowband raster frequency obtained from the wideband RF samples) using a set of IFOs estimated for each raster frequency. More specifically, each IFO in a set of IFOs may be estimated for a different SCS step size (e.g., 0.25SCS, 0.5SCS, etc.) across an SCS range (e.g., -3 to +3SCS, -4 to +4 SCS). Each IFO may be used for PSS correlation and/or convolution for its associated grating frequency. Then, for each raster frequency, the PSS candidate with the largest correlation peak score may be selected for further processing.

At 412, the baseband chip 202 (e.g., PSS processing circuit 304) may be configured to process each PSS candidate with the estimated coarse FO, sector Identification (ID) and symbol timing for each of the plurality of raster frequencies. For example, referring to fig. 4a, PSS processing circuitry 304 may be configured to determine information 305, which information 305 includes a coarse FO estimate, symbol timing and sector ID for each PSS candidate. Additional details regarding the PSS processing by the PSS processing circuit 304 are set forth below in conjunction with fig. 4C.

At 414, the baseband chip 202 (e.g., SSS processing circuitry 306) may be configured to perform SSS processing to estimate a cell ID and a frequency offset for each of the plurality of raster frequencies. SSS processing may be performed based at least in part on the estimated coarse frequency offset, sector ID, and symbol timing for each of the plurality of raster frequencies. For example, referring to fig. 3a, pss processing circuitry 304 may be configured to input information 305 including a coarse FO estimate, symbol timing, and sector ID into SSS processing circuitry 306. Using the FO and PSS symbol timings determined by the maximum correlation peak fraction that have been estimated, and using the information 305, the SSS processing circuitry 306 can determine the SSS symbol timing accordingly, and the SSS samples can be extracted and, with appropriate FO compensation, the SSS detection can be made more accurately using the same correlation method as discussed above in connection with the PSS processing circuitry 304 of fig. 3B. SSS detection can be done with up to 336 SSS references, well over 3 PSS references. The large number of SSS references not only provides more capacity for service but also reduces the interference opportunities between cells or neighboring cells. Thus, in addition to carrying information associated with the cell ID, the SSS symbols 332 may also be used for reliable measurements of signal quality and strength. Using the extracted SSS symbols 332 in the time domain, the SSS processing circuitry 306 may compensate the SSS samples using FO estimated in the time domain before demodulation in the frequency domain. Additional details regarding the SSS processing by the SSS processing circuitry 306 are set forth below in conjunction with fig. 4C.

At 416, the baseband chip 202 (e.g., PBCH processing circuitry 308) may be configured to perform PBCH processing to assign a value to each raster frequency that indicates a probability of being correct with respect to the coarse frequency offset, sector ID, and symbol timing estimated for each of the plurality of raster frequencies. For example, referring to fig. 3a, PBCH processing circuitry 308 may be configured to perform PBCH processing to assign a value to each raster frequency, where the value indicates a correct probability with respect to coarse frequency offset, sector ID, and symbol timing estimated for each of a plurality of raster frequencies. Additional details associated with the operations performed by PBCH processing circuit 308 are set forth below in conjunction with figure 4D. Information 309 associated with the value for each of the plurality of grating frequencies is provided to the measurement circuitry. Additional details associated with the operations performed by PBCH processing circuit 308 are described below in conjunction with figure 4D.

At 418, the baseband chip 202 (e.g., PBCH processing circuitry 308) may be configured to input information associated with the values for each of the plurality of grating frequencies to measurement circuitry. For example, referring to fig. 3A, information 309 associated with a value for each of a plurality of raster frequencies may be input into measurement circuitry 310.

At 420, the baseband chip 202 (e.g., measurement circuitry 310) may be configured TO measure one or more of SSS or PBCH symbols for each of the plurality of raster frequencies TO estimate one or more of RSSI, RSRP, reference Signal Received Quality (RSRQ), SINR, fine TO, or fine FO. For example, referring TO fig. 3A, with a demodulated SSS reference, the measurement circuitry 310 may be configured TO measure one or more of SSS or PBCH for each of a plurality of raster frequencies TO estimate a Received Signal Strength Indicator (RSSI), a Reference Signal Received Power (RSRP), a Reference Signal Received Quality (RSRQ), a signal TO interference and noise ratio (SINR), a fine Timing Offset (TO), or a fine FO.

At 422, the baseband chip 202 (e.g., measurement circuitry 310) may be configured TO send information associated with one or more of sector ID, symbol timing, cell ID, symbol index, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO TO the PHY layer controller for cell selection. For example, referring TO fig. 3A, the measurement circuitry 310 may be further configured TO send information 311 associated with one or more of sector ID, symbol timing, cell ID, symbol index RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO TO the PHY layer controller 312 for cell selection. Using information 311, phy layer controller 312 may select a cell and associated raster frequency for acquisition.

Fig. 4B illustrates a flow diagram of a second exemplary method 401 for wireless communication of a PSS processing circuit according to some embodiments of the disclosure. Examples of devices that may perform the operations of method 401 include, for example, device 200, PSS processing circuit 304, or node 500. It should be understood that the operations shown in method 400 are not exhaustive, and that other operations may be performed before, after, or in between any of the illustrated operations. Further, some operations may be performed concurrently, or in a different order than shown in FIG. 4B. Fig. 4C illustrates a flow diagram of a third example method 403 for wireless communication by the SSS processing circuitry 306, in accordance with some embodiments of the present disclosure. Examples of an apparatus that may perform the operations of method 403 include, for example, apparatus 200, SSS processing circuitry 306, or node 500. It should be understood that the operations shown in method 400 are not exhaustive, and that other operations may be performed before, after, or in between any of the illustrated operations. Further, some operations may be performed concurrently, or in a different order than shown in FIG. 4C. Figure 4D illustrates a flow diagram of a fourth example method 403 for wireless communication of PBCH processing circuitry 308 in accordance with some embodiments of the present disclosure. Examples of an apparatus that may perform the operations of method 403 include, for example, apparatus 200, PBCH processing circuitry 308, or node 500. It should be understood that the operations shown in method 400 are not exhaustive, and that other operations may be performed before, after, or in between any of the illustrated operations. Further, some operations may be performed concurrently, or in a different order than shown in FIG. 4D. Fig. 4B to 4D will be described together.

Referring to fig. 4B, at 430, pss processing circuit 304 may be configured to buffer raster frequency 303, which has been frequency shifted and decimated by FSD circuit 302. At 432, the pss processing circuit 304 may be configured to obtain one or more SSB samples from the buffer for further processing.

At 434, the pss processing circuit 304 may be configured to input the SSB samples to the FFT. For example, referring to fig. 3B, using FFT 316 and IFFT320 further enhances the benefits of estimating multiple IFOs across SCS ranges in the frequency domain, since these two transforms reduce or eliminate multiplication, thereby reducing computational complexity and power consumption when estimating FO hypotheses as compared to performing computations in the time domain.

At 436, the PSS processing circuit 304 may be configured to perform PSS correlation of the samples output by the FFT. For example, referring to fig. 3B and 3F, estimating IFO at different SCS steps across the SCS range may require multiplying each sample before performing convolution in the time domain. On the other hand, if the correlation is taken into account in the frequency domain by means of subcarrier shifting, no multiplication may be required. The use of FFT 316 and IFFT320 further enhances the benefits of estimating multiple IFOs across the SCS range in the frequency domain, since these two transforms reduce or eliminate multiplication, thereby reducing computational complexity and power consumption by estimating the FO hypothesis in the frequency domain compared to performing the computation in the time domain. Thus, the correlation result (obtained by correlation circuit 318) is mapped back to the time domain using IFFT320, and the correlation result in the frequency domain (e.g., output 2 315) may be defined by each of the three PSS references used to obtain the correlation peak in the time domain, which may correspond to the start timing of the PSS symbol. In addition to timing accuracy, FO is estimated to reduce and/or eliminate signal interference caused by FO, since otherwise PSS correlation performance would be degraded, as shown in fig. 3F. Referring to FIG. 3F, in the presence of large FOs, the multiple SCS FOs can cause more than 20dB loss in PSS correlation performance. Therefore, it may be beneficial to estimate the IFO of different SCS's when estimating FO. The SCS range of the estimated IFO may be provided to the PSS processing circuit 304 by upper layer management, e.g., based on information from the most likely FO in SCS units. Taking 20ppm of 3GHz carrier frequency as an example, the maximum FO is 60kHz; if the current SCS =15kHz, 60kHz equals 4SCS, but if the current SCS =30kHz, 60kHz equals 2SCS. Then, using this example, for a smaller SCS =15kHz, the scan spans an SCS range of-4 to +4, the IFO is estimated for { -4, -3, -2, -1,0, +1, +2, +3, +4} with an SCS step size of 1. Conversely, for larger SCS =30khz, SCS range is-2 to +2, for { -2, -1,0, +1, +2} the IFO is estimated, with SCS step size of 1. As shown in fig. 3F, when IFO =0, ideal correlation performance can be obtained. By rotating the grating frequency 303 using various IFOs, the curve will shift the offset of the IFOs to the left or right accordingly, and the peak fraction of the correlation can be measured with the grating frequency 303 of the IFO rotation (or compensation) at FO =0. By scanning a limited number of IFOs (up to the limit of RF crystal mismatch), the maximum PSS peak can be correlated with the PSS reference and the corresponding rotated IFO rotated samples, which gives an estimated IFO for this SCS step size. Since each FO hypothesis is tested with a given SCS step size, the resulting error of FO should not exceed half the step size. Still referring to fig. 3F, if FO is further reduced to fine resolution (also referred to herein as "fine FO") and the FO is estimated using an SCS step size of 0.5 instead of 1.0, the residual FO may not exceed 0.25SCS. FIG. 3F shows that the performance loss of 0.25SCS is about 0.4768dB. In other words, when the PSS processing circuit 304 estimates FO with an SCS step size of 0.5, the performance degradation of the PSS correlation will be reduced from 2dB to 0.4768dB in the worst case compared to using an SCS step size of 1.0. Another way that the PSS processing circuit 304 may reduce the error associated with FO estimation is to perform the correlation in the frequency domain at the resolution of 1.0SCS or a fractional SCS, e.g., 0.5SCS or 0.25SCS. After determining the IFO, the related PSS samples are first compensated with the estimated IFO, and then the compensated and oversampled PSS samples can be used to estimate the residual FO. This solution using the FO hypothesis plus the residual FO estimate can halve the number of IFFT iterations, thereby increasing processing speed and/or saving power, but at the cost of sacrificing performance in the case of weak signals and severe fading.

At 438, the pss processing circuit 304 may be configured to determine whether the IFO has been estimated for all SCS steps (also referred to as "SCS bins") within SCS range. When it is determined (at 438) that the IFOs for all SCS steps have not been calculated, operation may return to 436 for subsequent IFO estimation for subsequent SCS steps. Otherwise, when it is determined (at 438) that the IFO has been estimated for each SCS step in the range, operation may move to 440.

At 440, the pss processing circuit 304 may be configured to input the IFO through an IFFT. For example, referring to fig. 3B, the correlation result (obtained by the correlation circuit 318) is mapped back to the time domain using an IFFT320, and the correlation result (e.g., output 2 315) in the frequency domain may be defined by each of the three PSS references used to obtain the correlation peak in the time domain, which may correspond to the start timing of the PSS symbol. In addition to timing accuracy, FO is estimated and compensated to reduce and/or eliminate signal interference caused by FO, which otherwise degrades PSS correlation performance, as shown in fig. 3F.

At 442, the pss processing circuit 304 may be configured to calculate a sample signal power associated with the grating frequency being tested. Then, at 444, the PSS processing circuit 304 may be configured to perform power normalization of the PSS correlation result (e.g., output 2315) based at least in part on the sample signal power.

At 446, the pss processing circuit 304 may be configured to determine whether all antennas have been tested for the received RF sample 301. When it is determined (at 446) that all antennas have not been tested, then operation may return to 434 where the raster frequency associated with another antenna may be tested. Otherwise, when it is determined (at 446) that all antennas have been tested, then operation may move to 448.

At 448, the PSS processing circuit 304 may be configured to perform antenna combining to combine information associated with the PSS from all antennas for that particular raster frequency. The PSS correlation results from the various antennas may be combined, i.e., the results (e.g., after power normalization) from the various antennas may be added together under the same conditions (e.g., raster frequency, offset from raster frequency, PSS ID, sampling time, etc.). Since this addition assigns the same weight to each antenna, it is sometimes called "equal gain combining". In turn, the final PSS correlation result may be achieved by equal gain combining.

At 450, the PSS processing circuit 304 may be configured to rank the PSS correlation results and obtain PSS candidates for further processing. For example, referring to fig. 3a, the PSS processing circuit 304 may end the detection by selecting a final PSS candidate for detection based on the result of PSS correlation. By oversampling by the 2-fold nyquist sampling rate (as described above) and searching for cells in the grating frequency with a step size of 0.5SCS, the correlation performance loss can be significantly reduced, and thus the probability of finding the correct grating frequency and cell ID can be increased. Furthermore, searching for cells in raster frequencies at 0.25SCS steps at low SNR may help to obtain detection results at higher cost, noting that the PSS processing circuit 304 may hold a limited number of correlation peaks and associated SSB samples for additional measurements, which may increase the chance of correct cell selection and raster frequency. This limited number of winners will be updated by an efficient ranking scheme when new PSS peaks are found by the optimization scheme. A threshold may be adaptively defined that may filter out many detected PSS scores, making the search more meaningful and power efficient. Merging and deletion schemes may also be applied.

At 452, the PSS processing circuit 304 may be configured to determine a coarse FO for each PSS candidate. The PSS processing circuit 304 may be configured to determine information 305, the information 305 including a coarse FO estimate, symbol timing and sector ID for each PSS candidate.

Referring to fig. 4C, at 460, the sss processing circuitry 308 may be configured to buffer the raster frequency samples after frequency shifting and decimation by the FSD circuitry 302. At 462, the SSS processing circuitry may be configured to obtain SSS samples from the buffer for further processing. The processing of the raster frequency may be directed to the PSS candidates determined by the PSS processing circuit 304. Information associated with the candidate symbol timing may be received from the PSS processing circuit 304.

At 464, the sss processing circuitry may be configured to perform coarse FO compensation based at least in part on the coarse FO and SCS steps determined by the PSS processing circuitry 304 for the grating frequency candidates. At 466, sss processing may input the selected candidate through FFT, as described above in connection with the PSS processing circuitry in fig. 4B.

At 468, the SSS processing circuitry 306 may be configured to perform descrambling for the SSS samples based at least in part on the sector ID of the PSS candidate. At 470, the SSS processing circuitry may be configured to calculate the SSS sample power.

At 472, the SSS processing circuitry 306 may be configured to perform SSS correlation and normalization. SSS correlation may be performed using the same or similar techniques as PSS correlation described above in connection with fig. 3B, 3F, and 4B. SSS normalization may be performed using sample power calculated for SSS samples.

At 474, the SSS processing circuitry 306 may be configured to determine whether all antennas have been tested for SSS samples. When it is determined (at 474) that all antennas have not been tested, operation may return to 460 where the raster frequency associated with another antenna may be tested. Otherwise, when it is determined (at 474) that all antennas have been tested, then operation may move to 476.

At 476, the sss processing circuitry 306 may be configured to perform antenna combining to combine information associated with PSS correlation from all antennas for the raster frequency.

At 478, the SSS processing circuitry 306 may be configured to perform SSS detection. At 480, the sss processing circuitry 306 may be configured to determine whether there are additional candidates to process from the PSS results in fig. 4B. When it is determined (at 480) that there are more additional candidates to be tested, operation may return to 460 to select a subsequent candidate. Otherwise, when it is determined (at 480) that all candidates have been tested, the operation may move to 482.

At 482, the sss processing circuitry 306 may be configured to rank each raster frequency candidate. For example, each SSS detection may provide its associated result score (e.g., a positive number) for the cell ID. Since the SSS detection is processed at a given frequency, measured by the raster frequency, the step size of the frequency offset (e.g., 0.25 SCS), and the coarse FO estimate, the SSS score may be associated with a particular frequency and at some sample timing. The SSS fraction may be measured by antenna combining. For example, the SSS scores may be sorted from large to small and relevant information recorded, such as raster frequency, FO provided by the PSS coarse FO estimate, sample index of sampling timing, measurements such as RSSI, etc. A larger score means that the SSS detection is more likely to be correct, so it can be assumed to be a correctly detected SSS ID. Since each PSS ID may correspond to multiple SSS IDs, it may be found that SSS detection (PSS ID has been applied in SSS detection) and associated SSS ID (and thus cell ID, consisting of PSS and SSS ID) may be more reliable. The final score for a cell may include SSS and PSS scores with different weights applied. If the PSS symbol has greater received power or is assumed to be relatively reliable, for example, if nearby interference is strong and SSS detection may be less reliable (but not limited to), applying a greater weight to the SSS score and a lesser weight to the PSS score may generate a corresponding cell score.

At 484, the sss processing circuitry 306 may be configured to perform fine FO estimation. For example, assuming that a coarse FO estimate based on PSS is successful, compensated by the coarse FO estimate in the time domain, the SSS detected input data samples may have less FO, since only the residual FO may remain in the SSS detected input. This FO reduction of input data samples may enhance SSS detection and improve its accuracy. After SSS detection, the SSS ID (also called "group ID") may be known, and using this SSS ID, an SSS sequence in the time domain may be generated, which may be selected as a reference signal (compared to the corresponding coarse FO compensated SSS input) to achieve FO estimation. Current SSS-based FO estimates can provide even smaller FO estimates, also referred to as "fine FO", because the FO error after PSS-based coarse FO estimates is relatively small. Finally, the sum of the coarse FO and the fine FO may be the amount of FO for that particular cell ID at that frequency and sample timing.

At 486, the sss processing circuitry 306 may be configured to perform signal quality measurements to estimate RSRP, RSRQ, RSSI, and so on. Information determined by SSS processing circuitry 306 may be input into PBCH processing circuitry 308 and/or measurement circuitry 310. An optimization scheme through nonlinear and adaptive filtering and estimated RSRP, RSSI, FO information may be used to reduce the false alarm rate of cell detection. By the optimization scheme, the cell detection rate can be improved, and the subsequent processing is more efficient.

Referring to fig. 4D, at 600, pbch processing circuit 308 may be configured to buffer the raster frequency that has been frequency shifted and decimated by FSD circuit 302. At 602, PBCH processing circuitry 308 may be configured to obtain PBCH samples from the buffer. The PBCH samples may be acquired based at least in part on the symbol timing determined by the PSS processing circuit 304.

At 604, the PBCH processing circuitry 308 may be configured to perform FO compensation of PBCH samples based at least in part on the coarse FO and the fine FO estimated by the PSS processing circuitry 304 and the SSS processing circuitry 306.

At 606, PBCH processing circuitry 308 may be configured to pass the FO compensated PBCH samples through an FFT, as described above in connection with fig. 3B and 4B. At 608, the PBCH processing circuitry 308 may be configured to perform channel estimation, noise estimation, equalization, and DMRS detection of PBCH samples based at least in part on the cell ID determined by the SSS processing circuitry 306 to estimate the SSB index and timing.

At 610, the PBCH processing circuitry 308 may be configured to perform PBCH decoding to decode a master information block including an SCS and a subframe number (SFN). At 612, PBCH processing circuitry 308 may be configured TO estimate and measure PBCH symbols TO obtain more accurate FO, TO, and RSRP. Information generated and/or obtained by PBCH processing circuitry 308 may be input into measurement circuitry 310 in fig. 3B.

In various aspects of the disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or encoded as instructions or code on a non-transitory computer-readable medium. Computer readable media includes computer storage media. A storage medium may be any available medium that can be accessed by a computing device, such as node 500 in fig. 5. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDDs, such as magnetic disk storage or other magnetic storage devices, flash drives, SSDs, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system (e.g., a mobile device or computer). Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk wherein disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

According to one aspect of the disclosure, a baseband chip is disclosed. The baseband chip may include: a frequency shifting/decimation circuit configured to receive the RF samples. The frequency offset/decimation circuit may be further configured to: the RF sample is rotated by a fixed amount relative to the SSB center frequency to obtain a plurality of grating frequencies, each of which is associated with a rotation of one of the fixed amounts. The baseband chip may further include: a PSS processing circuit configured to estimate a set of IFOs for each of a plurality of grating frequencies, wherein each IFO of the set of IFOs may be estimated for a different SCS step size across a SCS range. The PSS processing circuit may be further configured to perform PSS correlation for each IFO in a set of IFOs associated with each of the plurality of raster frequencies. The PSS processing circuit may be further configured to select a PSS candidate for each of the plurality of raster frequencies based at least in part on the PSS correlation performed for each of the raster frequencies, wherein the PSS candidate is selected for SSB detection.

The PSS processing circuit is further configured to: each PSS candidate is processed to estimate the coarse FO, sector ID, and symbol timing for each of the multiple raster frequencies.

The baseband chip may further include: SSS processing circuitry configured to perform SSS processing to estimate a cell ID and a fine FO for each of a plurality of raster frequencies, the SSS processing may be performed based at least in part on the coarse frequency offset, the sector ID, and the symbol timing estimated for each of the plurality of raster frequencies.

The baseband chip may further include: PBCH processing circuitry configured to perform PBCH processing to assign a value to each raster frequency that indicates a correct probability with respect to fine FO, sector ID, and symbol timing estimated for each raster frequency of a plurality of raster frequencies. The PBCH processing circuitry may be further configured to input information associated with the values for each of the plurality of grating frequencies to the measurement circuitry.

The baseband chip may further include: measurement circuitry configured to measure one or more of SSS or PBCH for each of a plurality of raster frequencies to estimate one or more of: RSSI, RSRP, RSRQ, SINR, TO, or fine FO.

The measurement circuit may be further configured to send information associated with one or more of the following to the PHY layer controller for cell selection: sector ID, symbol timing, cell ID, SSB index, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO.

The frequency shifting/decimation circuit may be further configured to decimate each of a plurality of raster frequencies obtained from the RF samples.

In accordance with another aspect of the present disclosure, an apparatus is disclosed. The apparatus may include: a receiver configured to receive the RF samples. The apparatus may also include a baseband chip. The baseband chip may include: a frequency shifting/decimation circuit configured to receive the RF samples. The frequency offset/decimation circuit may be further configured to: the RF sample is rotated by a fixed amount relative to the SSB center frequency to obtain a plurality of grating frequencies, each of which is associated with a rotation of one of the fixed amounts. The baseband chip may further include: a PSS processing circuit configured to estimate a set of IFOs for each of a plurality of grating frequencies, wherein each IFO of the set of IFOs may be estimated for a different SCS step size across a SCS range. The PSS processing circuit may be further configured to perform PSS correlation for each IFO of a set of IFOs associated with each of the plurality of grating frequencies. The PSS processing circuit may be further configured to select a PSS candidate for each of the plurality of grating frequencies based at least in part on the PSS correlation performed for each of the plurality of grating frequencies, wherein the PSS candidate is selected for SSB detection.

The PSS processing circuit is further configured to: each PSS candidate is processed to estimate coarse FO, sector ID, and symbol timing for each of the multiple raster frequencies.

The baseband chip may further include: SSS processing circuitry configured to perform SSS processing to estimate a cell ID and a fine FO for each of a plurality of raster frequencies, the SSS processing may be performed based at least in part on a coarse frequency offset, a sector ID, and a symbol timing estimated for each of the plurality of raster frequencies.

The baseband chip may further include: PBCH processing circuitry configured to perform PBCH processing to assign a value to each raster frequency that indicates a correct probability with respect to fine FO, sector ID, and symbol timing estimated for each raster frequency of a plurality of raster frequencies. The PBCH processing circuitry may be further configured to input information associated with the value of each of the plurality of grating frequencies to the measurement circuitry.

In accordance with another aspect of the present disclosure, a method is disclosed. The method can comprise the following steps: the receiver receives the RF samples. The method may further comprise: the frequency shifting/decimation circuit rotates the RF samples by a fixed amount relative to the SSB center frequency to obtain a plurality of raster frequencies, each of which is associated with a rotation of one of the fixed amounts. The method may further comprise: the PSS processing circuit estimates a set of IFOs for each of the plurality of grating frequencies, each IFO in the set of IFOs estimated for a different SCS step size across the SCS range. The method may further comprise: the PSS processing circuit performs PSS correlation for each IFO in a set of IFOs associated with each of a plurality of raster frequencies. The method may further comprise: the PSS processing circuit selects a PSS candidate for each raster frequency based at least in part on a PSS correlation performed for each of the plurality of raster frequencies, wherein the PSS candidate is selected for SSB detection.

The method may further comprise: the PSS processing circuit processes each PSS candidate to estimate the coarse FO, sector ID, and symbol timing for each of the multiple raster frequencies.

The method may further comprise: the SSS processing circuit performs SSS processing to estimate a cell identification, ID, and a fine FO for each of the plurality of raster frequencies, the SSS processing performed based at least in part on the coarse frequency offset, the sector ID, and the symbol timing estimated for each of the plurality of raster frequencies.

The method may further comprise: PBCH processing circuitry performs PBCH processing to assign a value to each raster frequency that indicates a correct probability with respect to the fine FO, sector ID, and symbol timing estimated for each raster frequency of the plurality of raster frequencies. The method may further comprise: the PBCH processing circuit inputs information associated with the value of each of the plurality of grating frequencies to the measurement circuit.

The method may further comprise: the measurement circuitry measures one or more of SSS or PBCH for each of a plurality of raster frequencies to estimate one or more of: RSSI, RSRP, RSRQ, SINR, fine TO, or fine FO. The method may further comprise: for each of the plurality of raster frequencies, sending information associated with one or more of: sector ID, symbol timing, cell ID, SSB index, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO.

The foregoing description of the specific embodiments will reveal the general nature of the disclosure so that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not all exemplary embodiments of the disclosure as contemplated by the inventors, and therefore, should not be construed to limit the disclosure and the appended claims in any way.

Various functional blocks, modules, and steps have been disclosed above. The particular arrangements provided are illustrative rather than limiting. Accordingly, the functional blocks, modules, and steps may be reordered or combined in a manner different from the examples provided above. Likewise, some embodiments include only a subset of the functional blocks, modules, and steps, and allow for any such subset.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A baseband chip, comprising:

a frequency shifting/decimation circuit configured to:

receiving Radio Frequency (RF) samples; and

rotating the RF samples by a fixed amount relative to a synchronization signal block SSB center frequency to obtain a plurality of raster frequencies, each of the plurality of raster frequencies associated with a rotation of one of the fixed amounts;

a primary synchronization signal PSS processing circuit configured to:

estimating a set of integer frequency offsets IFOs for each grating frequency of the plurality of grating frequencies, each integer frequency offset IFO of the set of IFOs estimated for a different SCS step size across a subcarrier spacing SCS range;

performing PSS correlation for each IFO in a set of IFOs associated with each of the plurality of raster frequencies; and

selecting a PSS candidate for each raster frequency based at least in part on a PSS correlation performed for each of the plurality of raster frequencies,

wherein the PSS candidate is selected for SSB detection.

2. The baseband chip of claim 1, wherein the PSS processing circuit is further configured to:

each PSS candidate is processed to estimate a coarse frequency offset FO, a sector identification ID, and symbol timing for each of the plurality of raster frequencies.

3. The baseband chip of claim 2, further comprising:

secondary synchronization signal SSS processing circuitry configured to: performing SSS processing to estimate a cell Identification (ID) and a fine FO for each of the plurality of raster frequencies, the SSS processing performed based at least in part on the estimated coarse frequency offset, sector ID, and symbol timing for each of the plurality of raster frequencies.

4. The baseband chip according to claim 3, further comprising:

physical broadcast channel PBCH processing circuitry configured to:

performing PBCH processing to assign a value to each raster frequency, the value indicating a correct probability with respect to fine FO, sector ID, and symbol timing estimated for each raster frequency of the plurality of raster frequencies; and

inputting information associated with the value for each of the plurality of grating frequencies to a measurement circuit.

5. The baseband chip of claim 4, wherein the measurement circuit is configured to:

measuring, for each of the plurality of grating frequencies, one or more of SSS or PBCH to estimate one or more of: a received signal strength indicator RSSI, a reference signal received power RSRP, a reference signal received quality RSRQ, a signal TO interference and noise ratio SINR, a fine timing offset TO, or a fine FO.

6. The baseband chip of claim 5, wherein the measurement circuit is further configured to:

sending information associated with one or more of the following to a physical PHY layer controller for cell selection: sector ID, symbol timing, cell ID, synchronization signal block SSB index, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO.

7. The baseband chip of claim 1, wherein the frequency offset/decimation circuit is further configured to:

each of the plurality of grating frequencies obtained from the RF sample is decimated.

8. An apparatus for wireless communication, comprising:

a receiver configured to receive radio frequency, RF, samples; and

a baseband chip comprising:

a frequency shifting/decimation circuit configured to:

a primary synchronization signal PSS processing circuit configured to:

estimating a set of integer frequency offsets IFOs for each of the plurality of grating frequencies, each integer frequency offset IFO of the set of IFOs estimated for a different SCS step size across a subcarrier spacing SCS range;

wherein the PSS candidate is selected for SSB detection.

9. The apparatus of claim 8, wherein the PSS processing circuit is further configured to:

each PSS candidate is processed to estimate a coarse frequency offset FO, a sector identification ID and a symbol timing for each of the plurality of raster frequencies.

10. The apparatus of claim 9, wherein the baseband chip further comprises:

11. The apparatus of claim 10, wherein the baseband chip further comprises:

physical broadcast channel PBCH processing circuitry configured to:

performing PBCH processing to assign a value to each raster frequency, the value indicating a correct probability for fine FO, sector ID, and symbol timing estimated for each raster frequency of the plurality of raster frequencies; and

12. The apparatus of claim 11, wherein the measurement circuitry is configured to:

13. The apparatus of claim 12, wherein the measurement circuit is further configured to:

14. The apparatus of claim 13, wherein the PHY layer controller is configured to select:

a cell for acquisition, the selection based at least in part on information associated with one or more of a sector ID, symbol timing, cell ID, SSB index, RSSI, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO sent by a measurement circuit.

15. The apparatus of claim 8, wherein the frequency offset/decimation circuit is configured to:

decimating each of the plurality of grating frequencies obtained from the RF sample.

16. A method of wireless communication of a User Equipment (UE), comprising:

a receiver receives Radio Frequency (RF) samples;

a frequency shifting/decimation circuit rotating the RF samples by a fixed amount relative to a synchronization signal block SSB center frequency to obtain a plurality of raster frequencies, each of the plurality of raster frequencies being associated with a rotation of one of the fixed amounts;

a primary synchronization signal PSS processing circuit estimating a set of integer frequency offsets IFO for each of the plurality of grating frequencies, each integer frequency offset IFO of the set of IFOs estimated for a different SCS step across a subcarrier spacing SCS range;

a PSS processing circuit performing PSS correlation for each IFO in a set of IFOs associated with each of the plurality of raster frequencies; and

the PSS processing circuit selects a PSS candidate for each of the plurality of raster frequencies based at least in part on a PSS correlation performed for each of the plurality of raster frequencies,

wherein the PSS candidate is selected for SSB detection.

17. The method of claim 16, further comprising:

the PSS processing circuit processes each PSS candidate to estimate a coarse frequency offset FO, a sector identification ID, and a symbol timing for each of the plurality of raster frequencies.

18. The method of claim 17, further comprising:

secondary Synchronization Signal (SSS) processing circuitry performs SSS processing to estimate a cell Identification (ID) and a fine FO for each of the plurality of raster frequencies, the SSS processing performed based at least in part on a coarse frequency offset, a sector ID, and a symbol timing estimated for each of the plurality of raster frequencies.

19. The method of claim 18, further comprising:

physical broadcast channel PBCH processing circuitry performs PBCH processing to assign a value to each raster frequency, the value indicating a correct probability for fine FO, sector ID, and symbol timing estimated for each raster frequency of the plurality of raster frequencies; and

PBCH processing circuitry inputs information associated with the value for each of the plurality of grating frequencies to measurement circuitry.

20. The method of claim 19, further comprising:

measurement circuitry measures, for each of the plurality of raster frequencies, one or more of SSS or PBCH to estimate one or more of: a received signal strength indicator RSSI, a reference signal received power RSRP, a reference signal received quality RSRQ, a signal TO interference and noise ratio SINR, a fine timing offset TO, or a fine FO; and

for each of the plurality of raster frequencies, sending information associated with one or more of: sector ID, symbol timing, cell ID, synchronization signal block SSB index, RSRP, RSRQ, SINR, fine TO, fine FO, or coarse FO.