CN115360980A

CN115360980A - Oscillator circuit and electronic device

Info

Publication number: CN115360980A
Application number: CN202211060887.4A
Authority: CN
Inventors: 陈雨田; 易律凡
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2022-09-01
Filing date: 2022-09-01
Publication date: 2022-11-18

Abstract

The application provides an oscillator circuit and an electronic device. The oscillation starting stage of the oscillator circuit comprises a first oscillation starting stage and a second oscillation starting stage, and in the first oscillation starting stage, the control circuit controls the on-chip oscillator to provide oscillation signals for the crystal; in the second oscillation starting stage, the control circuit controls the on-chip oscillator to stop providing oscillation signals for the crystal, and controls the negative resistance generation circuit to provide a counteracting resistance for the crystal, wherein the resistance value of the counteracting resistance is smaller than zero; wherein, in the first oscillation stage, the frequency of the oscillation signal provided by the on-chip oscillator is reduced from a first frequency to a second frequency, or is increased from the second frequency to the first frequency, the first frequency is greater than the resonance frequency of the crystal, and the second frequency is less than the resonance frequency of the crystal. The oscillator circuit of this application has faster oscillation starting speed.

Description

Oscillator circuit and electronic device

Technical Field

The present invention relates to the field of oscillator technologies, and in particular, to an oscillator circuit and an electronic device.

Background

The crystal is usually used as a clock source for frequency multiplication clock or frequency synthesis due to its excellent clock stability and low clock jitter. However, the oscillation start time of the crystal is relatively long, for example, the oscillation start time of the crystal in the MHz class is usually in the order of milliseconds, and the oscillation start time of the crystal in the KHz class is usually in the order of seconds. This makes the crystal unusable in application scenarios with high requirements on the attack time.

Therefore, how to reduce the oscillation starting time of the crystal becomes a technical problem to be solved urgently.

Disclosure of Invention

Embodiments of the present application relate to an oscillator circuit and an electronic device, so as to solve some or all of the above technical problems.

According to an aspect of the present application, there is provided an oscillator circuit including: the on-chip oscillator circuit is coupled with the crystal; the oscillation starting phase of the oscillator circuit comprises a first oscillation starting phase and a second oscillation starting phase, and in the first oscillation starting phase, the control circuit controls the on-chip oscillator to provide an oscillation signal to the crystal; in the second oscillation starting stage, the control circuit controls the on-chip oscillator to stop providing oscillation signals for the crystal, the control circuit controls the negative resistance generation circuit to provide a cancellation resistance for the crystal, the cancellation resistance is used for canceling an equivalent resistance generated by the crystal, and the resistance value of the cancellation resistance is smaller than zero; wherein, in the first oscillation phase, the frequency of the oscillation signal provided by the on-chip oscillator is reduced from a first frequency to a second frequency, or is increased from the second frequency to the first frequency, the first frequency is greater than the resonance frequency of the crystal, and the second frequency is less than the resonance frequency of the crystal.

According to yet another aspect of the present application, an electronic device is provided that includes an oscillator circuit and a crystal, the oscillator circuit being coupled to the crystal.

In the oscillator circuit, in a first oscillation stage, the control circuit controls the on-chip oscillator to provide oscillation signals for the crystal; in the second oscillation starting stage, the control circuit controls the on-chip oscillator to stop providing the oscillation signal to the crystal and controls the negative resistance generation circuit to provide the cancellation resistance to the crystal. The embodiment of the application improves the oscillation starting speed of the crystal through the cooperation of the on-chip oscillator and the negative resistance generating circuit, and reduces the oscillation starting time of the crystal.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a related art crystal oscillator circuit;

FIG. 2 is a schematic diagram of a chip including an oscillator circuit according to an embodiment of the present disclosure;

FIG. 3 is an equivalent circuit diagram of a crystal;

FIG. 4 is a schematic diagram of an oscillator circuit provided by an embodiment of the present application;

FIG. 5 illustrates another implementation of an amplifier in an oscillator circuit;

FIG. 6 illustrates one implementation of an on-chip oscillator in an oscillator circuit;

FIG. 7 illustrates another implementation of an on-chip oscillator in an oscillator circuit;

FIG. 8 is a schematic diagram of a counter provided by an embodiment of the present application;

fig. 9 is an equivalent circuit diagram of a negative resistance generation circuit in the oscillator circuit;

FIG. 10 illustrates one implementation of a negative resistance generation circuit in an oscillator circuit;

fig. 11 is a schematic view of an electronic device provided in an embodiment of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The crystal and oscillator circuit may cooperate to generate a standard pulse signal at a particular frequency as a clock signal or reference signal. Fig. 1 shows a connection relationship of a crystal and an oscillator circuit. The oscillator circuit includes an inverting amplifier INV, a capacitor CL1 and a capacitor CL2, and a resistor r1 and a resistor r2. The crystal includes a first electrode, a second electrode, and a crystal sheet between the first electrode and the second electrode. The output end of the inverting amplifier INV is connected with the first electrode of the crystal, and the input end of the inverting amplifier INV is connected with the second electrode of the crystal. In the oscillation starting stage of the crystal, the excitation signal is applied to an inverter amplifier INV, the crystal serves as a feedback path of the inverter amplifier INV, and the oscillation signal output by the inverter amplifier INV reaches a target frequency and amplitude. The problem to be solved is to increase the starting oscillation speed of the crystal, and the starting oscillation speed of the crystal is unacceptably low for low-power-consumption application scenes.

An oscillator circuit, a chip including the oscillator circuit, and an electronic device including the chip are described.

Fig. 2 is a schematic diagram of a chip including an oscillator circuit according to an embodiment of the present disclosure. The chip comprises an oscillator circuit 10. Examples of the chip include a CPU (central processing unit), an MCU (micro controller unit), an SOC (system on chip), and an internet of things (internet of things) chip. The chip is for example an already packaged chip. Oscillator circuit 10 and crystal 600 are used to provide a stable clock signal for the chip.

The oscillator circuit 10 includes: an on-chip oscillator 200, a negative resistance generation circuit 300, and a control circuit 400. Oscillator circuit 10 is coupled to crystal 600.

In a specific implementation of the present application, the first terminal and the second terminal of the on-chip oscillator 200 are coupled to the first terminal XI and the second terminal XO of the crystal 600 through the first switch S1 and the second switch S2, respectively. The first terminal and the second terminal of the negative resistance generating circuit 300 are coupled to the first terminal XI and the second terminal XO of the crystal 600 through the third switch S3 and the fourth switch S4, respectively. The first terminal XI of the crystal 600 is further connected to an input of an amplifier 100, and the second terminal XO of the crystal 600 is further connected to an output of the amplifier 100. The control circuit 400 is coupled to the first terminal and the second terminal of the on-chip oscillator 200, and controls the on-chip oscillator 200 to be connected to or disconnected from the first terminal XI and the second terminal XO of the crystal 600 by closing or opening the first switch S1 and the second switch S2, respectively. The control circuit 400 is coupled to the first terminal and the second terminal of the negative resistance generating circuit 300, and controls the negative resistance generating circuit 300 to be connected to or disconnected from the first terminal XI and the second terminal XO of the crystal 600 by closing or opening the third switch S3 and the fourth switch S4.

Illustratively, the on-chip oscillator 200 and the amplifier 100 and negative resistance generating circuit 300 are fabricated on the same die (die). The on-chip oscillator 200 may provide an oscillation signal (hereinafter may be referred to as a first oscillation signal). The frequency of the oscillation signal provided by the on-chip oscillator 200 may vary in a frequency interval (f 2, f 1) defined by the first frequency f1 and the second frequency f2. The first frequency f1 is greater than the resonant frequency of crystal 600, and the second frequency f2 is less than the resonant frequency fx of crystal 600, which ensures that the oscillating signal provided by on-chip oscillator 200 provides an oscillating signal with a frequency equal to the resonant frequency fx of crystal 600 during the variation of the frequency interval (f 2, f 1). If the frequency of the oscillation signal provided by the on-chip oscillator 200 is equal to the resonance frequency fx of the crystal 600, the oscillation signal provided by the on-chip oscillator 200 can excite the crystal 600 to oscillate. Specifically, the frequency of the oscillation signal provided by the on-chip oscillator 200 may vary between the frequency intervals (f 2, f 1) defined by the first frequency f1 and the second frequency f2, including decreasing from the first frequency f1 to the second frequency f2, or increasing from the second frequency f2 to the first frequency f1.

The start-up phase of oscillator circuit 10 includes a first start-up phase and a second start-up phase. The start-up phase of oscillator circuit 10 refers to the time period required for crystal 600 to oscillate from the beginning to the last stable oscillation. The stable oscillation of the crystal 600 means that the oscillation signal generated by the crystal is stable at the resonant frequency fx (also referred to as the target frequency or the operating frequency) and the target amplitude (amplitude).

In the first oscillation stage, the control circuit 400 controls the on-chip oscillator 200 to provide the oscillation signal to the crystal 600, and the control circuit 400 controls the negative resistance generating circuit 300 to stop providing the cancellation resistance to the crystal 600. In the first start-up phase, the frequency of the oscillation signal provided by the on-chip oscillator 200 is decreased from the first frequency f1 to the second frequency f2, or increased from the second frequency f2 to the first frequency f1. In the first oscillation stage, the oscillation signal provided by the on-chip oscillator 200 provides an oscillation signal with a frequency equal to the resonant frequency fx of the crystal 600 during the variation of the frequency interval (f 2, f 1), so that the crystal 600 generates an oscillation signal (hereinafter, may be referred to as a second oscillation signal) at the resonant frequency fx.

In the second oscillation starting stage, the control circuit 400 controls the on-chip oscillator 200 to stop providing the oscillation signal to the crystal 600, and the control circuit 400 controls the negative resistance generating circuit 300 to provide the cancellation resistance to the crystal 600. Wherein the resistance value of the offset resistor is less than zero. In the second oscillation starting stage, the negative resistance generation circuit 300 cancels the resistance of the crystal 600 to cancel the generated equivalent resistance of the crystal 600, so that the second oscillation signal generated by the crystal 600 can effectively reach the target amplitude quickly, thereby shortening the oscillation starting time of the oscillator circuit 10 and the crystal 600. Since the on-chip oscillator 200 will also generate a resistance, which affects the operation of the negative resistance generating circuit, the negative resistance generating circuit 300 mainly cancels the resistance of the crystal 600. The resistance of the on-chip oscillator 200 fluctuates with external conditions, and the negative resistance generation circuit 300 may cause a large error in canceling the resistance of the on-chip oscillator 200 and the crystal 600. The on-chip oscillator 200 stops providing the oscillation signal to the crystal 600 according to the embodiment of the present application, and the error caused by the fluctuation of the resistance of the on-chip oscillator 200 along with the external condition is also avoided.

The oscillator circuit 10 of the present application improves the oscillation starting speed of the crystal 600 by the cooperation of the on-chip oscillator 200 and the negative resistance generating circuit 300.

Specifically, the control circuit 400 controls whether the on-chip oscillator 200 operates or not through the first switch and the second switch, when the first switch and the second switch are closed, the on-chip oscillator 200 is connected to the crystal 600, the on-chip oscillator 200 provides the oscillation signal to the crystal 600, and when the first switch and the second switch are disconnected, the connection between the on-chip oscillator 200 and the crystal 600 is disconnected, and the on-chip oscillator 200 stops providing the oscillation signal to the crystal 600. The control circuit 400 controls whether the negative resistance generating circuit 300 works or not through the third switch and the fourth switch, when the third switch and the fourth switch are closed, the negative resistance generating circuit 300 is connected with the crystal 600, the negative resistance generating circuit 300 provides offset resistance for the crystal 600, when the third switch and the fourth switch are opened, the connection between the negative resistance generating circuit 300 and the crystal 600 is disconnected, and the negative resistance generating circuit 300 stops providing the offset resistance for the crystal 600. The control circuit 400 generates control signals that control the turning-off and turning-on of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, thereby controlling the connection between the on-chip oscillator 200 and the amplifier 100 and the connection of the negative resistance generation circuit 300 and the crystal 600.

In the embodiment of the application, the control circuit 400 outputs the control signal to the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 to control the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 to be turned off and on.

Fig. 3 is an equivalent circuit diagram of crystal 600. Crystal 600 operates as a resonator, the equivalent circuit of which includes: inductance Lm, resistance Rm, capacitance Cm, and capacitance Cshunt. The inductor Lm, the resistor Rm and the capacitor Cm are connected in series between the first pin XO and the second pin XI. The capacitor Cshunt is connected in parallel with a branch where the inductor Lm, the resistor Rm and the capacitor Cm are located. For a crystal oscillator formed by amplifier 100 and crystal 600, crystal 600 allows an oscillating signal to pass through at a frequency equal to the resonant frequency of crystal 600. The target frequency fx of the crystal is equal to the resonant frequency of the crystal 600. The quality factor Q of the crystal 600 characterizes the energy loss.

The quality factor Q is calculated by equation 1:

equation 1

The quality factor Q is inversely proportional to the magnitude of the resistance Rm. The magnitude of the resistance Rm affects the starting speed of the crystal formed by the amplifier 100 and the crystal 600. The smaller the resistance Rm is, the faster the crystal starts to oscillate. Therefore, in the oscillation starting stage, by connecting the negative resistance generation circuit 300 to the crystal 600, the negative resistance can provide greater driving capability for oscillation starting, and the oscillation starting speed of the crystal can be increased.

In a specific implementation of the present application, the first oscillation stage of the oscillator circuit 10 of the present embodiment precedes the second oscillation stage. Firstly, the on-chip oscillator 200 excites the crystal 600 to generate a second oscillation signal with gradually increasing amplitude, and then the negative resistance generation circuit provides a cancellation resistance with a resistance value smaller than zero for the crystal 600, so that the amplitude of the second oscillation signal generated by the crystal 600 is rapidly increased, and the oscillation starting time of the oscillator circuit 10 and the crystal 600 is shortened.

In the first start-up phase, the control circuit 400 controls the first switch S1 and the second switch S2 to be closed, the third switch S3 and the fourth switch S4 to be opened, when the first switch S1 and the second switch S2 are closed, the on-chip oscillator 200 is connected to the amplifier 100, and when the third switch S3 and the fourth switch S4 are opened, the negative resistance generation circuit 300 is disconnected from the crystal 600. Specifically, when the frequency of the first oscillation signal provided by the on-chip oscillator 200 decreases from the first frequency f1 to the second frequency f2 or increases from the second frequency f2 to the first frequency f1, and in this process, the frequency of the first oscillation signal provided by the on-chip oscillator 200 is equal to the resonance frequency fx of the crystal 600, the crystal 600 is excited to generate the second oscillation signal, but the amplitude of the second oscillation signal generated by the crystal 600 is smaller. If the start-up speed is increased only by the first oscillation signal provided by the on-chip oscillator 200, it takes a long time for the amplifier connected to the crystal 600 to increase the amplitude of the second oscillation signal generated by the crystal 600 to the target amplitude. For example, the target frequency fx of the second oscillation signal of the crystal 600 is 32MHz, and after the frequency of the first oscillation signal provided by the on-chip oscillator 200 is decreased from the first frequency f1 to the second frequency f2 or increased from the second frequency f2 to the first frequency f1, the amplitude of the second oscillation signal generated by the crystal excited by the first oscillation signal provided by the on-chip oscillator 200 is 1mV, but the target amplitude of the oscillation signal of the crystal is 1V. Therefore, the on-chip oscillator 200 needs to decrease the frequency of the first oscillating signal from the first frequency f1 to the second frequency f2 or increase the second frequency f2 to the first frequency f1 many times, which makes the time for the crystal 600 to start oscillating extremely long, and therefore, the present solution provides the first and second oscillation starting stages to increase the resonant speed of the crystal 600.

In the second oscillation starting stage, the control circuit 400 controls the first switch S1 and the second switch S2 to be opened, the third switch S3 and the fourth switch S4 to be closed, when the first switch S1 and the second switch S2 are opened, the on-chip oscillator 200 is disconnected from the amplifier 100, and when the third switch S3 and the fourth switch S4 are closed, the negative resistance generating circuit 300 is connected to the crystal 600. The negative resistance generation circuit 300 provides the crystal 600 with a cancellation resistance, and the resistance value of the cancellation resistance is negative, so that the quality factor Q of the crystal 600 is reduced, and the amplitude of the second oscillation signal of the crystal 600 is increased to the target amplitude more quickly.

In a specific implementation of the present application, after the amplitude of the second oscillation signal of the crystal 600 reaches the target amplitude, the second oscillation starting phase is ended, and the control circuit 400 controls the negative resistance generation circuit 300 to stop providing the cancellation resistance to the crystal 600. Specifically, the control circuit 400 controls the third switch S3 and the fourth switch S4 to be turned off so that the negative resistance generation circuit 300 is disconnected from the crystal 600, and the second oscillation signal with the frequency fx is stably supplied to the chip by the amplifier 100 and the crystal 600. Therefore, the embodiment of the present application can avoid the extra loss caused by the negative resistance generating circuit 300 and avoid the oscillation frequency of the crystal 600 from shifting.

In some embodiments, during the first oscillation phase, the oscillation signal provided by the on-chip oscillator 200 performs a plurality of scanning processes of decreasing from the first frequency f1 to the second frequency f2, or increasing from the second frequency f2 to the first frequency f1.

In some embodiments, during the first oscillation phase, the oscillation signal provided by the on-chip oscillator 200 decreases from the first frequency f1 to the second frequency f2, and then increases from the second frequency f2 to the first frequency f1; or the oscillation signal provided by the on-chip oscillator 200 increases from the second frequency f2 to the first frequency f1 and then decreases from the first frequency f1 to the second frequency f2.

In some embodiments, at a start point of the first start phase, the frequency of the oscillating signal provided by the on-chip oscillator starts to decrease from the first frequency until the first start phase ends when the frequency of the oscillating signal provided by the on-chip oscillator decreases to the second frequency; or, at the starting point of the first oscillation stage, the frequency of the oscillation signal provided by the on-chip oscillator starts to increase from the second frequency until the frequency of the oscillation signal provided by the on-chip oscillator increases to the first frequency, and the first oscillation stage is ended; the length of the first oscillation starting stage is smaller than that of the second oscillation starting stage. That is, the on-chip oscillator 200 performs the sweep process of decreasing from the first frequency f1 to the second frequency f2 or the sweep process of increasing from the second frequency f2 to the first frequency f1 only once in the first start-up phase. When the number of scans of the on-chip oscillator 200 is small, the length of the first oscillation stage is smaller than the length of the second oscillation stage. For example, when the on-chip oscillator sweeps from a high frequency to a low frequency once, the first oscillation stage may be 33us, and then the negative resistance generating circuit operates 160us, i.e., the second oscillation stage may be 160us.

In one specific implementation of the present application, the first frequency f1 is, for example, 2 times the target frequency fx of the crystal, and the second frequency f2 is, for example, 1/2 of the target frequency fx of the crystal, so that the arrangement can ensure that the oscillating signal of the on-chip oscillator 200 sweeps across the target frequency fx of the crystal when the first oscillation stage changes, and the frequency sweep time of the oscillating signal of the on-chip oscillator 200 is not too long. Because only the oscillation signal with the frequency of fx among the oscillation signals of the on-chip oscillator 200 can excite the crystal, the frequency sweep interval of the oscillation signal of the on-chip oscillator 200 is too large, which increases the oscillation starting time of the crystal.

Specifically, the amplifier 100 may be a CMOS inverter-based amplifier, or may be a single-transistor amplifier.

Fig. 4 is a schematic diagram of an oscillator circuit provided in an embodiment of the present application. In the embodiment shown in fig. 4, amplifier 100 is a CMOS inverter. The oscillator circuit further includes: feedback resistance R1, resistance R2, electric capacity C1 and electric capacity C2. A feedback resistor R1 is connected between the input terminal 101 and the output terminal 102 of the amplifier 100. Resistor R2 is connected between the output 102 of the amplifier 100 and the first electrode 601 of the crystal 600. A capacitor C1 is arranged between the second electrode 602 of the crystal 600 and the terminal N, and a capacitor C2 is arranged between the first electrode 601 of the crystal 600 and the terminal N. Terminal N is, for example, grounded. The capacitor C1 and the capacitor C2 may be provided on-chip, i.e. fabricated on one die with the oscillator circuit 10. The capacitor C1 and the capacitor C2 may be disposed off-chip. The capacitor C1 and the capacitor C2 can be used to reduce the influence of the capacitor Cshunt and the trace capacitance on the resonant frequency of the crystal 600, and improve the accuracy of the oscillation frequency of the crystal.

Fig. 5 shows another implementation of an amplifier in an oscillator circuit. In the embodiment shown in fig. 5, amplifier 100 is a single transistor amplifier. The amplifier 100 is implemented, for example, as an NMOS transistor having a gate as an input of the amplifier and a drain as an output of the amplifier. The crystal oscillator further includes: a capacitor C1 and a capacitor C2. One end of the capacitor C1 is connected to the source of the NMOS transistor, and the other end is connected to the second electrode of the transistor 600 through the second pin XI. One end of the capacitor C2 is connected to the source of the NMOS transistor, and the other end is connected to the first electrode of the crystal 600 through the first pin XO.

The on-chip oscillator 200 is, for example, an RC oscillator. The RC oscillator provides the first oscillating signal as an excitation to the crystal only in the first oscillation stage, and thus the power consumption is low. Fig. 6 shows an exemplary circuit diagram of an RC oscillator. The on-chip oscillator 200 includes:

current sources

201 and 202, resistor 203, capacitor 204, comparator COMP, logic circuit 206 and switch 205. The current source 201 and the resistor 203 are connected in series between a power source terminal and ground, and an intermediate node Nr of the current source 201 and the resistor 203 has a fixed voltage Vr. The current source 202 and the capacitor 204 are connected in series between a power supply terminal and ground. A first terminal of the switch 205 is connected to a first terminal of the capacitor 204, and a second terminal of the switch 205 is connected to a second terminal of the capacitor 204. A first input terminal of the comparator COMP is connected to the intermediate node Nc of the current source 202 and the capacitor 204, and a second input terminal is connected to the node Nr. The comparator COMP compares the voltage Vr at the node Nr and the voltage Vc at the node Nc. An output terminal of the comparator COMP is connected to an input terminal of the logic circuit 206, and an output terminal of the logic circuit 206 is connected to a control terminal of the switch 205 through a feedback path. When the switch 205 is turned off, the current source 202 charges the capacitor 204, and the voltage Vc at the node Nc rises. Since the current source 202 supplies a constant current, the voltage Vc of the node Nc increases linearly, and the voltage Vc of the node Nc is a ramp voltage. When the voltage Vc is greater than the voltage Vr, the output signal of the comparator COMP is inverted to generate a square-wave clock signal Fout through the logic circuit 206. The clock signal Fout is provided to the control terminal of the switch 205 via a feedback path. When the clock signal Fout is at the first level, the switch 205 is turned on, and the capacitor 204 is discharged to ground, and when the clock signal Fout is at the second level, the capacitor 204 is charged. This repetition produces a stable square wave clock signal, i.e., the oscillating signal provided by the on-chip oscillator 200. The period of the square wave clock signal is equal to RC, and the frequency is 1/RC, where R is the resistance of the resistor 203 and C is the capacitance of the capacitor 204. By controlling the resistance R of the resistor 203 to be small to large or the capacitance C of the capacitor 204 to be small to large, the on-chip oscillator 200 can generate an oscillating signal with a frequency reduced from the first frequency f1 to the second frequency f2. The on-chip oscillator 200 further includes:

inverters

207 and 208. The input of inverter 207 is connected to the output of logic circuit 206 and the output of inverter 207 is connected to the input of inverter 208. The output of inverter 207 is connected to one of the input 101 and output 102 of amplifier 100 and the output of inverter 208 is connected to the other of the input 101 and output 102 of amplifier 100. For example, the output terminal of the inverter 207 serves as the first terminal of the on-chip oscillator 200 and is connected to the input terminal 101 of the amplifier 100 through the first switch S1, and the output terminal of the inverter 208 serves as the second terminal of the on-chip oscillator 200 and is connected to the output terminal 102 of the amplifier 100 through the second switch S2. The output of inverter 207 and the output of inverter 208 provide oscillating signals that are the same frequency and 180 degrees out of phase. The RC oscillator has the advantage of low power consumption. However, the error between the on-chip resistor and capacitor is large due to the chip manufacturing process, and even if the target resistance value is realized by using the resistor and capacitor array controlled by the switch, the capacitance value has a large error. Therefore, the control resistor 203 or the capacitor 204 may have a larger error when the resistance R or the capacitance C is increased. Therefore, on-chip oscillator 200 preferably uses an oscillator that does not include or has fewer resistors and capacitors to reduce errors.

In a specific implementation of the present application, the on-chip oscillator is a ring oscillator or an RC oscillator. However, for the RC oscillator, the reduction of the frequency of the output oscillation signal from the first frequency to the second frequency or the increase of the frequency of the output oscillation signal from the second frequency to the second frequency needs to be realized by adjusting the resistor R and the capacitor C, but the process of adjusting the resistor R and the capacitor C is easy to introduce errors. In the chip manufacturing process, the absolute values of the resistor and the capacitor are generally set to be 20% of errors by default, and although several groups of switches can be added to control the resistor/capacitor array, the switches are closed much, which means that the number of resistors/capacitors connected into the circuit is large, but the errors are still large. Therefore, the ring oscillator is adopted in the embodiment of the application, so that the frequency of the output oscillation signal is reduced from the first frequency to the second frequency or the frequency of the output oscillation signal is increased from the second frequency to the second frequency. When the input signal of the ring oscillator is a ramp signal which is reduced from a high voltage to a low voltage, the frequency of the oscillation signal output by the ring oscillator is reduced from a first frequency to a second frequency; when the input signal of the ring oscillator is a ramp signal rising from a low voltage to a high voltage, the frequency of the oscillation signal output by the ring oscillator is increased from the second frequency to the second frequency.

In particular, fig. 7 illustrates an exemplary circuit diagram of an on-chip oscillator 200 for a ring oscillator implementation. As shown in fig. 7, the on-chip oscillator 200 includes: the inverter comprises a first inverter, a second inverter, a third inverter, a current source 209, a fourth inverter 210 and a fifth inverter 211 which are cascaded, wherein the first inverter comprises: a first PMOS transistor P1 and a first NMOS transistor N1 connected in series, the second inverter comprising: a second PMOS transistor P2 and a second NMOS transistor N2 connected in series, the third inverter comprising: a third PMOS transistor P3 and a third NMOS transistor N3 connected in series, the current source comprising: the fourth NMOS transistor N4, the resistor 2091, and the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are sequentially connected in series between a power end and ground, the fourth NMOS transistor N4 receives the ramp signal from the high voltage to the low voltage or the ramp signal from the low voltage to the high voltage, a current on a path formed by the fifth PMOS transistor P5, the fourth NMOS transistor N4, and the resistor 2091 is a bias current, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 form a current mirror, the bias current is copied to the first inverter, the second inverter, and the third inverter of the cascade, outputs of the first inverter, the second inverter, and the third inverter of the cascade are connected to the first end XI of the crystal 600 through the fourth inverter 210, and outputs of the first inverter, the second inverter, and the third inverter of the cascade are connected to the second end of the crystal 600 through the fourth inverter 210 and the fifth inverter 211 in sequence. It will be appreciated that in the embodiment shown in fig. 7, the bias current provided to the first inverter, the second inverter, and the third inverter is one third of Ibias. The gate of the fourth NMOS transistor N4 receives the ramp voltage. The ramp voltage is decreased linearly from the high voltage VH to the low voltage VL, for example, so that the bias current Ibias changes from large to small and the frequency of the oscillation signal generated by the on-chip oscillator 200 changes from large to small. By setting the magnitudes of the high voltage VH and the low voltage VL, it is possible to achieve a reduction in the frequency of the oscillation signal generated by the on-chip oscillator 200 from the first frequency f1 to the second frequency f2. Similarly, the ramp voltage is linearly increased from the low voltage VL to the high voltage VH, and the frequency of the oscillation signal generated by the on-chip oscillator 200 can be increased from the second frequency f2 to the first frequency f1. The rate of increase or decrease of the frequency of the oscillation signal generated by the on-chip oscillator 200 can be controlled by controlling the slope of the ramp voltage. For example, it may take 15us to set the ramp voltage to linearly decrease from the high voltage VH =1V to the low voltage VL = 0V.

Specifically, the control circuit 400 is configured to determine an end time of the first oscillation starting phase and a start time and an end time of the second oscillation starting phase.

In some embodiments, when the frequency of the oscillation signal provided by the on-chip oscillator 200 reaches the predetermined frequency (f 1 or f 2), the control circuit 400 controls the on-chip oscillator 200 to be disconnected from the amplifier 100, and the first oscillation phase ends. For example, in the first oscillation phase, the frequency of the oscillation signal generated by the on-chip oscillator 200 completes one sweep of decreasing from the first frequency f1 to the second frequency f2, and when the oscillation signal generated by the on-chip oscillator 200 is the second frequency f2, the control circuit 400 controls the on-chip oscillator 200 to be disconnected from the amplifier 100, and the first oscillation phase ends. For another example, in the first oscillation phase, the frequency of the oscillation signal generated by the on-chip oscillator 200 is swept twice from the first frequency f1 to the second frequency f2, and when the oscillation signal generated by the on-chip oscillator 200 is swept for the second time to the second frequency f2, the control circuit 400 controls the on-chip oscillator 200 to be disconnected from the amplifier 100, and the first oscillation phase is ended. In some embodiments, the control circuit 400 comprises a frequency detection circuit arranged to detect the frequency of the oscillating signal provided by the on-chip oscillator 200 in the first stage of oscillation.

In some embodiments, the first oscillation phase ends when the number of cycles of the first oscillation signal generated by the on-chip oscillator 200 in the first oscillation phase reaches a first predetermined number of cycles. Referring to fig. 1, the control circuit 400 may connect the first terminal and the second terminal of the on-chip oscillator 200 to count the number of cycles of the first oscillation signal generated by the on-chip oscillator 200. Specifically, the control circuit 400 may count the number of cycles of the first oscillation signal generated by the on-chip oscillator 200 by a counter or a microprocessor.

Since the amplitude of the second oscillation signal generated by the crystal 600 is small in the first oscillation stage, for example, counting the number of cycles of the first oscillation signal generated by the crystal 600 in the first oscillation stage is prone to cause an error in the counted number of cycles. In the embodiment of the present application, the control circuit 400 (a counter or a microcontroller) is used to count the number of cycles of the first oscillation signal generated by the on-chip oscillator 200 in the first oscillation starting stage to determine the ending time of the first oscillation starting stage and the starting time of the second oscillation starting stage, so that the ending time of the first oscillation starting stage and the starting time of the second oscillation starting stage can be accurately obtained.

In some embodiments, referring to fig. 8, the control circuit 400 includes a counter 401. The counter 401 counts the number of cycles of the oscillation signal generated by the oscillator circuit 10. Specifically, a first predetermined number of cycles is written to the register of the counter 401 before the first start-up phase begins. In the first oscillation starting phase, the counter 401 counts each period of the first oscillation signal generated by the on-chip oscillator 200 in the oscillator circuit 10, and when the count value of the counter 401 reaches a first predetermined number of periods, the counter 401 generates the control signal such that the first switch S1 and the second switch S2 are turned off, the third switch S3 and the fourth switch S4 are turned off, the first oscillation starting phase ends, and the second oscillation starting phase begins. In the second oscillation starting period, the counter 401 counts each period of the second oscillation signal generated by the crystal 600, when the count value of the counter 401 reaches a second predetermined number of periods, the counter 401 generates the control signal to turn off the third switch S3 and the fourth switch S4, and the second oscillation starting period ends. The counter is typically a conventional existing circuit in the chip. Therefore, the counter detects the period number of the oscillation signal, the existing counter in the chip can be multiplexed, no additional circuit is needed, and the area of the oscillator circuit 10 is reduced. The control circuit 400 may also be a microprocessor, which has the same implementation principle as the counter, and therefore, the detailed description thereof is omitted.

In some embodiments, the second oscillation-starting phase ends when the number of cycles of the second oscillation signal generated by the crystal 600 during the second oscillation-starting phase reaches a second predetermined number of cycles. Referring to fig. 2, in the second oscillation starting phase, the control circuit 400 may connect the first terminal and the second terminal of the negative resistance generating circuit 300, since the first terminal and the second terminal of the negative resistance generating circuit 300 are coupled to the first terminal XI and the second terminal XO of the crystal 600 through the third switch S3 and the fourth switch S4, respectively. In the second oscillation starting stage, the third switch S3 and the fourth switch S4 are closed, and the control circuit 400 counts the number of cycles of the second oscillation signal generated by the crystal 600 through the first terminal and the second terminal of the negative resistance generation circuit 300. Specifically, the control circuit 400 may count the number of cycles of the second oscillation signal generated by the crystal 600 through a counter or a microprocessor.

Although the amplitude of the second oscillation signal of the crystal 600 has not yet reached the target amplitude in the second oscillation starting stage, the amplitude is significantly improved compared with the amplitude in the first oscillation starting stage, so that the statistical error of the number of cycles of the second oscillation signal generated in the second oscillation starting stage is smaller, and the control circuit 400 is adopted to count the number of cycles of the second oscillation signal generated in the second oscillation starting stage by the crystal 600 in the embodiment of the present application to determine the ending time of the second oscillation starting stage.

The first predetermined number of cycles and the second predetermined number of cycles may be set as desired. For example, the second predetermined number of cycles may be 5000 cycles.

In some embodiments, the counter used in the first oscillation starting stage and the counter used in the second oscillation starting stage may be the same counter or different counters.

In some embodiments, when the amplitude of the oscillation signal generated by the crystal is greater than the target amplitude, the control circuit 400 controls the negative resistance generation circuit 300 to be disconnected from the crystal 600, and the second oscillation starting phase is ended. The control circuit 400 may detect the oscillating signal generated by the crystal 600. The control circuit 400 includes, for example, an amplitude detection circuit for detecting whether the amplitude of the oscillation signal is larger than a target amplitude. When the amplitude of the oscillation signal output by the oscillator circuit 10 is larger than the target amplitude, the control circuit 400 turns off the third switch S3 and the fourth switch S4, and the negative resistance generation circuit 300 is disconnected from the crystal 600, so that the extra loss caused by the negative resistance generation circuit 300 can be avoided and the oscillation frequency of the crystal oscillator can be prevented from being shifted.

In some embodiments, when the number of cycles of the oscillation signal generated by the crystal 600 in the second oscillation starting phase reaches the second predetermined number of cycles, the control circuit 400 controls the negative resistance generating circuit 300 to be disconnected from the crystal 600, and the second oscillation starting phase ends. The control circuit 400 may detect an oscillating signal at the input 101 of the amplifier 100 or at the output 102 of the amplifier 100. The control circuit 400 may be connected to the first pin XO or the second pin XI to detect an oscillation signal at the first pin XO or at the second pin XI. The second predetermined number of cycles is sufficiently large that the amplitude of the oscillating signal generated by the oscillator circuit 10 reaches the target amplitude. Since the number of cycles of the detection oscillation signal is simpler to implement than the detection of the amplitude of the oscillation signal, it is more advantageous to use the number of cycles of the oscillation signal generated by the oscillator circuit 10 in the second oscillation-starting stage as the determination condition for ending the second oscillation-starting stage.

Counters are conventional circuits in a chip. Therefore, the number of cycles of the oscillation signal detected by the counter is used as a judgment condition for ending the second oscillation starting stage, the existing counter in the chip can be multiplexed, no additional circuit is needed, and the area of the oscillator circuit 10 is reduced.

The equivalent circuit of the negative resistance generation circuit 300 includes: the negative resistance, negative resistance 310, is a cancelling resistance. Fig. 9 is an equivalent circuit diagram of the negative resistance generation circuit 300 in the oscillator circuit 10. Specifically, the negative resistance generation circuit 300 includes: a resistor 310 and a capacitor 320 connected in parallel. In some embodiments, the absolute value of the resistance value of the resistor 310 is greater than or equal to the resistance Rm of the crystal 600. For example, the resistance Rm of the crystal 600 is 40 ohms, the resistance 310 is-40 ohms; or the resistor 310 is-100 ohms or-400 to-300 ohms. The negative resistance generating circuit 300 is used to provide the same system function as that provided by the parallel connected resistor 310 and capacitor 320.

The negative resistance generating circuit 300 of fig. 10 is used to provide the same system function as that provided by the parallel connected resistor 310 and capacitor 320; wherein the resistance value of the resistor 310 is less than zero. Referring to fig. 10, the negative resistance generating circuit 300 may include a first N-type transistor Mn1, a second N-type transistor Mn2, a first capacitor C1, a second capacitor C2, and a third capacitor Cx. The first N-type transistor Mn1 and the second N-type transistor Mn2 form an intercoupling pair, and cooperate with the third capacitor Cx to provide a negative impedance (negative impedance) required by the negative resistance generating circuit 300, so as to shorten the start-up time of the crystal 600; in some embodiments, the first N-type transistor Mn1 and the second N-type transistor Mn2 have the same geometric dimensions (channel width, channel length) and electrical characteristics. More specifically, the drain of the first N-type transistor Mn1 is coupled to a first reference voltage VDD, and the source thereof is coupled to a second reference voltage GND, wherein the first reference voltage VDD is higher than the second reference voltage GND. The drain of the second N-type transistor Mn2 is coupled to the first reference voltage VDD, and the source is coupled to the second reference voltage GND; the gate of the second N-type transistor Mn2 is coupled to the drain of the first N-type transistor Mn1, and the drain of the second N-type transistor Mn2 is coupled to the gate of the first N-type transistor Mn 1. The third capacitor Cx is coupled between the source of the first N-type transistor Mn1 and the source of the second N-type transistor Mn 2. The first capacitor C1 is coupled between the drain of the first N-type transistor Mn1 and the first terminal XI of the crystal 600, and the second capacitor C2 is coupled between the drain of the second N-type transistor Mn2 and the second terminal XO of the crystal 600; in some embodiments, the first capacitor C1 and the second capacitor C2 have the same capacitance value. The first capacitor C1 and the second capacitor C2 have a function of isolating direct current to avoid affecting direct current bias points of other circuits.

It is understood that the implementation of the negative resistance generation circuit 300 is not limited to the embodiment shown in fig. 9, and the negative resistance generation circuit 300 may be modified to obtain substantially the same effect. A circuit topology capable of realizing the equivalent circuit shown in fig. 8 can be used to realize the negative resistance generation circuit 300 of the present application.

The embodiment of the application also provides a chip. The chip includes: a first pin, a second pin and the oscillator circuit of the above embodiment. The input end of the amplifier is connected with the first pin, and the output end of the amplifier is connected with the second pin. The chip is for example the chip shown in fig. 1. The chip includes but is not limited to CPU, MCU, SOC, IOT chip. The chip is, for example, a low power consumption chip.

The embodiment of the application also provides an electronic device. Fig. 11 is a schematic view of an electronic device provided in an embodiment of the present application. The electronic device comprises the oscillator circuit and the crystal of the embodiment, and the oscillator circuit is coupled with the crystal.

It should be noted that the terms "first" and "second" in the description of the present invention are used merely for convenience in describing different components or names, and are not to be construed as indicating or implying a sequential relationship, relative importance, or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

It should be noted that, although the specific embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention should not be construed as limited to the scope of the present invention. Various modifications and changes may be made by those skilled in the art without inventive step within the scope of the present invention as described in the appended claims.

The examples of the embodiments of the present invention are intended to briefly describe the technical features of the embodiments of the present invention, so that those skilled in the art can intuitively understand the technical features of the embodiments of the present invention, and the embodiments of the present invention are not unduly limited.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. An oscillator circuit, comprising: the on-chip oscillator circuit comprises an on-chip oscillator, a negative resistance generating circuit and a control circuit, wherein the oscillator circuit is coupled with a crystal;

the oscillation starting phase of the oscillator circuit comprises a first oscillation starting phase and a second oscillation starting phase, and in the first oscillation starting phase, the control circuit controls the on-chip oscillator to provide an oscillation signal to the crystal; in the second oscillation starting stage, the control circuit controls the on-chip oscillator to stop providing oscillation signals for the crystal, the control circuit controls the negative resistance generation circuit to provide a cancellation resistance for the crystal, the cancellation resistance is used for canceling an equivalent resistance generated by the crystal, and the resistance value of the cancellation resistance is smaller than zero;

wherein, in the first oscillation phase, the frequency of the oscillation signal provided by the on-chip oscillator is reduced from a first frequency to a second frequency, or is increased from the second frequency to the first frequency, the first frequency is greater than the resonance frequency of the crystal, and the second frequency is less than the resonance frequency of the crystal.

2. The oscillator circuit of claim 1, wherein the control circuit controls the negative resistance generation circuit to stop providing a cancellation resistance to the crystal during the first start-up phase.

3. The oscillator circuit according to claim 2, wherein the on-chip oscillator is a ring oscillator, and when the input signal of the ring oscillator is a ramp signal that decreases from a high voltage to a low voltage, the frequency of the oscillation signal output by the ring oscillator decreases from the first frequency to the second frequency; when the input signal of the ring oscillator is a ramp signal rising from the low voltage to the high voltage, the frequency of the oscillation signal output by the ring oscillator is increased from the second frequency to the second frequency.

4. The oscillator circuit of claim 3, wherein the ring oscillator comprises: a first inverter, a second inverter, a third inverter, a current source, a fourth inverter and a fifth inverter,

the first inverter includes: a first PMOS transistor and a first NMOS transistor connected in series, the second inverter comprising: a second PMOS transistor and a second NMOS transistor connected in series, the third inverter comprising: a third PMOS transistor and a third NMOS transistor connected in series;

the current source includes: the fourth NMOS transistor, the fifth PMOS transistor and the resistor are sequentially connected in series between a power supply end and the ground, the fourth NMOS transistor receives the ramp signal which is decreased from high voltage to low voltage or the ramp signal which is increased from low voltage to high voltage, the current on a path formed by the fourth NMOS transistor, the fifth PMOS transistor and the resistor is bias current, the fifth PMOS transistor and the sixth PMOS transistor form a current mirror, and the bias current is copied to the first inverter, the second inverter and the third inverter which are cascaded;

the output of the first phase inverter, the second phase inverter and the third phase inverter of the cascade is connected to the first end of the crystal through the fourth phase inverter, and the output of the first phase inverter, the second phase inverter and the third phase inverter of the cascade is connected to the second end of the crystal through the fourth phase inverter and the fifth phase inverter in sequence.

5. The oscillator circuit of claim 1, further comprising an amplifier having an input coupled to a first end of the crystal and an output coupled to a second end of the crystal, wherein the amplifier is a single transistor amplifier or an inverter based amplifier.

6. The oscillator circuit according to any one of claims 1 to 5, wherein the first frequency is 2 times a resonance frequency of the crystal and the second frequency is half the resonance frequency of the crystal.

7. The oscillator circuit of claim 6, wherein the first oscillation stage precedes the second oscillation stage.

8. The oscillator circuit of claim 7, wherein at a start point of the first start-up phase, the frequency of the oscillating signal provided by the on-chip oscillator begins to decrease from the first frequency until the first start-up phase ends when the frequency of the oscillating signal provided by the on-chip oscillator decreases to the second frequency; or,

at the starting point of the first oscillation stage, the frequency of the oscillation signal provided by the on-chip oscillator starts to increase from the second frequency until the first oscillation stage is finished when the frequency of the oscillation signal provided by the on-chip oscillator increases to the first frequency;

the length of the first oscillation starting stage is smaller than that of the second oscillation starting stage.

9. The oscillator circuit of claim 8, wherein the control circuit controls the negative resistance generation circuit to stop providing the cancellation resistance to the crystal when the amplitude of the oscillating signal of the crystal reaches a target amplitude during a second start-up phase, and the second start-up phase ends.

10. The oscillator circuit of claim 9, wherein the first start-up phase ends and the second start-up phase begins when the number of cycles of the oscillating signal provided by the on-chip oscillator to the crystal in the first start-up phase is greater than a first predetermined number of cycles.

11. The oscillator circuit of claim 10, wherein the second start-up phase ends when a number of cycles of the oscillating signal of the crystal is greater than a second predetermined number of cycles in the second start-up phase, wherein the first predetermined number of cycles is less than the second predetermined number of cycles.

12. The oscillator circuit of claim 11, wherein the control circuit comprises a counter configured to count the number of cycles of the oscillating signal provided by the oscillator to the crystal and the oscillating signal of the crystal; or

The control circuit includes a microprocessor for counting the number of cycles of the oscillation signal provided by the oscillator to the crystal and the oscillation signal of the crystal.

13. The oscillator circuit of claim 12, further comprising: a first switch, a second switch, a third switch and a fourth switch, the first switch and the second switch are respectively connected between the on-chip oscillator and the first end and the second end of the crystal, the third switch and the fourth switch are respectively connected between the negative resistance generating circuit and the first end and the second end of the crystal,

in the first oscillation phase, the on-chip oscillator provides an oscillation signal to the crystal, and the negative resistance generation circuit stops providing a cancellation resistance to the crystal, including: the control circuit controls the first switch and the second switch to be closed so that the on-chip oscillator provides an oscillation signal to the crystal, and controls the third switch and the fourth switch to be opened so that the negative resistance generation circuit stops providing a cancellation resistance to the crystal;

in the second oscillation starting phase, the control circuit controls the on-chip oscillator to stop providing the oscillation signal to the crystal, and the control circuit controls the negative resistance generation circuit to provide the cancellation resistance to the crystal, including: the control circuit controls the first switch and the second switch to be opened so that the on-chip oscillator stops providing the oscillation signal to the crystal, and controls the third switch and the fourth switch to be closed so that the negative resistance generation circuit provides the offset resistance to the crystal;

the second oscillation starting phase is ended, and the control circuit controls the negative resistance generation circuit to stop providing the counteracting resistance for the crystal, and the method comprises the following steps: the control circuit controls the third switch and the fourth switch to be opened so that the negative resistance generation circuit stops providing the cancellation resistance to the crystal.

14. The oscillator circuit of claim 1, wherein the negative resistance generation circuit comprises: a first N-type transistor having a drain coupled to a first reference voltage and a source coupled to a second reference voltage, wherein the first reference voltage is higher than the second reference voltage; a second N-type transistor, wherein a drain of the second N-type transistor is coupled to the first reference voltage, a source of the second N-type transistor is coupled to the second reference voltage, a gate of the second N-type transistor is coupled to a drain of the first N-type transistor, and a gate of the first N-type transistor is coupled to a drain of the second N-type transistor; a first capacitor coupled between the drain of the first N-type transistor and a first terminal of the transistor; a second capacitor coupled between the drain of the second N-type transistor and the second terminal of the transistor; and a third capacitor coupled between the source of the first N-type transistor and the source of the second N-type transistor.

15. An electronic device, comprising: the oscillator circuit and crystal as claimed in any one of claims 1 to 14, the oscillator circuit being coupled to the crystal.