CN115360187A - Semiconductor device and method for sharing capacitor device between functional blocks - Google Patents

Semiconductor device and method for sharing capacitor device between functional blocks Download PDF

Info

Publication number
CN115360187A
CN115360187A CN202210442388.5A CN202210442388A CN115360187A CN 115360187 A CN115360187 A CN 115360187A CN 202210442388 A CN202210442388 A CN 202210442388A CN 115360187 A CN115360187 A CN 115360187A
Authority
CN
China
Prior art keywords
functional block
connection node
capacitive
controlled
capacitive device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210442388.5A
Other languages
Chinese (zh)
Inventor
段志刚
陈永青
梁昌
陈京好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Singapore Pte Ltd
Original Assignee
MediaTek Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Singapore Pte Ltd filed Critical MediaTek Singapore Pte Ltd
Publication of CN115360187A publication Critical patent/CN115360187A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a semiconductor device, comprising: a first function block for providing at least a first predetermined function; a second function block for providing at least a second predetermined function; a first capacitive device disposed physically proximate to the first functional block; a second capacitive device disposed physically proximate to the second functional block; a first coupling path including at least one first connection node connected with the first functional block; a first switching device coupled to the first capacitive device and controlled to selectively connect the first capacitive device to the first connection node; and a second switching device coupled to the second capacitive device and controlled to selectively connect the second capacitive device to the second functional block or the second connection node, wherein the second connection node is disposed on the first coupling path and connected to the first connection node.

Description

Semiconductor device and method for sharing capacitor device between functional blocks
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for sharing a capacitor device among functional blocks.
Background
A decoupling capacitor (decoupling capacitor) is a capacitor (capacitor) mounted on the power supply terminals of components in a circuit. The capacitor can provide a stable power supply, and simultaneously can reduce the noise (decoupling noise) of the component coupled to the power supply end, and can indirectly reduce the influence of the noise of the component on other components. Large decoupling capacitors can generally provide greater power supply noise reduction performance. However, the cost of the above becomes higher, and the circuit area also increases.
With the explosive growth of cell phones, tablet computers, and other portable electronic devices, the need for smaller form factor products with better electrical performance has spurred research into decoupling capacitor (capacitance) designs. Therefore, there is a strong need for a semiconductor device having flexibility in capacitor design to achieve better electrical performance.
Disclosure of Invention
The present invention solves the above-mentioned problems by providing a semiconductor device and a method for sharing a capacitor device among functional blocks.
According to a first aspect of the present invention, there is disclosed a semiconductor device comprising:
a first function block for providing at least a first predetermined function;
a second function block for providing at least a second predetermined function;
a first capacitive device disposed physically proximate to the first functional block;
a second capacitive device disposed physically proximate to the second functional block;
a first coupling path including at least one first connection node connected with the first functional block;
a first switching device coupled to the first capacitive device and controlled to selectively connect the first capacitive device to the first connection node; and
a second switching device coupled to the second capacitive device and controlled to selectively connect the second capacitive device to the second functional block or the second connection node,
the second connection node is disposed on the first coupling path and connected to the first connection node.
According to a second aspect of the present invention, there is disclosed a semiconductor device comprising:
a first function block for providing at least a first predetermined function;
a second function block for providing at least a second predetermined function;
a first capacitive device disposed physically proximate to the first functional block;
a second capacitive device disposed physically proximate to the second functional block;
a first coupling path including at least one first connection node connected with the first functional block;
a first switching device coupled to the first capacitive device and controlled to selectively connect the first capacitive device to the first connection node; and
a second switching device coupled to the second capacitive device and controlled to selectively connect the second capacitive device to the second functional block or the second connection node,
wherein the second connection node is disposed on the first coupling path and connected to the first connection node, and
wherein the second switching device is controlled to connect the second capacitance device to the second connection node under the control of the first functional block when it is determined that the first functional block is in a heavy load state.
According to a third aspect of the invention, there is disclosed a method of sharing capacitive means between functional blocks, comprising:
configuring a first coupling path comprising at least a first connection node and a second connection node, wherein the first connection node is connected to the second connection node and is also connected to a first functional block;
controlling a first capacitive device to be connected to the first functional block when the first functional block is in operation or under light load, wherein the first capacitive device is physically disposed near the first functional block; and
controlling a second capacitive means to be connected to the second connection node when a second functional block is inactive or lightly loaded, wherein the second capacitive means is physically disposed in the vicinity of the second functional block.
The semiconductor device of the present invention includes: a first function block for providing at least a first predetermined function; a second function block for providing at least a second predetermined function; a first capacitive device disposed physically proximate to the first functional block; a second capacitive device disposed physically proximate to the second functional block; a first coupling path including at least one first connection node connected with the first functional block; a first switching device coupled to the first capacitive device and controlled to selectively connect the first capacitive device to the first connection node; and a second switching device coupled to the second capacitive device and controlled to selectively connect the second capacitive device to the second functional block or the second connection node, wherein the second connection node is disposed on the first coupling path and connected to the first connection node. By adopting the mode, the second capacitor device can be provided for the first functional block to be used when needed, so that the working stability and excellent performance of the first functional block are ensured, and when the capacitor device is not needed or the second functional block is working, the second capacitor device can be switched back to be connected with the second functional block, so that the normal working of the second functional block is not influenced; therefore, the scheme of the invention can flexibly schedule according to different working conditions of the functional blocks, does not need to arrange redundant or excessive capacitor devices, maximally utilizes each capacitor device, improves the operation efficiency and saves the cost.
Drawings
Fig. 1 shows an exemplary block diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 2 illustrates an exemplary perspective view of a semiconductor device according to an embodiment of the present invention.
Fig. 3 illustrates an exemplary cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 4 illustrates an exemplary cross-sectional view of a semiconductor device according to another embodiment of the present invention.
Fig. 5 is a schematic diagram showing an equivalent circuit of a semiconductor device having one coupling path configured to share a capacitance device between a plurality of functional blocks according to an embodiment of the present invention.
Fig. 6 is an equivalent circuit diagram of a semiconductor device having two coupling paths configured to share a capacitive device among a plurality of functional blocks according to another embodiment of the present invention.
FIG. 7 illustrates an exemplary flow diagram of a method of sharing a capacitive device among a plurality of functional blocks according to an embodiment of the present invention.
Detailed Description
In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The invention relates to a method for preparing a high-temperature-resistant ceramic material. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.
It will be understood that, although the terms "first," "second," "third," "primary," "secondary," and the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or major element, component, region, layer or section discussed below could be termed a second or minor element, component, region, layer or section without departing from the teachings of the present inventive concept.
Furthermore, spatially relative terms such as "below," "under," "above," "over," and the like may be used herein for ease of description to facilitate describing the relationship of an element or feature. Another element or feature is shown. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terms "about," "approximately," and "about" generally mean within a range of ± 20% of a stated value, or ± 10% of the stated value, or ± 5% of the stated value, or ± 3% of the stated value, or ± 2% of the stated value, or ± 1% of the stated value, or ± 0.5% of the stated value. The specified values of the present invention are approximate values. Where not specifically stated, the stated values include the meanings of "about", "approximately" and "approximately". The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be understood that when an "element" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly adjacent to" another element or layer, there are no intervening elements or layers present.
Note that: (i) Like features will be denoted by like reference numerals throughout the drawings, and will not necessarily be described in detail in each of the drawings in which they appear, and (ii) a series of drawings may show different aspects of a single item, each aspect being associated with various reference labels that may appear throughout the sequence, or may appear only in selected figures of the sequence.
Fig. 1 shows an exemplary block diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor apparatus 100 may include a plurality of functional blocks, for example, functional blocks 110, 120, 130, and 140. Each function block is configured to provide at least one predetermined function. In order to reduce power supply noise and provide a relatively stable power supply, each functional block may be provided with a respective capacitive means, such as a capacitor or a decoupling capacitor, physically located close to the respective functional block, e.g. overlapping the projection of the functional block above and below it.
Fig. 2 illustrates an exemplary perspective view of a semiconductor device 200 according to an embodiment of the present invention. In an embodiment of the present invention, each functional block may be implemented as a silicon die (silicon die), such as silicon die 210, 220, 230, and 240. The silicon grains 210, 220, 230, and 240 may be disposed on a substrate or film (RDL) redistribution layer (RDL), which may be further connected to a Printed Circuit Board (PCB) through solder balls depending on the process and/or packaging technology.
According to one embodiment of the present invention, each silicon die may be equipped with a respective capacitive (capacitor) device, such as capacitive devices 215, 225, 235, and 245. Capacitive device 215 is physically close to silicon die 210 (and corresponding functional blocks). The capacitive device 225 is physically located near the silicon die 220 (and corresponding functional block). The capacitive device 235 is physically located near the silicon die 230 (and corresponding functional block). The capacitive device 245 is physically located near the silicon die 240 (and corresponding functional blocks). In embodiments of the present invention, the capacitive devices 215, 225, 235, and 245 may be implemented as pad-side capacitors (LSCs) or near-die-side capacitors (DSCs) attached under the die shadow.
Fig. 3 illustrates an exemplary cross-sectional view of a semiconductor device according to an embodiment of the present invention, for illustrating one possible placement of a capacitive device (capacitive device) when using Fan-Out (Fan-Out) Wafer Level Packaging (WLP) technology. The semiconductor device 300 may include silicon grains 31 disposed on one side of the thin film RDL 32. Capacitive devices 35 physically proximate to the silicon die 31 may be disposed on opposite sides of the thin film RDL 32. The capacitor device 35 and the silicon die 31 are respectively disposed on opposite sides of the thin film RDL 32. The thin film RDL 32 may be connected to the PCB 34 by one or more solder balls 33. In this embodiment, the capacitor device 35 may be a decoupling capacitor configured for the silicon die 31 to reduce power supply noise and provide a relatively stable power supply. The silicon die 31 in fig. 3 may be any of the silicon die 210, 220, 230, and 240 in fig. 2, and the capacitive device (capacitive means or capacitive apparatus) 35 in fig. 3 may be any of the corresponding capacitive devices 215, 225, 235, and 245 in fig. 2.
Fig. 4 shows an exemplary cross-sectional view of a semiconductor device according to another embodiment of the invention for illustrating another possible placement of capacitive devices when employing flip-chip packaging techniques. The semiconductor device 400 may include silicon grains 41 disposed on a flip chip (flip chip) substrate 46. Silicon die 41 may be attached to one side of a flip-chip substrate 46 by one or more solder balls 42. The capacitive devices 45 may be disposed on opposite sides of the flip-chip substrate 46 in physical proximity to the silicon die 41. The flip chip substrate 46 may be connected to the PCB 44 by one or more solder balls 43. In this embodiment, the capacitive means 45 may be a decoupling capacitor configured for the silicon die 41 to reduce power supply noise and provide a relatively stable power supply. The silicon die 41 in fig. 4 may be any of the silicon die 210, 220, 230, and 240 in fig. 2, and the capacitive device (apparatus or device) 45 in fig. 4 may be any of the corresponding capacitive devices 215, 225, 235, and 245 in fig. 2.
According to an embodiment of the present invention, in order to provide flexibility in capacitor (or capacitance) design, thereby achieving better electrical performance for semiconductor devices, one or more coupling paths may be introduced and configured in the respective semiconductor devices to implement the proposed method of sharing a capacitance device among a plurality of functional blocks or silicon dies.
Fig. 5 is a schematic diagram showing an equivalent circuit of a semiconductor device having one coupling path configured to share a capacitance device between a plurality of functional blocks according to an embodiment of the present invention. Semiconductor device 500 may include functional blocks 510, 520, 530, and 540, capacitive devices 515, 525, 535, and 545, switching devices 513, 523, 533, and 543, and coupling path 550.
Each functional block is configured to provide at least one predetermined function and is provided with a corresponding capacitive device, such as a capacitor or a decoupling capacitor, physically disposed in proximity to (e.g., proximate to) the corresponding functional block. As an example, capacitive device 515 is physically disposed near functional block 510, capacitive device 525 is physically disposed near functional block 520, capacitive device 535 is physically disposed near functional block 530, and capacitive device 545 is physically disposed near functional block 540. The way in which the capacitive device (or capacitive means) is brought into physical proximity with the functional block can be referred to the schematic shown in fig. 3 or fig. 4.
Coupling path 550 may include connecting nodes N1, N2, and N3, where connecting nodes N1, N2, and N3 are all connected to functional block 510. Switching device 513 is connected to capacitive device 515 and is controlled (controlled) to selectively connect capacitive device 515 to connection node N1, where switching device 513 connects capacitive device 515 to switching node SN1-1 and then to connection node N1, as needed. Switching device 523 is connected to capacitive device 525 and is controlled to selectively connect capacitive device 525 to either functional block 520 or to connection node N2. More specifically, switching device 523 may be controlled to connect capacitive device 525 to switching node SN2-1 or switching node SN2-2, where switching node SN2-1 is connected to functional block 520 and switching node SN2-2 is connected to connection node N2.
Similarly, switching device 533 is connected to capacitive device 535 and is controlled to selectively connect capacitive device 535 to either functional block 530 or connection node N3. More specifically, switching device 533 may be controlled to connect capacitive device 535 to switching node SN3-1 or switching node SN3-2, where switching node SN3-1 is connected to function block 530 and switching node SN3-2 is connected to connection node N3. Similarly, switching device 543 may be controlled to connect capacitive device 545 to switching node SN4-1 or switching node SN4-2, where switching node SN4-1 is connected to functional block 540 and switching node SN4-2 is connected to connection node N3.
According to one embodiment of the invention, the semiconductor device 500 may be a multicore processor chip, and the functional blocks 510 to 540 may be processing cores of the multicore processor chip, respectively. According to another embodiment of the present invention, the semiconductor device 500 may be a chip device, and the functional blocks 510 to 540 may be different Processing units, such as but not limited to a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU) … of a chip device (or device). In one embodiment, the function block 510 may be a main function block, such as a large core or a main processing unit. However, whether one functional block is designed as a main functional block is not a limitation of the present invention.
According to an embodiment of the invention, when any of the functional blocks 520-540 (any of the functional blocks 520-540) is not operating (or not running) or operating (or running) but performs a relatively light load task (e.g., a light load), the respective switching devices 523-543 may be controlled, by way of example and not limitation, to connect the corresponding capacitive devices 525, 535, 545 to the switching nodes SN2-2, SN3-2, SN4-2, respectively, under control of the functional block 510, thereby coupling the corresponding capacitive devices to the connection nodes N2 and/or N3 (and to the connection node N1 and the functional block 510).
More specifically, when functional block 520 is not operating or is operating but performing a relatively light load task (e.g., a light load), by way of example and not limitation, switching device 523 may be controlled under the control of functional block 510 to connect capacitive device 525 to switch node SN2-2 to couple the corresponding capacitive device 525 to connection node N2 and then connect connection node N2 to connection node N1 and functional block 510. Thus, the capacitive device 525 configured for the function block 520 is shared with the function block 510 and provided to the function block 510 as a supplemental capacitive device to the function block 510. The control mechanisms of the switching devices 533, 543 can be analogized.
Note that in one embodiment of the invention, when a functional block 510 is running (or operational) and when one or more of the plurality of functional blocks 520-540 are not running (or operational) or are running but performing a relatively light load task (e.g., a light load), one or more capacitive devices configured for the corresponding functional block 520-540 may be shared with the functional block 510 and provided to the functional block 510 in a similar manner. In an embodiment of the present invention, how many capacitive devices (or capacitive means) are connected to the functional block 510 can be flexibly controlled according to the actual load condition of the functional block 510.
According to another embodiment of the invention, the function block
Figure BDA0003614497990000061
When any of the devices is not operating or is operating but performing a relatively light load task, and when the functional block 510 is determined to be operating under relatively heavy load conditions (e.g., heavy load), the switching devices 523-543 may be controlled under control of the functional block 510 to connect the corresponding capacitive devices 525-545 to the switching nodes SN 2-SN 4-2 to couple the corresponding capacitive devices to the connection nodes N2 and/or N3 (e.g., and the connection node N1 and the functional block 510), by way of example and not limitation.
More specifically, when the function block 520 is not operating or working but is performing a relatively light-loaded task, and when the function block 510 is determined to be operating under relatively heavy load conditions (e.g., heavy load), the switching device 523 may be controlled, by way of example and not limitation, the switching device 523 may be controlled under the control of the function block 510 to connect the capacitive device 525 to the switch node SN2-2 to couple the corresponding capacitive device 525 to the connection node N2 and then to the connection node N1 and the function block 510. In this manner, the capacitive device 525 configured for the functional block 520 is shared with the functional block 510 and provided to the functional block 510 as its supplemental capacitive device. The control mechanism of the switching devices 533, 543 can be analogized.
Similarly, in embodiments of the invention, when the function block 510 is operating under relatively heavy load conditions (e.g., heavy load), and when one or more of the plurality of function blocks 520-540 are not operating or are operating but performing relatively light load tasks, the one or more function blocks may be flexibly controlled
Figure BDA0003614497990000071
The corresponding capacitive device is connected to a function block 510.
According to one embodiment of the invention, 4 levels, e.g., 1-4 levels, may be provided to define the load of the function block 510. When it is determined that the function block 510 is operating under class 1 load conditions, no auxiliary capacitance device is needed. When it is determined that the function block 510 is operating under a level 2 load condition, an auxiliary capacitance arrangement may be required. When it is determined that the function block 510 is operating under a level 3 load condition, two auxiliary capacitance devices may be required. When it is determined that the function block 510 is operating under 4-level load conditions, three auxiliary capacitance devices may be required. As described above, when one or more auxiliary capacitive devices are needed, a corresponding number of switching devices may be controlled to connect the corresponding capacitive device to the functional block 510 through the corresponding switching node, connection node, and coupling path 550. In the embodiment of the present invention, 5, 6, or more, or less levels may be set to define the load of the functional block 510, or 5, 6, or more, or less levels may be defined according to the number of the shared capacitive devices. The judgment of the light load or the heavy load can be made by the load current, for example, the class 1 load condition can be that the load current is in the range of 0% -30% of the rated current, the class 2 load condition can be that the load current is in the range of 30% -70% of the rated current, the class 3 load condition can be that the load current is in the range of 75% -100% of the rated current, the class 4 load condition can be that the load current is in the range of 101% -110% of the rated current, and so on. Light loads may be, for example, class 1 load conditions and class 2 load conditions, heavy loads may be, for example, class 3 load conditions and class 4 load conditions; alternatively, a light load may be, for example, a class 1 load condition, a heavy load may be, for example, a class 2 load condition, a class 3 load condition, and a class 4 load condition, and so on. Of course, the above description is only an example, and the load level, the light load and the heavy load in the embodiment of the present invention may be freely designed and specified as needed, and only the spirit of the present invention needs to be comprehended according to the present invention. The number of levels and the number of shared capacitive means in embodiments of the invention are not limited to those described above, and any number implemented according to the inventive idea may be applied.
According to another embodiment of the present invention, 4 sharing conditions, e.g., sharing condition 1 to sharing condition 4, may be set to define how to share the capacitive device (capacitive means) with the functional block 510. For example, when all functional blocks are working or heavily loaded, then the common condition 1 is satisfied and the capacitive device is not shared with the functional block 510. When a functional block is inactive or lightly loaded, the sharing condition 2 is satisfied, and the capacitive device (capacitive device) corresponding to the inactive or lightly loaded functional block (i.e., configured as a capacitor) will be shared with the functional block 510 and provided to the functional block 510 via the corresponding switch node, connection node, and coupling path 550 in the manner described above. When two functional blocks are inactive or lightly loaded, the sharing condition 3 is satisfied, and the capacitive devices corresponding to (i.e., configured as) the inactive or lightly loaded functional blocks will be shared with the functional block 510 and provided to the functional block 510 through the corresponding switching nodes, connection nodes, and coupling paths 550 in the manner described above. When the three functional blocks are inactive or lightly loaded, the common condition 4 is satisfied, and the capacitive devices corresponding to (i.e., configured as) the inactive or lightly loaded functional blocks will be shared with the functional block 510 and provided to the functional block 510 via the corresponding switching nodes, connection nodes, and coupling paths 550 in the manner described above. In the embodiment of the present invention, the determination condition for using the shared or shared capacitor device may be when the load of one or more function blocks is heavy load, and/or when the load of one or more function blocks handles light load. Therefore, in the embodiment of the present invention, a common capacitor device may be used according to at least one of the above determinations. When the load of one or more functional blocks is in heavy load, the method can find out whether other functional blocks do not work or are in light load, and then the capacitance devices corresponding to the functional blocks are connected to the one or more heavy load functional blocks. When the load of one or more functional blocks handles light load, whether the functional blocks which are working or heavy load exist in other functional blocks can be searched, and then the capacitance devices corresponding to the one or more light load functional blocks are connected to the functional blocks which are working or heavy load. Either of these can be used alternatively or in combination to provide faster sharing of capacitive devices. When there are a plurality of functional blocks that need to use the capacitive devices of other functional blocks, the capacitive devices may be sorted for sharing according to the order of entering the overload, the order of issuing the requests, or the importance degree of the functional blocks, and the number of the capacitive devices that need to be shared may also be freely set according to the requirements, for example, if the load current decreases to a predetermined value after the capacitive devices are connected, it may be regarded that no additional shared capacitive devices are needed.
It should be noted that, although four functional blocks and four corresponding capacitive elements and switching elements are used in the embodiment for convenience of description, the number of the functional blocks and the corresponding capacitive elements and switching elements should not be limited to four, and may be any positive integer greater than 1.
Fig. 6 is an equivalent circuit diagram of a semiconductor device having two coupling paths configured to share a capacitive device among a plurality of functional blocks according to another embodiment of the present invention. The semiconductor device 600 may include functional blocks 610, 620, 630, and 640, capacitive devices 615, 625, 635, and 645, switching devices 613, 623, 633, and 643, and two coupling paths 650 and 660.
The equivalent circuit of the semiconductor device 600 is similar to that of the semiconductor device 500, except that one more coupling path 660 is introduced into the semiconductor device 600. Coupling path 660 may include connecting nodes N4 and N5, where both connecting nodes N4 and N5 are connected to functional block 620. The same reference numbers in fig. 5 and 6 may indicate similar or functionally similar elements. Accordingly, some descriptions are omitted herein for the sake of brevity.
The switching device 613 is connected to the capacitance device 615 and is controlled to selectively connect the capacitance device 615 to the connection node N1 (the connection node N1 is also connected to the function block 610) or the connection node N4. The switching device 623 is connected to the capacitive device 625 and is controlled to selectively connect the capacitive device 625 to either connection node N2 or connection node N4 (connection node N4 is also connected to function block 620). The switching device 633 is connected to the capacitive device 635 and is controlled to selectively connect the capacitive device 635 to the functional block 630, the connection node N3, or the connection node N5. The switching device 643 is connected to the capacitance device 645 and is controlled to selectively connect the capacitance device 645 to the functional block 640, the connection node N3, or the connection node N5.
Note that in the present embodiment, the switching devices 633 and 643 may be controlled to switch between three switching nodes. In addition, it is noted that, unlike the embodiment shown in fig. 5, in the present embodiment, the switching device 613 may also be controlled to selectively connect the capacitance device 615 to the connection node N1 or the fourth connection node N4, and when it is determined that the second functional block (the functional block 620) is in a heavy load condition (e.g., a heavy load), the switching device 613 may be controlled to connect the capacitance device 615 to the connection node N4 and then to the functional block 620. As such, the capacitive device 615 configured for the functional block 610 is shared with the functional block 620 and provided to the functional block 620 as its supplemental capacitive device. The control mechanism for the switching devices 633 and 643 can be analogized.
According to one embodiment of the invention, the semiconductor device 600 may be a multicore processor chip, and the functional blocks 610 to 640 may be processing cores of the multicore processor chip, respectively. According to another embodiment of the present invention, the semiconductor device 600 may be a chip device, and the functional blocks 610-640 may be different processing units such as, but not limited to, a CPU, a GPU, an NPU …, etc. of the chip device. In one embodiment, the function block 610 may be a main function block, such as a large core or a main processing unit. However, whether one functional block is designed as a main functional block is not a limitation of the present invention.
Similarly, to provide auxiliary capacitive devices to the function block 620, when any one of the function blocks 610, 630, and 640 is inactive or active but performing a relatively light load task, the respective switching devices 613, 633, and 643 may be controlled, by way of example and not limitation, to connect the corresponding capacitive devices 615, 635, and 645 to the connection node N4 or N5 (and then to the function block 620) under control of the function block 620 or the function block 610, according to an embodiment of the present invention.
According to another embodiment of the present invention, when any one of the functional blocks 610, 630, and 640 is not running or running but performing a relatively light load task, and when the functional block 620 is determined to be running (e.g., heavily loaded) under relatively heavy load conditions, the switching devices 613, 633, and 643 may be controlled under the control of the functional block 620 or the functional block 610 to connect the corresponding capacitive devices 615, 635, and 645 to the connection node N4 or N5 (and then to the functional block 620), by way of example and without limitation.
In one embodiment of the present invention, capacitive devices corresponding to the more than one functional blocks 610, 630, and 640 may be flexibly controlled to be connected to the functional block 620 when the functional block 620 is operating (or operating under relatively heavy load conditions) and when more than one of the functional blocks 610, 630, and 640 is not operating (is not working) or is operating but performing a relatively light load task (e.g., a light load).
For the mechanism of defining the load of the functional block 620 by using multiple stages and then controlling the corresponding switching devices of the remaining functional blocks to connect the corresponding capacitive devices to the functional block 620 through the switching nodes, the connection nodes and the coupling path 660, reference may be made to the relevant paragraphs of fig. 5, which are not described herein for brevity.
Similarly, with respect to the mechanism that uses a plurality of sharing conditions to define how to share the capacitive devices with the functional block 620 and then control the corresponding switching devices of the remaining functional blocks to connect the corresponding capacitive devices to the functional block 620 through the switching nodes, the connection nodes and the coupling path 660, reference may be made to the corresponding paragraphs of fig. 5, which are omitted here for the sake of brevity.
According to embodiments of the present invention, coupling paths 550, 650, and 660 may be implemented by traces, copper wires or metal wires, or any other signal transmission lines.
It should be noted again that although four functional blocks and four corresponding capacitive devices and switching devices are used in the example for ease of description, the number of functional blocks and corresponding capacitive devices and switching devices should not be limited to four and may be any positive integer greater than 1.
Furthermore, although one or two coupling paths are used in the examples for expression, the present invention should not be limited thereto. Since the structure of a semiconductor device having more than two coupling paths is easily derived by those skilled in the art based on the teaching of fig. 5 and 6, the corresponding drawings and description are omitted here for the sake of brevity. In embodiments of the invention, when it is expected that one or more of the functional blocks requires another one or more capacitive devices as the supplemental capacitive devices (i.e. the capacitive devices of the other functional blocks act as a common capacitive device), the connection node of the one or more functional blocks may be connected to the switchable switch of the one or more capacitive devices (e.g. as an access point for the switching device), so that when it is required and able to act as a supplemental capacitive device, the switching device may be switched into connection with the one or more functional block switch access points to act as a supplemental capacitive device for the one or more functional blocks. Wherein the need to act as a supplemental capacitive device may refer to the one or more functional blocks of the above embodiments, for example, during heavy duty operation; the device capable of serving as a supplementary capacitor may refer to the functional block corresponding to the candidate supplementary capacitor in the above embodiment being in a non-operation or light-load operation.
FIG. 7 illustrates an exemplary flow diagram of a method of sharing capacitive devices among functional block(s) in accordance with an embodiment of the present invention. The proposed method may comprise the steps of:
step S702: a first coupling path is configured, the first coupling path including at least a first connection node and a second connection node connected to the first functional block.
Step S704: when the first functional block is in operation (or reloading), the first capacitive means is controlled to be connected to the first connection node and to the first functional block, wherein the first capacitive means is physically arranged close to the first functional block.
Step S706: and when the second functional block does not work or is lightly loaded, controlling the second capacitor device to be connected to the second connecting node, wherein the second capacitor is arranged close to the second functional block physically.
In some embodiments of the invention, step S706 may further include: judging whether the first functional block is in a heavy load state; controlling the second capacitive device to be connected to the second connection node when it is determined that the first functional block is in the heavy load condition.
Furthermore, in some embodiments of the invention, the method may further comprise the optional steps of: controlling the third capacitive means to be connected to a third connection node when the third functional block is inactive or lightly loaded, wherein the third connection node is disposed on the first coupling path and connected to the first connection node, and the third capacitive means is disposed physically close to the third functional block.
Furthermore, in some embodiments of the invention, the method may further comprise some optional steps: configuring a second coupling path comprising at least a fourth connection node, wherein the fourth connection node is connected to the second functional block; when the second functional block works, the second capacitor is controlled to be connected to the fourth connecting node; when the first functional block does not work or is lightly loaded, controlling the first capacitor to be connected to the fourth connecting node; and controlling the third capacitor to be connected to a fifth connection node when the third functional block is not operated or is lightly loaded, wherein the fifth connection node is disposed on the second coupling path and connected to the fourth connection node, and the third capacitor is disposed physically close to the third functional block.
Based on the proposed semiconductor device structure with flexibility in capacitance design, better electrical performance is achieved by sharing capacitance means between functional blocks to provide one or more capacitance means as auxiliary capacitance means when needed.
Those skilled in the art will readily observe that numerous modifications and variations of the apparatus and method may be made while maintaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (14)

1. A semiconductor device, comprising:
a first function block for providing at least a first predetermined function;
a second function block for providing at least a second predetermined function;
a first capacitive device disposed physically proximate to the first functional block;
a second capacitive device disposed physically proximate to the second functional block;
a first coupling path including at least one first connection node connected to the first functional block;
a first switching device coupled to the first capacitive device and controlled to selectively connect the first capacitive device to the first connection node; and
a second switching device coupled to the second capacitive device and controlled to selectively connect the second capacitive device to the second functional block or the second connection node,
the second connection node is disposed on the first coupling path and connected to the first connection node.
2. The semiconductor device of claim 1, wherein the second switching device is controlled to connect the second capacitive device to the second connection node when the first functional block is determined to be in a heavy load condition.
3. The semiconductor device according to claim 1, further comprising:
a third function block for providing at least a third predetermined function;
a third capacitive device physically disposed proximate to the third functional block; and
a third switching device coupled to a third capacitive device and controlled to selectively connect the third capacitive device to the third functional block or the third connection node,
the third connection node is disposed on the first coupling path and connected to the first connection node.
4. The semiconductor device of claim 3, wherein the third switching device is controlled to connect the third capacitive device to the third connection node when the first functional block is determined to be in a heavy load condition.
5. The semiconductor device according to claim 1, further comprising:
a second coupling path comprising at least a fourth connection node connected to the second functional block,
wherein the first switching device is also controlled to selectively connect the first capacitive device to the first connection node or the fourth connection node, and the first switching device is controlled to connect the first capacitive device to the fourth connection node when it is determined that the second functional block is in a heavy load condition.
6. The semiconductor device according to claim 3, further comprising:
a second coupling path comprising at least a fourth connection node connected to the second functional block,
wherein the third switching means is further controlled to selectively connect the third capacitive means to the third functional block, the third connection node or the fifth connection node, an
Wherein a fifth connection node is provided on the second coupling path and connected to the fourth connection node, and the third switching device is controlled to connect the third capacitive device to the fifth connection node when it is determined that the second functional block is in a heavy load condition.
7. The semiconductor device of claim 1, wherein the semiconductor device is a multicore processor chip, and the first functional block and the second functional block are each a processing core of the multicore processor chip.
8. The semiconductor device of claim 1, wherein the semiconductor device is a chip device, and the first functional block and the second functional block are different processing units of the chip device.
9. A semiconductor device, comprising:
a first function block for providing at least a first predetermined function;
a second function block for providing at least a second predetermined function;
a first capacitive device disposed physically proximate to the first functional block;
a second capacitive device disposed physically proximate to the second functional block;
a first coupling path including at least one first connection node connected with the first functional block;
a first switching device coupled to the first capacitive device and controlled to selectively connect the first capacitive device to the first connection node; and
a second switching device coupled to the second capacitive device and controlled to selectively connect the second capacitive device to the second functional block or the second connection node,
wherein the second connection node is disposed on the first coupling path and connected to the first connection node, and
wherein the second switching device is controlled to connect the second capacitance device to the second connection node under the control of the first functional block when it is determined that the first functional block is in a heavy load state.
10. The semiconductor device according to claim 9, further comprising:
a third function block configured to provide at least a third predefined mining function;
a third capacitive device physically disposed proximate the third functional block; and
a third switching device coupled to the third capacitive device and controlled to selectively connect the third capacitive device to the third functional block or the third connection node,
wherein the third connection node is disposed on the first coupling path and connected to the first connection node, and
controlling the third switching means to connect the third capacitive means to the third connection node under control of the first functional block when the first functional block determines a heavy load condition.
11. The semiconductor device according to claim 9, further comprising:
a second coupling path comprising at least a fourth connection node connected to the second functional block,
wherein the first switching device is also controlled to selectively connect the first capacitive device to the first connection node or the fourth connection node, the first switching device being controlled to connect the first capacitive device to the fourth connection node under control of the first functional block when it is determined that the second functional block is in a heavy load condition.
12. The semiconductor device according to claim 10, further comprising:
a second coupling path comprising at least a fourth connection node connected to the second functional block,
wherein the third switching device is further controlled to selectively connect a third capacitive device to the third functional block, the third connection node, or the fifth connection node, an
Wherein the fifth connection node is disposed on the second coupling path and connected to the fourth connection node, and the third switching device is controlled to connect the third capacitance to the fifth connection node under the control of the first functional block when it is determined that the second functional block is in a heavy load condition.
13. A method of sharing capacitive devices between functional blocks, comprising:
configuring a first coupling path comprising at least a first connection node and a second connection node, wherein the first connection node is connected to the second connection node and is also connected to a first functional block;
controlling a first capacitive device to be connected to the first functional block when the first functional block is operational, wherein the first capacitive device is physically disposed proximate the first functional block; and
controlling a second capacitive means to be connected to the second connection node when a second functional block is inactive or lightly loaded, wherein the second capacitive means is physically disposed in the vicinity of the second functional block.
14. The method of claim 13, further comprising:
configuring a second coupling path comprising at least a fourth connection node, wherein the fourth connection node is connected to the second functional block;
when the second functional block works, the second capacitor is controlled to be connected to the fourth connecting node;
when the first functional block does not work or is lightly loaded, controlling the first capacitor to be connected to the fourth connecting node; and
when the third functional block is not working or is lightly loaded, the third capacitance device is controlled to be connected to the fifth connecting node,
wherein the fifth connection node is disposed on the second coupling path and connected to the fourth connection node, and the third capacitive device is disposed physically close to the third functional block.
CN202210442388.5A 2021-04-27 2022-04-25 Semiconductor device and method for sharing capacitor device between functional blocks Pending CN115360187A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163180148P 2021-04-27 2021-04-27
US63/180,148 2021-04-27

Publications (1)

Publication Number Publication Date
CN115360187A true CN115360187A (en) 2022-11-18

Family

ID=84030826

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210442388.5A Pending CN115360187A (en) 2021-04-27 2022-04-25 Semiconductor device and method for sharing capacitor device between functional blocks

Country Status (1)

Country Link
CN (1) CN115360187A (en)

Similar Documents

Publication Publication Date Title
US11715695B2 (en) Size and efficiency of dies
US7598630B2 (en) IC with on-die power-gating circuit
US7986532B2 (en) Split thin film capacitor for multiple voltages
US11564317B2 (en) Integrated power delivery board for delivering power to an ASIC with bypass of signal vias in a printed circuit board
US8717093B2 (en) System on chip power management through package configuration
US11147165B2 (en) Electronic system and interposer having an embedded power device module
US7266788B2 (en) Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
CN115360187A (en) Semiconductor device and method for sharing capacitor device between functional blocks
WO2012058189A1 (en) An apparatus for monolithic power gating on an integrated circuit
WO2022053085A1 (en) Multiphase interleaved buck power supply and electronic device
US7227260B2 (en) Method and system for a pad structure for use with a semiconductor package
TW202243382A (en) Semiconductor device and method for sharing capacitive devices among multiple functional block
US20120178217A1 (en) Method and apparatus for low inductive design pattern
US11552049B2 (en) Embedded power device module, processor substrate and electronic system
US20240194568A1 (en) Substrate and semiconductor device including the same
WO2023039576A1 (en) Half-bridge switching circuits with parallel switches
WO2024102593A2 (en) Methods, apparatuses, integrated circuits, and circuit boards for power conversion with reduced parasitics
CN116936531A (en) Integrated circuit substrate design with integrated power converter module and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination